A Quasi-Cyclic Low-Density Parity Check Encoding Processing Method and Apparatus

Abstract

This paper discloses a quasi-cyclic LDPC encoding processing method and apparatus. The quasi-cyclic LDPC encoding processing method includes: determining a processing strategy for quasi-cyclic low-density parity-check (LDPC) encoding according to the data characteristics of an information bit sequence to be encoded; and performing quasi-cyclic LDPC encoding on the information bit sequence based on a base matrix and a lifting value according to the processing strategy. The technical solution of this paper can improve the adaptability and flexibility of quasi-cyclic LDPC encoding.

Description

[0001] This application is a divisional application of Chinese patent application No. 201710184762.5, filed on March 24, 2017, entitled "A Quasi-Cyclic Low-Density Parity Check Encoding Processing Method and Apparatus". Technical Field

[0002] This invention relates to the field of communication technology, and in particular to a quasi-cyclic low-density parity check (LDPC) coding processing method and apparatus. Background Technology

[0003] Figure 1 It is a structural block diagram of a digital communication system based on relevant technologies, such as Figure 1 As shown, a digital communication system generally includes three parts: a transmitter, a channel, and a receiver. The transmitter performs channel coding on the information bit sequence to obtain coded codewords, interleaves the coded codewords, and maps the interleaved bits to modulation symbols. Then, it processes and transmits the modulation symbols according to the communication channel information. In the channel, factors such as multipath propagation and motion cause specific channel responses, all of which distort data transmission. Noise and interference further degrade data transmission. The receiver receives the modulation symbol data after it has passed through the channel. At this point, the modulation symbol data is distorted and requires specific processing to recover the original information sequence.

[0004] Based on the encoding method used by the transmitting end to encode the information sequence, the receiving end can process the received data accordingly to reliably recover the original information bit sequence. The encoding method must be visible to both the transmitting and receiving ends. Generally, the encoding method is based on forward error correction (FEC) coding, where FEC adds redundant information to the information sequence. The receiving end can use this redundant information to reliably recover the original information sequence.

[0005] At the transmitting end, the transport block to be transmitted needs to be segmented into multiple smaller transport blocks. Then, each of these smaller transport blocks undergoes FEC coding. The transport block to be transmitted has a certain transport block size (TBS) and coding rate. The FEC coding rate is generally defined as the ratio of the number of bits in the original information bit sequence entering the encoder to the number of bits in the actual transmitted bit sequence (or rate-matched output sequence). In Long Term Evolution (LTE) communication systems, the transport block size is relatively flexible, thus meeting the various data packet size requirements of LTE communication systems. LTE communication systems use a Modulation and Coding Scheme (MCS) index to indicate different combinations of modulation order and coding rate R. The TBS index is determined through control information such as Downlink Control Information (DCI) or Channel Quality Indication (CQI), and the size of the actual information bit sequence is determined jointly based on the number of resource blocks (RBs) and the TBS index. Channel types can include data channels and control channels. Data channels generally carry data from User Equipment (UE), while control channels carry control information, including MCS index number, channel information, DCI, CQI, and other control information. Bandwidth generally refers to the spectrum width allocated by the system for data transmission; in LTE systems, bandwidths are divided into 20MHz, 10MHz, 5MHz, etc. Data transmission directions include uplink data and downlink data. Uplink data generally refers to data transmitted from the UE to the base station, while downlink data refers to data transmitted from the base station to the UE.

[0006] Some common FEC codes include convolutional codes, Turbo codes, and Low Density Parity Check (LDPC) codes. In FEC coding, a k-bit information sequence is FEC-coded to obtain an n-bit FEC codeword (with nk bits of redundancy). LDPC codes are linear block codes that can be defined using a very sparse parity check matrix or a bipartite graph. It is precisely by utilizing the sparsity of its parity check matrix that low-complexity encoding and decoding can be achieved, thus making LDPC practical. Through various practical and theoretical proofs, LDPC codes have demonstrated to be the best-performing channel code in Additive White Gaussian Noise (AWGN) channels, with performance very close to the Shannon limit.

[0007] LDPC codes are widely used in IEEE 802.11ac, IEEE 802.11ad, IEEE 802.11aj, IEEE 802.16e, IEEE 802.11n, microwave communication, and fiber optic communication. In the parity check matrix of an LDPC code, each row is a parity check code. If the value of an element at a certain index position in each row is equal to 1, it means that the bit participates in the parity check; if it is equal to 0, it means that the bit at that position does not participate in the parity check. Because quasi-cyclic LDPC coding is very simple to describe and the decoder structure is simple, it is used in various communication standards. Quasi-cyclic LDPC coding, also known as structured LDPC coding, has a parity check matrix H of mb×Z rows and nb×Z columns, composed of mb×nb submatrices. Each submatrix is ​​a different power of a Z×Z fundamental permutation matrix, obtained by 1-bit right cyclic shift (or left cyclic shift by 1); alternatively, each submatrix can be considered as a Z×Z identity matrix obtained by several bits right cyclic shift (or left cyclic shift). In this case, knowing the cyclic shift values ​​and the submatrix sizes is sufficient to determine a quasi-cyclic LDPC code. All shift values ​​corresponding to each submatrix constitute an mb×nb matrix, which can be called the base matrix, base parity check matrix, or base protograph. The submatrix size can be called the extension factor, lift size, or submatrix size; here, it is described as the lift size. Because the quasi-cyclic LDPC code is very compact and simple in structure, and highly advantageous for decoder implementation, it is also called a structured LDPC code. According to the definition of quasi-cyclic LDPC codes, the parity check matrix of a quasi-cyclic LDPC code has the following form:

[0008]

[0009] If hb ij ==-1, then It is a square matrix of size Z×Z containing all zeros, if hb ij ≠-1, then hb equal to the basic permutation matrix P ij To more easily describe the cyclic shift of the identity matrix mathematically, a fundamental permutation matrix P of size Z×Z is defined here in the quasi-cyclic LDPC code base matrix described above. The cyclic shift of the identity matrix is ​​equivalent to raising the fundamental permutation matrix P to a power of the corresponding size. The fundamental permutation matrix P is shown below:

[0010]

[0011] Through such a power hb ij This allows each block matrix to be uniquely identified. If a block matrix is ​​a square matrix of all zeros, it is generally represented by -1 or a null value in the underlying matrix; while if it is obtained by cyclic shifting 's' of the identity matrix, then it is equal to 's', so all hb ij A fundamental matrix Hb can be constructed, and the fundamental matrix (or fundamental parity check matrix) Hb of the LDPC code can be represented as follows:

[0012]

[0013] Therefore, a quasi-cyclic LDPC code can be uniquely determined by the fundamental matrix Hb and the lift value Z. Thus, the fundamental matrix Hb of a quasi-cyclic LDPC code includes two types of elements: elements indicating the all-zero square matrix and elements indicating the shift size of the cyclic shift of the identity matrix. The elements indicating the all-zero square matrix are generally represented by -1 or null values, while the elements indicating the shift size of the cyclic shift of the identity matrix are represented by an integer from 0 to (Z-1). In the fundamental matrix Hb, if any row contains q non--1 elements (elements indicating the shift size of the identity matrix), then the row weight of that row is considered to be q. Similarly, the column weight can be defined as the number of all non--1 elements (elements indicating the shift size of the identity matrix) in any column of the fundamental matrix Hb. The fundamental matrix includes several parameters: mb, nb, and kb, where mb is the number of rows in the fundamental matrix (equal to the number of parity columns), nb is the total number of columns in the fundamental matrix, and kb = nb - mb is the number of systematic columns in the fundamental matrix.

[0014] For example, the fundamental matrix Hb (2 rows and 4 columns) is as follows, and the lift value z is equal to 4:

[0015]

[0016] The parity check matrix is ​​then:

[0017]

[0018] Since quasi-cyclic LDPC codewords are systematic codes, meaning the systematic bits in the codeword are equal to the information bits before encoding, only the parity bits need to be calculated in quasi-cyclic LDPC encoding. Quasi-cyclic LDPC encoding can then be performed based on the parity check matrix described above. For example, the parity check matrix H can be described as two parts: H = [Hs; Hp], where Hs corresponds to the systematic bit matrix and Hp corresponds to the parity bit matrix. According to the LDPC encoding principle, for a quasi-cyclic LDPC codeword C (including the systematic bits Cs and the parity bits Cp), the condition H × C = 0 is satisfied, i.e., [Hs; Hp] × [Cs; Cp] = 0; therefore, it can be deduced that Hs × Cs = Hp × Cp, and thus Cp = (Hp) / (Hp). -1 ×Hs×Cs, where '×' in the formula represents binary matrix multiplication, (x) -1 It is a binary matrix inversion calculation; therefore, the parity bit Cp of the quasi-cyclic LDPC codeword can be calculated, thus obtaining the quasi-cyclic LDPC codeword C = [Cs; Cp].

[0019] In the quasi-cyclic LDPC codes described above, each element position in the fundamental matrix has only one shift value or a -1 value. This can be described as the quasi-cyclic LDPC code having one edge, meaning that the corresponding non--1 element position in the fundamental matrix has only one shift value. However, there are also fundamental matrices with more than one edge in quasi-cyclic LDPC codes, where the non--1 element positions in the fundamental matrix contain multiple shift values. For example, in the parity check matrix, the submatrix is ​​composed of multiple identity matrices with cyclic shifts superimposed. In this case, the quasi-cyclic LDPC code has more than one edge. For instance, the fundamental matrix Hb (2 rows, 4 columns) is shown below, and the lift value z equals 4. Since the non--1 element positions in the fundamental matrix contain at most two shift values, the example fundamental matrix has two edges. The number of edges in the fundamental matrix is ​​equal to the maximum number of shift values ​​in the non--1 element positions of the fundamental matrix.

[0020]

[0021] The parity check matrix is ​​then:

[0022]

[0023] During LDPC encoding, the original information data to be transmitted (i.e., the information bit sequence) undergoes encoding processing. This processing can include: First, padding the information bit sequence with dummy bits (the dummy bits are known to the transceiver and do not need to be transmitted) to ensure the length of the padded bit sequence reaches the system bit length for LDPC encoding. If the length of the information bit sequence is equal to the system bit length, padding is unnecessary. Second, quasi-cyclic LDPC encoding is performed on the padded information bit sequence to obtain an LDPC encoded output sequence. Then, bit selection is performed on the LDPC encoded output sequence to obtain a rate-matched output sequence. The ratio of the length of the information bit sequence to the length of the rate-matched output sequence is the code rate of the rate-matched output sequence. Finally, the rate-matched output sequence is transmitted. For the receiving end, the decoding process is as follows: First, after receiving the data sent by the sending end, which is generally a Log Likelihood Ratio (LLR) sequence (or, it can be described as a soft sequence or soft bit information sequence); second, the received LLR sequence is deselected (or rate matched), and the data at the corresponding dummy bit positions filled by the sending end is assigned a large value (such as infinity), thereby obtaining a LLR sequence to be decoded that is the same length as the LDPC encoded output sequence of the sending end; then, the LLR sequence to be decoded is LDPC decoded to obtain the LDPC decoded output sequence; finally, the filled dummy bits are removed from the LDPC decoded output sequence to obtain the original data to be received (or the information bit sequence sent by the sending end).

[0024] In LDPC encoding and decoding, the design of the LDPC code parity check matrix is ​​crucial to ensuring excellent performance, high throughput, high flexibility, and low complexity. Conversely, a poorly designed LDPC parity check matrix will degrade performance and may also negatively impact complexity and flexibility.

[0025] Although quasi-cyclic LDPC codes have been applied in various communication standards, analysis reveals that the code rates and code lengths of these standards are relatively limited, resulting in poor flexibility, difficulty in compatibility with various application scenarios, and inconsistent complexity due to different decoding algorithms under different conditions. For example, the IEEE 802.11ad standard only has one code length (672) and four code rates (1 / 2, 5 / 8, 3 / 4, 13 / 16); the IEEE 802.11n standard only has three code lengths (648, 1296, 1944) and four code rates (1 / 2, 2 / 3, 3 / 4, 5 / 6). It can be observed that since quasi-cyclic LDPCs are defined by a partial fundamental matrix, the main drawback of these used quasi-cyclic LDPC codes is insufficient flexibility, referring to the ability to flexibly vary the coding rate and code length. In new Radio Access Technology (new RAT) systems, channel coding schemes need to support flexible code rates and code lengths, meaning they must support information lengths with granularity at least the same as or even lower than LTE systems, and the code rate can be flexibly varied. For example, new RAT systems include the following application scenarios: enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), or massive machine-type communications (mMTC). In eMBB scenarios, the maximum downlink throughput can reach 20Gbps, and the maximum uplink data throughput can reach 10Gbps; in URLLC, it can support a minimum BLER (Block Error Rate) of 10e-5 and a minimum uplink / downlink latency of 0.5 milliseconds; and in mMTC, devices can have batteries that can operate for many years without interruption.

[0026] However, LDPC codes have limitations in adaptability to various application scenarios, such as high-throughput and low-throughput scenarios, large-coverage and small-coverage requirements, and different operating modes. Currently, there is no effective solution to the adaptability problem of LDPC codes in related technologies. Summary of the Invention

[0027] The technical problem to be solved by the present invention is to provide a quasi-cyclic LDPC encoding processing method and apparatus, which can improve the adaptability and flexibility of quasi-cyclic LDPC encoding.

[0028] This invention provides a quasi-cyclic LDPC encoding processing method, comprising:

[0029] The processing strategy for quasi-cyclic low-density parity-check LDPC encoding is determined based on the data characteristics of the bit sequence to be encoded.

[0030] Based on the processing strategy, the information bit sequence is quasi-cyclic LDPC encoded and rate-matched output based on the fundamental matrix and boost value.

[0031] This invention also provides a quasi-cyclic LDPC encoding processing apparatus, comprising:

[0032] The processing module is used to determine the processing strategy of quasi-cyclic low-density parity-check LDPC encoding based on the data characteristics of the information bit sequence to be encoded; and, based on the processing strategy, to perform quasi-cyclic LDPC encoding and rate matching output on the information bit sequence based on the fundamental matrix and the boost value.

[0033] A storage module is used to store the base matrix and the boost value.

[0034] Compared with the prior art, the quasi-cyclic LDPC encoding processing method and apparatus provided by the embodiments of the present invention determine the processing strategy of quasi-cyclic low-density parity-check LDPC encoding based on the data characteristics of the information bit sequence to be encoded; according to the processing strategy, the information bit sequence is quasi-cyclic LDPC encoded and rate-matched output based on the fundamental matrix and boost value. The technical solution of the embodiments of the present invention can improve the adaptability and flexibility of quasi-cyclic LDPC encoding. Attached Figure Description

[0035] Figure 1 It is a structural block diagram of a digital communication system based on relevant technologies;

[0036] Figure 2 This is a flowchart of a quasi-cyclic LDPC encoding processing method according to Embodiment 1 of the present invention;

[0037] Figure 3 This is a schematic diagram of the basic matrix example 1 in Embodiment 1 of the present invention;

[0038] Figure 4 This is a schematic diagram of Example 1 of the core matrix verification block B in the basic matrix of Embodiment 1 of the present invention;

[0039] Figure 5 This is a schematic diagram of example 2 of the basic matrix in embodiment 1 of the present invention;

[0040] Figure 6 This is a schematic diagram of example 3 of the basic matrix in embodiment 1 of the present invention;

[0041] Figure 7 This is a schematic diagram of example 4 of the basic matrix in embodiment 2 of the present invention;

[0042] Figure 8 This is a schematic diagram of example 5 of the basic matrix in embodiment 2 of the present invention;

[0043] Figure 9 This is a schematic diagram of example 6 of the basic matrix in embodiment 2 of the present invention;

[0044] Figure 10 This is a schematic diagram of example 7 of the basic matrix in embodiment 2 of the present invention;

[0045] Figure 11 This is a schematic diagram of example 8 of the basic matrix in embodiment 2 of the present invention;

[0046] Figure 12 This is a schematic diagram of example 9 of the basic matrix in embodiment 2 of the present invention;

[0047] Figure 13 This is a schematic diagram of a quasi-cyclic LDPC encoding processing device according to Embodiment 3 of the present invention;

[0048] Figure 14 This is a schematic diagram of an electronic device for quasi-cyclic LDPC encoding processing according to Embodiment 4 of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0050] The quasi-cyclic LDPC coding processing method provided in this embodiment of the invention can be used in New Radio Access Technology (new RAT) communication systems, as well as in LTE mobile communication systems, future fifth-generation mobile communication systems, or other wireless and wired communication systems.

[0051] The data transmission direction is either the base station sending data to the mobile user (User Equipment UE) (downlink transmission service data), or the mobile user (User Equipment UE) sending data to the base station (uplink transmission service data).

[0052] Mobile users include: mobile devices, access terminals, user terminals, user stations, user units, mobile stations, remote stations, remote terminals, user agents, user equipment, user devices, or other similar terms. Base stations include: access points (APs), node Bs, radio network controllers (RNCs), evolved node Bs (eNBs), base station controllers (BSCs), base transceiver stations (BTSs), base stations (BSs), transceiver functional units, radio routers, radio transceivers, basic service sets (BSSs), extended service sets (ESSs), radio base stations (RBSs), or other similar terms.

[0053] Example 1

[0054] like Figure 2 As shown, Embodiment 1 of the present invention provides an example of a quasi-cyclic LDPC encoding processing method, including the following steps:

[0055] Step S210: Determine the processing strategy for quasi-cyclic low-density parity-check (LDPC) encoding based on the data characteristics of the information bit sequence to be encoded.

[0056] Step S220: According to the processing strategy, the information bit sequence is quasi-cyclic LDPC encoded and rate-matched output based on the base matrix and boost value.

[0057] In this embodiment, the information bit sequence refers to the original information bit sequence that enters quasi-cyclic LDPC encoding. Depending on the usage of the information bit sequence (e.g., application scenario, working mode, transmission direction, user equipment type, etc.), the information bit sequence has different data characteristics.

[0058] In this embodiment, the data characteristics of the information bit sequence include at least one of the following:

[0059] The information bit sequence includes the operating mode, application scenario, link direction, user equipment type, length, modulation and coding scheme (MCS) level, control channel element (CCE) aggregation level, search space, scrambling method, cyclic redundancy check (CRC) format, channel type, control information format, and channel state information. Information (CSI) process, subframe index number of the information bit sequence, carrier frequency corresponding to the information bit sequence, release version of the information bit sequence, coverage area of ​​the information bit sequence, length of the rate-matched output sequence obtained by quasi-cyclic LDPC coding and bit selection of the information bit sequence, bit rate of the rate-matched output sequence, combination of bit rate and length of the rate-matched output sequence, combination of bit rate and length of the rate-matched output sequence, and Hybrid Automatic Repeat Request (HARQ) data transmission version number of the information bit sequence.

[0060] Among them, the rate-matched output sequence is the sequence obtained by bit selection of the LDPC encoded sequence obtained by quasi-cyclic LDPC encoding;

[0061] In this embodiment, the processing strategy includes determining at least one of the following parameters:

[0062] The processing strategy for determining quasi-cyclic low-density parity-check (LDPC) encoding includes determining at least one of the following:

[0063] The core matrix parity block structure of the fundamental matrix; the orthogonality of the fundamental matrix; the characteristics of the fundamental matrix; the maximum number of systematic columns of the fundamental matrix; the maximum number of systematic columns of the quasi-cyclic LDPC encoding; the number of fundamental matrices; the element correction method of the fundamental matrix; the number of edges of the fundamental matrix; the minimum code rate of the fundamental matrix under the maximum information bit sequence length; the minimum code rate of the fundamental matrix under shortened encoding; the method for determining the boost value; the method for determining the granularity of the boost value; the maximum value of the boost value; the number of systematic columns in the rate-matched output sequence obtained by performing quasi-cyclic LDPC encoding and bit selection on the information bit sequence; the rate-matched output sequence... The following methods are described: parity column puncturing method; interleaving method of the rate-matched output sequence; starting bit position of bit selection in the rate-matched output sequence; maximum information length supported by the quasi-cyclic LDPC encoding; method for determining the information bit length supported by the quasi-cyclic LDPC encoding; method for determining the granularity of the information bit length supported by the quasi-cyclic LDPC encoding; maximum number of shortened codes in the quasi-cyclic LDPC encoding; hybrid automatic repeat request (HARQ) merging method in the quasi-cyclic LDPC encoding; starting bit position of bit selection in the rate-matched output sequence; maximum number of HARQ transmissions in the quasi-cyclic LDPC encoding; and number of HARQ transmission versions in the quasi-cyclic LDPC encoding.

[0064] In one implementation, the operating modes include: in-band operating mode, out-of-band operating mode, and stand-alone operating mode.

[0065] In one implementation, the application scenarios of the information bit sequence include: enhanced mobile broadband (eMBB) scenarios, ultra-reliable low-latency communication (URLLC) scenarios, and massive machine-type communication (mMTC) scenarios.

[0066] In one implementation, the link direction of the information bit sequence includes: uplink data and downlink data.

[0067] In one embodiment, the length information of the information bit sequence includes: length information greater than a positive integer value K0 and length information less than or equal to a positive integer value K0, wherein K0 is an integer greater than 128.

[0068] In one implementation, the fundamental matrix Hb is:

[0069] Among them, the matrix [AB] formed by submatrix A and submatrix B is the core matrix of the basic matrix, and submatrix B is the core matrix verification block;

[0070] The core matrix verification block structure is selected from at least two of the following structure types: lower triangular structure, double diagonal structure, and quasi-double diagonal structure;

[0071] The lower triangular matrix has the following three characteristics: a) the elements with row index i and column index j are both equal to -1 and j > i; b) all elements on the diagonal of the matrix are non--1 elements; c) at least one non--1 element exists among all elements below the diagonal of the matrix.

[0072] The double-diagonal matrix has the following two features a)-b): a) The first column of the matrix contains three non--1 elements, where the first and last elements of the first column are both non--1 elements; b) The elements with column index i and row index (i-1) and the elements with column index i and row index i are all non--1 elements, i = 1, 2, ..., (I0-1), where I0 is the row number of the matrix;

[0073] The quasi-double-diagonal matrix includes any of the following characteristics: a) the elements indicated by row index (mb0-1) and column index 0 are non--1 elements, and the submatrix formed by the upper right (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; b) the elements indicated by row index (mb0-1) and column index (mb0-1) of the matrix are non--1 elements, and the submatrix formed by the upper left (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; c) the elements indicated by row index 0 and column index 0 of the matrix are non--1 elements, and the submatrix formed by the lower right (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; wherein mb0 is the row number of the matrix.

[0074] In one implementation, the fundamental matrix Hb is:

[0075] Wherein, the number of columns of submatrix D is less than or equal to the number of columns of the core matrix [AB] formed by submatrix A and submatrix B, and the orthogonality of the base matrix is ​​the orthogonality property of the submatrix D. The orthogonality of the base matrix is ​​selected from at least two of the following types: orthogonality property, quasi-orthogonality property, and non-orthogonality property.

[0076] The orthogonality property includes: no intersection between the row index sets RowSETi (i = 0, 1, ..., (I-1)); the union of all the row index sets RowSETi (i = 0, 1, ..., (I-1)) constitutes all the row indexes of the submatrix D; in the submatrix D, the submatrix Di formed by all the rows indicated by the row index sets RowSETi has at most one non--1 element among all the elements indicated by any column index; wherein I is a positive integer less than the number of rows of the submatrix D; and the RowSETi (i = 0, 1, ..., (I-1)) includes at least two elements.

[0077] The quasi-orthogonality property includes: two column index sets ColSET0 and ColSET1, ColSET0 and ColSET1 having no intersection and the union of ColSET0 and ColSET1 forming all column indexes of the submatrix D, the submatrix D0 formed by all columns indicated by the column index set ColSET0 in the submatrix D, and the submatrix D1 formed by all columns indicated by the column index set ColSET1 in the submatrix D, wherein D1 has the orthogonality property, while D0 does not have the orthogonality property;

[0078] The non-orthogonal property includes: the submatrix D does not have the orthogonal and quasi-orthogonal properties as described above.

[0079] In one implementation, the maximum number of systematic columns of the base matrix is ​​selected from at least two integer values ​​from 2 to 32.

[0080] In one implementation, the maximum number of systematic columns of the basic matrix is ​​selected from at least two of the following integer values: 4, 6, 8, 10, 16, 24, 30, 32.

[0081] In one implementation, the number of the basic matrices is selected from at least two of the following integer values: 1, 2, 3, 4.

[0082] In one implementation, the element correction method of the fundamental matrix is ​​selected from at least two of the following methods: proportional down rounding, mixed remainder method, adjusted and proportional down rounding method, binary bit sequence extraction method, remainder method with respect to positive integer powers of 2, modified and remainder method with respect to positive integer powers of 2, remainder method, remainder method with respect to a specific integer value, element correction and remainder method, remainder method with respect to prime numbers, element correction and down rounding method, and remainder method with respect to prime numbers related to row and column index numbers; specifically:

[0083] Method 1 (Rounding down proportionally):

[0084] There exist one or more base matrices with maximum lift Zmax. The non--1 elements of the base matrix corresponding to all lift values ​​Z less than Zmax are obtained by proportionally rounding down the base matrix of the maximum lift Zmax. For example, the elements P of the base matrix are calculated using the following formula (1-1). i,j :

[0085]

[0086] Method 2 (Mixed Modulus Method):

[0087] The elements P of the fundamental matrix are calculated using the following formula (1-2). i,j :

[0088]

[0089] Method 3 (Adjust and round down proportionally):

[0090] The elements P of the fundamental matrix are calculated using the following formula. i,j :

[0091]

[0092] Method 4 (Binary bit sequence extraction method):

[0093] The elements P of the fundamental matrix are obtained as follows: i,j :

[0094] Each non--1 element position in the base matrix has an L-bit sequence. All lift values ​​form H sets of lift values. If Z belongs to the k-th set of lift values, then the element value of the non--1 position in the base matrix corresponding to the k-th set of lift values ​​is: select the leftmost k bits, the 2k-1 bits, and the 2k-1 bits from the L-bit sequence corresponding to the non--1 element position to form a (k+2)-bit sequence. The value corresponding to the (k+2)-bit sequence is the element value of the corresponding non--1 element position in the base matrix of the corresponding lift value Z.

[0095] Method 5 (Method for finding the remainder when raising a positive integer power to 2):

[0096] For example, the elements P of the fundamental matrix are calculated using the following formula. i,j :

[0097]

[0098] Method 6 (Modified method with remainder when raised to a positive integer power of 2): Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0099]

[0100] Method 7 (Modal Method): Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0101]

[0102] Method 8 (Modal method for determining integer values): Calculate the elements P of the fundamental matrix according to the following formula. i,j :

[0103]

[0104] Method 9 (Element Correction and Modulo Method): Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0105]

[0106] Method 10 (Modal with respect to prime numbers): Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0107] P i,j =V i,j mod z prime

[0108] Method 11 (Element Correction and Floor Method): Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0109]

[0110] Method 12 (Method for finding the remainder of a prime number related to row and column indices):

[0111] The element values ​​of the modified fundamental matrix are calculated based on the row index i, column index j, and lifting value Z of the fundamental matrix. For example, the element P of the fundamental matrix is ​​calculated using the following formula (1-12). i,j :

[0112]

[0113] Wherein, z prime It is the largest prime number that is less than or equal to the lift value Z.

[0114] Among them, V i,j It corresponds to Z max The value of the element in the i-th row and j-th column of the fundamental matrix, P i,jZ is the value of the element in the i-th row and j-th column of the fundamental matrix Z, where Z is the lift value of the quasi-cyclic LDPC encoding. max Z is an integer greater than 0, and Z is less than or equal to Z. max Positive integers;

[0115] The t mentioned is:

[0116] The s mentioned is such that 2 s The largest integer whose ≤ Z is true;

[0117] The w is a definite integer value corresponding to the boost value Z; the z prime It is the largest prime number that is less than or equal to the lift value Z.

[0118] In one implementation, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least two real values ​​that are greater than 0 and less than 1.

[0119] In one implementation, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least two of the following code rate types: 1 / 12, 1 / 8, 1 / 6, 1 / 5, 1 / 4, 1 / 3, 1 / 2, and 2 / 3.

[0120] In one implementation, the minimum code rate of the base matrix under shortened coding is selected from at least two real values ​​that are greater than 0 and less than 1.

[0121] In one implementation, the minimum bitrate of the base matrix under shortened coding is selected from at least two bitrate types: 1 / 12, 1 / 8, 1 / 6, 1 / 5, 1 / 4, and 1 / 3.

[0122] In one implementation, the method for determining the boost value is selected from at least two of the following types of methods: multiplying a positive integer power of 2 by a positive integer, a continuous value method, a method of continuously increasing the value at intervals, a segmented value method, a method of calculating and fine-tuning the value based on the length of the information bit sequence and the number of columns in the basic matrix system, and a method of determining the value by a positive integer power of 2. Specifically,

[0123] Method 1:

[0124] The promotion value is the product of 2 raised to the power of d and a positive integer c; where c is an element of the set of positive integers C and d is an element of the set of non-negative integers D.

[0125] Method 2:

[0126] The boost value is a consecutive integer taken from Zmin to Zmax;

[0127] Where Zmin and Zmax are integers greater than 0, and Zmax is greater than Zmin;

[0128] Method 3:

[0129] The difference between adjacent boost values ​​is equal to an integer power of 2;

[0130] All the lift values ​​form a set Zset, which includes multiple subsets. The difference between any two adjacent lift values ​​of any size within a subset is equal to a non-negative integer power of 2.

[0131] Method 4:

[0132] The boost value is determined by the length of the information bit sequence and the number of columns in the basic matrix system;

[0133] Method 5:

[0134] The boost value is determined by the length of the information bit sequence, the number of columns in the basic matrix system, and the set of integers W;

[0135] Method 6:

[0136] The boost value is equal to a positive integer power of 2.

[0137] In one embodiment, in the method 1 for determining the boost value, the set C and set D are one of the following set pairs: C = {4, 5, 6, 7} and D = {1, 2, 3, 4, 5, 6, 7}; C = {4, 5, 6, 7} and D = {0, 1, 2, 3, 4, 5, 6, 7}; C = {3, 4, 5, 6, 7, 8} and D = {0, 1, 2, 3, 4, 5, 6}; C = {4, 5, 6, 7} and D = { 0,1,2,3,4,5,6,7};C={16,20,24,28}andD={0,1,2,3,4,5};C={16,20,24,28}andD={0,1,2,3,4};C={1,2,3,4,5,6,7}andD={1,2,3,4,5,6,7};C={1,2,3,4,5,6,7}andD={0,1,2,3,4,5,6,7};

[0138] In one implementation, in the method 3 for determining the boost value, the set Zset includes one of the following sets: {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256}}, {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256},{288:32:320}}, {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256},{288:32:512 ...},{10:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256}}、{{1:1:8},{10:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256},{320:64: 512}}、{{2:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256}}、{{2:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256},{320:64:512}};

[0139] In the set {a:b:c}, a is the first element of the set, c is the last element of the set, and b is the interval between two adjacent elements in the set.

[0140] In one implementation, in the method 4 for determining the boost value, the boost value Z is:

[0141] Where K is the length of the information bit sequence, and kb is the number of columns in the basic matrix system;

[0142] In one embodiment, in the method 5 for determining the lift value, the lift value Z is: Z = Z orig +W(Z orig );

[0143] in, K is the length of the information bit sequence, kb is the number of columns in the basic matrix system, and W(Z) orig ) is the integer set W corresponding to the Z. orig One element value;

[0144] In one embodiment, in the method 6 for determining the boost value, the boost value is taken from one of the following sets: {2,4,8,16,32,64,128,256,512}, {2,4,8,16,32,64,128,256}, {2,4,8,16,32,64,128}, {2,4,8,16,32,64}, {2,4,8,16,32}.

[0145] In one implementation, the granularity of the boost value is the difference between any two adjacent boost values ​​of any size among all boost values, and the granularity of the boost value is determined by selecting from at least two of the following methods: the method of determining the value by a non-negative integer power of 2; the method of determining the value by a fixed positive integer; and the method of determining the value by multiplying a first set of positive integers by a second positive integer.

[0146] In one implementation, when the method for determining the granularity of the boost value is the method of determining the value by a non-negative integer power of 2, the set of granularity values ​​for the boost value includes one of the following: {1,2,4,8,16}, {1,2,4,8,16,32}, {1,2,4,8,16,32,64}, {1,2,4,8,16,32,64,128}.

[0147] When the granularity of the boost value is determined using the fixed positive integer method, the fixed positive integer is a positive integer less than or equal to 128.

[0148] In one implementation, the maximum value of the boost is selected from at least two integer values ​​from 4 to 1024.

[0149] In one implementation, the maximum value of the boost value is selected from at least two of the following integer values: 16, 32, 64, 128, 256, 320, 384, 512, 768, 1024.

[0150] In one implementation, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least two integer values ​​from 128 to 8192.

[0151] In one implementation, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 256, 512, 768, 1024, 2048, 4096, 6144, 7680, and 8192.

[0152] In one implementation, the granularity of the information bit length supported by the quasi-cyclic LDPC encoding is the difference between any two adjacent lengths of any size among all supported information bit lengths, and the method for determining the granularity of the information bit length is to select at least two integer values ​​from 2 to 256.

[0153] In one implementation, the information bit length granularity supported by the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 2, 4, 8, 16, 32, 64, 128, 256.

[0154] In one implementation, the maximum number of columns in the shortened code of the quasi-cyclic LDPC encoding is Where ΔK is the maximum number of bits filled in the quasi-cyclic LDPC encoding, Z is the boost value, and the maximum number of columns in the shortened encoding is selected from at least two integer values ​​from 1 to 24.

[0155] In one implementation, the maximum number of columns in the shortened code of the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 0, 1, 2, 3, 4, 5, 6, 8, 12, 16, 24.

[0156] In one implementation, the number of system columns in the rate-matched output sequence is selected from at least two integer values: 0, 1, 2, and 3.

[0157] In one implementation, the HARQ merging method of the quasi-cyclic LDPC encoding is selected from at least two of the following types: soft merging, incremental redundancy merging, and a hybrid of soft merging and incremental redundancy merging.

[0158] In one implementation, the maximum number of HARQ transmissions for the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 1, 2, 3, 4, 5, 6.

[0159] In one implementation, the number of HARQ transport versions is selected from at least two integer values ​​from 1 to 64.

[0160] In one implementation, the number of HARQ transmission versions is selected from at least two of the following integer values: 2, 4, 6, 8, 12, 16, 24, 32.

[0161] In one implementation, the fundamental matrix is ​​selected from Y fundamental matrices, where Y is an integer greater than 1;

[0162] The Y fundamental matrices include at least one of the following features:

[0163] Among the Y fundamental matrices, there are at least two fundamental matrices with the same template matrix;

[0164] Among the Y fundamental matrices, there are at least two fundamental matrices with quasi-identical template matrices;

[0165] Among the Y fundamental matrices, there are at least two fundamental matrices with quasi-identical matrix elements;

[0166] Among the Y basic matrices, at least two basic matrices are nested template matrices;

[0167] Among the Y fundamental matrices, there exist at least two fundamental matrices with the same subset of template matrices;

[0168] Among the Y fundamental matrices, there exist at least two fundamental matrices with the same subset of fundamental matrices;

[0169] The template matrix is ​​obtained by assigning "1" to the non--1 element positions and "0" to the -1 element positions in the base matrix.

[0170] The term "template matrices are identical" means that the two template matrices have a different elements, where a is an integer greater than 0 and less than or equal to 10.

[0171] The term "quasi-identical matrix elements" means that the two basic matrices have b distinct elements, where b is an integer greater than 0 and less than or equal to 10.

[0172] In the two nested basic matrices of the template matrix, the template matrix of the smaller basic matrix is ​​a submatrix of the template matrix of the larger basic matrix;

[0173] The equality of the template matrix subsets means that there exists a submatrix in the template matrix of the basic matrix 1 that is equal to a submatrix in the template matrix of the basic matrix 2.

[0174] The equality of the subsets of the fundamental matrices means that there exists a submatrix in fundamental matrix 1 that is equal to a submatrix in fundamental matrix 2.

[0175] The following is an explanation of the fundamental matrix and the boosting value:

[0176] The fundamental matrix of the quasi-cyclic LDPC encoding comprises elements of two types: 1) elements indicating an all-zero square matrix, typically represented by -1 or a null value, here represented by -1; 2) elements indicating the shift size of the identity matrix cyclic shift, with values ​​ranging from 0 to Z-1, where Z is the lift value of the quasi-cyclic LDPC encoding. The fundamental matrix of the quasi-cyclic LDPC encoding has the following form:

[0177]

[0178] Among them, the matrix [AB] formed by submatrix A and submatrix B is the core matrix (core matrix or kernel matrix) of the quasi-cyclic LDPC coding base matrix, while submatrix A is the core matrix system block and submatrix B is the core matrix check block; submatrix C, submatrix D and submatrix E are three submatrixes that are used to extend the core matrix to obtain a lower code rate.

[0179] In such Figure 3 In the example of the base matrix shown, submatrix A is 401, submatrix B is 402, submatrix C is 403, submatrix D is 404, and submatrix E is 405. The core matrix check block structure (B) of the base matrix can be selected from at least two of the following structures: lower triangular structure, double diagonal structure, and quasi-double diagonal structure.

[0180] The lower triangular structure refers to a matrix with three properties: 1) Elements with row index i and column index j are both equal to -1 (indicating elements in a square matrix of all zeros), and column index j is greater than row index i; 2) All elements on the diagonal of the matrix are non--1 elements; 3) At least one non--1 element exists among all elements below the diagonal of the matrix. Figure 4 The matrix example shown in (a) is a lower triangular structure.

[0181] The double diagonal structure refers to a matrix with two characteristics: 1) the first column of the matrix contains three non--1 elements, where the first and last elements of the first column are both non--1; 2) the two elements indicated by column index i, row index (i-1), and row index i are both non--1, where i = 0, 1, 2, ..., (I0-1), and I0 is the row number of the matrix. Figure 4 The matrix example shown in (b) is a double diagonal structure.

[0182] The quasi-double diagonal structure includes one of the following: 1) the elements indicated by row index (mb0-1) and column index 0 in the matrix are non--1 elements, and the submatrix formed by the upper right row (mb0-1) and column (mb0-1) in the matrix is ​​a double diagonal structure; in such cases... Figure 4 (c) In the matrix structure example of mb0×mb0=5×5 shown, the 4×4 submatrix in the upper right corner is a double diagonal structure, and the element in the 4th row and 0th column is a non--1 element; 2) the elements indicated by the row index (mb0-1) and column index (mb0-1) in the matrix are non--1 elements, and the submatrix formed by the upper left row (mb0-1) and column (mb0-1) in the matrix is ​​a double diagonal structure; in such Figure 4(d) shows an example of a 5×5 matrix structure where mb0×mb0=5×5. The 4×4 submatrix in the upper left corner is a double diagonal structure, and the element in the 4th row and 4th column is a non--1 element; 3) the elements indicated by row index 0 and column index 0 in the matrix are non--1 elements, and the submatrix formed by the lower right (mb0-1) row and (mb0-1) column is a double diagonal structure; in such Figure 4 Example of a matrix structure mb0×mb0=5×5 shown in (e), the 4×4 submatrix in the lower right corner is a double diagonal structure, and the element in the 0th row and 0th column is a non--1 element; wherein mb0 is the row number of the matrix.

[0183] The orthogonality of the fundamental matrix refers to the orthogonality of the submatrix D in the fundamental matrix of the quasi-cyclic LDPC encoding described above. The orthogonality of the fundamental matrix can be selected from at least two of the following: orthogonality, quasi-orthogonality, non-orthogonality, quasi-non-orthogonality, etc.

[0184] The orthogonality property refers to the following: the sets of row indices RowSETi (i = 0, 1, ..., (I-1)) have no intersection; the union of all sets of row indices RowSETi (i = 0, 1, ..., (I-1)) constitutes all row indices of submatrix D; and in submatrix Di, which is formed by all rows indicated by the row indices RowSETi, at most one non--1 element (an element indicating the shift size of the identity matrix cyclic shift) exists among all elements indicated by any column index in submatrix D, where I is a positive integer less than the number of rows in submatrix D. All elements in the set of row indices RowSETi are consecutive positive integers, i = 0, 1, ..., (I-1).

[0185] In such Figure 5 In the example of the fundamental matrix shown, the submatrix D is as follows: Figure 5In submatrix D (601), there are four sets of row indices: RowSET0 = {0, 1, 2}, RowSET1 = {3, 4}, RowSET2 = {5, 6, 7, 8}, and RowSET3 = {9, 10, 11, 12}. It can be seen that in submatrix D (601), submatrix 602 (3 rows, 20 columns), which is formed by all rows indicated by row index set RowSET0, has at most one non--1 element among all three elements indicated by any column index. The element (the element used to indicate the shift size of the cyclic shift of the identity matrix); similarly, it can be seen that in submatrix D(601), the submatrix 603 (2 rows and 20 columns) consisting of all rows indicated by the row index set RowSET1 has at most one non--1 element (the element used to indicate the shift size of the cyclic shift of the identity matrix) among all the elements (2 elements) indicated by any column index. Submatrixes 604 and 605 also have the same characteristics. The submatrix D has orthogonal properties, and it can be considered that... Figure 5 The fundamental matrix shown in the figure has orthogonality, and other fundamental matrices with the same orthogonality also belong to the category of orthogonality.

[0186] The quasi-orthogonality property refers to the following: two sets of column index numbers, ColSET0 and ColSET1, have no intersection and the union of ColSET0 and ColSET1 constitutes all the column index numbers of the submatrix D. The submatrix D composed of all the columns indicated by the column index number set ColSET0 is called D0, and the submatrix D composed of all the columns indicated by the column index number set ColSET1 is called D1. D1 has the orthogonality property as described above, while D0 does not have the orthogonality property described above.

[0187] In such Figure 6 In the example of the basic matrix shown, submatrix D (13 rows and 20 columns) is shown as 701 in the figure, ColSET0 = {0,1}, ColSET1 = {2,3,4,…,19}, and the submatrix D0 formed by all the columns indicated by the column index set ColSET0 is shown as D0. Figure 6 In the example 702, the submatrix D consisting of all columns indicated by the column index set ColSET1 is called D1. Figure 6From 703, it can be observed that submatrix D1 possesses the orthogonality property described above, while submatrix D0 does not. Other fundamental matrices possessing the same quasi-orthogonality property also fall under the category of quasi-orthogonality. During rate matching, the rate matching output sequence obtained by bit selection does not contain F×Z bit system bits, where the F×Z bit system bits correspond to column index number ColSET2 of the fundamental matrix, and ColSET2 is a subset of ColSET0. Figure 6 In the example of the basic matrix shown, ColSET2 = {0,1}, i.e., F = 2, is a system bit that does not contain the first F×Z = 2×Z bits of the quasi-cyclic LDPC mother codeword in the rate-matched output sequence.

[0188] The non-orthogonality property refers to the fact that the submatrix D does not possess the orthogonality and quasi-orthogonality properties described above, for example, Figure 7 The example of the fundamental matrix shown is a submatrix D(801).

[0189] The quasi-orthogonal property refers to the fact that the submatrix D does not possess the orthogonal and quasi-orthogonal properties described above, and the submatrix D satisfies the following condition: the remainders obtained by dividing any two adjacent non--1 element values ​​in any column of the matrix by a positive integer P are equal, where P is an integer greater than 1. Figure 8 The example of the base matrix shown has a submatrix D of 901. In submatrix D, the remainders of any two adjacent non--1 elements divided by the positive integer P = 2 are equal; that is, any two adjacent non--1 elements are either both even or both odd. Figure 8 Two or more adjacent non--1 elements circled in the middle. The advantages are: it simplifies the design of quasi-cyclic LDPC decoders, eliminates address conflicts between rows in row-parallel or block-parallel decoding, and can significantly improve decoding throughput.

[0190] The characteristics of the base matrix can be described as follows: the base matrix of the quasi-cyclic LDPC encoding can also be described as [Hb0 Hb1], where the number of columns of the submatrix Hb0 is equal to the number of columns of the core matrix of the base matrix, and the number of rows of the submatrix Hb0 is equal to the number of rows of the base matrix. The characteristics of the base matrix refer to the characteristics of the submatrix Hb0, which includes: two sets of row indices, RowX and RowY, where RowX and RowY have no intersection and their union constitutes the set of all row indices of the submatrix Hb0; and two sets of column indices, ColX and ColY, where ColX and ColY have no intersection and their union constitutes the set of all column indices of the submatrix Hb0.

[0191] The basic matrix properties include at least two of the following: 1) Column block quasi-congruence property: In the submatrix Hb0, the remainders obtained by dividing any two adjacent non--1 elements in any column by a positive integer P0 are equal, while the remainders obtained by dividing any two adjacent non--1 elements in any column by a positive integer P0 in the submatrix Hb0, which is composed of all rows indicated by the row index set Row Y, are not equal, and the positive integer P0 is an integer greater than 1; 2) Row block quasi-congruence property: In the submatrix Hb0, the remainders obtained by dividing any two adjacent non--1 elements in any column by a positive integer P1 are equal, while the remainders obtained by dividing any two adjacent non--1 elements in any column by a positive integer P1 in the submatrix Hb0, which is composed of all columns indicated by the column index set Col Y, are equal, and the positive integer P0 is an integer greater than 1.

[0192] The number of fundamental matrices refers to the number of fundamental matrices used in the quasi-cyclic LDPC encoding process. Different template matrices are considered different fundamental matrices. The template matrix is ​​the matrix obtained by setting non--1 elements to "1" and -1 elements to "0" in the fundamental matrix of quasi-cyclic LDPC encoding. Furthermore, different numbers of rows or columns in the parent fundamental matrix used in quasi-cyclic LDPC encoding are also considered different fundamental matrices. The number of fundamental matrices can be selected from at least two of the following: 2, 3, 4, 5, and 6.

[0193] The aforementioned method (pattern) for determining the boost value refers to different ranges of boost values. The boost value pattern includes at least two of the following:

[0194] The first method for determining the boost value is to multiply a positive integer power of 2 by a positive integer, such as boost value Z = c × 2. dHere, c is an element from set C, and d is an element from set D. For example, if set C is {4,5,6,7} and set D is {0,1,2,3,4,5,6,7}, then the set of promotion values ​​is: {4,5,6,7,8,10,12,14,16,20,24,28,32,40,48,56,64,80,96,112,128,160,192,224,256,320,38}. 4,448,512,640,768,896}; Set C is {4,5,6,7}, Set D is {1,2,3,4,5,6,7}; Set C is {4,5,6,7}, Set D is {1,2,3,4,5,6,7}; Set C is {3,4,5,6,7,8}, Set D is {0,1,2,3,4,5,6};

[0195] The second method for selecting the promotion value is: a continuous value method, {1,2,3,4,5,…,Zmax} or {2,3,4,5,…,Zmax}, where Zmax is an integer greater than or equal to 128;

[0196] The third method for determining the enhancement value is a continuously increasing value with intervals, where the continuously increasing value is a positive integer power of 2, for example, {1:1:8,9:1:16,18:2:32,36:4:64,72:8:128,144:16:256,288:32:Zmax}, where Zmax is an integer greater than or equal to 128. The expression x0:g:x1 refers to starting from integer x0 and incrementing by positive integers g. Extract integers not greater than x1. If x0 is greater than x1, the expression is empty. Also, {2:1:8,10:2:16,20:4:32,40:8:64,80:16:128,160:32:256,320:64:Zmax}, where Zmax is an integer greater than or equal to 128. Also, {2:2:8,12:4:32,40:8:64,80:16:128,160:32:256}.

[0197] The fourth method for selecting the promotion value is a segmented selection method, which includes at least one of the following promotion value sets: {8,16,24}; {32,48,64,96}; {128,192,256}; {8,16,24}; {32,48,64,96}.

[0198] The lifting value is determined by the following method: The lifting value is calculated and finely adjusted based on the information bit sequence length and the number of columns in the basic matrix system. For example, it can be determined by the information bit sequence length K and the number of columns in the basic matrix system kb, where kb is the number of columns in the basic matrix of the quasi-cyclic LDPC encoding (equal to the total number of columns nb of the basic matrix minus the total number of rows mb). The lifting value can be obtained in one of the following ways: 1) The actual coding lift value is Z = Z orig +ΔZ, where the value of ΔZ depends on different Z orig Value obtained; 2) Actual coding boost value is

[0199] The promotion value is taken in pattern 6 as a positive integer power of 2, {2 4 8 16 32 64 128256 512}.

[0200] The promotion value can be selected using pattern 7 as follows: {256,192,144,108,81,61,46,35,27,21} or {256,156,96,64,40,25,16,10,6}.

[0201] The promotion value selection pattern 8 is: satisfying a×2 j Let a = {16, 20, 24, 28}, j = 0, 1, 2, ..., J. If a = 16, then J = 5; otherwise, J = 4. That is, the promotion value is the set {16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384, 448, 512}.

[0202] The granularity pattern of the lift value refers to the interval between any two adjacent lift values ​​of different sizes in the lift value set preset and stored in the quasi-cyclic LDPC encoding. The granularity pattern of the lift value can be selected from at least two of the following: 1) a method where the interval is a non-negative integer power of 2, such as a lift value set of {2:2:8,12:4:32,40:8:64,80:16:128,160:32:256}, i.e., the granularity pattern set of the lift value is {2,4,8,16,32}; 2) a method where the interval is a positive integer, such as a lift value set of {2:2:256}, i.e., the granularity pattern of the lift value is {2}; 3) a method where the interval is a second positive integer multiple of the first positive integer set, where the interval is... Let G0 be a set of positive integers, and G1 be a set of all the second positive integers. For example, if G0 is a set of non-negative powers of 2, and an example of G0 is {1,2,4}, then the set of granularity patterns for the promotion values ​​is {1,2,4,8,16}, and an example of the promotion value set is {1:1:16,18:2:32,36:4:64,72:8:128,144:16:256}. In another example, if G0 is {1,2,3} and G1 is {1,4}, then the set of granularity patterns for the promotion values ​​is {1,2,3,4,8,16}.

[0203] The maximum value of the boost can be selected from at least two of the following: 16, 32, 64, 128, 256, 384, 512, 768 and 1024.

[0204] The maximum number of systematic columns in the base matrix is ​​equal to the difference between the total number of columns and the total number of rows in the quasi-cyclic LDPC encoding base matrix, i.e., kb = nb - mb, where kb is the maximum number of systematic columns in the base matrix, nb is the total number of columns in the base matrix, and mb is the total number of rows in the base matrix. The maximum number of systematic columns kb in the base matrix can be selected from at least two of the following: 1) kb = 8; 2) kb = 10; 3) kb = 16; 4) kb = 24; 5) kb = 30; 6) kb = 32.

[0205] The maximum number of systematic columns in the quasi-cyclic LDPC encoding is equal to the maximum number of systematic columns in the base matrix actually used for quasi-cyclic LDPC encoding. For example, the maximum number of systematic columns in the original base matrix is ​​kb, while the number of systematic columns in the base matrix actually used for quasi-cyclic LDPC encoding is less than or equal to kb. That is, the base matrix actually used for quasi-cyclic LDPC encoding consists of some or all of the systematic columns and some or all of the parity columns of the original base matrix. The maximum number of systematic columns in the quasi-cyclic LDPC encoding is selected from at least two integer values ​​from 2 to 32; preferably, the maximum number of systematic columns in the quasi-cyclic LDPC encoding can be selected from at least two of the following: 1) 3; 2) 4; 3) 5; 4) 6; 5) 7; 6) 8.

[0206] The information bit length pattern supported by the quasi-cyclic LDPC encoding refers to the length of the information bit sequence that the quasi-cyclic LDPC encoding can support under certain padding dummy bits. The information bit length pattern supported by the quasi-cyclic LDPC encoding can be selected from at least two of the following: 1) with a fixed number of bits as the interval, such as the information bit length pattern being the set {TBS', TBS'+ΔTBS, TBS'+2×ΔTBS,…,TBSmax}, where TBS' equals 8, 16, 24, 32 or 40, TBSmax equals 2048, 4096, 6144 or 8192, and ΔTBS is a fixed positive integer; 2) with an interval of the set {8, 16, 32, 64}, such as the information bit length pattern being the set {{TBS0, TBS0+8, TBS0+2×8,…,TBSmax}. S0+L1×8},{TBS0+L1×8+16,TBS0+2×16,…,TBS0+L1×8+L2×16},{TBS0+L1×8+L2×16+32,TBS0+ L1×8+L2×16+2×32,…,TBS0+L1×8+L2×16+L3×32},{TBS0+L1×8+L2×16+L3×32+64,TBS0+L1×8+L 2×16+L3×32+2×64,…,TBS0+L1×8+L2×16+L3×32+L4×64}}, where TBS0 equals 8, 16, 24, 32 or 40; 3. equal to a positive integer power of 2, wherein the information bit length pattern is the set {2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384}.

[0207] The number of basic matrices refers to the number of basic matrices required in the quasi-cyclic LDPC encoding process. The number of basic matrices can be selected from at least two of the following: 1) 1 basic matrix; 2) 2 basic matrices; 3) 3 basic matrices; 4) 4 basic matrices.

[0208] The maximum information length supported by the quasi-cyclic LDPC encoding refers to the maximum information bit sequence length supported by the quasi-cyclic LDPC encoding base matrix. It is generally equal to the integer value obtained by multiplying the maximum number of systematic columns of the quasi-cyclic LDPC encoding base matrix by the maximum lift value. The maximum information length supported by the quasi-cyclic LDPC encoding can be selected from at least two of the following: Maximum information bit sequence length 1: Kmax = 1024; Maximum information bit sequence length 2: Kmax = 2048; Maximum information bit sequence length 3: Kmax = 4096; Maximum information bit sequence length 4: Kmax = 6144; Maximum information bit sequence length 5: Kmax = 8192; Maximum information bit sequence length 6: Kmax = 512; Maximum information bit sequence length 7: Kmax = 12288; Maximum information bit sequence length 8: Kmax = 768.

[0209] The minimum code rate of the base matrix under the maximum information bit sequence length refers to the minimum code rate supported by the quasi-cyclic LDPC coding base matrix under the maximum information bit sequence length. The minimum code rate of the base matrix under the maximum information bit sequence length can be selected from at least two of the following: minimum code rate 1: 1 / 12; minimum code rate 2: 1 / 8; minimum code rate 3: 1 / 6; minimum code rate 4: 1 / 5; minimum code rate 5: 1 / 4; minimum code rate 6: 1 / 3; minimum code rate 7: 1 / 2; minimum code rate 8: 2 / 3.

[0210] The system column non-transmission pattern of the rate-matched output sequence refers to the number of system columns corresponding to the non-transmission of system bits during the rate-matching process of quasi-cyclic LDPC encoding. The system column non-transmission pattern can be selected from at least two of the following: system column non-transmission pattern 1: 0; system column non-transmission pattern 2: 1; system column non-transmission pattern 3: 2; system column non-transmission pattern 4: 3.

[0211] The shortened coding pattern of the quasi-cyclic LDPC encoding refers to the maximum number of systematic columns occupied by the dummy bits filled during the quasi-cyclic LDPC encoding process. The shortened coding pattern can be selected from at least two of the following: shortened coding pattern 1:0; shortened coding pattern 2:1; shortened coding pattern 3:2; shortened coding pattern 4:3; shortened coding pattern 5:4; shortened coding pattern 6:5; shortened coding pattern 7:6; shortened coding pattern 8:8; shortened coding pattern 9:12; shortened coding pattern 9:16. During shortened coding, the quasi-cyclic LDPC encoding can achieve a lower code rate. For example, if the basic matrix size is mb rows and nb columns, the number of systematic columns is kb = nb – mb, and the code rate is R = kb / nb, if shortened coding is performed by Δkb columns, the code rate becomes R' = (kb - Δkb) / (nb - Δkb), thus achieving a lower code rate.

[0212] The parity column puncturing pattern of the rate-matched output sequence refers to the rearrangement of the parity bits generated by the core matrix during the rate-matching process of quasi-cyclic LDPC encoding, using Z (encoding boost value) bits as the unit. The rearranged index sequence is the parity column puncturing pattern. The parity column puncturing pattern can be selected from at least two of the following: Parity column puncturing pattern 1: a set consisting of even numbers from 0 to mb'-1 first and odd numbers from 0 to mb'-1 last; Parity column puncturing pattern 2: a set consisting of odd numbers from 0 to mb'-1 first and even numbers from 0 to mb'-1 last; Parity column puncturing pattern 3: [0,1,2,…,mb'-1]; Parity column puncturing pattern 4: [mb'-1,mb'-2,…2,1,0]; where mb' is the number of parity columns in the core matrix, and mb' is an integer greater than or equal to 3.

[0213] The information bit length granularity pattern supported by the quasi-cyclic LDPC encoding refers to the interval between any two adjacent information transmission block sizes determined by the system. The information bit sequence length granularity pattern can be selected from at least two of the following: Information bit sequence length granularity pattern 1: 2 bits; Information bit sequence length granularity pattern 2: 4 bits; Information bit sequence length granularity pattern 3: 8 bits; Information bit sequence length granularity pattern 4: 16 bits; Information bit sequence length granularity pattern 5: 32 bits; Information bit sequence length granularity pattern 6: 64 bits; Information bit sequence length granularity pattern 7: 128 bits; Information bit sequence length granularity pattern 8: 256 bits. The set of information bit lengths supported by all of the quasi-cyclic LDPC encodings can be described by a formula or a data table.

[0214] The number of edges of the base matrix refers to the maximum number of shift values ​​for all element positions in the base matrix of the quasi-cyclic LDPC encoding. The number of edges of the base matrix can be selected from at least two of the following: base matrix edge number 1: 1 edge; base matrix edge number 2: 2 edges; base matrix edge number 3: 3 edges.

[0215] The HARQ merging method of quasi-cyclic LDPC encoding refers to the data merging method adopted by quasi-cyclic LDPC encoding when retransmitted data occurs. The HARQ merging method can be selected from at least two of the following: HARQ merging method 1: Chase Combine (CC); HARQ merging method 2: Incremental Redundancy (IR); HARQ merging method 3: Hybrid Chase Combine and Incremental Redundancy Combine.

[0216] The bit selection start bit position of the rate-matched output sequence refers to the starting bit position for bit selection during retransmission of data in quasi-cyclic LDPC encoding. The bit selection start bit position of the rate-matched output sequence can be selected from at least two of the following: Bit selection start bit position 1: is the next cycle bit position after the last bit of the previous transmitted data; Bit selection start bit position 2: is related to the quasi-cyclic LDPC encoding mother code length L, the maximum HARQ transmission count TXmax, the number of system queues not transmitted P, and the boost value Z. For example, the bit selection start bit position of the rate-matched output sequence for the RV-th transmission is... The starting bit position 3 of the bit selection for the rate-matched output sequence is related to the quasi-cyclic LDPC encoding mother code length L, the number of HARQ transmission versions RVnum, the number of system column non-transmissions P, and the boost value Z. For example, the starting bit position of the bit selection for the rate-matched output sequence in the RVth transmission is...

[0217] The maximum number of HARQ transmissions for quasi-cyclic LDPC encoding refers to the maximum number of transmissions (including initial transmission and retransmission) that occur during data transmission if a transmission error occurs. The maximum number of HARQ transmissions can be selected from at least two of the following: HARQ maximum transmission mode 1: 2 times; HARQ maximum transmission mode 2: 3 times; HARQ maximum transmission mode 3: 4 times; HARQ maximum transmission mode 4: 5 times; HARQ maximum transmission mode 5: 1 time.

[0218] The number of HARQ transmission versions in the quasi-cyclic LDPC encoding refers to the number of transmission versions provided by the quasi-cyclic LDPC encoding in case of data transmission errors. Each transmission version number corresponds to a bit selection start position for transmitted data. The number of transmission versions is an integer greater than or equal to the maximum number of HARQ transmissions of the quasi-cyclic LDPC encoding. When a data transmission error requires retransmission, a transmission version number and the corresponding bit selection start position for transmitted data are selected from the multiple transmission versions for rate matching and transmission. The number of HARQ transmission versions can be selected from at least two of the following: HARQ transmission version number 1:2; HARQ transmission version number 2:4; HARQ transmission version number 3:6; HARQ transmission version number 4:8; HARQ transmission version number 5:12; HARQ transmission version number 6:16; HARQ transmission version number 7:24; HARQ transmission version number 8:32; HARQ transmission version number 9:48; HARQ transmission version number 10:64.

[0219] The interleaving pattern of the rate-matched output sequence refers to the interleaving operation performed on the rate-matched output sequence obtained after rate matching following quasi-cyclic LDPC coding. The interleaving pattern can be selected from at least two of the following: 1. Bit rearrangement, which involves dispersing the parity bits and system bits of the rate-matched output sequence among each other, dispersing the parity bits among the system bits, such as using a row-and-column block interleaving method. The depth of the block interleaving method is related to at least one of the following parameters: boost value Z, total number of columns in the basic matrix, number of system columns kb, number of rows in the basic matrix mb, information length K, code rate R, and code length; 2. In the constellation modulation process of retransmitted data, bit rearrangement is performed on the overlapping part of the retransmitted data and the previous transmitted data, so that the low reliability bits of the overlapping data in the previous transmission constellation modulation symbol are in the high reliability bits of the constellation modulation symbol in the current retransmission, in order to compensate for the soft information amplitude fluctuations caused by high-order constellation modulation; 3. Cyclic interleaving, which involves cyclically interleaving the rate-matched output sequence with W×Z bits, where Z is the boost value used by the quasi-cyclic LDPC coding, and W is an integer greater than 0.

[0220] Example 2

[0221] Embodiment 2 of the present invention provides a quasi-cyclic LDPC encoding processing method, comprising:

[0222] Step S310: Based on the maximum information length supported by the quasi-cyclic LDPC coding, the pre-encoding transport block is segmented into code blocks to obtain multiple information bit sequences, the length of which is not greater than the maximum information length shown.

[0223] Step S320: According to the information bit length pattern supported by the quasi-cyclic LDPC encoding, padding bits are added to the end of the plurality of information bit sequences, so that the length of the plurality of information bit sequences reaches the length in the information bit length pattern supported by the quasi-cyclic LDPC encoding, and the added padding bits are minimized.

[0224] Step S330: Based on the length of the added information bit sequence, select the lifting value used by the quasi-cyclic LDPC encoding from the lifting value value pattern, and obtain the basic matrix used by the quasi-cyclic LDPC encoding; modify the elements in the basic matrix according to the lifting value to obtain the modified basic matrix;

[0225] Step S340: Based on the boost value and the corrected fundamental matrix, perform quasi-cyclic LDPC encoding on the added information bit sequence to obtain the LDPC encoded output sequence;

[0226] Step S350: Rate-matched interleaving is performed on the LDPC encoded output sequence to obtain an interleaved output sequence. Bit selection is performed on the interleaved output sequence according to the bit selection start bit position determined by the transmission version number to obtain a rate-matched output sequence. The purpose of rate-matched interleaving is to ensure that the bit selection order is continuous.

[0227] Step S360: Select an interleaving method according to the interleaving pattern of the rate matching output sequence, and interleave the rate matching output sequence to obtain the interleaved bit sequence;

[0228] Step S370: Perform constellation symbol modulation on the interleaved bit sequence to obtain a constellation modulated symbol sequence, and send the constellation modulated symbol sequence.

[0229] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the release version of the information bit sequence.

[0230] The release version examples mentioned include different release version numbers in the 3GPP standard protocol, such as release12, release13, release14, release15, release16, release17, release18, release19, etc., and will also apply when more version numbers exist in the future.

[0231] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the operating mode of the information bit sequence.

[0232] The working modes mentioned above include at least: in-band working mode, out-of-band working mode, independent working mode and hybrid working mode, and the definitions of other working modes also apply.

[0233] In one implementation, the processing strategy for quasi-cyclic LDPC coding can be determined based on the user equipment category of the information bit sequence.

[0234] The user equipment types mentioned above include at least the various user equipment types defined in the LTE system, which are divided into multiple user types according to different peak transmission rates, and other user equipment types are also applicable.

[0235] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the coverage area.

[0236] The coverage range includes at least: large coverage range, small coverage range, etc. The large coverage range can be a scenario where the signal is easy to transmit, such as outdoors, and the small coverage range can be a scenario such as indoors. Other coverage range definitions also apply.

[0237] In one implementation, a quasi-cyclic LDPC encoding processing strategy can be determined based on the bit rate of the output sequence matched with the rate.

[0238] The bitrate mentioned here includes at least: the existence of G bitrate thresholds, and the selection of bitrates among the G bitrate thresholds. For example, if G equals 1, that is, there is G = 1 bitrate threshold R0, then the bitrate is divided into bitrates less than or equal to R0 and bitrates greater than R0; if G equals 2, that is, there are G = 2 bitrate thresholds R0 and R1 (R0 is less than R1), then the bitrate is divided into bitrates less than or equal to R0, bitrates greater than R0 and less than or equal to R1, and bitrates greater than R1; other bitrate range definitions also apply in the same way.

[0239] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the length of the information bit sequence (information length).

[0240] The length of the information bit sequence includes at least the following: there are G1 information length thresholds, and the selection of an information length set between these G1 information length thresholds. For example, if G1 equals 1, that is, there is G1 = 1 information length threshold K0, then the information length is divided into a set of information lengths less than or equal to K0 and a set of information lengths greater than K0; if G1 equals 2, that is, there are G1 = 2 information length thresholds K0 and K1 (K0 is less than K1), then the information length is divided into a set of information lengths less than or equal to K0, a set of information lengths greater than K0 and less than or equal to K1, and a set of information lengths greater than K1; other information length range definitions also apply.

[0241] In one implementation, the processing strategy for quasi-cyclic LDPC coding can be determined based on a combination of the bitrate of the rate-matched output sequence and the length (code length) of the rate-matched output sequence.

[0242] The bitrate includes at least the following: there are G bitrate thresholds, and the bitrate selection is performed among the G bitrate thresholds. For example, if G equals 1, that is, there is G = 1 bitrate threshold R0, then the bitrate is divided into bitrates less than or equal to R0 and bitrates greater than R0; if G equals 2, that is, there are G = 2 bitrate thresholds R0 and R1 (R0 is less than R1), then the bitrate is divided into bitrates less than or equal to R0, bitrates greater than R0 and less than or equal to R1, and bitrates greater than R1; other bitrate range definitions also apply.

[0243] The code length includes at least the following: there are G1 length thresholds, and the selection of a set of lengths between the G1 length thresholds. For example, if G1 equals 1, that is, there is G1 = 1 length threshold K0, then the code length is divided into a set of lengths less than or equal to K0 and a set of lengths greater than K0; if G1 equals 2, that is, there are G1 = 2 length thresholds K0 and K1 (K0 is less than K1), then the code length is divided into a set of lengths less than or equal to K0, a set of lengths greater than K0 and less than or equal to K1, and a set of lengths greater than K1; other code length range definitions also apply.

[0244] In one implementation, a quasi-cyclic LDPC encoding processing strategy can be determined based on a combination of the bit rate of the rate-matched output sequence and the length of the information bit sequence (information length).

[0245] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the control information format of the information bit sequence.

[0246] The control information format is determined by the system and includes downlink control information (DCI) format, such as coding and modulation scheme (MCS), HARQ retransmission, resource scheduling information, and other control information.

[0247] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the Cyclic Redundancy Check (CRC) format of the information bit sequence.

[0248] The CRC scrambling format is determined by the system and is used to scramble downlink data or control information to improve system robustness, such as by carrying some control information.

[0249] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the search space corresponding to the information bit sequence.

[0250] The search space refers to the Common Search Space and UE-Specific Search Space defined by the LTE system, and may also include other search space definitions.

[0251] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the CSI (Channel State Information) process corresponding to the information bit sequence.

[0252] The CSI process refers to the channel state information defined by the LTE system, and may also include other channel state information definitions, such as those in 5G or NR systems.

[0253] In one implementation, the processing strategy for quasi-cyclic LDPC coding can be determined based on the subframe set index number of the information bit sequence.

[0254] The subframe set index number refers to the following: In a radio frame data segmented into multiple subframes (e.g., 10 subframes in an LTE system, each subframe comprising 2 time slots), each subframe is assigned a subframe index number, which is the subframe set index. Furthermore, the subframe set index number may also include definitions from other systems, such as those in 5G or NR systems.

[0255] In one implementation, the processing strategy for quasi-cyclic LDPC coding can be determined based on the modulation and coding scheme (MCS) level of the information bit sequence.

[0256] The modulation and coding scheme (MCS) level of the information bit sequence is a level index number used by the communication system to indicate the modulation order and code rate, such as 16 levels, 32 levels, or 64 levels. The MCS level may also include MCS level definitions defined by other systems, such as those in 5G or NR systems.

[0257] In one implementation, the processing strategy for quasi-cyclic LDPC coding can be determined based on at least one of the following: the link direction of the information bit sequence, the aggregation level of the control channel unit (CCE) of the information bit sequence, the scrambling method of the information bit sequence; the channel type of the information bit sequence, the carrier frequency of the information bit sequence, and the HARQ data transmission version number of the information bit sequence.

[0258] The link direction of the information bit sequence includes uplink data or downlink data; uplink data is data transmitted from the user equipment to the base station, and downlink data is data transmitted from the base station to the user equipment.

[0259] The aggregation level of the control channel element (CCE) of the information bit sequence refers to the number of resource elements allocated to control signaling, such as {1,2,4,8} in the LTE system. The corresponding definitions in other communication systems, such as the 5G system or the NR system, are also applicable.

[0260] The scrambling method of the information bit sequence refers to scrambling the information bit sequence to disrupt or randomize it. There are many scrambling methods, such as performing an XOR operation with a random sequence of equal length. The random sequence can take many forms.

[0261] The channel type of the information bit sequence may include: data channel, control channel, broadcast channel, etc.; or, more specifically, may include: physical downlink shared channel (PDSCH, used to carry downlink user information and higher-layer signaling), physical broadcast channel (PBCH, used to carry master system information block information, transmitted for initial access), physical multicast channel (PMCH, used to carry multimedia / multicast information), physical control format indication channel (PCFICH, used to carry information on the size of the control area on the subframe), physical downlink control channel (PDCCH, used to carry downlink control information, such as uplink scheduling instructions, downlink data transmission instructions, common control information, etc.), and physical HARO indication channel (PHICH, used to carry ACK / NACK feedback information for the terminal's uplink data).

[0262] The carrier frequency of the information bit sequence refers to the center frequency within the frequency bandwidth carrying the information bit sequence. Generally speaking, a higher carrier frequency allows for a larger bandwidth, while a lower carrier frequency allows for a smaller bandwidth.

[0263] The HARQ data transmission version number of the information bit sequence is the HARQ version number of the current data transmission obtained from the control information.

[0264] In one implementation, the processing strategy for quasi-cyclic LDPC encoding can be determined based on the application scenario of the information bit sequence.

[0265] The application scenarios include: eMBB (enhanced Mobile Broadband), URLLC (Ultra-Reliable and Low Latency Communications), and mMTC (massive Machine Type Communications). The definitions of other application scenarios also apply.

[0266] In one embodiment, the quasi-cyclic LDPC encoding includes Y basic matrices. Based on the data characteristics of the representation information bit sequence, one basic matrix is ​​selected from the Y basic matrices for quasi-cyclic LDPC encoding to obtain an LDPC encoded sequence, where Y is an integer greater than 1.

[0267] The Y fundamental matrices must include at least one of the following properties:

[0268] 1) Among the Y basic matrices, at least two basic matrices share the same template matrix. The shared template matrix means that the two basic matrices are M1 and M2, the template matrix of M1 is equal to the template matrix of M2, and at least one non--1 element in each of the two basic matrices has a different value. The template matrix is ​​obtained by assigning "1" to the non--1 elements and "0" to the -1 elements in the basic matrices. The beneficial effect of this shared template matrix characteristic is that the basic matrices have a nested structure, making the quasi-cyclic LDPC decoder structure more unified, unifying the soft information storage and retrieval routes, and making the decoder more compact and simple.

[0269] 2) Among the Y basic matrices, there are at least two basic matrices with quasi-identical template matrices. Quasi-identical template matrices mean that the two template matrices have a different number of elements, where a is an integer greater than 0 and less than or equal to 10. For example, the two basic matrices are M3 and M4, where the number of rows in M3 is equal to the number of rows in M4, the number of columns in M3 is equal to the number of columns in M4, the set of row and column index pairs corresponding to all non--1 elements in M3 is SET3, and the set of row and column index pairs corresponding to all non--1 elements in M4 is SET4. The difference between the set SET3 and the set SET4 is DS3, where the number of elements in DS3 is less than or equal to TH3, and the difference between the set SET4 and the set SET3 is DS4, where the number of elements in DS4 is less than or equal to TH4. Where TH3 and TH4 are positive integers less than 10.

[0270] In such Figure 9 In the example of the fundamental matrix shown, the fundamental matrix (a) (as shown) Figure 9 (a) The set SET3, consisting of the row and column index pairs corresponding to all non--1 elements, is {[0,0],[2,0],[0,1],[1,1],[2,1],[0,2],[1,2],[2,2],[0,3],[1,3],[2,3],[0,4],[1,4],[1,5],[2,5],[2,6]}. The fundamental matrix (b) (as shown in the figure) Figure 9The set SET4, which consists of the row and column index pairs corresponding to all non--1 elements shown in (b), is {[0,0],[1,0],[2,0],[0,1],[1,1],[0,2],[2,2],[0,3],[1,3],[2,3],[0,4],[1,4],[1,5],[2,5],[2,6]}. It can be found that the difference set DS3 between the set SET3 and the set SET4 is {[2,1],[1,2]}, and the difference set DS4 between the set SET4 and the set SET3 is {[1,0]}. That is, the template matrix of the basic matrix (a) and the template matrix of the basic matrix (b) have 3 different elements, which can be considered as the two basic matrices being quasi-identical template matrices.

[0271] The beneficial effects of the quasi-identical characteristics of the template matrix are: it not only makes the structure of the quasi-cyclic LDPC decoder more unified, the soft information storage and reading routes unified, and the decoder more compact and simple; but also allows each basic matrix to have some special characteristics, so that the performance of quasi-cyclic LDPC encoding can be good with almost no change or very small change to the decoder structure.

[0272] 3) Among the Y basic matrices, at least two basic matrices have quasi-identical matrix elements. Quasi-identical matrix elements mean that the two basic matrices have b different elements, where b is an integer greater than 0 and less than or equal to 10. For example, the two basic matrices are M5 and M6, with at most TH5 row and column index pairs. The element indexed by the row and column index pairs in M5 is not equal to the element indexed by the same row and column index pairs in M6. The template matrix is ​​obtained by assigning "1" to the non--1 element positions and "0" to the -1 element positions in the basic matrices, where TH5 is a positive integer less than 10. The beneficial effect of this quasi-identical matrix element feature is that it allows the interleaving network in the quasi-cyclic LDPC decoder to remain highly uniform. Although some elements differ, the impact on the increased complexity is minimal, making the decoder simple and easy to design. Figure 10 (a) and Figure 10 In the example of the basic matrix shown in (b), TH5 = 2, where TH5 = 2 row and column index pairs [1,0] and [0,1]. Of course, the template matrix can also have the property that the two basic matrices have quasi-identical matrix elements in different cases.

[0273] 4) Among the Y basic matrices, at least two basic matrices contain nested template matrices. This nesting refers to the situation where, in the two nested basic matrices, the template matrix of the smaller basic matrix is ​​a submatrix of the template matrix of the larger basic matrix. For example, if the two basic matrices are M7 and M8, the number of rows in M7 is less than the number of rows in M8, the number of columns in M7 is less than the number of columns in M8, and the template matrix of M7 is a submatrix of the template matrix of M8. The template matrix is ​​obtained by assigning "1" to the non--1 elements and "0" to the -1 elements in the basic matrix. The beneficial effect of this template matrix subset equality feature is that, with different basic matrix sizes, the smaller basic matrix is ​​a subset of the larger basic matrix, i.e., the smaller basic matrix is ​​nested within the larger basic matrix. This allows for compatibility of the quasi-cyclic LDPC code decoder, enabling decoding of different basic matrix sizes using the same decoder, simplifying the decoding design. Figure 11 As shown, the fundamental matrix (a) (as shown) Figure 11 (a) is shown as the fundamental matrix (b) (as shown in the image) Figure 11 (b) is a submatrix.

[0274] 5) Among the Y fundamental matrices, there exist at least two fundamental matrices with equal subsets of template matrices. Equal subsets of template matrices mean that the template matrix of fundamental matrix 1 contains a submatrix equal to a submatrix in the template matrix of fundamental matrix 2. For example, if the two fundamental matrices are M9 and M10, the number of rows in M9 is less than the number of rows in M10, and the number of columns in M9 is less than the number of columns in M10. Both fundamental matrices M9 and M10 have the following structure:

[0275]

[0276] In this matrix, submatrix A and submatrix B constitute the core matrix of the base matrix. Submatrix C, submatrix D1, submatrix D2, and submatrix E are all extensions of the core matrix and support lower bit rates. Equal subsets of the template matrix include one of the following characteristics: 1) The core matrix of the M9 template matrix is ​​a submatrix of the core matrix of the M10 template matrix; 2) Submatrix D1 of the M9 template matrix is ​​a submatrix of submatrix D1 of the M10 template matrix; 3) Submatrix D2 of the M9 template matrix is ​​a submatrix of submatrix D2 of the M10 template matrix. The template matrix is ​​obtained by assigning "1" to the non--1 elements and "0" to the -1 elements in the base matrix. The beneficial effects of the equal subsets of the template matrix are: the base matrix design is more convenient, optimization is performed on a unified template, the decoder design is unified, and the required routing network is consistent.

[0277] 6) Among the Y basic matrices, there exist at least two basic matrices with equal subsets of basic matrices. That is, equal subsets of basic matrices mean that there is a submatrix in basic matrix 1 that is equal to a submatrix in basic matrix 2. For example, the two basic matrices have the matrix structure described above (including submatrix A, submatrix B, submatrix C, submatrix D1, submatrix D2, and submatrix E). Equal subsets of basic matrices mean that the two basic matrices are M11 and M12, the number of rows in M11 is less than the number of rows in M12, and the number of columns in M11 is less than the number of columns in M12. Equal subsets of basic matrices include one of the following characteristics: 1) The core matrix of M11 is a submatrix of the core matrix of M12; 2) Submatrix D1 of M11 is a submatrix of submatrix D1 of M12; 3) Submatrix D2 of M11 is a submatrix of submatrix D2 of M12. The beneficial effect of the equality feature of the basic matrix subset is that the equality of some submatrices in the basic matrix not only unifies the decoder routing network and shift network, but also makes the characteristics of the basic matrix elements basically consistent, which is conducive to ensuring that the performance of quasi-cyclic LDPC coding is maintained well. The submatrix D1 can correspond to the submatrix composed of the system columns that are not transmitted during the rate matching process;

[0278] In one implementation, at least a predetermined proportion of the non--1 elements in the base matrix are in the same positions as the '1' elements in the reference template matrix, wherein the reference template matrix is ​​a submatrix of the following template matrix:

[0279]

[0280] In the template matrix, an element equal to '1' indicates that the element at the corresponding position in the base matrix is ​​a non--1 value, and an element equal to '0' indicates that the element at the corresponding position in the base matrix is ​​a -1 value. Preferably, the preset ratio is a real number greater than 60% and less than or equal to 100%.

[0281] Preferably, the fundamental matrix is ​​as follows: Figure 12 The example of the basic matrix shown has a preset ratio of 100%.

[0282] Example 3

[0283] like Figure 13 As shown, Embodiment 3 of the present invention also provides a quasi-cyclic LDPC encoding processing apparatus, comprising:

[0284] The processing module 1301 is used to determine a quasi-cyclic low-density parity-check LDPC encoding processing strategy based on the data characteristics of the information bit sequence to be encoded; and, based on the processing strategy, to perform quasi-cyclic LDPC encoding and rate matching output on the information bit sequence based on the fundamental matrix and the boost value.

[0285] Storage module 1302 is used to store the basic matrix and the boost value.

[0286] In one implementation, the data features include at least one of the following:

[0287] The information bit sequence includes the operating mode, application scenario, link direction, user equipment type, length, modulation and coding scheme (MCS) level, control channel element (CCE) aggregation level, search space, scrambling method, cyclic redundancy check (CRC) format, channel type, control information format, channel state information (CSI) process, subframe index, carrier frequency, release version, coverage area, length of rate-matched output sequence obtained by quasi-cyclic LDPC coding and bit selection, code rate, combination of code rate and length, combination of code rate and length, and Hybrid Automatic Repeat Request (HARQ) data transmission version number.

[0288] In one implementation, the processing module is configured to determine the processing strategy for quasi-cyclic low-density parity-check (LDPC) coding in the following manner:

[0289] Determine at least one of the following:

[0290] The core matrix parity block structure of the fundamental matrix; the orthogonality of the fundamental matrix; the characteristics of the fundamental matrix; the maximum number of systematic columns of the fundamental matrix; the maximum number of systematic columns of the quasi-cyclic LDPC encoding; the number of fundamental matrices; the element correction method of the fundamental matrix; the number of edges of the fundamental matrix; the minimum code rate of the fundamental matrix under the maximum information bit sequence length; the minimum code rate of the fundamental matrix under shortened encoding; the method for determining the boost value; the method for determining the granularity of the boost value; the maximum value of the boost value; the number of systematic columns in the rate-matched output sequence obtained by performing quasi-cyclic LDPC encoding and bit selection on the information bit sequence; the rate-matched output sequence... The following methods are described: parity column puncturing method; interleaving method of the rate-matched output sequence; starting bit position of bit selection in the rate-matched output sequence; maximum information length supported by the quasi-cyclic LDPC encoding; method for determining the information bit length supported by the quasi-cyclic LDPC encoding; method for determining the granularity of the information bit length supported by the quasi-cyclic LDPC encoding; maximum number of shortened codes in the quasi-cyclic LDPC encoding; hybrid automatic repeat request (HARQ) merging method in the quasi-cyclic LDPC encoding; starting bit position of bit selection in the rate-matched output sequence; maximum number of HARQ transmissions in the quasi-cyclic LDPC encoding; and number of HARQ transmission versions in the quasi-cyclic LDPC encoding.

[0291] In one implementation, the operating modes include: in-band operating mode, out-of-band operating mode, and stand-alone operating mode;

[0292] The application scenarios include: enhanced mobile broadband (eMBB) scenario, ultra-reliable low-latency communication (URLLC) scenario, and massive machine-type communication (mMTC) scenario.

[0293] The link directions include: uplink data direction and downlink data direction.

[0294] In one embodiment, the length information of the information bit sequence includes: length information greater than a positive integer value K0 and length information less than or equal to a positive integer value K0, wherein K0 is an integer greater than 128.

[0295] In one implementation, the fundamental matrix Hb is:

[0296] Among them, the matrix [AB] formed by submatrix A and submatrix B is the core matrix of the basic matrix, and submatrix B is the core matrix verification block;

[0297] The core matrix verification block structure is selected from at least two of the following structure types: lower triangular structure, double diagonal structure, and quasi-double diagonal structure;

[0298] The lower triangular matrix has the following three characteristics: a) the elements with row index i and column index j are both equal to -1 and j > i; b) all elements on the diagonal of the matrix are non--1 elements; c) at least one non--1 element exists among all elements below the diagonal of the matrix.

[0299] The double-diagonal matrix has the following two features a)-b): a) The first column of the matrix contains three non--1 elements, where the first and last elements of the first column are both non--1 elements; b) The elements with column index i and row index (i-1) and the elements with column index i and row index i are all non--1 elements, i = 1, 2, ..., (I0-1), where I0 is the row number of the matrix;

[0300] The quasi-double-diagonal matrix includes any of the following characteristics: a) the elements indicated by row index (mb0-1) and column index 0 are non--1 elements, and the submatrix formed by the upper right (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; b) the elements indicated by row index (mb0-1) and column index (mb0-1) of the matrix are non--1 elements, and the submatrix formed by the upper left (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; c) the elements indicated by row index 0 and column index 0 of the matrix are non--1 elements, and the submatrix formed by the lower right (mb0-1) row and (mb0-1) column of the matrix is ​​double-diagonal; wherein mb0 is the row number of the matrix.

[0301] In one implementation, the fundamental matrix Hb is:

[0302] Wherein, the number of columns of submatrix D is less than or equal to the number of columns of the core matrix [AB] formed by submatrix A and submatrix B, and the orthogonality of the base matrix is ​​the orthogonality property of the submatrix D. The orthogonality of the base matrix is ​​selected from at least two of the following types: orthogonality property, quasi-orthogonality property, and non-orthogonality property.

[0303] The orthogonality property includes: no intersection between the row index sets RowSETi (i = 0, 1, ..., (I-1)); the union of all the row index sets RowSETi (i = 0, 1, ..., (I-1)) constitutes all the row indexes of the submatrix D; in the submatrix D, the submatrix Di formed by all the rows indicated by the row index sets RowSETi has at most one non--1 element among all the elements indicated by any column index; wherein I is a positive integer less than the number of rows of the submatrix D; and the RowSETi (i = 0, 1, ..., (I-1)) includes at least two elements.

[0304] The quasi-orthogonality property includes: two column index sets ColSET0 and ColSET1, ColSET0 and ColSET1 having no intersection and the union of ColSET0 and ColSET1 forming all column indexes of the submatrix D, the submatrix D0 formed by all columns indicated by the column index set ColSET0 in the submatrix D, and the submatrix D1 formed by all columns indicated by the column index set ColSET1 in the submatrix D, wherein D1 has the orthogonality property, while D0 does not have the orthogonality property;

[0305] The non-orthogonal property includes: the submatrix D does not have the orthogonal and quasi-orthogonal properties as described above.

[0306] In one implementation, the maximum number of systematic columns of the base matrix is ​​selected from at least two integer values ​​from 2 to 32.

[0307] In one implementation, the maximum number of systematic columns of the basic matrix is ​​selected from at least two of the following integer values: 4, 6, 8, 10, 16, 24, 30, 32.

[0308] In one implementation, the number of the basic matrices is selected from at least two of the following integer values: 1, 2, 3, 4.

[0309] In one implementation, the method for modifying the elements of the fundamental matrix is ​​selected from at least two of the following methods:

[0310] Method 1: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0311]

[0312] Method 2: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0313]

[0314] Method 3: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0315]

[0316] Method 4: Obtain the elements P of the fundamental matrix as follows. i,j :

[0317] Each non--1 element position in the base matrix has an L-bit sequence. All lift values ​​form H sets of lift values. If Z belongs to the k-th set of lift values, then the element value of the non--1 position in the base matrix corresponding to the k-th set of lift values ​​is: select the leftmost k bits, the 2k-1 bits, and the 2k-1 bits from the L-bit sequence corresponding to the non--1 element position to form a (k+2)-bit sequence. The value corresponding to the (k+2)-bit sequence is the element value of the corresponding non--1 element position in the base matrix of the corresponding lift value Z.

[0318] Method 5: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0319]

[0320] Method 6: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0321]

[0322] Method 7: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0323]

[0324] Method 8: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0325]

[0326] Method 9: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0327]

[0328] Method 10: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0329] P i,j =V i,j mod z prime

[0330] Method 11: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0331]

[0332] Method 12: Calculate the elements P of the fundamental matrix using the following formula. i,j :

[0333]

[0334] Among them, V i,j It corresponds to Z max The value of the element in the i-th row and j-th column of the fundamental matrix, P i,j Z is the value of the element in the i-th row and j-th column of the fundamental matrix Z, where Z is the lift value of the quasi-cyclic LDPC encoding. max Z is an integer greater than 0, and Z is less than or equal to Z. max Positive integers;

[0335] The t mentioned is:

[0336] The s mentioned is such that 2 s The largest integer whose ≤ Z is true;

[0337] The w is a definite integer value corresponding to the boost value Z; the z prime It is the largest prime number that is less than or equal to the lift value Z.

[0338] In one implementation, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least two real values ​​that are greater than 0 and less than 1.

[0339] In one implementation, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least two of the following code rate types: 1 / 12, 1 / 8, 1 / 6, 1 / 5, 1 / 4, 1 / 3, 1 / 2, and 2 / 3.

[0340] In one implementation, the minimum code rate of the base matrix under shortened coding is selected from at least two real values ​​that are greater than 0 and less than 1.

[0341] In one implementation, the minimum bitrate of the base matrix under shortened coding is selected from at least two bitrate types: 1 / 12, 1 / 8, 1 / 6, 1 / 5, 1 / 4, and 1 / 3.

[0342] In one implementation, the method for determining the boost value is selected from at least two of the following methods:

[0343] Method 1:

[0344] The promotion value is the product of 2 raised to the power of d and a positive integer c; where c is an element of the set of positive integers C and d is an element of the set of non-negative integers D.

[0345] Method 2:

[0346] The boost value is a consecutive integer taken from Zmin to Zmax;

[0347] Where Zmin and Zmax are integers greater than 0, and Zmax is greater than Zmin;

[0348] Method 3:

[0349] The difference between adjacent boost values ​​is equal to an integer power of 2;

[0350] All the lift values ​​form a set Zset, which includes multiple subsets. The difference between any two adjacent lift values ​​of any size within a subset is equal to a non-negative integer power of 2.

[0351] Method 4:

[0352] The boost value is determined by the length of the information bit sequence and the number of columns in the basic matrix system;

[0353] Method 5:

[0354] The boost value is determined by the length of the information bit sequence, the number of columns in the basic matrix system, and the set of integers W;

[0355] Method 6:

[0356] The boost value is equal to a positive integer power of 2.

[0357] In one embodiment, in method 1, the set C and set D are one of the following set pairs: C = {4, 5, 6, 7} and D = {1, 2, 3, 4, 5, 6, 7}; C = {4, 5, 6, 7} and D = {0, 1, 2, 3, 4, 5, 6, 7}; C = {3, 4, 5, 6, 7, 8} and D = {0, 1, 2, 3, 4, 5, 6}; C = {4, 5, 6, 7} and D = {0, 1, 2, 3, 4, 5, 6}. C = {16,20,24,28} and D = {0,1,2,3,4,5}; C = {16,20,24,28} and D = {0,1,2,3,4}; C = {1,2,3,4,5,6,7} and D = {1,2,3,4,5,6,7}; C = {1,2,3,4,5,6,7} and D = {0,1,2,3,4,5,6,7};

[0358] In method 3, the set Zset includes one of the following sets: {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256}}, {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256},{288:32:320}}, {{1:1:8},{9:1:16},{18:2:32},{36:4:64},{72:8:128},{144:16:256},{288:32:512}}, {{1:1:8},{10:2 :16},{20:4:32},{40:8:64},{80:16:128},{160:32:256}}、{{1:1:8},{10:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256},{320:64:512} {{2:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256}},{{2:2:16},{20:4:32},{40:8:64},{80:16:128},{160:32:256},{320:64:512}};

[0359] In the set {a:b:c}, a is the first element of the set, c is the last element of the set, and b is the interval between two adjacent elements in the set.

[0360] In method 4, the boost value Z is:

[0361] Where K is the length of the information bit sequence, and kb is the number of columns in the basic matrix system;

[0362] In method 5, the lift value Z is: Z = Z orig +W(Z orig );

[0363] in, K is the length of the information bit sequence, kb is the number of columns in the basic matrix system, and W(Z) orig ) is the integer set W corresponding to the Z. orig One element value;

[0364] In method 6, the boost value takes the value of one of the following sets: {2,4,8,16,32,64,128,256,512}, {2,4,8,16,32,64,128,256}, {2,4,8,16,32,64,128}, {2,4,8,16,32,64}, {2,4,8,16,32}.

[0365] In one implementation, the granularity of the boost value is the difference between any two adjacent boost values ​​of any size among all boost values, and the granularity of the boost value is determined by selecting from at least two of the following methods: the method of determining the value by a non-negative integer power of 2; the method of determining the value by a fixed positive integer; and the method of determining the value by multiplying a first set of positive integers by a second positive integer.

[0366] In one implementation, when the method for determining the granularity of the boost value is the method of determining the value by a non-negative integer power of 2, the set of granularity values ​​for the boost value includes one of the following: {1,2,4,8,16}, {1,2,4,8,16,32}, {1,2,4,8,16,32,64}, {1,2,4,8,16,32,64,128}.

[0367] When the granularity of the boost value is determined using the fixed positive integer method, the fixed positive integer is a positive integer less than or equal to 128.

[0368] In one implementation, the maximum value of the boost is selected from at least two integer values ​​from 4 to 1024.

[0369] In one implementation, the maximum value of the boost value is selected from at least two of the following integer values: 16, 32, 64, 128, 256, 320, 384, 512, 768, 1024.

[0370] In one implementation, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least two integer values ​​from 128 to 8192.

[0371] In one implementation, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 256, 512, 768, 1024, 2048, 4096, 6144, 7680, and 8192.

[0372] In one implementation, the granularity of the information bit length supported by the quasi-cyclic LDPC encoding is the difference between any two adjacent lengths of any size among all supported information bit lengths, and the method for determining the granularity of the information bit length is to select at least two integer values ​​from 2 to 256.

[0373] In one implementation, the information bit length granularity supported by the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 2, 4, 8, 16, 32, 64, 128, 256.

[0374] In one implementation, the maximum number of columns in the shortened code of the quasi-cyclic LDPC encoding is Where ΔK is the maximum number of bits filled in the quasi-cyclic LDPC encoding, Z is the boost value, and the maximum number of columns in the shortened encoding is selected from at least two integer values ​​from 1 to 24.

[0375] In one implementation, the maximum number of columns in the shortened code of the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 0, 1, 2, 3, 4, 5, 6, 8, 12, 16, 24.

[0376] In one implementation, the number of system columns in the rate-matched output sequence is selected from at least two integer values: 0, 1, 2, and 3.

[0377] In one implementation, the HARQ merging method of the quasi-cyclic LDPC encoding is selected from at least two of the following types: soft merging, incremental redundancy merging, and a hybrid of soft merging and incremental redundancy merging.

[0378] In one implementation, the maximum number of HARQ transmissions for the quasi-cyclic LDPC encoding is selected from at least two of the following integer values: 1, 2, 3, 4, 5, 6.

[0379] In one implementation, the number of HARQ transport versions is selected from at least two integer values ​​from 1 to 64.

[0380] In one implementation, the number of HARQ transmission versions is selected from at least two of the following integer values: 2, 4, 6, 8, 12, 16, 24, 32.

[0381] In one implementation, the fundamental matrix is ​​selected from Y fundamental matrices, where Y is an integer greater than 1;

[0382] The Y fundamental matrices include at least one of the following features:

[0383] Among the Y fundamental matrices, there are at least two fundamental matrices with the same template matrix;

[0384] Among the Y fundamental matrices, there are at least two fundamental matrices with quasi-identical template matrices;

[0385] Among the Y fundamental matrices, there are at least two fundamental matrices with quasi-identical matrix elements;

[0386] Among the Y basic matrices, at least two basic matrices are nested template matrices;

[0387] Among the Y fundamental matrices, there exist at least two fundamental matrices with the same subset of template matrices;

[0388] Among the Y fundamental matrices, there exist at least two fundamental matrices with the same subset of fundamental matrices;

[0389] The template matrix is ​​obtained by assigning "1" to the non--1 element positions and "0" to the -1 element positions in the base matrix.

[0390] The term "template matrices are identical" means that the two template matrices have a different elements, where a is an integer greater than 0 and less than or equal to 10.

[0391] The term "quasi-identical matrix elements" means that the two basic matrices have b distinct elements, where b is an integer greater than 0 and less than or equal to 10.

[0392] In the two nested basic matrices of the template matrix, the template matrix of the smaller basic matrix is ​​a submatrix of the template matrix of the larger basic matrix;

[0393] The equality of the template matrix subsets means that there exists a submatrix in the template matrix of the basic matrix 1 that is equal to a submatrix in the template matrix of the basic matrix 2.

[0394] The equality of the subsets of the fundamental matrices means that there exists a submatrix in fundamental matrix 1 that is equal to a submatrix in fundamental matrix 2.

[0395] In one implementation, at least a predetermined proportion of the non--1 elements in the base matrix are in the same positions as the '1' elements in the reference template matrix, wherein the reference template matrix is ​​a submatrix of the following template matrix:

[0396]

[0397] In the template matrix, an element equal to '1' indicates that the element at the corresponding position in the base matrix is ​​a non--1 value, and an element equal to '0' indicates that the element at the corresponding position in the base matrix is ​​a -1 value. Preferably, the preset ratio is a real number greater than 60% and less than or equal to 100%.

[0398] Example 4

[0399] Embodiment 4 of the present invention provides an electronic device for quasi-cyclic LDPC encoding processing, comprising: a memory and a processor;

[0400] The memory is used to store a program for quasi-cyclic LDPC encoding processing. When the program for quasi-cyclic LDPC encoding processing is read and executed by the processor, it performs the following operations:

[0401] The processing strategy for quasi-cyclic low-density parity-check LDPC encoding is determined based on the data characteristics of the bit sequence to be encoded.

[0402] Based on the processing strategy, the information bit sequence is quasi-cyclic LDPC encoded and rate-matched output based on the fundamental matrix and boost value.

[0403] The method embodiment provided in Embodiment 1 of this application can be executed in the electronic device provided in Embodiment 3. Figure 14 This is a hardware structure block diagram of an electronic device for quasi-cyclic LDPC encoding processing according to Embodiment 3 of the present invention. Figure 14 As shown, the electronic device 10 may include one or more (only one is shown in the figure) processors 102 (processors 102 may include, but are not limited to, processing devices such as microprocessors (MCUs) or programmable logic devices (FPGAs)) and a memory 104 for storing data. Those skilled in the art will understand that... Figure 14 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device described above. For example, the electronic device may also include components that are more... Figure 14 The more or fewer components shown, or having the same Figure 14 The different configurations shown.

[0404] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to the quasi-cyclic LDPC encoding processing method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 1402, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0405] Example 5

[0406] Embodiment 5 of the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0407] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical units; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0408] It should be noted that the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A quasi-cyclic LDPC encoding processing method, comprising: Based on the data characteristics of the information bit sequence to be encoded, determine one or more properties of the fundamental matrix of the quasi-cyclic low-density parity-check LDPC encoding to perform the quasi-cyclic LDPC encoding. The one or more properties include the orthogonality of the basis matrices used for the quasi-cyclic LDPC encoding; The orthogonality of the fundamental matrices includes at least: quasi-orthogonality and non-orthogonality; and Based on one or more of the aforementioned characteristics, the quasi-cyclic LDPC encoding is performed on the basis matrix.

2. The method as described in claim 1, characterized in that, The data characteristics include at least one of the following: The length and code rate of the information bit sequence.

3. The method as described in claim 1, characterized in that, The quasi-orthogonality property of the fundamental matrix is ​​characterized by the quasi-orthogonality property of the submatrix D in the fundamental matrix; The non-orthogonal property means that the submatrix D in the basic matrix does not have orthogonal or quasi-orthogonal properties.

4. The method as described in claim 3, characterized in that, In the fundamental matrix with the quasi-orthogonal property, the submatrix D in the fundamental matrix is ​​defined by the column index set ColSET0 as D0, and the submatrix D1 is defined by the column index set ColSET1. The submatrix D0 does not have the orthogonal property, and the submatrix D1 has the orthogonal property. ColSET0 and ColSET1 have no intersection, and the union of ColSET0 and ColSET1 constitutes all the column indexes of the submatrix D.

5. The method as described in claim 4, characterized in that, The ColSET0 is {0,1}.

6. The method as described in claim 4, characterized in that, After performing the quasi-cyclic LDPC encoding, rate matching is then performed to obtain the rate-matched output sequence that does not contain F×Z bits of system bits. The F×Z bits of system bits correspond to the column index number of the basic matrix, ColSET2, which is a subset of ColSET0.

7. The method as described in claim 6, characterized in that, The ColSET2 is {0,1}.

8. The method as described in claim 3 or 4, characterized in that, The orthogonality property refers to the fact that in the submatrix D, which is composed of all rows indicated by the row index set RowSETi, there is at most one non--1 element among all elements indicated by any column index, where RowSETi includes at least two elements, i = 0, 1, ..., (I-1). The row index sets have no intersection, and the union of all row index sets constitutes all row indexes of the submatrix D. I is a positive integer less than the number of rows in the submatrix D, and the non--1 element is used to indicate the element of the identity matrix cyclic shift.

9. The method as described in claim 8, characterized in that, All elements in the row index set RowSETi are consecutive positive integers.

10. The method as described in claim 3 or 4, characterized in that, The submatrix D is a low bitrate extended submatrix, and the submatrix D is the lower left corner matrix of the base matrix.

11. A quasi-cyclic LDPC encoding processing apparatus, comprising: A processing module is configured to determine one or more characteristics of the basis matrix of the quasi-cyclic low-density parity-check LDPC encoding based on the data characteristics of the information bit sequence to be encoded, and to perform the quasi-cyclic LDPC encoding, wherein the one or more characteristics include the orthogonality of the basis matrix for the quasi-cyclic LDPC encoding, and the orthogonality of the basis matrix includes at least: quasi-orthogonal characteristics and non-orthogonal characteristics; and to perform the quasi-cyclic LDPC encoding based on the basis matrix according to the one or more characteristics. A storage module is used to store the basic matrix.

12. The apparatus as claimed in claim 11, characterized in that, The data characteristics include at least one of the following: The length and code rate of the information bit sequence.

13. The apparatus as claimed in claim 11, characterized in that, The quasi-orthogonality property of the fundamental matrix is ​​characterized by the quasi-orthogonality property of the submatrix D in the fundamental matrix; The non-orthogonal property means that the submatrix D in the basic matrix does not have orthogonal or quasi-orthogonal properties.

14. The apparatus as claimed in claim 13, characterized in that, In the fundamental matrix with the quasi-orthogonal property, the submatrix D in the fundamental matrix is ​​defined by the column index set ColSET0 as D0, and the submatrix D1 is defined by the column index set ColSET1. The submatrix D0 does not have the orthogonal property, and the submatrix D1 has the orthogonal property. ColSET0 and ColSET1 have no intersection, and the union of ColSET0 and ColSET1 constitutes all the column indexes of the submatrix D.

15. The apparatus as claimed in claim 14, characterized in that, The ColSET0 is {0,1}.

16. The apparatus as claimed in claim 14, characterized in that, After performing the quasi-cyclic LDPC encoding, rate matching is then performed to obtain the rate-matched output sequence that does not contain F×Z bits of system bits. The F×Z bits of system bits correspond to the column index number of the basic matrix, ColSET2, which is a subset of ColSET0.

17. The apparatus as claimed in claim 16, characterized in that, The ColSET2 is {0,1}.

18. The apparatus as claimed in claim 13 or 14, characterized in that, The orthogonality property refers to the fact that in the submatrix D, which is composed of all rows indicated by the row index set RowSETi, there is at most one non--1 element among all elements indicated by any column index, where RowSETi includes at least two elements, i = 0, 1, ..., (I-1). The row index sets have no intersection, and the union of all row index sets constitutes all row indexes of the submatrix D. I is a positive integer less than the number of rows in the submatrix D, and the non--1 element is used to indicate the element of the identity matrix cyclic shift.

19. The apparatus as claimed in claim 18, characterized in that, All elements in the row index set RowSETi are consecutive positive integers.

20. The apparatus as claimed in claim 13 or 14, characterized in that, The submatrix D is a low bitrate extended submatrix, and the submatrix D is the lower left corner matrix of the base matrix.

21. A computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement the method of any one of claims 1 to 10.

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