Tuning component for radio frequency identification chip

Abstract

A tuning assembly (10) for a radio frequency identification (RFID) chip includes an input port (12), a control unit (14), and a plurality of capacitors (16a, 16b, 16c, 16d, 16e) in parallel between the input port and the control unit. A selector circuit (18) is coupled to each capacitor and to the control unit and is configured to selectively allow and block current flow through any of the capacitors in response to commands from the control unit, thereby adjusting the capacitance of the RFID chip. The commands include one that always allows current flow through the capacitors, another that always blocks current flow through the capacitors, and a third that selectively allows and blocks current flow through the capacitors (e.g., for automatically adjusting the capacitance of the RFID chip). Programming of the control unit can be performed before or after the RFID chip is coupled to an antenna, including after a fully assembled RFID tag is attached to an item.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 954,479, filed December 28, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates to a tunable radio frequency identification ("RFID") device. More particularly, the present invention relates to a radio frequency identification chip having an adjustable capacitance. BACKGROUND

[0004] Radio frequency identification tags and labels (collectively referred to herein as "devices") are widely used to associate objects with an identification code. Radio frequency identification devices typically have a combination of an antenna and analog and / or digital electronic components, which can include, for example, communication electronics, data storage, and control logic. For example, radio frequency identification tags are used in conjunction with security locks on cars, for access control to buildings, and for tracking inventory and packages.

[0005] At a most basic level, a radio frequency identification device includes a radio frequency identification chip coupled to an antenna. The radio frequency identification chip and antenna can be variously configured, Figure 1 One embodiment of a combination of a radio frequency identification chip "M" and an antenna "A" is shown, referred to herein as a radio frequency identification inlay "N". Figure 1 The radio frequency identification chip "M" is coupled to a conductive loop "L" to define a reactive strap "S", while the antenna "A" (which is shown as a dipole antenna) is separate from the reactive strap "S". Although the antenna "A" is physically separate from the reactive strap "S", the two components work in combination to exchange signals with a radio frequency identification reader.

[0006] For radio frequency identification straps that are configured for capacitive or conductive coupling to an antenna (e.g., by connecting the antenna to a conductive pad of the strap), the configuration of the antenna can be modified to adjust the frequency of the resulting radio frequency identification inlay. However, Figure 1 The reactive strap "S" of the type shown has a resonant frequency that is determined by the capacitance of the radio frequency identification chip "M" and the inductance of the conductive loop "L", such that reconfiguring the antenna "A" will not have the same effect as it would for a non-reactive strap. In other words, in the case of a capacitive or conductive coupling strap, the reactive strap is part of a tuning loop, while Figure 1The reactive type connection band "S" shown is the tuning ring.

[0007] More specifically, Figure 1 The antenna response of the RFID inlay "N" of the type shown will include two basic poles, one related to the resonant frequency of the reactive connection band "S" and the other related to the antenna "A". The coupling between the reactive connection band "S" and the antenna "A", as well as their relative position in the frequency domain, can be used to optimize the performance of the RFID inlay "N" at specific frequencies and in some applications involving dielectric loading and proximity to metals or other RFID devices.

[0008] like Figure 2 As shown, the inputs of the RFID chip "M" can be considered as a resistive element "R" and a capacitive element "C". In Figure 2 In the diagram, the input port of the RFID chip "M" is identified as "P", the capacitor of the RFID chip "M" is identified as "T", and the core of the RFID chip "M" is identified as "B". Figure 2 In a conventional RFID chip "M" of the type shown, the interconnection between the input port "P" and the core "B" via capacitor "T" is fixed, such that the capacitance of the RFID chip "M" cannot be adjusted to adjust the resonant frequency of the reactive connection band "S" (i.e., the RFID chip "M" is untunable).

[0009] Since reactive connection bands may perform better at different frequencies, depending on numerous factors (e.g., the nature of the item to which the reactive connection band is ultimately associated), a tunable RFID chip "U" (i.e., a chip with adjustable capacitance) has been proposed, such as... Figure 3 As shown. In Figure 3 In the embodiments, Figure 2 The single capacitor "T" is replaced by three capacitors "T1", "T2", and "T3". One of the capacitors "T1" is connected to... Figure 2Similar to a single capacitor "T", providing a fixed minimum capacitance for the RFID chip "U", two other capacitors "T2" and "T3" (which may be referred to as "tunable" capacitors) are configured (under the control of the automatic adjustment circuit "D") to selectively receive current to adjust the total capacitance of the RFID chip "U" (and thus the resonant frequency). Specifically, when the RFID chip "U" attempts to power up after receiving a signal from the RFID reader, the automatic adjustment circuit "D" automatically determines whether each of the tunable capacitors "T2" and "T3" will receive current to maximize the power received by the RFID chip "U" via the input port "P" (i.e., from the associated antenna). This function—that the RFID chip "U" can automatically adjust its capacitance to improve its sensitivity—is commonly referred to as "auto-tuning".

[0010] Although Figure 3 The tunable RFID chip "U" may be for... Figure 2 The current chip is an improvement on the fixed-frequency RFID chip "M", but it is not without its drawbacks. For example, all the tunable capacitors "T2" and "T3" are tuned every time the RFID chip "U" attempts to power on. By default, each tunable capacitor "T2" and "T3" will receive current when the RFID chip "U" attempts to power on. It is possible that the initial capacitance (the current received by each of capacitors "T1", "T2", and "T3") causes such a mismatch between the antenna and the RFID chip "U" that insufficient power is supplied to the auto-tuning circuit "D". This necessitates a higher power level (corresponding to lower sensitivity and requiring the RFID inlay to be closer to the RFID reader) to initiate the auto-tuning process and optimize the power supply so that the RFID chip "U" reaches its operating threshold.

[0011] It would be advantageous to provide a tunable RFID chip that is unlikely to be initialized with a capacitor that prevents sufficient power from being supplied to the RFID chip.

[0012] Therefore, this document describes a tuning component that allows tuning of an RFID chip without initialization using a capacitor that prevents sufficient power from being supplied to the RFID chip, and describes the use and manufacturing method of the tuning component. Summary of the Invention

[0013] The application has several aspects, which can be embodied alone or together in the devices and systems described and claimed below. The aspects can be used alone or in combination with other aspects of the subject matter described herein, and the description of the aspects together is not intended to preclude separate use of the aspects, or protection under separate claims for the aspects alone or in different combinations, as can be listed in the accompanying claims for the invention.

[0014] A tuning assembly for a radio frequency identification chip is described herein. The tuning assembly includes an input port, a control unit, and a plurality of capacitors connected in parallel between the input port and the control unit. A selector circuit is coupled to each of the capacitors and to the control unit, and is configured to selectively allow and block current flow through any of the capacitors in response to commands from the control unit, thereby adjusting a capacitance of the radio frequency identification chip. The commands from the control unit to the selector circuit include a command that always allows current flow through any one or more of the capacitors, another command that always blocks current flow through any one or more of the capacitors, and a third command that selectively allows and blocks current flow through any one or more of the capacitors. In some embodiments, the tuning assembly enables the radio frequency identification chip to be coupled to a conductive loop, and the combination of the radio frequency identification chip and the conductive loop defines an antipodal connection strap.

[0015] A method for manufacturing a radio frequency identification inlay containing a tunable radio frequency identification chip is also described herein. The method includes providing a tuning assembly for the radio frequency identification chip, where the tuning assembly includes an input port, a control unit, a plurality of capacitors connected in parallel between the input port and the control unit, and a selector circuit coupled to each of the capacitors and to the control unit, and configured to selectively allow and block current flow through any of the capacitors in response to commands from the control unit to adjust a capacitance of the radio frequency identification chip. The control unit is programmed to issue a plurality of commands to the selector circuit, including a command that always allows current flow through any one or more of the capacitors, another command that always blocks current flow through any one or more of the capacitors, and a third command that selectively allows and blocks current flow through any one or more of the capacitors. The radio frequency identification chip is coupled to an antenna to define a radio frequency identification inlay. In some embodiments, the radio frequency identification chip is coupled to an antenna as part of an antipodal connection strap to define the radio frequency identification inlay. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1is a schematic diagram of an electrically reactive connection strap and associated antenna according to a conventional design.

[0017] Figure 2 and Figure 3 is a schematic diagram of a radio frequency identification chip according to a conventional design.

[0018] Figure 4 is a schematic diagram of an example tuning assembly for a radio frequency identification chip according to an aspect of the present application. DETAILED DESCRIPTION

[0019] Some detailed embodiments of the present application are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the present application which can be embodied in various forms. Therefore, specific details disclosed herein are not to be interpreted as limiting, but rather as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriate design. In this respect, it should be understood that the present application is under no

[0020] Figure 4 An example embodiment of a tuning assembly 10 for a radio frequency identification chip 11 according to an aspect of the present application is shown. The tuning assembly 10 includes an antenna or input port 12 and a control unit 14. A plurality of capacitors 16a-16e are connected in parallel between the input port 12 and the control unit 14. Figure 4 Five capacitors are shown, but it is to be understood that a tuning assembly 10 according to the present application can include more than five capacitors or less than five capacitors. A selector circuit 18 is coupled to each of the capacitors 16 and to the control unit 14. It is to be understood that a tuning assembly 10 according to the present application can include other components, such as a storage or memory unit, in addition to the components shown in FIG. 1. Figure 1 An example embodiment of a tuning assembly 10 for a radio frequency identification chip 11 according to an aspect of the present application is shown. The tuning assembly 10 includes an antenna or input port 12 and a control unit 14. A plurality of capacitors 16a-16e are connected in parallel between the input port 12 and the control unit 14.

[0021] The capacitances of the individual capacitors 16 can vary without departing from the scope of the application. In one embodiment, each capacitor 16 has a different capacitance, which can be advantageous to enable a greater range of different combined capacitances to be possible within the achievable range, as will be described in greater detail herein. For example, in one example embodiment, the first capacitor 16a has a capacitance of approximately 50 fF, the second capacitor 16b has a capacitance of approximately 100 fF, the third capacitor 16c has a capacitance of approximately 200 fF, the fourth capacitor 16d has a capacitance of approximately 400 fF, and the fifth capacitor 16e has a capacitance of approximately 800 fF. As can be seen, in this example embodiment, each capacitor 16 (except the first capacitor 16a) has a capacitance that is twice the capacitance of the capacitor 16 with the next lowest capacitance (similar to a binary number sequence). This can be advantageous to enable a more complete range of possible combined capacitances, as will be described in greater detail herein. Although it can be advantageous for each capacitor 16 to have a different capacitance, it is within the scope of the application for two or more of the capacitors 16 to have the same capacitance and / or for each capacitor 16 to have the same capacitance.

[0022] The selector circuit 18 is configured to selectively allow and prevent current flow through any of the capacitors 16 in response to commands from the control unit 14. By selectively allowing and preventing current flow through different combinations of the capacitors 16, the total or combined capacitance of the radio frequency identification chip 11 can be adjusted to achieve improved sensitivity. The selector circuit 18 can be variously configured to achieve this functionality. In one example embodiment, each capacitor 16 includes an associated switch that is opened by the selector circuit 18 to prevent current flow through the capacitor 16, or closed by the selector circuit 18 to allow current flow through the capacitor 16. Other configurations can also be employed without departing from the scope of the application.

[0023] When the selector circuit 18 acts to prevent current flow through each of the capacitors 16, the capacitors 16 will contribute nothing to the combined capacitance of the radio frequency identification chip 11, so the combined capacitance of the radio frequency identification chip 11 is equal to the base input capacitance of the radio frequency identification chip 11 (which in the above-described embodiment is 100 fF). When the selector circuit 18 acts to allow current flow through each of the capacitors 16, the combined capacitance of the radio frequency identification chip 11 is equal to the sum of the capacitances of the individual capacitors 16 (which in the above-described embodiment is 1550 fF) and the base input capacitance (which in the above-described embodiment is 100 fF), i.e. the combined capacitance in the above-described embodiment is 1650 fF.

[0024] When the selector circuit 18 allows current to flow through at least one, but not all, of the capacitors 16, the combined capacitance will be between the base input capacitance of the RFID chip 11 and the maximum possible capacitance (i.e. the combined capacitance when current is allowed to flow through all of the capacitors 16). In the above described embodiment, combined capacitances (including the base input capacitance) in the range 100 fF and 1650 fF can be achieved, in increments of 50. For example, by selecting the circuit 18 to allow current to flow through only the first capacitor 16a (which has a capacitance of 50 fF in addition to the base input capacitance of 100 fF), a combined capacitance of 150 fF can be achieved. By selecting the selector circuit 18 to allow current to flow through only the second capacitor 16b (which has a capacitance of 100 fF in addition to the base input capacitance of 100 fF), a combined capacitance of 200 fF can be achieved. By selecting the selector circuit 18 to allow current to flow through both the first and second capacitors 16a and 16b, a combined capacitance of 250 fF can be achieved, and so on, up to the maximum achievable combined capacitance. This dense coverage of achievable combined capacitance values can be achieved in a number of possible ways, but can be efficiently achieved (i.e. using the minimum number of capacitors 16) by using capacitors 16 having different capacitance values, and by ensuring that the capacitance difference between any pair of capacitors 16 is different from the capacitance difference between any other pair of capacitors 16, as described in the above described embodiment.

[0025] The control unit 14 can be configured to command the selector circuit 18 to automatically alternate between allowing and preventing current flow through each of the capacitors 16 until the maximum sensitivity is achieved, thus acting like a conventional auto-tuning system. Furthermore, the control unit 14 can be configured to issue additional commands to the selector circuit 18 which can be advantageous over conventional auto-tuning arrangements. For example, the control unit 14 can be configured to command the selector circuit 18 to always allow current flow through any one or more of the capacitors 16. This can be advantageous in situations where it is known that the RFID chip 11 will be used for an application which requires a combined capacitance within a narrower range than the full range of capacitance values achievable by the RFID chip 11. For example, if it is known (e.g. from testing of similarly configured RFID chips in similar applications) that the RFID chip 11 will need to have a combined capacitance of at least a certain minimum value, the control unit 14 can be configured to command the selector circuit 18 to always allow current flow through the most suitable capacitor 16 to ensure that the combined capacitance is always at least that minimum value.

[0026] Similarly, control unit 14 can be configured such that command selector circuit 18 always blocks current from flowing through any one or more of capacitors 16. This may be advantageous when it is known that RFID chip 11 will be used in an application that requires a combined capacitance within a narrower range than the full range of capacitance values ​​achievable by RFID chip 11. For example, if (e.g., from testing RFID chips with similar configurations in similar applications) it is known that RFID chip 11 will require a combined capacitance below a certain maximum value, control unit 14 can be configured such that command selector circuit 18 always blocks current from flowing through the most suitable capacitor 16 to ensure that the combined capacitance never exceeds that maximum value.

[0027] "Freezing" the state of the tunable capacitor 16 (i.e., by always allowing current to flow through it or always preventing current from flowing through it) avoids problems that may occur in conventional autotuning systems. As explained in the description of prior art systems, conventional autotunable RFID chips "U" (such as...) Figure 3 The initial capacitance (as shown) may cause a mismatch between the antenna and the RFID chip "U", resulting in insufficient power being delivered to the autotuning circuit "D". This necessitates a higher power level (corresponding to lower sensitivity and requiring the RFID inlay to be closer to the RFID reader) to initiate the autotuning process and optimize the power delivery so that the RFID chip "U" reaches its operating threshold. By "freezing" the state of one or more capacitors 16, the RFID chip 11 according to the invention will have an initial or initial combined capacitance that is sufficiently close to the target value to avoid this mismatch. Starting with this initial configuration (i.e., the state of one or more of the capacitors 16 may be "frozen"), the control unit 14 and the selection circuit 18 work together to regulate the states of the individual capacitors 16 that are not "frozen" (comparing the following two amounts: the amount of power delivered to the RFID chip 11 via the input port 12 when a particular combination of capacitors 16 is allowed to flow, and the amount of power delivered to the RFID chip 11 via the input port 12 when a different combination of capacitors 16 is allowed to flow), until a combined capacitance is reached under which the amount of power delivered to the RFID chip 11 via the input port 12 is maximized. After the comparison, based at least in part on the amount of power delivered to the RFID chip 11 via the input port 12 when allowing and blocking current flow through any one of the capacitors 16, the control unit 14 commands the selector circuit 18 to allow or block current flow through any one of the capacitors 16.

[0028] The state of the capacitor 16 can be set at any of a number of different times and places (e.g., set to a "frozen" state or set to allow automatic adjustment). In one embodiment, the state of the capacitor 16 is set before the associated RFID chip 11 (as part of the reactive connection strap) is coupled to the antenna. In another embodiment, the state of the capacitor 16 is set after the RFID chip 11 has been coupled to the antenna to define the RFID inlay. This can include programming the RFID chip 11 during inlay testing, or after the RFID inlay has been incorporated into an RFID label or tag. It can also include programming the RFID chip 11 after the RFID chip 11 (as part of the RFID label or tag) has been associated with an item.

[0029] Because it can be difficult to determine the proper combination capacitance of an RFID chip 11 before it is put into use, the present application provides a method for using data collected from previously deployed RFID chips 11 so that the RFID chip 11 can be programmed at a relatively early stage of manufacture. In this method, an RFID reader is run at a relatively high power to detect RFID tags that have been put into use (e.g., by being attached to a cotton shirt or pair of jeans item). The RFID reader is then run at a lower power to determine the minimum operating power at which the RFID tag is detected. Next, the RFID reader is run at a power greater than the previously determined minimum operating power, and the control unit 14 of the tuning assembly 10 of the RFID chip 11 for the RFID tag is programmed to instruct the selector circuit 16 to deliver current through the capacitor 16 at different combinations to achieve different combination capacitances. The RFID reader is then run at a power lower than the previously determined minimum operating power to determine whether a lower minimum operating power has been reached (i.e., whether the RFID tag can be detected at the new capacitance). This process can be repeated until the lowest minimum operating power has been reached.

[0030] The above process can be repeated for a plurality of RFID tags of similar configuration and placement to determine average programming (which can include average combination capacitance). This information can then be used to program the control unit 14 and set the state of the capacitor 16 of future RFID chips 11 relatively early in the manufacturing process (once it is known how the RFID chip 11 will be used) without having to wait until the RFID chip 11 has been put into use.

[0031] It is understood that the examples described above are merely illustrative of some applications of the principles of the application. Numerous modifications may be made by those skilled in the art without departing from the spirit and scope of the claimed subject matter, including that which is disclosed in connection with the various features and combinations thereof as individually disclosed or claimed. For these reasons, the scope of the application is not limited to the above description, but is instead as set forth in the appended claims, and it is understood that the claims can be directed to features individually disclosed or claimed, as well as combinations thereof.

Claims

1. A tuning component for a radio frequency identification chip, comprising: Input port; Control unit; Multiple capacitors connected in parallel between the input port and the control unit; as well as A selector circuit, coupled to each of the capacitors and the control unit, is configured to selectively allow and block current flow through any of the capacitors in response to a command from the control unit to adjust the capacitance of the RFID chip, wherein the control unit is configured to issue multiple commands to the selector circuit, including: A command that always allows current to flow through any one or more of the capacitors, such that the combined capacitance is not lower than a predetermined minimum. A command that always prevents current from flowing through any one or more of the capacitors, so that the combined capacitance does not exceed a predetermined maximum value; and A command that selectively allows and prevents current from flowing through any one or more of the capacitors; Each capacitor has a capacitance in the range of 50fF to 800fF, and the plurality of capacitors are configured to selectively allow and block current from flowing through any one or more of the plurality of capacitors via the selector circuit to provide the combined capacitance between 0fF and 1550fF, such that the value of the combined capacitance can densely cover between the minimum and maximum values.

2. The tuning assembly as claimed in claim 1, wherein, Each of the plurality of capacitors has a different capacitance.

3. The tuning assembly as claimed in claim 2, wherein, The capacitance difference between any two pairs of capacitors is different from the capacitance difference between any other pair of capacitors.

4. The tuning assembly as claimed in claim 2, wherein, One of the capacitors has a lower capacitance than the others. Another capacitor among the plurality of capacitors has a larger capacitance than the others, and Each of the other capacitors in the plurality of capacitors has a capacitance that is twice the capacitance of the capacitor with the lowest adjacent capacitance and half the capacitance of the capacitor with the highest adjacent capacitance.

5. The tuning assembly as claimed in claim 1, wherein, The plurality of capacitors includes: A first capacitor with a capacitance of 50 fF; A second capacitor with a capacitance of 100 fF; A third capacitor with a capacitance of 200 fF; A fourth capacitor with a capacitance of 400 fF; and The fifth capacitor has a capacitance of 800fF.

6. The tuning component as described in any one of claims 1-5, wherein, The control unit is configured such that commands given to the selector circuit selectively allow and block current flow through any one or more of the plurality of capacitors to provide a combined capacitor under which the amount of power delivered to the RFID chip via the input port is maximized.

7. The tuning assembly of claim 6, wherein, The control unit is configured to command the selector circuit to either always allow or always block current from flowing through at least one of the capacitors.

8. The tuning assembly of claim 6, wherein, The command that selectively allows and blocks current from flowing through the combination of the plurality of capacitors includes: Compare the following two items: the amount of power supplied to the RFID chip via the input port when current is allowed to flow through a specific combination of the capacitors, and the amount of power supplied to the RFID chip via the input port when current is allowed to flow through a different combination of the capacitors; and The selector circuit is instructed to allow or block current from flowing through any one or more of the capacitors, based at least in part on the amount of power supplied to the RFID chip via the input port when allowing or blocking current flow through any one or more of the capacitors.

9. The tuning assembly as claimed in any one of claims 1-5 or 7-8, wherein, The tuning component enables the RFID chip to couple to the conductive ring, and the combination of the RFID chip and the conductive ring defines a reactive connection band.

10. A method of manufacturing a radio frequency identification (RFID) inlay, the RFID inlay comprising an RFID chip configured for tuning, the method comprising the following steps: A tuning assembly for the radio frequency identification (RFID) chip is provided, the tuning assembly comprising: an input port, a control unit, a plurality of capacitors connected in parallel between the input port and the control unit, and a selector circuit coupled to each of the capacitors and coupled to the control unit, and configured to selectively allow and block current flow through any one of the capacitors in response to a command from the control unit to adjust the capacitance of the RFID chip; The control unit is programmed to issue multiple commands to the selector circuit, the commands including: a command that always allows current to flow through any one or more of the capacitors, such that the combined capacitance is not lower than a predetermined minimum value; a command that always blocks current from flowing through any one or more of the capacitors, such that the combined capacitance is not higher than a predetermined maximum value; and a command that selectively allows and blocks current from flowing through any one or more of the capacitors; and The RFID chip is coupled to the antenna to define the RFID inlay; Each capacitor has a capacitance in the range of 50fF to 800fF, and the plurality of capacitors are configured to selectively allow and block current from flowing through any one or more of the plurality of capacitors via the selector circuit to provide the combined capacitance between 0fF and 1550fF, such that the value of the combined capacitance can densely cover between the minimum and maximum values.

11. The method of claim 10, wherein, The control unit is programmed before the RFID chip is coupled to the antenna.

12. The method of claim 10, wherein, The control unit is programmed after the RFID chip is coupled to the antenna.

13. The method of claim 12, further comprising subjecting the RFID inlay to testing, wherein, The control unit is programmed during the test.

14. The method of claim 12, further comprising integrating the RFID inlay into an RFID tag, wherein, The control unit is programmed after the RFID inlay is integrated into the RFID tag.

15. The method of any one of claims 10-14, further comprising: Integrate the RFID inlay into the RFID label; as well as The radio frequency identification (RFID) tag is associated with the item, wherein the control unit is programmed after the RFID tag is associated with the item.

16. The method of claim 15, wherein, The programming of the control unit includes: (a) Operating the RFID reader at relatively high power to detect the RFID tag; (b) Operate the RFID reader at a lower power level to determine the minimum operating power; (c) Operate the RFID reader at a power greater than the minimum operating power; (d) When the RFID reader is operating at a power greater than the minimum operating power, the control unit is programmed; (e) Operating the RFID reader at a power level below the minimum operating power to determine whether a lower minimum operating power has been reached; and (f) Repeat steps (c)-(e) until the minimum operating power has been reached.

17. The method of claim 16, further comprising: Perform steps (a)-(f) on multiple RFID tags with similar configurations and settings; The average programming of the control unit of the plurality of similarly configured and positioned RFID tags is determined; as well as The control unit of at least one radio frequency identification chip is programmed based at least in part on the mean programming.

Images