Display panel and driving method thereof, and display device

Abstract

A display panel (100) and a driving method thereof, and a display device (200), wherein the display panel (100) has a display area (AA), and comprises: a substrate (10), a plurality of display units (20), a driving circuit (30), and a gating circuit (40). The plurality of display units (20) are on the substrate (10) and in the display area (AA). The driving circuit (30) is on the substrate (10) and outside the display area (AA). The gating circuit (40) is on the substrate (10) and in the display area (AA) and outside the plurality of display units (20). Each display unit (20) comprises a plurality of pixel islands (21), and each pixel island (21) comprises a plurality of sub-pixels (P) of the same color. The driving circuit (30) is configured to output a plurality of driving signals. The gating circuit (40) is coupled to the driving circuit (30) and is also coupled to at least one display unit (20). The gating circuit (40) is configured to control the driving circuit (30) to be connected to at least one display unit (20), so that the at least one display unit (20) drives a plurality of sub-pixels (P) in a plurality of pixel islands (21) in the at least one display unit (20) to display according to at least one driving signal from the driving circuit (30).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] Self-luminous devices have the advantages of high brightness, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, and high luminous efficiency. They are widely used in various terminal display products with high-resolution color screens. Summary of the invention

[0003] On the one hand, a display panel is provided. The display panel has a display area. The display panel includes a substrate, a plurality of display units, a driving circuit and a gating circuit. The plurality of display units are arranged on the substrate and located in the display area. The driving circuit is arranged on the substrate and located outside the display area. The gating circuit is arranged on the substrate and located in the display area and outside the plurality of display units. Each display unit includes a plurality of pixel islands, and each pixel island includes a plurality of sub-pixels of the same color. The driving circuit is configured to output a plurality of driving signals. The gating circuit is coupled to the driving circuit, and the gating circuit is also coupled to at least one display unit. The gating circuit is configured to control the driving circuit to be turned on with the at least one display unit, so that the at least one display unit drives the plurality of sub-pixels in the plurality of pixel islands in the at least one display unit to display according to at least one driving signal from the driving circuit.

[0004] In some embodiments, the display panel further comprises a plurality of control signal lines. The plurality of drive signal lines are disposed on the substrate. The drive circuit comprises: a plurality of drive signal output terminals. The plurality of drive signal output terminals are configured to output the plurality of drive signals. The gating circuit comprises: a plurality of gating subcircuits. A gating subcircuit is coupled to at least one control signal line, a display unit and at least one drive signal output terminal. The gating subcircuit is configured to transmit at least one drive signal received at the at least one drive signal output terminal to a plurality of subpixels in each pixel island in the display unit in response to a control signal transmitted by the at least one control signal line.

[0005] In some embodiments, the display unit includes at least one row of sub-pixels. The gating sub-circuit includes: at least one switch sub-circuit. One switch sub-circuit is coupled to a control signal line, a drive signal output terminal, and a row of sub-pixels in the display unit. The switch sub-circuit is configured to transmit a drive signal received at the drive signal output terminal to a row of sub-pixels coupled to the switch sub-circuit in response to a control signal transmitted by the control signal line.

[0006] In some embodiments, the plurality of display units are arranged in an array. In each display unit in a row of display units, the switch sub-circuit to which the sub-pixels in the same row are coupled is coupled to the same drive signal output terminal.

[0007] In some embodiments, at least one switch sub-circuit in the gating sub-circuit is coupled to the same control signal line.

[0008] In some embodiments, the switch subcircuit includes: a gate transistor, wherein a control electrode of the gate transistor is coupled to the control signal line, a first electrode of the gate transistor is coupled to the drive signal output terminal, and a second electrode of the gate transistor is coupled to a row of sub-pixels in the display unit.

[0009] In some embodiments, different gating sub-circuits are coupled to different control signal lines.

[0010] In some embodiments, the display panel further comprises: a plurality of input signal lines. The plurality of input signal lines are disposed on the substrate. The driving circuit comprises: a plurality of driving sub-circuits. Each driving sub-circuit is coupled to an input signal line, and the driving sub-circuit comprises a plurality of driving signal output terminals. The driving sub-circuit is configured to output a plurality of driving signals from the plurality of driving signal output terminals of the driving sub-circuit according to the input signal transmitted by the input signal line.

[0011] In some embodiments, the driving subcircuit includes a plurality of cascaded shift registers. The output end of each stage of the shift register is a driving signal output end. The input end of the first stage of the shift register is coupled to an input signal line; the output end of each stage of the shift register except the last stage of the shift register is coupled to the input end of the next stage of the shift register.

[0012] In some embodiments, the display panel further comprises: a plurality of data lines. The plurality of data lines are disposed on the substrate. The sub-pixel comprises a pixel circuit. The pixel circuit comprises a data writing sub-circuit; the data writing sub-circuit is coupled to the gating circuit and a data line. The data writing sub-circuit is configured to write a data signal transmitted by the data line in response to a driving signal from the gating circuit.

[0013] In some embodiments, the sub-pixel includes a light-emitting device. The light-emitting device includes a light-emitting layer; and the light-emitting layers of the light-emitting devices in the plurality of sub-pixels in one pixel island have no gaps.

[0014] In some embodiments, the display panel further comprises an optical film. The optical film is disposed on a side of the plurality of display units away from the substrate. The optical film is configured to refract light emitted by each sub-pixel in each pixel island in the display unit in the display panel to disperse the light to a plurality of pixel regions.

[0015] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments.

[0016] In some embodiments, the display device further comprises a processing device. The processing device is configured to output at least one control signal to a gating circuit in the display panel according to information of the area to be displayed of the display panel, so as to control the conduction between a driving circuit in the display panel and at least one display unit corresponding to the area to be displayed in the display panel; and, according to information of the area to be displayed of the display panel, output at least one input signal to a driving circuit in the display panel, so as to enable the driving circuit to output at least one driving signal to at least one display unit corresponding to the area to be displayed.

[0017] In some embodiments, the display device further comprises an information collection device. The information collection device is configured to collect user sight information. The processing device is further configured to obtain the user sight information, and determine information of the to-be-displayed area of ​​the display panel according to the user sight information.

[0018] On the other hand, a method for driving a display panel as described in any of the above embodiments is provided. The driving method comprises: outputting at least one input signal to a driving circuit in the display panel according to information of the area to be displayed of the display panel, so that the driving circuit outputs at least one driving signal to at least one display unit corresponding to the area to be displayed in response to the at least one input signal; outputting at least one control signal to a gating circuit in the display panel according to information of the area to be displayed of the display panel, so that the gating circuit controls the driving circuit to conduct with at least one display unit corresponding to the area to be displayed among a plurality of display units according to the at least one control signal, so that the at least one display unit receives at least one driving signal from the driving circuit, and drives the at least one display unit corresponding to the area to be displayed to display.

[0019] In some embodiments, the driving method further includes: acquiring user sight line information; and determining information of a to-be-displayed area of ​​the display panel according to the user sight line information. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is a structural diagram of a display device according to some embodiments;

[0022] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0023] Figure 3 is a structural diagram of a sub-pixel according to some embodiments;

[0024] Figure 4 is a structural diagram of a light emitting device according to some embodiments;

[0025] Figure 5 is another structural diagram of a display panel according to some embodiments;

[0026] Figure 6 is another structural diagram of a display panel according to some embodiments;

[0027] Figure 7 is another structural diagram of a display panel according to some embodiments;

[0028] Figure 8 is another structural diagram of a display panel according to some embodiments;

[0029] Fig. 9 is another structural diagram of a display panel according to some embodiments;

[0030] Fig. 10A is another structural diagram of a display panel according to some embodiments;

[0031] Fig. 10B is a structural diagram of a driving sub-circuit according to some embodiments;

[0032] Fig.11 is a structural diagram of a shift register according to some embodiments;

[0033] Fig.12 is another structural diagram of a shift register according to some embodiments;

[0034] Fig.13is a driving timing diagram of a shift register according to some embodiments;

[0035] Fig.14 is another structural diagram of a display panel according to some embodiments;

[0036] Fig.15 is another structural diagram of a display panel according to some embodiments;

[0037] Fig.16 is another structural diagram of a display panel according to some embodiments;

[0038] Fig.17 is another structural diagram of a display panel according to some embodiments;

[0039] Fig.18A is another structural diagram of a display panel according to some embodiments;

[0040] Fig.18B for Fig.18A A cross-sectional view of the display panel along the AB direction;

[0041] Fig.19 is an optical schematic diagram of an optical film according to some embodiments;

[0042] Fig. 20 is another structural diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0048] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0050] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] The embodiments of the present disclosure provide a display device. Exemplarily, the display device may be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. The embodiments of the present disclosure do not place any special restrictions on the specific form of the above-mentioned display device. Exemplarily, the display device may be a micro display device; for example, the micro display device may include a head-mounted display device; for example, the head-mounted display device may include a VR (Virtual Reality) display device or an AR (Augmented Reality) display device, etc.

[0052] In some embodiments, Figure 1 As shown, the display device 200 includes a display panel 100. Figure 2 As shown, the display panel 100 has an active area (AA) and a peripheral area S. The peripheral area S is at least located on one side outside the AA area.

[0053] In some embodiments, the display panel includes a plurality of sub-pixels located in the AA region. Figure 3 As shown, at least one sub-pixel P (eg, each sub-pixel P) includes a pixel circuit 110 and a light-emitting device L. The pixel circuit 110 is coupled to the light-emitting device L. The pixel circuit 110 is configured to drive the light-emitting device L to emit light. Exemplarily, the pixel circuits are arranged in an array.

[0054] It should be noted that the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, and can be designed according to actual conditions. Exemplarily, the pixel circuit is composed of electronic devices such as transistors (such as thin film transistors (TFT)), capacitors (Capacitance, C for short). For example, the pixel circuit may include two transistors and one capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two transistors and at least one capacitor, such as seven transistors and one capacitor to form a 7T1C structure.

[0055] For example, the light emitting device may be a current driven light emitting device including an LED (light emitting diode), an OLED (organic light emitting diode), or a quantum dot light emitting diode (quantum light emitting diode, QLED). Figure 4 As shown, the light-emitting device L includes a cathode 1202 and an anode 1201, and a light-emitting functional layer 1203 located between the cathode 1202 and the anode 1201. The light-emitting functional layer 1203 may include, for example, a light-emitting layer E, a hole transport layer (HTL) located between the light-emitting layer E and the anode 1201, and an electron transport layer (ETL) located between the light-emitting layer E and the cathode 1202. Of course, in some embodiments, a hole injection layer (HIL) may be provided between the hole transport layer HTL and the anode, and an electron injection layer (EIL) may be provided between the electron transport layer ETL and the cathode 1202 as required.

[0056] Exemplarily, the anode may be formed of a transparent conductive material with a high work function, and its electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum zinc oxide (AZO) and carbon nanotubes, etc.; the cathode may be formed of a material with high conductivity and low work function, and its electrode material may include alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl) or metal single substances such as magnesium (Mg), aluminum (Al), lithium (Li) and silver (Ag). The material of the light-emitting layer can be selected according to the different colors of the light emitted. For example, the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material. For example, in at least one embodiment of the present disclosure, the light-emitting layer may adopt a doping system, that is, a doping material is mixed into the main light-emitting material to obtain a usable light-emitting material. For example, the main light-emitting material may adopt a metal compound material, anthracene derivatives, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, benzene diamine derivatives and triarylamine polymers, etc.

[0057] An embodiment of the present disclosure provides a display panel. Figure 2 As shown, the display panel 100 includes a substrate 10, a plurality of display units 20, a driving circuit 30, and a gate circuit 40. The plurality of display units 20, the driving circuit 30, and the gate circuit 40 are all disposed on the substrate 10.

[0058] For example, the substrate 10 may include: a rigid substrate such as glass (or called a hard substrate), or a flexible substrate such as PI (Polyimide); and may also include: a thin film such as a buffer layer disposed on the rigid substrate or the flexible substrate. For example, the substrate 10 may be a silicon-based substrate.

[0059] Among them, Figure 5 As shown, each display unit 20 includes a plurality of pixel islands 21. Each pixel island 21 includes a plurality of sub-pixels P of the same color. For example, the colors of the plurality of pixel islands 21 in the display unit 20 are different. It can be understood that the plurality of display units 20 are located in the AA area.

[0060] For example, a plurality of pixel islands may be arranged in an array; for example, Figure 5 The pixel islands 21 arranged in a row in the X direction (horizontal direction) are called pixel islands in the same row. Figure 5 The pixel islands 21 arranged in a row along the Y direction (vertical direction) are referred to as the same column of pixel islands. For example, the plurality of sub-pixels may be arranged in an array. Figure 5 The sub-pixels P arranged in a row in the X direction are called sub-pixels in the same row. Figure 5 The sub-pixels P arranged in a row in the Y direction are called sub-pixels in the same column.

[0061] It should be noted that the number of sub-pixels in a pixel island can be designed according to actual conditions, for example, according to the size of the area where the user's visual range is mapped on the display panel. For example, multiple sub-pixels in a pixel island are arranged in an array of 3 rows and 3 columns (e.g. Figure 5 Alternatively, a plurality of sub-pixels in a pixel island are arranged in an array of 5 rows and 5 columns, which is not limited to the specific arrangement herein.

[0062] Exemplarily, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; correspondingly, the plurality of pixel islands include a first color pixel island, a second color pixel island, and a third color pixel island. For example, the first color, the second color, and the third color are three primary colors; for example, the first color, the second color, and the third color are red, green, and blue, respectively; that is, the plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the plurality of pixel islands include a red pixel island, a green pixel island, and a blue pixel island. Exemplarily, one display unit includes one red pixel island, one green pixel island, and one blue pixel island.

[0063] In some embodiments, the sub-pixel includes a light-emitting device, and the light-emitting device includes a light-emitting layer. The light-emitting layers of the light-emitting devices in the multiple sub-pixels in one pixel island are free of gaps. For example, the light-emitting layers of the light-emitting devices in the multiple sub-pixels in one pixel island are connected into an integrated structure.

[0064] Exemplarily, the light-emitting layers of the light-emitting devices in the plurality of sub-pixels in the pixel island are connected into an integrated structure. For example, in the process of forming the light-emitting layer in the process, each opening of the mask plate (e.g., FMM (Fine Metal Mask)) can correspond to the light-emitting layers of all the light-emitting devices in one pixel island, that is, the light-emitting layers in the pixel island are jointly evaporated through the same opening of the mask plate; that is, the light-emitting layers in the light-emitting devices in the pixel island can be jointly evaporated through the same opening of the mask plate.

[0065] For a display panel with a high pixel density (Pixels Per Inch, PPI), the spacing between adjacent sub-pixels is small. In the process of forming a light-emitting layer by evaporation of a mask plate, the light-emitting layer of the light-emitting device in each sub-pixel is formed by evaporation through an opening of the mask plate, resulting in relatively high requirements for the mask plate. Due to the limitation of the mask plate, the preparation process is difficult. In this case, the embodiment of the present disclosure can form the light-emitting layer of the light-emitting device in multiple sub-pixels by evaporation through the same opening of the mask plate, and the requirements for the mask plate are relatively low. The light-emitting layer in a high PPI (for example, 1000PPI~10000PPI) display panel can be produced by preparing a mask plate for the light-emitting layer in a low PPI (for example, 400PPI) display panel. In this way, a display panel with a large number of pixels per inch can be produced by a mask plate with a small number of openings per inch. In this way, while realizing a high PPI display panel, the difficulty of preparing the mask plate and the difficulty of the evaporation process can also be reduced.

[0066] Exemplarily, each pixel island has the same size, and the number and size of sub-pixels in each pixel island are also the same. Exemplarily, the size of a pixel island is related to the size of the sub-pixels it contains; for example, the size of a pixel island is approximately equal to the size of n sub-pixels, where n is the number of sub-pixels in a pixel island.

[0067] The driving circuit 30 is located outside the AA region, that is, the driving circuit 30 is located in the peripheral region S. The gating circuit 40 is located in the AA region, and the gating circuit 40 is located outside the plurality of display units 20. The gating circuit 40 is coupled to the driving circuit 30, and the gating circuit 40 is also coupled to at least one display unit 20. The driving circuit 30 is configured to output a plurality of driving signals. Exemplarily, the driving signal may be a gate driving signal.

[0068] The selection circuit 40 is configured to control the driving circuit 30 to be connected to at least one display unit 20 so that at least one display unit 20 drives multiple sub-pixels P in multiple pixel islands 21 in at least one display unit 20 to display according to at least one driving signal from the driving circuit 30.

[0069] It can be understood that the gating circuit 40 controls at least one display unit 20 among the multiple display units 20 to be connected to the driving circuit 30, and the driving circuit 30 transmits at least one driving signal to at least one display unit 20 connected thereto, so that the multiple sub-pixels P in the multiple pixel islands 21 in the display unit 20 receive the driving signal, that is, the pixel circuit 110 in the multiple sub-pixels P generates a driving current according to the received driving signal, drives the light-emitting device L to emit light, so that at least one display unit 20 among the multiple display units 20 displays. In this case, some display units (one or more display units) among the multiple display units in the display panel display, and the remaining display units do not display, that is, a local area in the display panel displays, and the remaining area does not display. In this way, through the gating circuit, the conduction state of each display unit and the driving circuit can be individually controlled, and each display unit in the display panel can be individually controlled to be in a display state or a non-display state, so as to realize independent driving of multiple display units and independent control of the display of multiple display units. Therefore, compared with the situation where all sub-pixels in the display panel are connected to the driving circuit, that is, all sub-pixels are driven so that the display panel can only perform full-screen display, the display panel provided by the embodiment of the present disclosure can achieve partitioned display, thereby reducing display power consumption.

[0070] Exemplarily, the display panel (or display screen) can be divided into multiple sub-display screens according to multiple display units, one display unit corresponds to one sub-display screen, and the display area of ​​the display unit corresponds to the display area of ​​the sub-display screen. In this way, when some of the multiple display units are displaying, some of the sub-display screens in the display panel are displayed, and the remaining sub-display screens are not displayed, thereby realizing split-screen display; when all of the multiple display units are displaying, all of the sub-display screens in the display panel are displayed, thereby realizing full-screen display.

[0071] Therefore, an embodiment of the present disclosure provides a display panel, in which a gating circuit in the display panel controls the conduction between a driving circuit and at least one display unit, so that at least one display unit drives multiple sub-pixels in multiple pixel islands in at least one display unit to display according to at least one driving signal from the driving circuit. In this case, through the gating circuit, the conduction state of each display unit and the driving circuit can be individually controlled, and each display unit in the display panel can be individually controlled to be in a display state or a non-display state, so as to realize independent driving of multiple display units and independent control of the display of multiple display units. Therefore, compared with a display panel that can only perform full-screen display, the display panel provided by the embodiment of the present disclosure can realize partitioned display, thereby reducing display power consumption.

[0072] In some embodiments, Figure 6As shown, the display panel 100 further includes a plurality of control signal lines CL. The plurality of control signal lines CL are disposed on the substrate 10. It is understood that the control signal lines are configured to transmit control signals; for example, one control signal line can transmit one control signal. Figure 6 As shown, the driving circuit 30 includes a plurality of driving signal output terminals OUT. The plurality of driving signal output terminals OUT are configured to output a plurality of driving signals. The gating circuit 40 includes a plurality of gating sub-circuits 41. One gating sub-circuit 41 is coupled to at least one control signal line CL, one display unit 20 and at least one driving signal output terminal OUT. Exemplarily, the number of the gating sub-circuits is the same as the number of the display units.

[0073] It should be noted that the location of the gating subcircuit can be designed according to actual conditions, and is not limited here. For example, the gating subcircuit can be located in the peripheral area; for example, the gating subcircuit can be located in the area outside the display unit to which it is coupled; for example, the gating subcircuit is located in the area between two adjacent display units.

[0074] The gating subcircuit is configured to transmit at least one driving signal received at at least one driving signal output terminal to a plurality of sub-pixels in each pixel island in the display unit in response to a control signal transmitted by at least one control signal line. It can be understood that under the control of the control signal, the gating subcircuit is turned on, and the display unit to which it is coupled is turned on with the driving circuit, so that the driving signal output by the driving circuit can be transmitted to the display unit, and the plurality of sub-pixels in each pixel island in the display unit are displayed under the control of the driving signal, that is, the pixel circuits in the plurality of sub-pixels provide driving current to the light-emitting device under the control of the driving signal, driving the light-emitting device to emit light. In this case, by controlling the gating subcircuit to be turned on or off, the display unit and the driving circuit can be controlled to be turned on or off, the display unit that is turned on with the driving circuit is displayed, and the display unit that is not turned on with the driving circuit is not displayed, so that the display panel realizes partitioned display, thereby reducing the power consumption of the display panel.

[0075] In some embodiments, the display unit includes at least one row of sub-pixels. Figure 5 The display unit 20 includes a plurality of Figure 5 The display unit includes three pixel islands arranged in sequence (in the X direction), the three pixel islands respectively including red sub-pixels, green sub-pixels and blue sub-pixels. A row of sub-pixels in the display unit includes a row of red sub-pixels in a pixel island, a row of green sub-pixels in a pixel island and a row of blue sub-pixels in a pixel island, and the row of red sub-pixels, the row of green sub-pixels and the row of blue sub-pixels are included in the same row of sub-pixels.

[0076] like Figure 7As shown, the gating subcircuit 41 includes at least one switch subcircuit 411. One switch subcircuit 411 is coupled to one control signal line CL, one drive signal output terminal OUT and one row of sub-pixels in the display unit 20. Exemplarily, the number of switch subcircuits is the same as the number of rows of sub-pixels included in the display unit; for example, in the case where the display unit 20 includes two rows of sub-pixels P, refer to Figure 7 The gating subcircuit 41 coupled to the display unit 20 includes two switch subcircuits 411; for example, when the display unit includes three rows of sub-pixels, the gating subcircuit coupled to the display unit includes three switch subcircuits.

[0077] The switch subcircuit is configured to transmit the drive signal received at the drive signal output terminal to a row of sub-pixels coupled to the switch subcircuit in response to a control signal transmitted by the control signal line. It can be understood that under the control of the control signal, the switch subcircuit is turned on, and a row of sub-circuits is connected to a drive signal output terminal of the drive circuit, so that a row of sub-pixels receives the drive signal from the drive signal output terminal, and the pixel circuits in a row of sub-pixels drive the light-emitting devices to emit light under the control of the drive signal, so that a row of sub-pixels can be displayed. When the switch subcircuit coupled to each row of sub-pixels in the display unit is turned on, each row of sub-pixels in the display unit can receive the drive signal, so that the sub-pixels in each pixel island in the display unit can be displayed. Exemplarily, multiple rows of sub-pixels in the display unit can be driven row by row and displayed row by row.

[0078] For example, Figure 8 As shown, the switch sub-circuit 411 includes a gate transistor MK. The control electrode of the switch transistor MK is coupled to the control signal line CL, the first electrode of the gate transistor MK is coupled to the drive signal output terminal OUT, and the second electrode of the gate transistor MK is coupled to a row of sub-pixels P in the display unit 20. It can be understood that the gate transistor MK responds to the control signal transmitted by the control signal line CL, the gate transistor MK is turned on, and the drive signal received at the drive signal output terminal OUT is transmitted to a row of sub-pixels P, so as to drive a row of sub-pixels P to display.

[0079] Exemplarily, the plurality of display units are arranged in an array. In each display unit in a row of display units, the switch sub-circuit to which the sub-pixels in the same row are coupled is coupled to the same drive signal output terminal.

[0080] It should be noted that in a row of display units, sub-pixels with the same row number in each pixel island are sub-pixels in the same row. For example, in a row of display units, the i-th row of sub-pixels in each pixel island in each display unit are sub-pixels in the same row and are the i-th row of sub-pixels in the display unit, where i is a positive integer.

[0081] It can be understood that the driving circuit outputs driving signals to the display units row by row, and by controlling the opening or closing of the switch sub-circuit, the display units in each row of display units that are connected to the driving circuit are displayed. At least one column of display units in each row of display units can be controlled to display, thereby realizing partitioned driving of the display units.

[0082] Exemplarily, at least one switch subcircuit in the gating subcircuit is coupled to the same control signal line. In this case, the wiring design of the display panel can be simplified. Exemplarily, at least one switch subcircuit in the gating subcircuit receives the same control signal, and at least one switch subcircuit in the gating subcircuit can be turned on or off at the same time.

[0083] In some embodiments, different gating subcircuits are coupled to different control signal lines. In this case, different gating subcircuits receive different control signals, so that the display unit and the driving circuit are turned on at different times, and the display panel is controlled to realize partition display.

[0084] In some embodiments, Fig. 9 As shown, the display panel 100 further includes a plurality of input signal lines STV. The plurality of input signal lines STV are disposed on the substrate 10. The input signal lines are configured to transmit input signals.

[0085] like Fig. 9 As shown, the driving circuit 30 includes a plurality of driving sub-circuits 31. Each driving sub-circuit 31 is coupled to an input signal line STV. The driving sub-circuit 31 includes a plurality of driving signal output terminals OUT. The driving sub-circuit 31 is configured to output a plurality of driving signals from the plurality of driving signal output terminals OUT of the driving sub-circuit 31 according to the input signal transmitted by the input signal line STV. It can be understood that, according to different input signals, different driving sub-circuits can be controlled to output driving signals to control different display units to display.

[0086] Exemplarily, each driving subcircuit can provide a driving signal to a row of display units. When a row of display units is not displaying, that is, the selection subcircuit coupled to each display unit in the row of display units is in an off state, that is, each display unit in the row of display units is not conducting with the driving subcircuit. At this time, the driving subcircuit that provides the driving signal to the row of display units may not work, and there is no input signal transmission on the input signal line coupled to the driving subcircuit that is not working. In this case, there is input signal transmission on the input signal line coupled to the driving subcircuit that provides the driving signal to the display unit that needs to be displayed, these driving subcircuits work, and other driving subcircuits may not work, which can reduce the power consumption of the display panel.

[0087] For example, when the display panel is in a full-screen display state, each sub-pixel in the display panel can be driven row by row; when the display panel is in a partial display state, each sub-pixel in the display panel can be driven row by row to drive each sub-pixel in the display unit to be displayed.

[0088] Exemplarily, along the row direction of the sub-pixel arrangement, a driving circuit 30 may be provided on one of the two relatively outer sides of the AA region, and the display panel 100 outputs a driving signal from a single side through the driving circuit 30, so that the area of ​​the peripheral area S can be reduced and the circuit design of the display panel 100 can be simplified. Exemplarily, along the row direction of the sub-pixel arrangement, two driving circuits 30 may be provided on the two relatively outer sides of the AA region, respectively, in which case, the display panel 100 may adopt a dual-side simultaneous driving, and the two driving circuits 30 output driving signals from both sides at the same time, so that the voltage drop generated by the driving signal during the transmission process can be reduced, thereby improving the display uniformity; or, the display panel 100 may adopt a dual-side cross driving, and the two driving circuits 30 may output driving signals alternately from both sides.

[0089] In some embodiments, Fig. 10A and Fig. 10B As shown, the driving sub-circuit 31 includes a plurality of cascaded shift registers RS (eg Fig. 10B The first stage shift register RS(1), the second stage shift register RS(2), the third stage shift register RS(3)...). The output terminal Oput of each stage shift register is a drive signal output terminal OUT. It can be understood that the output terminal Oput of each stage shift register RS ​​is configured to output a drive signal.

[0090] The input end of the first shift register is coupled to an input signal line. The output end of each shift register except the last shift register is coupled to the input end of the next shift register. Fig. 10B , the input terminal IN of the first-stage shift register RS(1) is coupled to the input signal line STV; the output terminal Oput of the first-stage shift register RS(1) is coupled to the input terminal IN of the second-stage shift register RS(2); the output terminal Oput of the second-stage shift register RS(2) is coupled to the input terminal IN of the third-stage shift register RS(3), and so on, until the input terminal of the last-stage shift register is coupled to the output terminal of the previous-stage shift register of the last-stage shift register.

[0091] It can be understood that the number of shift registers is the same as the number of rows of sub-pixels in the display unit. Each shift register in each driving sub-circuit outputs a driving signal to a row of sub-pixels in the display unit to which the driving sub-circuit is coupled. Fig. 10AWhen the plurality of sub-pixels P in the display unit 20 are arranged in three rows, the driving sub-circuit 31 includes three shift registers RS(1), RS(2) and RS(3) which are cascaded in sequence.

[0092] It should be noted that Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig. 10A Only a schematic diagram of the connection between the pixel island and each circuit is shown, and the actual circuit connection is not limited to this and can be designed according to the actual situation, which is not limited here.

[0093] Exemplarily, the first clock signal terminals of two adjacent cascaded shift registers are respectively coupled to different clock signal lines, and the second clock signal terminals are respectively coupled to different clock signal lines. Fig. 10B , the first clock signal terminal CLK1 in the odd-numbered shift register is coupled to the first clock signal line CLKA, and the second clock signal terminal CLK2 in the odd-numbered shift register is coupled to the second clock signal line CLKB; the first clock signal terminal CLK1 in the even-numbered shift register is coupled to the second clock signal line CLKB, and the second clock signal terminal CLK2 in the even-numbered shift register is coupled to the first clock signal line CLKA. The signal transmitted by the first clock signal line CLKA and the signal transmitted by the second clock signal line CLKB have a certain phase difference; for example, the signal transmitted by the first clock signal line CLKA and the signal transmitted by the second clock signal line CLKB are inverted signals of each other.

[0094] For example, Fig.11 As shown, the shift register RS ​​includes an input subcircuit 121 and an output subcircuit 122. The input subcircuit 121 is coupled to the input signal terminal IN and the pull-up node PU. The output subcircuit 122 is coupled to the pull-up node PU, the first clock signal terminal CLK1 and the output terminal Oput. The input subcircuit 121 is configured to transmit the input signal to the pull-up node PU in response to the input signal received at the input signal terminal IN. The output subcircuit 122 is configured to transmit the first clock signal received at the first clock signal terminal CLK1 to the output terminal Oput in response to the voltage of the pull-up node PU. It can be understood that the signal output by the output terminal Oput is a driving signal.

[0095] For example, Fig.12 As shown, the input sub-circuit 121 includes a first transistor M1. The control electrode and the first electrode of the first transistor M1 are respectively coupled to the input signal terminal IN, and the second electrode of the first transistor M1 is coupled to the pull-up node PU. Fig.12As shown, the output subcircuit 122 includes a second transistor M2 and a first capacitor C1. The control electrode of the second transistor M2 is coupled to the pull-up node PU, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CLK1, and the second electrode of the second transistor M2 is coupled to the output terminal Oput. The first electrode of the first capacitor C1 is coupled to the pull-up node PU, and the second electrode of the first capacitor C2 is coupled to the output terminal Oput.

[0096] For example, Fig.11 As shown, the shift register RS ​​also includes a pull-down control subcircuit 123. The pull-down control subcircuit 123 is coupled to the second clock signal terminal CLK2, the pull-up node PU, the pull-down node PD and the voltage terminal VGL. The pull-down control subcircuit 123 is configured to transmit the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2; and, in response to the voltage of the pull-up node PU, transmit the voltage of the voltage terminal VGL to the pull-down node PD. Exemplarily, the voltage terminal VGL is configured to transmit a DC low-level signal.

[0097] For example, Fig.12 As shown, the pull-down control subcircuit 123 includes a third transistor M3 and a fourth transistor M4. The control electrode and the first electrode of the third transistor M3 are respectively coupled to the second clock signal terminal CLK2, and the second electrode of the third transistor M3 is coupled to the pull-down node PD. The control electrode of the fourth transistor M4 is coupled to the pull-up node PU, the first electrode of the fourth transistor M4 is coupled to the voltage terminal VGL, and the second electrode of the fourth transistor M4 is coupled to the pull-down node PD.

[0098] For example, Fig.11 As shown, the shift register RS ​​also includes a first noise reduction sub-circuit 124. The first noise reduction sub-circuit 124 is coupled to the voltage terminal VGL, the reset signal terminal Rst and the pull-up node PU. The first noise reduction sub-circuit 124 is configured to transmit the voltage of the voltage terminal VGL to the pull-up node PU in response to the reset signal received at the reset signal terminal Rst. In this way, the pull-up node can be noise-reduced in the non-valid output stage of the shift register to avoid signal interference.

[0099] For example, Fig.12 As shown, the first noise reduction sub-circuit 124 includes a fifth transistor M5. A control electrode of the fifth transistor M5 is coupled to the reset signal terminal Rst, a first electrode of the fifth transistor M5 is coupled to the voltage terminal VGL, and a second electrode of the fifth transistor M5 is coupled to the pull-up node PU.

[0100] For example, Fig.11As shown, the shift register RS ​​also includes a second noise reduction subcircuit 125. The second noise reduction subcircuit 125 is coupled to the pull-down node PD, the voltage terminal VGL and the pull-up node PU. The second noise reduction subcircuit 125 is configured to transmit the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD. In this way, the pull-up node can be noise-reduced in the non-valid output stage of the shift register to avoid signal interference.

[0101] For example, Fig.12 As shown, the second noise reduction sub-circuit 125 includes a sixth transistor M6. A control electrode of the sixth transistor M6 is coupled to the pull-down node PD, a first electrode of the sixth transistor M6 is coupled to the voltage terminal VGL, and a second electrode of the sixth transistor M6 is coupled to the pull-up node PU.

[0102] For example, Fig.11 As shown, the shift register RS ​​also includes a third noise reduction sub-circuit 126. The third noise reduction sub-circuit 126 is coupled to the pull-down node PD, the voltage terminal VGL and the output terminal Oput. The third noise reduction sub-circuit 126 is configured to transmit the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD. In this way, the output terminal can be noise-reduced in the non-effective output stage of the shift register to avoid signal interference.

[0103] For example, Fig.12 As shown, the third noise reduction sub-circuit 126 includes a seventh transistor M7. A control electrode of the seventh transistor M7 is coupled to the pull-down node PD, a first electrode of the seventh transistor M7 is coupled to the voltage terminal VGL, and a second electrode of the seventh transistor M7 is coupled to the output terminal Oput.

[0104] For example, Fig.11 As shown, the shift register RS ​​also includes a first voltage stabilizing subcircuit 127. The first voltage stabilizing subcircuit 127 is coupled to the pull-down node PD, the voltage terminal VGL and the output terminal Oput. The first voltage stabilizing subcircuit 127 is configured to transmit the voltage of the voltage terminal VGL to the pull-down node PD in response to the signal received at the output terminal Oput, and control the voltage of the pull-down node PD. Exemplarily, when the signal output by the output terminal Oput is a valid signal (e.g., a high-level signal), the first voltage stabilizing subcircuit 127 transmits the voltage of the voltage terminal VGL to the pull-down node PD, controls the voltage of the pull-down node PD to remain stable (e.g., the voltage of the pull-down node PD remains at a low level), so that the output terminal Oput can be stably output.

[0105] For example, Fig.12As shown, the first voltage stabilizing sub-circuit 127 includes an eighth transistor M8. A control electrode of the eighth transistor M8 is coupled to the output terminal Oput, a first electrode of the eighth transistor M8 is coupled to the voltage terminal VGL, and a second electrode of the eighth transistor M8 is coupled to the pull-down node PD.

[0106] For example, Fig.11 As shown, the shift register RS ​​also includes a second voltage stabilizing subcircuit 128. The second voltage stabilizing subcircuit 128 is coupled to the voltage terminal VGL and the pull-down node PD. The second voltage stabilizing subcircuit 128 is configured to control the voltage of the pull-down node PD according to the voltage of the voltage terminal VGL and the voltage of the pull-down node PD. Exemplarily, when there is no signal input to the pull-down node PD, the voltage of the pull-down node PD is unstable, and the second voltage stabilizing subcircuit 128 can control the voltage of the pull-down node PD, for example, control the voltage of the pull-down node PD to be a high level voltage, so that the voltage of the pull-down node PD remains stable, so as to ensure that the shift register can work normally.

[0107] For example, Fig.12 As shown, the second voltage stabilizing sub-circuit 128 includes a second capacitor C2. A first electrode of the second capacitor C2 is coupled to the voltage terminal VGL, and a second electrode of the second capacitor C2 is coupled to the pull-down node PD.

[0108] Exemplarily, each transistor in the shift register is an N-type transistor. For example, in the first stage of operation of a shift register RS ​​(refer to Fig.13 In the embodiment of the present invention, the input sub-circuit 121 transmits the input signal to the pull-up node PU in response to the input signal received at the input terminal IN, and charges the pull-up node PU. Under the control of the voltage of the pull-up node PU, the output sub-circuit 122 transmits the first clock signal received at the first clock signal terminal CLK1 to the output terminal OUT. For example, the first transistor M1 in the input sub-circuit 121 responds to the high-level input signal, the first transistor M1 is turned on, and the input signal is transmitted to the pull-up node PU, so that the voltage of the pull-up node PU is a high-level voltage, and the first capacitor C1 in the output sub-circuit 122 is charged. The second transistor M2 in the output sub-circuit 122 responds to the high-level voltage of the pull-up node PU, and transmits the low-level first clock signal to the output terminal Oput. At this time, the driving signal output by the output terminal Oput is a low-level signal.

[0109] The pull-down control subcircuit 123 transmits the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2; and, in response to the voltage of the pull-up node PU, transmits the voltage of the voltage terminal VGL to the pull-down node PD. For example, under the control of the high-level second clock signal, the third transistor M3 in the pull-down control subcircuit 123 is turned on to transmit the second clock signal to the pull-down node PD; the fourth transistor M4 is turned on in response to the high-level voltage of the pull-up node PU, and transmits the low-level voltage of the voltage terminal VGL to the pull-down node PD. Since the width-to-length ratio of the channel of the fourth transistor M4 is greater than the width-to-length ratio of the channel of the third transistor M3, the voltage of the pull-down node PD is a low-level voltage.

[0110] In addition, the first noise reduction subcircuit 124, the second noise reduction subcircuit 125 and the third noise reduction subcircuit 126 are all inoperative, that is, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off. The first voltage stabilization subcircuit 127 is also inoperative, that is, the eighth transistor M8 is turned off.

[0111] For example, in the second stage of a shift register RS ​​operation (reference Fig.13 Q2 in the pull-up node PU), under the control of the voltage of the pull-up node PU, the output sub-circuit 122 transmits the first clock signal received at the first clock signal terminal CLK1 to the output terminal Oput. For example, the first transistor M1 in the input sub-circuit 121 is turned off under the control of the low-level input signal. Due to the bootstrap effect of the first capacitor C1, the voltage of the pull-up node PU is still a high-level voltage. The second transistor M2 in the output sub-circuit 122 responds to the high-level voltage of the pull-up node PU and transmits the low-level first clock signal to the output terminal OUT. At this time, the driving signal output by the output terminal Oput is a high-level signal.

[0112] The pull-down control subcircuit 123 transmits the voltage of the voltage terminal VGL to the pull-down node PD in response to the voltage of the pull-up node PU. For example, the third transistor M3 in the pull-down control subcircuit 123 is turned off under the control of the low-level second clock signal; the fourth transistor M4 is turned on when the voltage of the pull-up node PU is high, and the low-level voltage of the voltage terminal VGL is transmitted to the pull-down node PD, so the pull-down node PD is a low-level potential, so that the voltage of the pull-down node PD is a low-level voltage.

[0113] The first voltage stabilizing subcircuit 127 transmits the voltage of the voltage terminal VGL to the pull-down node PD in response to the signal received at the output terminal Oput. For example, the eighth transistor M8 in the first voltage stabilizing subcircuit 127 transmits the low-level voltage of the voltage terminal VGL to the pull-down node PD in response to the high-level signal received at the output terminal Oput. At this time, the voltage of the pull-down node PD is a low-level voltage.

[0114] In addition, the first noise reduction sub-circuit, the second noise reduction sub-circuit and the third noise reduction sub-circuit are all inoperative.

[0115] For example, in the third stage of a shift register RS ​​operation (reference Fig.13 The first noise reduction sub-circuit 124 transmits the voltage of the voltage terminal VGL to the pull-up node PU in response to the reset signal received at the reset signal terminal Rst. For example, the fifth transistor M5 in the first noise reduction sub-circuit 124 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level reset signal.

[0116] The pull-down control subcircuit 123 transmits the second clock signal to the pull-down node PD in response to the second clock signal received at the second clock signal terminal CLK2. For example, under the control of the high-level second clock signal, the third transistor M3 in the pull-down control subcircuit 123 is turned on, and the high-level second clock signal is transmitted to the pull-down node PD, so that the voltage of the pull-down node PD is a high-level voltage; the fourth transistor M4 is turned off under the control of the low-level voltage of the pull-up node PU, and at this time, the voltage of the pull-down node PD is a high-level voltage.

[0117] The second noise reduction sub-circuit 125 transmits the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD. For example, the sixth transistor M6 in the second noise reduction sub-circuit 125 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level voltage of the pull-down node PD. At this time, the voltage of the pull-up node PU is a low-level voltage. In this case, the second transistor M2 in the output sub-circuit 122 is controlled by the low-level voltage of the pull-up node PU, and the second transistor M2 is turned off, and the first clock signal will not be output. At this time, the third noise reduction sub-circuit 127 transmits the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD. For example, the eighth transistor M8 in the third noise reduction sub-circuit 127 transmits the low-level voltage of the voltage terminal VGL to the output terminal Oput in response to the high-level voltage of the pull-down node PD, so that the low-level signal output by the output terminal Oput, that is, the drive signal is a low-level signal.

[0118] For example, in the fourth stage of a shift register RS ​​operation (reference Fig.13Q4 in the pull-down control subcircuit 123), the third transistor M3 in the pull-down control subcircuit 123 is turned off under the control of the low-level second clock signal; and the voltage of the pull-up node PU is the low-level voltage of the previous stage, and the fourth transistor M4 is turned off under the control of the low-level voltage of the pull-up node PU. In this case, the third transistor M3 will not transmit the second clock signal to the pull-down node PD, and the fourth transistor M4 will not transmit the voltage of the voltage terminal VGL to the pull-down node PD. At this time, the voltage of the pull-down node PD is unstable. The second voltage stabilizing subcircuit 128 controls the voltage of the pull-down node PD according to the voltage of the pull-down node PD and the voltage of the voltage terminal VGL. For example, due to the storage effect of the second capacitor C2 in the second voltage stabilizing subcircuit 128, according to the low-level voltage of the voltage terminal VGL, the voltage of the pull-down node PD is controlled to be a high-level voltage.

[0119] The fifth transistor M5 in the first noise reduction sub-circuit 124 is in a cut-off state under the control of a low-level reset signal. The second noise reduction sub-circuit 125 transmits the voltage of the voltage terminal VGL to the pull-up node PU in response to the voltage of the pull-down node PD. For example, the sixth transistor M6 in the second noise reduction sub-circuit 125 transmits the low-level voltage of the voltage terminal VGL to the pull-up node PU in response to the high-level voltage of the pull-down node PD. At this time, the voltage of the pull-up node PU is a low-level voltage. In this case, the second transistor M2 in the output sub-circuit 122 is controlled by the low-level voltage of the pull-up node PU, and the second transistor M2 is cut off, and the first clock signal will not be output. At this time, the third noise reduction sub-circuit 127 transmits the voltage of the voltage terminal VGL to the output terminal Oput in response to the voltage of the pull-down node PD. For example, the eighth transistor M8 in the third noise reduction sub-circuit 127 transmits the low level voltage of the voltage terminal VGL to the output terminal Oput in response to the high level voltage of the pull-down node PD, so that the low level signal output by the output terminal Oput, that is, the driving signal is a low level signal.

[0120] In some embodiments, in the driving sub-circuit, except for the first stage shift register, the output terminal of each stage shift register is coupled to the reset signal terminal of the previous stage shift register. Fig. 10BIn the driving sub-circuit 31, the output terminal Oput of the second-stage shift register RS(2) is coupled to the reset signal terminal Rst of its previous-stage shift register, i.e., the first-stage shift register RS(1); the output terminal Oput of the third-stage shift register RS(3) is coupled to the reset signal terminal Rst of its previous-stage shift register, i.e., the second-stage shift register RS(2). It can be understood that at the stage where each stage of the shift register outputs a valid signal, the previous-stage shift register is reset. Exemplarily, the reset signal terminal of the last-stage shift register in the driving sub-circuit can be coupled to the reset signal line in the display panel to reset the last-stage shift register.

[0121] In some embodiments, Fig.14 As shown, the display panel 100 includes a plurality of data lines DL. The plurality of data lines DL are disposed on the substrate 10. Exemplarily, the extension direction of the plurality of data lines is parallel to the column direction of the sub-pixels, the column direction of the pixel islands 21, and the column direction of the display units 20; for example, referring to Fig.14 , a plurality of data lines extend along the Y direction. It can be understood that the data lines are configured to transmit data signals.

[0122] like Fig.15 As shown, the sub-pixel P includes a pixel circuit 110. The pixel circuit 110 includes a data writing sub-circuit 111. The data writing sub-circuit 111 is coupled to the gating circuit 40 and a data line DL. Exemplarily, in the case where the gating circuit 40 includes a gating sub-circuit 41, the data writing sub-circuit 111 in the pixel circuit 110 in each sub-pixel in a display unit 20 is coupled to a gating sub-circuit 41; in the case where the gating sub-circuit 41 includes a switch sub-circuit 411, the data writing sub-circuit 111 in the pixel circuit 110 in a row of sub-pixels in a display unit 20 is coupled to a switch sub-circuit 411; in the case where the switch sub-circuit 411 includes a gating transistor MK, the second electrode of the gating transistor MK is coupled to the data writing sub-circuit 111. The gating circuit 40 is coupled to the driving circuit 30, and the gating circuit 40 can transmit a driving signal from the driving circuit 30. The data writing sub-circuit 111 is configured to write the data signal transmitted by the data line DL in response to a driving signal from the gating circuit 40. The gating circuit controls the data writing sub-circuit and the driving circuit to form a conductive path. Exemplarily, a column of sub-pixels in a column of display units is coupled to the same data line.

[0123] For example, Fig.12As shown, the pixel circuit includes a light-emitting driving subcircuit 112, which is coupled to the data writing subcircuit 111 and the first power supply voltage terminal VDD. The light-emitting driving subcircuit 112 is configured to output a driving current. The light-emitting driving subcircuit 112 is also coupled to the light-emitting device L. The light-emitting driving subcircuit 112 can transmit the driving circuit to the light-emitting device L to drive the light-emitting device L to emit light. For example, referring to Fig.16 The light emitting driving sub-circuit 112 includes a driving transistor MD and a storage capacitor Cst.

[0124] For example, reference Fig.16 , the data writing sub-circuit 111 includes a data writing transistor MA. The control electrode of the data writing transistor MA is coupled to the gating circuit 40, the first electrode of the data writing transistor MA is coupled to the data line DL, and the second electrode of the data writing transistor MA is coupled to the light emitting driving sub-circuit 112, for example, the second electrode of the data writing transistor MA is coupled to the driving transistor MD in the light emitting driving sub-circuit 112; for example, the second electrode of the data writing transistor MA is coupled to the control electrode of the driving transistor MD. Exemplarily, referring to Fig.17 In the case where the switch sub-circuit 411 includes the gate transistor MK, the control electrode of the data writing transistor MA is coupled to the second electrode of the gate transistor MK.

[0125] For example, refer to Fig.16 , the control electrode (gate) of the data writing transistor MA is used to receive a driving signal (i.e., a gate driving signal). Under the control of the driving signal, the data writing transistor MA is turned on. At this time, the data signal is written to the control electrode of the driving transistor MD through the transistor M1. The first electrode of the driving transistor MD receives the first power supply voltage of the first power supply voltage terminal VDD. When the voltage difference between the control electrode and the first electrode of the driving transistor MD meets the turning-on condition of the driving transistor MD, the driving transistor MD generates a driving current, and transmits the driving current to the light-emitting device L to drive the light-emitting device L to emit light. Exemplarily, one electrode (e.g., an anode) of the light-emitting device L receives the driving current from the pixel circuit, and the other electrode (e.g., a cathode) of the light-emitting device L is coupled to the second power supply voltage terminal VSS. For example, the first power supply voltage of the first power supply voltage terminal and the second power supply voltage of the second power supply voltage terminal are both DC voltages; for example, the first power supply voltage is a DC high voltage, and the second power supply voltage is a DC low voltage.

[0126] It should be noted that the transistors used in the various circuits (such as the driving circuit, the gating circuit, and the pixel circuit) provided in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (FET), complementary metal oxide semiconductors (CMOS), or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto. For example, when the substrate of the display panel is a silicon-based substrate, the transistors may be CMOS tubes.

[0127] In some embodiments, the control electrode of each transistor described herein is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain thereof may be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure may be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0128] In the circuit provided by the embodiments of the present disclosure, the various nodes described in the text (such as pull-up nodes and pull-down nodes, etc.) do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0129] In the circuits provided in the embodiments of the present disclosure, for example, the various circuits described herein include: a driving circuit, a driving subcircuit in a driving circuit, a shift register in a driving subcircuit, a gating circuit, a gating subcircuit in a gating circuit, a switch subcircuit in a gating subcircuit, a pixel circuit, a data writing subcircuit in a pixel circuit, and a light-emitting driving subcircuit, etc. The specific implementation methods are not limited to the methods described above, and they can be any implementation methods used, such as conventional connection methods well known to those skilled in the art, as long as the corresponding functions are achieved. The above examples do not limit the scope of protection of the present disclosure. In actual applications, technicians can choose to use or not use one or more of the above circuits according to the circumstances. Various combination variations based on the aforementioned circuits do not deviate from the principles of the present disclosure, and will not be described in detail.

[0130] It should be noted that, for the convenience of description, the embodiments of the present disclosure use the same symbols to represent some signal terminals, signals transmitted by some signal terminals, and signal lines coupled to some signal terminals, but their properties are different.

[0131] In some embodiments, Fig.18A and Fig.18B As shown, the display panel 100 further includes an optical film 50. The optical film 50 is disposed on a side of the plurality of display units 20 away from the substrate 10, that is, along a direction perpendicular to the plane where the display panel 100 is located (eg Fig.18B The optical film 50 is further away from the substrate 10 than the plurality of display units 20. The optical film 50 is configured to refract the light emitted from each sub-pixel P in each pixel island 21 in the display unit 20 in the display panel 100 to disperse the light to the plurality of pixel regions H (refer to Fig.19 ).

[0132] Among them, a pixel area refers to the area where a pixel is located; the light emitted by the pixel is composed of the light emitted by sub-pixels of different colors, and the sub-pixels of different colors come from different pixel islands. For example, the red light emitted by the red sub-pixel in the display unit is refracted by the optical film to be dispersed to multiple pixel areas; the green light emitted by the green sub-pixel in the display unit is refracted by the optical film to be dispersed to multiple pixel areas; the blue light emitted by the blue sub-pixel in the display unit is refracted by the optical film to be dispersed to multiple pixel areas. For example, after the light of different colors emitted by sub-pixels of different colors is refracted by the optical film, it is superimposed on each other in a direction perpendicular to the plane where the display panel is located, and converges to the same pixel area to achieve grayscale display. In this case, the size of the pixel area is the same as the size of the sub-pixel, which can increase the design space of the circuit for driving the sub-pixel to emit light, and can also facilitate the improvement of the PPI of the display panel. Or, for example, after the light of different colors emitted by sub-pixels of different colors is refracted by the optical film, it is arranged at intervals in a direction parallel to the plane where the display panel is located and converges to the same pixel area to achieve grayscale display. In this case, the size of the pixel area is approximately n times the size of the sub-pixel, and n represents the number of sub-pixels converged in the same pixel area.

[0133] Exemplarily, the optical film includes a microlens film. Light emitted by each sub-pixel in the display unit is refracted through the microlens film and dispersed to multiple pixel areas. Exemplarily, the microlens film includes a plurality of microlenses arranged in sequence, for example, one microlens corresponds to a sub-pixel position, or, for example, one microlens corresponds to a pixel island position, and the microlens can refract light emitted by the corresponding sub-pixel to multiple pixel areas.

[0134] It should be noted that the optical film can be designed according to actual conditions so that the light refracted by the optical film is dispersed to a plurality of designated pixel areas. Fig.19 , a plurality of pixel regions H are included in the to-be-displayed region T; for example, the to-be-displayed region may be a region where a user views the display device (or display panel).

[0135] In the display device provided by the present disclosure, if Fig. 20 As shown, the display device further includes a processing device 210. Exemplarily, the processing device 210 is coupled to the display panel 100. Exemplarily, the processing device includes a timing controller (TimingController, TCON).

[0136] The processing device is configured to output at least one control signal to the selection circuit in the display panel according to the information of the area to be displayed of the display panel, so as to control the driving circuit in the display panel and at least one display unit corresponding to the area to be displayed in the display panel to be turned on; and, according to the information of the area to be displayed of the display panel, output at least one input signal to the driving circuit in the display panel, so that the driving circuit outputs at least one driving signal to the at least one display unit corresponding to the area to be displayed in the display panel, so that the area to be displayed is displayed.

[0137] Among them, if the display area (for example, multiple pixel areas) of at least one display unit for display is the same as or corresponds to the area to be displayed, then the at least one display unit is at least one display unit corresponding to the area to be displayed.

[0138] In this case, the processing device outputs at least one control signal to the gating circuit according to the information of the area to be displayed of the display panel, and the control signal received by the gating circuit (for example, the gating subcircuit in the gating circuit) controls at least one display unit corresponding to the area to be displayed and the driving circuit to be turned on, so that at least one display unit corresponding to the area to be displayed can receive the driving signal from the driving circuit. In addition, the processing device outputs at least one input signal to the driving circuit according to the information of the area to be displayed of the display panel, so that the driving circuit (for example, the driving subcircuit in the driving circuit) that is turned on with at least one display unit corresponding to the area to be displayed receives the input signal and outputs at least one driving signal. In this way, at least one display unit corresponding to the area to be displayed can receive the driving signal, so that at least one display unit that receives the driving signal performs display, thereby realizing display of the area to be displayed. In this case, the display panel realizes partitioned drive and partitioned display, saving power consumption of the display device.

[0139] In some embodiments, Fig. 20As shown, the display device 200 also includes an information collection device 220. For example, the information collection device 220 is coupled to the processing device 210. The information collection device is configured to collect user sight information. The processing device is also configured to obtain the user sight information, and determine the information of the to-be-displayed area of ​​the display panel according to the user sight information.

[0140] Exemplarily, the information collection device may be any device with a line of sight collection function, such as a camera, an eye tracker, etc.

[0141] It is understandable that the information collection device collects user sight information and sends the user sight information to the processing device. The processing device obtains the user sight information and determines the information of the area to be displayed of the display panel according to the user sight information. For example, the information of the area to be displayed includes the position and size of the area to be displayed. For example, according to the information of the area to be displayed, at least one display unit corresponding to the area to be displayed can be obtained.

[0142] Therefore, according to the actual viewing situation of the user, the information of the area to be displayed can be obtained, the display unit corresponding to the area to be displayed can be determined, and the display unit can be driven to display the area to be displayed. In this way, the display area of ​​the display device can be adjusted according to the actual viewing situation of the user, so that the display device is in a partial display state or a full-screen display state, thereby meeting the user's usage requirements while reducing the power consumption of the display device.

[0143] Exemplarily, the display device further includes a driver chip. For example, the driver chip is a driver IC, for example, the driver IC includes a source driver. For example, the driver chip is configured to provide a driving signal to each sub-pixel in the display panel; for example, the driving signal includes a data signal.

[0144] An embodiment of the present disclosure provides a method for driving a display panel. The display panel is the display panel in any of the above embodiments. The driving method includes:

[0145] According to the information of the area to be displayed of the display panel, at least one input signal is output to the driving circuit in the display panel, so that the driving circuit responds to the at least one input signal and outputs at least one driving signal to at least one display unit corresponding to the area to be displayed.

[0146] Exemplarily, when the driving circuit includes a driving subcircuit, the driving subcircuit receives an input signal and outputs a driving signal. Exemplarily, when the driving subcircuit includes a shift register, the shift register outputs a driving signal. Exemplarily, the input signal is output to the driving subcircuit in the driving circuit coupled to the display unit corresponding to the area to be displayed, and the input signal is not output to the driving subcircuit coupled to the remaining display units, so as to reduce power consumption.

[0147] According to the information of the area to be displayed of the display panel, at least one control signal is output to the selection circuit in the display panel, so that the selection circuit controls the driving circuit to be connected to at least one display unit corresponding to the area to be displayed among the multiple display units according to the at least one control signal, so that the at least one display unit receives at least one driving signal from the driving circuit and drives the at least one display unit corresponding to the area to be displayed to display.

[0148] Exemplarily, in the case where the gating circuit includes a plurality of gating subcircuits, at least one gating subcircuit receives at least one control signal to connect at least one display unit to the driving circuit. Exemplarily, in the case where the gating subcircuit includes a switch subcircuit, a switch subcircuit in the gating subcircuit receives a control signal to connect each row of sub-pixels in the display unit to the driving circuit. Exemplarily, a control signal is output to a gating subcircuit in the gating circuit coupled to the display unit corresponding to the area to be displayed, and a control signal is not output to the gating subcircuit coupled to the remaining display units, so as to reduce power consumption.

[0149] In this case, in the display panel, at least one display unit corresponding to the area to be displayed is displayed, and the other display units are not displayed, so that the area to be displayed is in a display state, and the other areas are in a non-display state, that is, part of the display panel is displayed, and part of the area is not displayed, thereby realizing partition control of the display unit and reducing the power consumption of the display panel.

[0150] In some embodiments, the driving method further includes: obtaining user sight information; and determining information of a to-be-displayed area of ​​the display panel according to the user sight information. In this way, the display of the display panel can meet the actual viewing situation of the user, thereby improving the user experience.

[0151] It should be noted that the beneficial effects of the above-mentioned display panel driving method are the same as the beneficial effects of the display panel and the display device described in some of the above-mentioned embodiments. Please refer to the description of the corresponding parts and will not be repeated here.

[0152] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel having a display area; the display panel comprising: Substrate, A plurality of display units are disposed on the substrate and located in the display area, each display unit includes a plurality of pixel islands, and each pixel island includes a plurality of sub-pixels of the same color; The sub-pixel includes a light-emitting device; the light-emitting device includes a light-emitting layer; the light-emitting layers of the light-emitting devices in the plurality of sub-pixels in one pixel island have no gaps; A driving circuit is disposed on the substrate and outside the display area; the driving circuit is configured to output a plurality of driving signals; A gating circuit is arranged on the substrate, located in the display area and outside the multiple display units; the gating circuit is coupled to the driving circuit, and the gating circuit is also coupled to at least one display unit; the gating circuit is configured to control the driving circuit to be connected to the at least one display unit, so that the at least one display unit drives the multiple sub-pixels in the multiple pixel islands in the at least one display unit to display according to at least one driving signal from the driving circuit.

2. The display panel according to claim 1, further comprising: A plurality of control signal lines are arranged on the substrate; The driving circuit comprises: a plurality of driving signal output terminals; the plurality of driving signal output terminals are configured to output the plurality of driving signals; The gating circuit comprises: a plurality of gating sub-circuits; one gating sub-circuit is coupled to at least one control signal line, a display unit and at least one driving signal output terminal; The gating subcircuit is configured to transmit at least one driving signal received at the at least one driving signal output terminal to a plurality of sub-pixels in each pixel island in the display unit in response to a control signal transmitted by the at least one control signal line.

3. The display panel according to claim 2, wherein: The display unit includes at least one row of sub-pixels; The gating subcircuit comprises: At least one switch subcircuit; a switch subcircuit is coupled to a control signal line, a drive signal output terminal and a row of sub-pixels in the display unit; the switch subcircuit is configured to transmit a drive signal received at the drive signal output terminal to a row of sub-pixels coupled to the switch subcircuit in response to a control signal transmitted by the control signal line.

4. The display panel according to claim 3, wherein: The multiple display units are arranged in an array; In each display unit in a row of display units, the switch sub-circuit to which the sub-pixels in the same row are respectively coupled is coupled to the same driving signal output terminal.

5. The display panel according to claim 3 or 4, wherein: At least one switch subcircuit in the gating subcircuit is coupled to the same control signal line.

6. The display panel according to claim 3, wherein: The switch subcircuit comprises: A gate transistor; a control electrode of the gate transistor is coupled to the control signal line, a first electrode of the gate transistor is coupled to the drive signal output terminal, and a second electrode of the gate transistor is coupled to a row of sub-pixels in the display unit.

7. The display panel according to claim 2, wherein: Different gating sub-circuits are coupled to different control signal lines.

8. The display panel according to claim 2, further comprising: A plurality of input signal lines are arranged on the substrate; The driving circuit comprises: A plurality of driving sub-circuits, each driving sub-circuit being coupled to an input signal line, and the driving sub-circuit comprising a plurality of driving signal output terminals; The driving sub-circuit is configured to output a plurality of driving signals from a plurality of driving signal output terminals of the driving sub-circuit according to the input signal transmitted by the input signal line.

9. The display panel according to claim 8, wherein: The driving subcircuit comprises a plurality of cascaded shift registers; the output end of each stage of the shift register is a driving signal output end; An input terminal of the first stage shift register is coupled to an input signal line; The output terminal of each stage of shift register except the last stage of shift register is coupled to the input terminal of the next stage of shift register.

10. The display panel according to claim 1, further comprising: A plurality of data lines are arranged on the substrate; The sub-pixel includes a pixel circuit; The pixel circuit includes a data writing subcircuit; The data writing sub-circuit is coupled to the gating circuit and a data line; the data writing sub-circuit is configured to write a data signal transmitted by the data line in response to a driving signal from the gating circuit.

11. The display panel according to claim 1, further comprising: An optical film is disposed on a side of the plurality of display units away from the substrate; The optical film is configured to refract light emitted from each sub-pixel in each pixel island in a display unit in the display panel to disperse the light to a plurality of pixel regions.

12. A display device, comprising: The display panel according to any one of claims 1 to 11.

13. The display device according to claim 12, further comprising: Processing device; The processing device is configured to output at least one control signal to a gating circuit in the display panel according to information of the area to be displayed of the display panel, so as to control the driving circuit in the display panel and at least one display unit in the display panel corresponding to the area to be displayed to be turned on; And, according to the information of the area to be displayed of the display panel, at least one input signal is output to the driving circuit in the display panel, so that the driving circuit outputs at least one driving signal to at least one display unit corresponding to the area to be displayed.

14. The display device according to claim 13, further comprising: An information collection device configured to collect user sight information; The processing device is further configured to obtain the user sight line information, and determine information of the to-be-displayed area of ​​the display panel according to the user sight line information.

15. A method for driving a display panel according to any one of claims 1 to 11, comprising: Outputting at least one input signal to a driving circuit in the display panel according to information of the area to be displayed of the display panel, so that the driving circuit outputs at least one driving signal to at least one display unit corresponding to the area to be displayed in response to the at least one input signal; According to the information of the area to be displayed of the display panel, at least one control signal is output to the selection circuit in the display panel, so that the selection circuit controls the driving circuit to be connected to at least one display unit corresponding to the area to be displayed among the multiple display units according to the at least one control signal, so that the at least one display unit receives at least one driving signal from the driving circuit and drives the at least one display unit corresponding to the area to be displayed to display.

16. The driving method according to claim 15, further comprising: Get user's sight information; Information of a to-be-displayed area of ​​the display panel is determined according to the user sight line information.

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