Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate (201), a driving circuit layer, a light-emitting layer and a touch layer arranged on the substrate (201); in a direction away from the substrate (201), a first reset transistor (T1) is at least partially covered by a first light shielding structure, the first light shielding structure comprising a power signal line (VDD); and in a direction away from the substrate (201), the first reset transistor (T1) is at least partially covered by a second light shielding structure, the second light shielding structure comprising an anode of the light-emitting layer or a metal trace (250) of the touch layer. The reliability of the first reset transistor (T1) can be improved, and the display effect can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] In a driving process, a display substrate usually needs to set a transmission of a thin film transistor (TFT) control signal, an active layer of the TFT includes a semiconductor material, and the semiconductor material is sensitive to light. SUMMARY

[0003] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a substrate, a driving circuit layer, a light emitting layer and a touch layer disposed on the substrate.

[0004] The driving circuit layer includes at least a driving transistor, a first reset transistor, a compensation control transistor, a reset control line, an initialization signal line, a switch control line, a light emitting control signal line, a data signal line and a power signal line; the driving transistor, the first reset transistor and the compensation control transistor each include a control terminal, a first electrode and a second electrode; the light emitting layer includes a light emitting element corresponding to each sub-pixel; wherein,

[0005] The first electrode of the driving transistor is electrically connected to the power signal line, and the second electrode thereof is coupled to the corresponding light emitting element.

[0006] The control terminal of the first reset transistor is connected to the reset control line, the first electrode thereof is coupled to the initialization signal line, and the second electrode thereof is coupled to the control terminal of the driving transistor.

[0007] The control terminal of the compensation control transistor is coupled to the switch control line, the first electrode thereof is coupled to the second electrode of the driving transistor, and the second electrode thereof is coupled to the control terminal of the driving transistor.

[0008] In a direction away from the substrate, the first reset transistor is at least partially covered by a first light shielding structure, and the first light shielding structure includes the power signal line; and

[0009] In a direction away from the substrate, the first reset transistor is at least partially covered by a second light shielding structure, and the second light shielding structure includes an anode of the light emitting layer or a metal trace of the touch layer.

[0010] Optionally, the first light shielding structure shields the second electrode of the first reset transistor.

[0011] Optionally, the second light shielding structure shields the first electrode of the first reset transistor.

[0012] Optionally, the display substrate includes a green sub-pixel, a projection of the first reset transistor on the substrate substrate overlaps with a projection of the green sub-pixel on the substrate substrate, and the second light shielding structure is an anode of the green sub-pixel.

[0013] Optionally, the display substrate includes a green sub-pixel, a projection of the first reset transistor on the substrate substrate is located between projections of two adjacent green sub-pixels on the substrate substrate, and the second light shielding structure is a metal trace of the touch layer.

[0014] Optionally, a width of the metal trace of the touch layer is greater in a portion between two adjacent green sub-pixels than in a portion outside the two adjacent green sub-pixels.

[0015] Optionally, the active layer of the first reset transistor includes a first semiconductor portion and a second semiconductor portion arranged in a spaced manner, and a first conductor portion coupled to the first semiconductor portion and the second semiconductor portion, respectively, the first conductor portion is covered by a third light shielding structure, the third light shielding structure includes at least one of the reset control line and the initialization signal line.

[0016] Optionally, the drive circuit layer includes an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer, and the power supply signal line is located in the first source-drain metal layer.

[0017] In a direction away from the substrate substrate, at least part of the first conductor portion is shielded by the power supply signal line.

[0018] Optionally, the drive circuit layer further includes a second source-drain metal layer.

[0019] In a direction away from the substrate substrate, at least part of the first reset transistor is covered by the second source-drain metal layer.

[0020] Optionally, the second source-drain metal layer includes a power supply compensation signal line, the power supply compensation signal line has a shielding area corresponding to the first reset transistor, and in a direction away from the substrate substrate, at least part of the first reset transistor is covered by the reset control line.

[0021] Optionally, the active layer of the compensation control transistor includes a third semiconductor portion and a fourth semiconductor portion arranged in a spaced manner, and a second conductor portion coupled to the third semiconductor portion and the fourth semiconductor portion, respectively.

[0022] In a direction away from the substrate substrate, the second conductor portion is covered by the second light shielding structure.

[0023] Optionally, the display substrate further comprises a shielding structure, the driving circuit layer comprises an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer, and the shielding structure is located on the second gate metal layer.

[0024] In a direction away from the substrate, the second conductor portion is covered by the shielding structure.

[0025] Optionally, the display substrate comprises a red sub-pixel, the second light shielding structure comprises an anode of the red sub-pixel, the anode of the red sub-pixel is a rounded rectangle, the red sub-pixel comprises a target red sub-pixel, the anode of the target red sub-pixel further comprises a protruding portion, and in a direction away from the substrate, the protruding portion covers one compensation control transistor.

[0026] Optionally, the first reset transistor is covered by the first light shielding structure in an overlapping area and by the second light shielding structure in an overlapping area.

[0027] Optionally, the first reset transistor is covered by the first light shielding structure in an overlapping area and by the second light shielding structure in an overlapping area.

[0028] Based on the above technical solutions of the display panel, the second aspect of the present disclosure provides a display device comprising the display substrate of any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A circuit diagram of a pixel driving circuit of a sub-pixel in an embodiment of the present disclosure;

[0030] Figure 2 A structure diagram of an active layer in at least one embodiment of the present disclosure;

[0031] Figure 3 A structure diagram of a display substrate in at least one embodiment of the present disclosure;

[0032] Figure 4 A structure diagram of a display substrate in at least one embodiment of the present disclosure; Figure 3 A structure diagram of a first gate metal layer in at least one embodiment of the present disclosure;

[0033] Figure 5 A structure diagram of a display substrate in at least one embodiment of the present disclosure;

[0034] Figure 6 A structure diagram of a display substrate in at least one embodiment of the present disclosure; Figure 5 A structure diagram of a second gate metal layer in at least one embodiment of the present disclosure;

[0035] Figure 7 A structure diagram of a display substrate in at least one embodiment of the present disclosure;

[0036] Figure 8 A structure diagram of a display substrate in at least one embodiment of the present disclosure;Figure 7 Structure diagram of first source-drain metal layer structure;

[0037] Figure 9 Structure diagram of display substrate in at least one embodiment of the present disclosure;

[0038] Figure 10 Structure diagram of display substrate in at least one embodiment of the present disclosure; Figure 9 Structure diagram of M-M' direction section view;

[0039] Figure 11 Structure diagram of N-N' direction section view; Figure 9 Structure diagram of N-N' direction section view;

[0040] Figure 12 Structure diagram of display substrate in at least one embodiment of the present disclosure;

[0041] Figure 13 Structure diagram of display substrate in at least one embodiment of the present disclosure; Figure 12 Structure diagram of metal trace of touch layer;

[0042] Figure 14 Structure diagram of anode of target red sub-pixel in at least one embodiment of the present disclosure;

[0043] Figure 15 Structure diagram of display substrate in at least one embodiment of the present disclosure;

[0044] Figure 16 Structure diagram of display substrate in at least one embodiment of the present disclosure; Figure 15 Structure diagram of second source-drain metal layer structure. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present disclosure.

[0046] The display substrate provided in the embodiments of the present disclosure comprises a substrate and a driving circuit layer on the substrate.

[0047] As shown in the drawings, Figure 1 Structure diagram of pixel driving circuit in an embodiment of the present disclosure, which is specifically a 7T1C pixel driving circuit. The driving circuit of each sub-pixel comprises a total of 7 TFTs (Thin Film Transistor), a storage capacitor Cst and a light emitting element EL. Figure 1

[0048] Figure 1 ​T1 to T7 shown are seven TFTs, each of which includes a control terminal, a first pole and a second pole. The control terminal of the TFT can be the gate of the TFT, and the first pole and the second pole of the TFT are the source and the drain, respectively, or the drain and the source, respectively.

[0049] In some embodiments, the driving circuit layer further includes a reset control line Reset_n, an initialization signal line Vint_n, a switch control line Gate_n, a light-emitting control signal line EM_n, a data signal line VData and a power signal line VDD.

[0050] As shown in FIG. 1, in one embodiment, the pixel driving circuit of each sub-pixel specifically includes: Figure 1

[0051] A first reset transistor T1, the control terminal of the first reset transistor T1 is coupled with the reset control line Reset_n, please also refer to FIG. 1, the first pole T1P1 of the first reset transistor T1 is coupled with the initialization signal line Vint_n, and the second pole T1P2 of the first reset transistor T1 is coupled with the first node N1. Figures 1 to 4

[0052] A compensation control transistor T2, please also refer to FIG. 1, the control terminal of the compensation control transistor T2 is coupled with the switch control line Gate_n, as shown in FIG. 1, Figures 1 to 4 Figure 1 Figure 3 Figure 4 The first pole T2P1 of the compensation control transistor T2 is coupled with the second node N2, and the second pole T2P2 of the compensation control transistor T2 is coupled with the first node N1.

[0053] A driving transistor T3, the control terminal of the driving transistor T3 is coupled with the first node N1, the first pole of the driving transistor T3 is coupled with the third node N3, and the second pole of the driving transistor T3 is coupled with the second node N2.

[0054] A switch transistor T4, the control terminal of the switch transistor T4 is coupled with the switch control line Gate_n, the first pole S4 of the switch transistor T4 is coupled with the data signal line VData, and the second pole D4 of the switch transistor T4 is coupled with the third node N3.

[0055] A first light-emitting control transistor T5, the control terminal of the first light-emitting control transistor T5 is coupled with the light-emitting control signal line EM_n, the first pole of the first light-emitting control transistor T5 is coupled with the power signal line VDD, and the second pole of the first light-emitting control transistor T5 is coupled with the third node N3.

[0056] ​​​​​The second light-emitting control transistor T6 has its control terminal coupled to the light-emitting control signal line EM_n, its first electrode coupled to the second node N2, and its second electrode coupled to the anode of the corresponding light-emitting element EL.

[0057] The second reset transistor T7 has its control terminal coupled to the reset control line Reset_n+1 in the adjacent next row of sub-pixels, its second terminal coupled to the anode of the corresponding light-emitting element EL, and its first terminal coupled to the initialization signal line Vint_n+1 in the adjacent next row of sub-pixels.

[0058] It should be noted that in this embodiment, the current row sub-pixel is taken as an example of a sub-pixel in the nth row of the display panel. In this way, the reset control line Reset_n and the initialization signal line Vint_n refer to the reset control line and the initialization signal line corresponding to the nth row sub-pixel, respectively. Correspondingly, the previous row sub-pixel adjacent to the current row is the (n-1)th row sub-pixel, and the reset control line and the initialization signal line corresponding to the (n-1)th row sub-pixel are the reset control line Reset_n-1 and the initialization signal line Vint_n-1, respectively. The next row sub-pixel adjacent to the current row is the (n+1)th row sub-pixel, and the reset control line and the initialization signal line corresponding to the (n+1)th row sub-pixel are the reset control line Reset_n+1 and the initialization signal line Vint_n+1, respectively.

[0059] like Figure 4 As shown, in an optional embodiment, the first plate Cst1 of the storage capacitor Cst is coupled to the gate T3G of the driving transistor T3. Therefore, the gate T3G of the driving transistor T3 can also be reused as the first plate Cst1 of the storage capacitor Cst, as shown. Figure 5 and Figure 6 As shown, the second plate Cst2 of the storage capacitor Cst is graphically coupled to the power signal line VDD. Here, the gate T3G of the driving transistor T3 can also be referred to as the control terminal of the driving transistor T3.

[0060] The cathode of the light-emitting element EL is coupled to the common power line VSS.

[0061] In the direction away from the substrate, the first reset transistor T1 is at least partially covered by a first light-shielding structure, the first light-shielding structure including the power signal line VDD; and,

[0062] In the direction away from the substrate, the first reset transistor T1 is at least partially covered by the second light-shielding structure, which includes the anode of the light-emitting element EL or the metal trace 250 of the touch layer.

[0063] In this embodiment, the first reset transistor T1 is at least partially covered by the first light-shielding structure and the second light-shielding structure. It can be understood that the orthographic projection of the first reset transistor T1 on the substrate overlaps with the orthographic projections of the first light-shielding structure and the second light-shielding structure on the substrate, and the first light-shielding structure and the second light-shielding structure are both located on the side of the first reset transistor T1 away from the substrate.

[0064] In this embodiment, the first light-shielding structure includes a power signal line VDD, and the second light-shielding structure includes the anode of the light-emitting layer or the metal trace 250 of the touch layer. In practice, the first reset transistor T1 is blocked by adjusting the position and structure of the power signal line VDD and the anode of the light-emitting layer or the metal trace of the touch layer.

[0065] In this way, external light cannot directly shine on the first reset transistor T1 because it is blocked by the first and second light-shielding structures, thereby reducing the potential impact of external light on the performance of the first reset transistor T1 and improving the reliability of the display panel.

[0066] It should be understood that, in this embodiment, the first and second light-shielding structures that block the first reset transistor T1 may or may not overlap. In other words, the orthographic projections of the first and second light-shielding structures that block the first reset transistor T1 onto the substrate may partially overlap or not overlap at all.

[0067] In some embodiments of this disclosure, the display substrate includes a first gate metal layer 220, a second gate metal layer 230, and a first source / drain metal layer 240. In other embodiments of this disclosure, the display substrate further includes a second source / drain metal layer 260.

[0068] like Figure 3 and Figure 4 As shown, the first gate metal layer 220 is used to form the gate of each transistor (e.g., T1 to T7) in the driving circuit of each sub-pixel on the display substrate, as well as the switch control line Gate, light emission control signal line EM, reset control line (e.g., Reset_n, Reset_n+1) and other structures included in the display substrate.

[0069] like Figure 5 As shown and Figure 6 As shown, the second gate metal layer 230 is used to form initialization signal lines (such as Vint_n, Vint_n+1), the second plate Cst2 of the storage capacitor, the first occlusion structure 231, and the second occlusion structure 232. It should be noted that the second occlusion structure 232 of a sub-pixel in the same row and the first occlusion structure 231 of the next sub-pixel in the same row can be set separately or as a whole.

[0070] The first source / drain metal layer 240 is used to form the data signal line VData, the power signal line VDD, and some conductive connections of the display substrate.

[0071] like Figure 8 As shown, in some embodiments, the conductive connection portion specifically includes a first conductive connection portion 241, a second conductive connection portion 242, and a third conductive connection portion 243. The first conductive connection portion 241 is connected to the initialization signal line Vint_n and the first terminal of the first reset transistor T1, respectively. The second conductive connection portion 242 is connected to the second terminal of the compensation control transistor T2 and the control terminal of the driving transistor T3, respectively. The third conductive connection portion 243 is connected to the second terminal of the second light-emitting control transistor T6 and the anode of the light-emitting element EL, respectively.

[0072] like Figure 15 and Figure 16 As shown, in an optional embodiment, the display substrate further includes a second source / drain metal layer 260, which includes a power compensation signal line 261 and a transition structure 262.

[0073] In some embodiments of this disclosure, the first light-shielding structure blocks the second electrode T1P2 of the first reset transistor T1.

[0074] The first light-shielding structure in this embodiment includes the power signal line VDD.

[0075] Please also refer to Figure 2 , Figure 3 and Figure 7 The power signal line VDD blocks the second terminal T1P2 of the first reset transistor T1 to reduce the direct light exposure to the second terminal T1P2 of the first reset transistor T1.

[0076] In some embodiments of this disclosure, the second light-shielding structure blocks the first terminal T1P1 of the first reset transistor T1.

[0077] like Figure 9 and Figure 10 As shown, in some embodiments of this disclosure, the orthographic projection of the first reset transistor T1 on the substrate 201 overlaps with the orthographic projection of the anode G1 of the green sub-pixel G on the substrate 201.

[0078] In this embodiment, the second light-shielding structure can be the anode G1 of the green sub-pixel G, such as... Figure 9 and Figure 10As shown, the orthographic projection of a portion of the first reset transistors on the substrate 201 overlaps with the orthographic projection of the green sub-pixel G on the substrate 201. In this way, the anode of the green sub-pixel G can be used to block these first reset transistors T1. Specifically, it can be to block the first electrode T1P1, the second electrode T1P2, and the channel region of these first reset transistors T1.

[0079] In some embodiments of this disclosure, the orthographic projection of the first reset transistor T1 onto the substrate 201 lies between the orthographic projections of two adjacent green sub-pixels G onto the substrate 201. The second light-shielding structure in this embodiment may also be a metal trace 250 including an anode of a light-emitting layer or a touch layer.

[0080] In some alternative embodiments, the second light-shielding structure is the metal trace 250 of the touch layer.

[0081] like Figure 9 , Figure 11 and Figure 12 As shown, a portion of the first reset transistor T1's orthogonal projection onto the substrate 201 is located along the first direction ( Figure 9 In the middle horizontal direction, between two adjacent green sub-pixels G, the metal traces 250 of the touch layer are used to block these first reset transistors T1. Specifically, this can be to block the first electrode T1P1, the second electrode T1P2, and the channel region of these first reset transistors.

[0082] like Figure 11 As shown, on the side of the driving circuit layer away from the substrate 201, it may also be necessary to fabricate structures such as a planarization layer 202, a pixel defining layer 203, an encapsulation layer 204, and an inorganic insulating layer 205. Furthermore, metal traces 250 of the touch layer can be fabricated on the side of the inorganic insulating layer 205 away from the substrate 201.

[0083] The metal traces 250 of the touch layer are specifically made using a metal mesh process, and the resulting touch layer includes intersecting and insulated receiving electrodes and transmitting electrodes.

[0084] like Figure 13 As shown, the metal trace 250 includes a trace structure 251 and an overlap structure 252. Multiple trace structures 251 are coupled at the overlap structure 252. By setting an overlap structure 252 with a certain area, the shielding effect on the first reset transistor T1 can be improved.

[0085] In some embodiments of this disclosure, the width of the metal trace 250 of the touch layer is greater in the portion located between two adjacent green sub-pixels G than in the portion located outside the portion located between two adjacent green sub-pixels G.

[0086] In the embodiment, the width of the metal trace 250 is further adjusted, so that the width of the part of the metal trace 250 corresponding to the first reset transistor T1 is greater than the width of other parts, so that the shielding effect on the first reset transistor T1 can be further improved.

[0087] In some embodiments of the present disclosure, the second light shielding structure is further used to cover the active layer 210 of the compensation control transistor T2.

[0088] As shown in Figure 2 , the active layer of the compensation control transistor T2 includes a third semiconductor part 214 and a fourth semiconductor part 215 arranged at intervals, and a second conductor part 216 coupled to the third semiconductor part 214 and the fourth semiconductor part 215 respectively, the second conductor part 216 is covered by the second light shielding structure.

[0089] In some embodiments, the display substrate includes a red sub-pixel R and a blue sub-pixel B, and the second light shielding structure is an anode of the red sub-pixel R and / or an anode of the blue sub-pixel B.

[0090] As shown in Figure 14 , in some optional embodiments, the anode of the red sub-pixel R is substantially rectangular, and the red sub-pixel R includes a target red sub-pixel, and the anode R1 of the target red sub-pixel further includes a protruding part R1A, in a direction away from the substrate, the protruding part R1A covers one compensation control transistor T2.

[0091] It should be understood that in the embodiment, the area of the anode of the blue sub-pixel B is relatively large, so that the anode of the blue sub-pixel B can be directly used to shield the compensation control transistor T2, and the size of the anode of the red sub-pixel R is relatively small, so that the structure of part or all of the anode of the red sub-pixel R can be adjusted to shield the compensation control transistor T2 by using the anode of the red sub-pixel R.

[0092] In the embodiment, the anode of the blue sub-pixel B and the anode of the target red sub-pixel R are used to shield the compensation control transistor T2, so as to improve the stability of the compensation control transistor T2.

[0093] In some optional embodiments of the present disclosure, the display substrate further includes a third light shielding structure.

[0094] As shown in Figure 2 , the third light shielding structure is used to cover the active layer 210 of the compensation control transistor T2. Figure 2As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint.

[0095] As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint. Figure 1 Figure 2 As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint.

[0096] It is worth noting that the initialization signal line Vint here can be the initialization signal line Vint_n of the sub-pixel corresponding to the first reset transistor, and can also be the initialization signal line of other sub-pixels, for example, the initialization signal line Vint_n-1 of the sub-pixels in the row along the second direction (vertical direction) of the sub-pixel corresponding to the first reset transistor. Figure 9

[0097] As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint. Figure 7 As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint.

[0098] Figure 1 As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint.

[0099] In the present embodiment, the second conductor portion 216 is further shielded by the shielding structure 232, which helps to improve the reliability of the compensation control transistor T2.

[0100] As shown in FIG. 10, in some embodiments of the present disclosure, the active layer 210 of the first reset transistor T1 includes a first semiconductor portion 211 and a second semiconductor portion 212 arranged in a spaced manner, and a first conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 respectively, the first conductor portion 213 is covered by a third light shielding structure, and the third light shielding structure includes an initialization signal line Vint. Figure 15 Figure 16 In the present embodiment, the second source-drain metal layer 260 can cover part of the first reset transistor T1, or can cover the whole first reset transistor T1. Please refer to FIG. 11.

[0101] In the present embodiment, the second source-drain metal layer 260 can cover part of the first reset transistor T1, or can cover the whole first reset transistor T1. Please refer to FIG. 11. Figure 15 ​​​​The power supply compensation signal line 261 of the second source-drain metal layer 260 has a shielding area, and the width of the shielding area is L. The shielding area can cover at least part of the first reset transistor T1.

[0102] It can be understood that when the width L of the shielding area is large enough, the first reset transistor T1 can be completely shielded, and when the width L of the shielding area is small, the first reset transistor T1 can be partially covered.

[0103] The display device of at least one embodiment of the present disclosure can include the display substrate described above.

[0104] The display device provided by at least one embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

[0105] The above merely describes the preferred embodiments of the present disclosure, and it should be noted that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present disclosure, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A display substrate, comprising a substrate, and a driving circuit layer, a light emitting layer and a touch layer disposed on the substrate; the driving circuit layer comprises at least a driving transistor, a first reset transistor, a compensation control transistor, a reset control line, an initialization signal line, a switch control line, a light emitting control signal line, a data signal line and a power signal line; the driving transistor, the first reset transistor and the compensation control transistor each comprise a control terminal, a first electrode and a second electrode; the light emitting layer comprises a light emitting element corresponding to each sub-pixel; wherein the first electrode of the driving transistor is electrically connected to the power signal line, and the second electrode thereof is coupled to the corresponding light emitting element; the control terminal of the first reset transistor is connected to the reset control line, the first electrode thereof is coupled to the initialization signal line, and the second electrode thereof is coupled to the control terminal of the driving transistor; the control terminal of the compensation control transistor is coupled to the switch control line, the first electrode thereof is coupled to the second electrode of the driving transistor, and the second electrode thereof is coupled to the control terminal of the driving transistor; in a direction away from the substrate, the first reset transistor is at least partially covered by a first light shielding structure, the first light shielding structure comprising the power signal line; and in a direction away from the substrate, the first reset transistor is at least partially covered by a second light shielding structure, the second light shielding structure comprising an anode of the light emitting layer or a metal trace of the touch layer; the second light shielding structure shields the first electrode of the first reset transistor; the display substrate comprises green sub-pixels, the orthographic projection of the first reset transistor on the substrate is located between the orthographic projections of two adjacent green sub-pixels on the substrate, and at least part of the second light shielding structure is a metal trace of the touch layer; the driving circuit layer further comprises a second source-drain metal layer; the second source-drain metal layer comprises a power compensation signal line, the power compensation signal line having a shielding area corresponding to the first reset transistor. the first light shielding structure shields the second electrode of the first reset transistor. 2.The display substrate of claim 1, wherein, the display substrate comprises green sub-pixels, the orthographic projection of the first reset transistor on the substrate overlaps the orthographic projection of the green sub-pixel on the substrate, and the second light shielding structure is an anode of the green sub-pixel. 3.The display substrate of claim 1, wherein, the width of the metal trace of the touch layer is greater in the part between two adjacent green sub-pixels than in the part outside the two adjacent green sub-pixels. 4.The display substrate of claim 1, wherein, the active layer of the first reset transistor comprises a first semiconductor part and a second semiconductor part arranged at intervals, and a first conductor part coupled to the first semiconductor part and the second semiconductor part respectively, the first conductor part is covered by a third light shielding structure, the third light shielding structure comprising the initialization signal line. 5.The display substrate of claim 1, wherein, the driving circuit layer comprises an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and the power signal line is located in the first source-drain metal layer; 6.The display substrate of claim 5, wherein, ​ At least part of the first conductor portion is shielded by the power signal line in a direction away from the substrate. 7.The display substrate of claim 6, wherein, The first reset transistor is at least partially covered by the second source-drain metal layer in a direction away from the substrate. 8.The display substrate of claim 7, wherein, The first reset transistor is at least partially covered by the reset control line in a direction away from the substrate. 9.The display substrate of claim 1, wherein, The active layer of the compensation control transistor comprises a third semiconductor portion and a fourth semiconductor portion arranged in a spaced manner, and a second conductor portion coupled to the third semiconductor portion and the fourth semiconductor portion respectively; The second conductor portion is covered by the second light shielding structure in a direction away from the substrate. 10.The display substrate of claim 9, wherein, Further comprising a shielding structure, the driving circuit layer comprises an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and the shielding structure is located on the second gate metal layer. The second conductor portion is covered by the shielding structure in a direction away from the substrate. 11.The display substrate of claim 1, wherein, The display substrate comprises a red sub-pixel, the second light shielding structure comprises an anode of the red sub-pixel, the anode of the red sub-pixel is a rounded rectangle, the red sub-pixel comprises a target red sub-pixel, the anode of the target red sub-pixel further comprises a protruding portion, and the protruding portion covers one compensation control transistor in a direction away from the substrate. 12.The display substrate of claim 1, wherein, The first reset transistor is covered by the first light shielding structure in a region and covered by the second light shielding structure in a region, and there is an overlapping part between the two regions. 13.The display substrate of claim 1, wherein, The first reset transistor is covered by the first light shielding structure in a region and covered by the second light shielding structure in a region, and there is no overlapping part between the two regions.

14. A display device comprising the display substrate of any one of claims 1 to 13.

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