Semiconductor device, liquid discharge head, and liquid discharge apparatus

Abstract

The present disclosure relates to a semiconductor device, a liquid discharge head, and a liquid discharge apparatus. A device includes a plurality of units arranged in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply the voltage to the plurality of units, wherein the plurality of units includes a first unit including a memory element arranged between the first terminal and the second terminal and a first transistor configured to write the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal corresponding to the first transistor of the first unit.

Description

Technical Field

[0001] The embodiments relate to semiconductor devices, drain heads, and draining devices. Background Technology

[0002] Some semiconductor devices include memory configured to be written to only once, known as OTP (Once Programmable) memory, as a memory element for storing specific information of the device after manufacturing is complete. As an OTP memory, an antifuse element is typically used (see Japanese Patent Publication No. 2014-58130).

[0003] In the aforementioned semiconductor device, as a component for properly implementing the writing of information to or reading of information from a memory element, it may be necessary to be able to evaluate the circuit configuration around the memory element, particularly the configuration of parasitic components in the circuit. Summary of the Invention

[0004] A first aspect of the embodiments provides a semiconductor device including: a plurality of units arranged in a predetermined direction; a first terminal configured to supply voltage to the plurality of units; and a second terminal configured to supply voltage to the plurality of units, wherein the plurality of units includes a first unit and a second unit, the first unit including a memory element disposed between the first terminal and the second terminal and a first transistor configured to write to the memory element, and the second unit including a second transistor disposed between the first terminal and the second terminal corresponding to the first transistor of the first unit.

[0005] A second aspect of the embodiment provides a drain head including the above-described semiconductor device and a plurality of drain ports corresponding to a plurality of printing elements of the device.

[0006] A third aspect of the embodiments provides a draining device including the above-mentioned drain head and a driver configured to drive the drain head.

[0007] Other features of this disclosure will become clear from the following description of exemplary embodiments (with reference to the accompanying drawings). Attached Figure Description

[0008] Figure 1 This is a circuit diagram illustrating an example of the configuration of a printed component substrate;

[0009] Figure 2A and Figure 2B This is a circuit diagram illustrating an example of the configuration of a printed component substrate;

[0010] Figure 3A and Figure 3B This is a cross-sectional view of an example used to explain the cross-sectional structure of a printed component substrate;

[0011] Figure 4A and Figure 4B These are circuit diagrams illustrating other examples of the configuration of the printed component substrate; and

[0012] Figures 5A to 5D This is an example view used to explain the configuration of the printing device. Detailed Implementation

[0013] In the following, exemplary embodiments will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments are not intended to limit the scope of the appended claims. Multiple features are described in the embodiments. However, not all of these multiple features are necessarily essential to all aspects of the embodiments, and the multiple features can be combined arbitrarily. Furthermore, the same reference numerals denote the same or similar parts, and repeated descriptions will be omitted.

[0014] (Example of printing device configuration)

[0015] Figure 5A The internal configuration of a printing apparatus 900 using an inkjet method is shown. The printing apparatus 900 includes a printhead 810 that dispenses printing material (in this example, ink) onto a predetermined printing medium P (in this example, a sheet-like component such as paper). The printhead 810 is mounted on a carriage 920, and the carriage 920 is attached to a lead screw 921 via a helical groove 904. The lead screw 921 can be rotated via drive force transmission gears 902 and 903 in a rotational interlocking manner with that of a drive motor 901. Therefore, the printhead 810 can move along a guide 919 in the direction of arrow a or b, together with the carriage 920.

[0016] The printing medium P is pressed and fixed to the table plate 906 by the paper pressure plate 905 along the carriage movement direction. The printing device 900 reciprocates the print head 810 and prints on the printing medium P that is conveyed to the table plate 906 by the conveying unit (not shown).

[0017] Additionally, via optocouplers 907 and 908, the printing device 900 confirms the position of the lever 909 positioned on the carriage 920 and switches the rotation direction of the drive motor 901. A support member 910 supports a cap member 911 configured to cover the nozzle (drain port, or simply discharge port) of the printhead 810. A suction member 912 performs a recovery process on the printhead 810 by suctioning the interior of the cap member 911 via an inner opening 913. A lever 917 is provided to initiate the recovery process via suction. The lever 917 moves along with the movement of a cam 918 engaging with the carriage 920 and is controlled by a known transmission component such as a clutch switch, which controls the driving force from the drive motor 901.

[0018] Furthermore, the main support plate 916 supports the moving member 915 and the cleaning blade 914. The moving member 915 moves the cleaning blade 914 to perform a wiping process to restore the printhead 810. Additionally, a control unit (not shown) is provided in the printing device 900. The control unit controls the drive of each of the above mechanisms.

[0019] Figure 5B The appearance of printhead 810 is shown. Printhead 810 may include a head 811 containing a plurality of nozzles 800 and a tank (liquid storage section) 812 for holding liquid to be supplied to head 811. Tank 812 and head 811 may be separated, for example, at the dashed line K, and tank 812 may be replaceable. Printhead 810 includes electrical contacts (not shown) configured to receive electrical signals from carriage 920 and to discharge liquid according to the electrical signals. Tank 812 includes, for example, a fibrous or porous liquid holding material (not shown), and the liquid may be held by the liquid holding material.

[0020] Figure 5C The internal configuration of the printhead 810 is shown. The printhead 810 includes a base 808, a channel wall member 801 disposed on the base 808 to form a channel 805, and a top plate 802 including a liquid supply path 803. Furthermore, heaters (electrothermal transducers) 806, which act as printing elements, are arranged correspondingly to the nozzles 800 on a substrate (printing element substrate) included in the printhead 810. Each heater 806 is driven and generates heat when a drive element (switching element, such as a transistor) corresponding to the heater 806 is set to an on state.

[0021] Liquid from liquid supply path 803 is stored in common liquid chamber 804 and supplied to nozzle 800 via channel 805. In response to the actuation of heater 806 corresponding to nozzle 800, liquid supplied to each nozzle 800 is discharged from nozzle 800.

[0022] Figure 5D The system configuration of a printing device 900 is shown. The printing device 900 includes an interface 1700, an MPU 1701, a ROM 1702, a RAM 1703, and a gate array 1704. External signals for performing printing are input to the interface 1700 from the outside. The ROM 1702 stores the control program to be executed by the MPU 1701. The RAM 1703 stores various signals and data, such as external signals for printing and data supplied to the print head 1708. The gate array 1704 controls the data supply to the print head 1708 and also controls data transfer between the interface 1700, the MPU 1701, and the RAM 1703.

[0023] The printing apparatus 900 also includes a head driver 1705, motor drivers 1706 and 1707, a transport motor 1709, and a carriage motor 1710. The carriage motor 1710 transports the print head 1708. The transport motor 1709 transports the printing media P. The head driver 1705 drives the print head 1708. The motor drivers 1706 and 1707 drive the transport motor 1709 and the carriage motor 1710, respectively.

[0024] When a drive signal is input to interface 1700, it can be converted into print data between gate array 1704 and MPU 1701. Each mechanism performs the desired operation based on the data, and thus drives printhead 1708.

[0025] In summary, the printing apparatus 900 includes a printhead 810 (or 1708), and a driver 1705 is configured to drive it. The printhead 810 includes a printing element substrate and a plurality of nozzles 800 arranged on the printing element substrate corresponding to a plurality of printing elements 806. A detailed configuration of the printing element substrate will be described in the following embodiments. The content is not limited to a printing element substrate and can be applied to various semiconductor devices.

[0026] (First Embodiment)

[0027] Figure 1 An example configuration of a print element substrate PS1 according to a first embodiment is shown. The print element substrate PS1 includes a plurality of print elements 201 arranged in a predetermined direction, a plurality of units U1 arranged in the same direction, and a controller 203. In a top view (plan view), the print element substrate PS1 generally has a rectangular shape, and the plurality of print elements 201 and, in one embodiment, the plurality of units U1 are arranged, for example, along the side direction of the print element substrate PS1.

[0028] Each printing element 201 includes a printing element Rh, a driving element MD2 configured to drive it, and logic circuitry (here, an AND circuit) configured to control the driving element MD2. As the printing element Rh, an element capable of performing the above-described printing is used. In this embodiment, a heater (electrothermal transducer) is used. As another embodiment, a piezoelectric element can be used. As the driving element MD2, a high breakdown voltage transistor is used. In this embodiment, a DMOS (double-diffused metal-oxide-semiconductor) transistor is used. The printing element Rh and the driving element MD2 are connected in series, and a voltage VH1 (e.g., 24 [V (volts)]) is applied to them.

[0029] Here, the controller 203 can drive multiple print elements Rh using a time-division multiplexing method. That is, the multiple print elements Rh are divided into multiple groups, and the controller 203 sequentially drives each of two or more print elements Rh in each group as a block. For example, if the number of groups is i, and each group includes j print elements Rh as a block, firstly, the controller 203 drives the first block (i print elements Rh) of each group from the first to the i-th group. Next, the controller 203 drives the second block (i print elements Rh) of each group from the first to the i-th group. Following the same process, the controller 203 sequentially drives the third, fourth, ..., j-th blocks (i print elements Rh in each block) of each group from the first to the i-th group.

[0030] To drive multiple print elements Rh using a time-division multiplexing method, controller 203 typically includes a decoder, shift register, latch circuit, selector, AND circuit, OR circuit, etc. Based on print data, clock signal CLK, latch signal LT, and hot-enabled signal HE, controller 203 drives the corresponding print elements Rh in a time-division multiplexing manner via group select signal 204 and block select signal 205, but detailed descriptions will be omitted.

[0031] Note that each of i and j is an integer of 2 or greater. Furthermore, groups can also be called time groups, and blocks can also be called time blocks.

[0032] The multiple units U1 include memory units (first units) 202 and evaluation units (second units) 207. Units U1 can be represented as, for example, functional units. In this embodiment, multiple memory units 202 are arranged, and an evaluation unit 207 is configured to juxtapose them.

[0033] The printed element substrate PS1 also includes a terminal (first terminal) A and a terminal (second terminal) B configured to supply voltage to a plurality of cells U1. Terminal A is configured to supply a voltage VH2 (e.g., 32 [V]) capable of enabling writing to memory elements Ca described later, and terminal B is configured to be grounded.

[0034] Figure 2A An example of the circuit configuration of memory cell 202 is shown, and Figure 3A An example of the structure of memory cell 202 is shown.

[0035] Memory cell 202 includes memory element Ca and a write / read transistor (first transistor) MD1 configured to write to and / or read from memory element Ca. A MOS (metal-oxide-semiconductor) structure is used in memory element Ca, and memory element Ca serves as an antifuse element capable of being written to through dielectric breakdown of the MOS structure. A high breakdown voltage transistor is used as transistor MD1. In this embodiment, a DMOS transistor is used.

[0036] Memory element Ca and transistor MD1 are arranged between terminals A and B and connected in series. When voltage VH2 is supplied to terminal A, transistor MD1 is turned on, causing dielectric breakdown of the MOS structure of memory element Ca, thereby writing to memory element Ca.

[0037] The memory cell 202 can be formed on a semiconductor substrate, such as a silicon substrate, using known semiconductor processes. In this embodiment, p-type wells 101a and 101b and n-type wells 102a and 102b are disposed on the p-type region 100. An n-type region 106a and a p-type region 107 are disposed in the p-type well 101a. An n-type region 106b is disposed in the n-type well 102a. An n-type region 106c is disposed in the n-type well 102b. A relatively thick insulating member 103 is disposed between regions 106a to 106c and 107. The insulating member 103 is formed by LOCOS (Local Oxidation of Silicon). Furthermore, gate electrodes 105a and 105b, made of polysilicon or the like, are configured as a relatively thin gate insulating film covering the space between the insulating members 103, and also partially covering the insulating members 103.

[0038] Transistor MD1 and memory element Ca are connected to wiring portions 109a to 109d via contact plugs 108. Transistor MD1 is connected to terminal B via wiring portion 109a in the source and back gate, to wiring portion 109b in the gate, and to wiring portion 109c in the drain. Furthermore, the antifuse element acting as memory element Ca is connected to wiring portion 109c in one terminal and to terminal A via wiring portion 109d in the other terminal.

[0039] Figure 2B An example of the circuit configuration of the evaluation unit 207 is shown, and Figure 3B An example of the structure of the evaluation unit 207 is shown.

[0040] Evaluation unit 207 includes transistor (second transistor) MD1' and MOS structure 11 corresponding to memory element Ca. Transistor MD1' is arranged between terminals A and B, corresponding to transistor MD1 of memory cell 202.

[0041] Additionally, evaluation unit 207 includes a p-channel MOS transistor MP1 and an n-channel MOS transistor MN1. They are connected in series to form inverter INV1. Logic circuitry (here, a "NAND" circuit) is arranged in the stage preceding inverter INV1. Using this configuration, a control signal Sig is input to inverter INV1.

[0042] from Figure 3A and Figure 3B A comparison reveals that the evaluation unit 207 differs from the memory unit 202 in the connection patterns of wiring portions 109c and 109d. That is, transistor MD1' and MOS structure 11 are juxtaposed, just as transistor MD1 and memory element Ca are. On the other hand, the connection patterns of wiring portions 109c and 109d differ from those in transistor MD1 and memory element Ca. More specifically, terminals A and B are connected to transistor MD1' via wiring portions 109a, 109c, and 109d, and wiring portions 109a, 109c, and 109d are not connected to MOS structure 11.

[0043] In this way, transistor MD1' is electrically isolated from MOS structure 11 and is set to a floating state in this embodiment. From the perspective of evaluating the function of unit 207 (described later), MOS structure 11 can be omitted. However, in one embodiment, MOS structure 11 is formed for the purpose of reducing manufacturing variations of the memory elements Ca arranged together.

[0044] The controller 203 is also configured to perform writes to memory elements Ca. In this embodiment, the controller 203 can write to multiple memory elements Ca using a time-division multiplexing method, and can write to a corresponding memory element Ca via a block select signal 205 and a control signal 206.

[0045] To prevent write errors to memory element Ca, a resistor (not shown) can be connected in parallel with memory element Ca. As the resistor, a resistor capable of forming a resistance of, for example, tens of [KΩ (kiloohms)] in one embodiment is used. This resistor can be made of polysilicon or a diffused resistor.

[0046] Using the above configuration, the controller 203 can drive multiple printing elements Rh using a time-division multiplexing method, and can also write to multiple memory elements Ca as needed using the time-division multiplexing method. The memory elements Ca can be written to, for example, to store specific information during the manufacturing of the printing element substrate PS1, or the memory elements Ca can be written to as needed when using the printing element substrate PS1 (e.g., to save usage history).

[0047] Here, the focus is placed on multiple units U1, which in this embodiment are multiple memory units 202 and an evaluation unit 207 (see [link]). Figure 1 Multiple cells U1 are used by setting one of the aforementioned transistors MD1 and MD1' to the on state.

[0048] For example, if one of the multiple memory cells 202 is selected to write to memory element Ca, then with a voltage VH2 applied to terminals A and B, the corresponding transistor MD1 is set to the ON state. During this period, the remaining transistors MD1 and MD1' are set to the OFF state. This achieves the writing of memory element Ca to the selected memory cell 202.

[0049] Furthermore, in order to use the evaluation unit 207, transistor MD1' is set to the on state with a voltage VH2 (or another voltage) applied to terminals A and B. During this period, all of the plurality of transistors MD1 are set to the off state. When the resistance between terminals A and B is measured in this state, the parasitic resistance of each of the plurality of memory cells 202 can be evaluated equivalently, and the evaluation results can be used, for example, for write or read characteristics. Since this is effective when the number of units U1 is large, it can be said to be particularly beneficial when increasing the capacity of memory.

[0050] (Second Embodiment)

[0051] As a second embodiment, the evaluation unit 207 described above can be used as an electrostatic discharge (ESD) protection element.

[0052] Figure 4A An example configuration of the print element substrate PS2 according to this embodiment is shown. In addition to the same configuration as the print element substrate PS1, the print element substrate PS2 also includes a rectifier element EP1 serving as an ESD protection element. The rectifier element EP1 is connected to terminal A in the anode and to terminal B in the cathode. The rectifier element EP1 can protect the circuit configuration in the print element substrate PS2 from ESD (electrostatic discharge) generated between terminals A and B.

[0053] For example, if an ESD-induced surge current is applied in the path from terminal B to terminal A, the surge current flows from terminal B to terminal A via rectifier element EP1. Note that examples of ESD types are HBM (human body model, electrostatic discharge from the human body) and MM (machine model, electrostatic discharge from robotic arms, etc., during manufacturing). ESD-induced surge currents typically flow for relatively short periods of time, e.g., tens [nsec (nanoseconds)] to tens [μsec (microseconds)].

[0054] The printed element substrate PS2 also includes a resistive element Rs that acts as another ESD protection element. The resistive element Rs is arranged between terminal A and the plurality of cells U1, and can protect the circuit configuration in the printed element substrate PS2 from ESD applied to terminal A. As the resistive element Rs, a resistive element of, for example, about 2 to 7 [Ω], and in one embodiment about 5 [Ω], is used. The resistive element Rs can typically be made of polysilicon.

[0055] Along with the resistive element Rs, the transistor MD1' in evaluation unit 207 serves as another ESD protection element. Transistor MD1' is normally in a non-conducting state. However, when an ESD-induced surge current is applied, the surge current can flow through the breakdown between the drain and source. Therefore, transistor MD1' can be considered a protection transistor for ESD protection, also known as a GGMOS (Gate Ground MOS).

[0056] Therefore, for example, if an ESD-induced surge current is applied in the path from terminal A to terminal B, the surge current flows from terminal A to terminal B via the resistive element Rs and the transistor MD1' of the evaluation unit 207.

[0057] According to the above configuration, if a relatively high voltage caused by ESD is applied to terminals A and B, multiple memory cells 202 can be protected.

[0058] Also in Figure 4A In the example shown, multiple cells U1 are arranged such that, in memory cell 202 and evaluation cell 207, evaluation cell 207 has the shortest path to the resistive element Rs. Therefore, if an ESD-induced surge current is applied in the path from terminal A to terminal B, the transistor MD1' of evaluation cell 207 acts as a protection transistor at a relatively early timing. Thus, transistor MD1' can appropriately protect multiple memory cells 202.

[0059] Figure 4B The illustration shows a modification of this embodiment in which the evaluation unit 207, among the memory unit 202 and the evaluation unit 207, is arranged in a pattern having the longest path to the resistive element Rs. According to... Figure 4B In the example shown, if an ESD-induced inrush current is applied along the path from terminal A to terminal B, the wiring resistance component before reaching evaluation unit 207, in addition to the resistive element Rs and transistor MD1', also contributes to ESD protection. Therefore, the resistance of transistor MD1' to inrush current can be improved.

[0060] As described above in the first embodiment, to prevent write errors to memory element Ca, a resistive element (not shown) can be connected in parallel with memory element Ca (hereinafter referred to as the "parallel resistor"). In this configuration, when the resistance between terminals A and B is measured using evaluation unit 207, it is also necessary to properly evaluate the parasitic resistance of each of the plurality of memory cells 202. It is also necessary to make the resistance value of the resistive element Rs small to prevent unexpected results from being read from memory element Ca. For this purpose, in one embodiment, the resistance value of the aforementioned parallel resistor is greater than the resistance value of the resistive element Rs, and the resistance value of transistor MD1' in the on state is less than the resistance value of the resistive element Rs.

[0061] As described above, according to this embodiment, in addition to the effects of the first embodiment, it is also beneficial from the perspective of protecting the printed element substrate PS2 from ESD.

[0062] (other)

[0063] In the above description, a printing device 900 using an inkjet method has been described as an example. However, the printing method is not limited to this. Moreover, the printing device 900 can be a single-function printer with only printing capabilities or a multi-function printer with multiple functions such as printing, faxing, and scanning. In addition, the printing device 900 can be a manufacturing device configured to manufacture, for example, color filters, electronic devices, optical devices, microstructures, etc., using a predetermined printing method.

[0064] Furthermore, the term "printing" in this specification should be interpreted in a broader sense. Therefore, the mode of "printing" is unrelated to whether the target formed on the printing medium is important information such as characters or graphic patterns, and also unrelated to whether the target is represented in a way that can be visually perceived by humans.

[0065] The term "printing media" should also be interpreted in a broader sense, just like "printing." Therefore, the concept of "printing media" can include not only paper as commonly used paper, but also any material capable of receiving ink, including fabrics, plastic films, metals, glass, ceramics, resins, wood, and leather.

[0066] The term "ink" should also be interpreted in a broader sense, just like "printing." Therefore, the concept of "ink" can include not only the liquid applied to the printing medium to form images, designs, patterns, etc., but also any accompanying liquid that can be used to process the printing medium or the ink (e.g., to cause the color material in the ink applied to the printing medium to solidify or become insoluble). From these perspectives, printing device 900 can also be expressed as a liquid drainage device 900, printhead 810 can also be expressed as a liquid drainage head 810, and printing element Rh can also be expressed as a liquid drainage element.

[0067] This disclosure is not limited to the embodiments described above, and various changes and modifications can be made within the spirit and scope of this disclosure. Therefore, the appended claims have been prepared to inform the public of the scope of this disclosure.

[0068] While this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to include all such modifications and equivalent structures and functions.

Claims

1. A semiconductor device, characterized in that, include: Multiple units are arranged in a predetermined direction; The first terminal is configured to supply voltage to the plurality of units; and The second terminal is configured to supply voltage to the plurality of units. The plurality of units include: A first unit includes a memory element disposed between a first terminal and a second terminal, and a first transistor configured to write to the memory element, wherein the first transistor is voltage-controlled by a first control signal on a first signal line carrying a block select signal to change between an on state and a off state, wherein when the first unit is selected to perform a write to the memory element, the first transistor is set to an on state with a supply voltage applied across the first terminal and the second terminal; and The second unit includes a second transistor disposed between the first terminal and the second terminal, corresponding to the first transistor of the first unit. The second transistor is voltage-controlled by a second control signal on a second signal line carrying the block selection signal to switch between an on state and a non-on state. In order to use the second unit, the second transistor is set to an on state when the supply voltage is applied across the first and second terminals. Wherein, the voltage of the first control signal on the first signal line can be controlled independently of the voltage of the second control signal on the second signal line, the voltage on the first terminal, and the voltage on the second terminal, and The voltage of the second control signal on the second signal line can be controlled independently of the voltage of the first control signal on the first signal line, the voltage on the first terminal, and the voltage on the second terminal.

2. The semiconductor device of claim 1, further comprising a resistive element configured to protect the plurality of cells from electrostatic discharge (ESD).

3. The semiconductor device according to claim 2, wherein, The plurality of units are arranged such that, among the first unit and the second unit, the second unit has the shortest path to the resistive element.

4. The semiconductor device according to claim 2, wherein, The plurality of units are arranged such that, of the first unit and the second unit, the second unit has the longest path to the resistive element.

5. The semiconductor device of claim 2, further comprising a rectifier element connected between the first terminal and the second terminal.

6. The semiconductor device according to claim 2, wherein, Between the first terminal and the second terminal, the second transistor serves as a protection transistor, which is configured to protect the first cell from ESD.

7. The semiconductor device according to claim 1, in, The first unit further includes a first inverter, wherein a third control signal formed by the first control signal on the first signal line is input to the first inverter, and The second unit further includes a second inverter, wherein a fourth control signal formed by the second control signal on the second signal line is input to the second inverter.

8. The semiconductor device according to claim 7, in, The third control signal input to the first inverter is formed by logic circuitry based on the first control signal on the first signal line and the control signal on the third signal line. The fourth control signal input to the second inverter is formed by another logic circuit based on the second control signal on the second signal line and the control signal on the third signal line.

9. The semiconductor device according to claim 7, in, The structure of the first inverter is the same as that of the second inverter.

10. The semiconductor device of claim 1, wherein The second unit also includes a metal-oxide-silicon (MOS) structure corresponding to the memory element of the first unit, and The first terminal and the second terminal are connected to the second transistor via a wiring portion, and the wiring portion is not connected to the MOS structure.

11. The semiconductor device of claim 1, further comprising a controller configured to control the first transistor to write to the memory element by providing the first control signal through a voltage of the first control signal on the first signal line. in, The first unit is one of a plurality of first units, and The controller writes to multiple memory elements corresponding to the multiple first units using a time-division multiplexing method.

12. The semiconductor device according to any one of claims 1 to 11, wherein The semiconductor device is a printed element substrate, and also includes: Multiple printed elements are arranged in the predetermined direction; and Multiple driving elements are configured to drive the multiple printing elements.

13. A drain head, characterized in that, include: The semiconductor device as defined in claim 12; and Multiple drain ports corresponding to multiple printing elements of the semiconductor device.

14. The drain head according to claim 13, wherein, The semiconductor device further includes a resistive element configured to protect the plurality of cells from electrostatic discharge (ESD).

15. The drain head according to claim 14, wherein, In the semiconductor device, the plurality of units are arranged such that, of the first unit and the second unit, the second unit has the shortest path to the resistive element.

16. The drain head according to claim 14, wherein, In the semiconductor device, the plurality of units are arranged such that, of the first unit and the second unit, the second unit has the longest path to the resistive element.

17. The drain head according to claim 13, wherein The second unit also includes a metal-oxide-silicon (MOS) structure corresponding to the memory element of the first unit, and The first terminal and the second terminal are connected to the second transistor via a wiring portion, and the wiring portion is not connected to the MOS structure.

18. The drain head according to claim 13, wherein, The semiconductor device further includes a controller configured to control the first transistor to write to the memory element by providing the first control signal with a voltage controlling the first control signal on the first signal line. Wherein, the first unit is one of a plurality of first units, and The controller writes to multiple memory elements corresponding to the multiple first units using a time-division multiplexing method.

19. The drain head according to claim 13, wherein The semiconductor device is a printed element substrate, and also includes: Multiple printed elements are arranged in the predetermined direction; and Multiple driving elements are configured to drive the multiple printing elements.

20. A drainage device, characterized in that, include: The drain head as defined in claim 13; and The driver is configured to drive the discharge head.

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