Method, System, Electronic Device and Medium for Improving CPU Execution Efficiency

Abstract

The present invention relates to a method, system, electronic device, and medium for improving CPU execution efficiency, comprising: obtaining an access request, the access request including a first access address of target data, the first access address representing the storage location of the target data in a temporary register; obtaining the target data from the temporary register according to the first access address, and if the target data is not obtained from the temporary register, determining a second access address corresponding to the target data according to the first access address, the second access address representing the storage location of the target data in a main memory; obtaining the target data from the main memory according to the second access address; and storing the target data in the temporary register according to the target storage address, the target storage address representing the storage address of the target data in the temporary register. The method solves the problem of low CPU execution efficiency when the current CPU fails to obtain data in the temporary register.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, system, electronic device, and medium for improving CPU execution efficiency. Background Art

[0002] With the improvement of technology, the frequency of CPU has been continuously increasing in recent decades. However, due to the limitations of manufacturing technology and cost, there has been no qualitative breakthrough in the access speed of computer memory / external storage. This has led to an increasing speed gap between the CPU and memory or external storage, which has greatly restricted system performance.

[0003] Flash is often used as main memory, and the access speed of main memory itself is much slower than that of the CPU. At the same time, main memory cannot perform read and store operations at the same time. That is, when the CPU accesses main memory, the main memory either performs a read operation or a store operation. Therefore, the memory access time will be much longer than the CPU execution time, resulting in the main bottleneck of instruction execution being the access efficiency of internal / external memory.

[0004] The existing technology usually adds a temporary register between the main memory and the CPU. The temporary register is a small-capacity memory with a speed equal to or close to the access speed of the next-level memory. It stores some of the currently required data in the next-level memory. Therefore, the CPU can directly obtain the required data from the temporary register without having to access the next-level memory. However, the temporary register has a disadvantage, that is, when the temporary register stores data in the main memory, it cannot provide the CPU with data to read at the same time. That is, when the CPU can obtain data in the temporary register, the CPU execution time is improved, but once the CPU fails to obtain the data, the execution efficiency is still low, and the CPU needs to wait until the temporary register has stored all the data in the main memory before it can continue to read data. Summary of the Invention

[0005] In order to solve the problem of low CPU execution efficiency when the CPU fails to obtain data in the temporary register, the present invention provides a method, system, electronic device and medium for improving CPU execution efficiency.

[0006] In a first aspect, in order to solve the above technical problems, the present invention provides a method for improving CPU execution efficiency, comprising the following steps:

[0007] S1, obtaining an access request, the access request including a first access address of target data, the first access address representing a storage location of the target data in a temporary register;

[0008] S2, obtaining target data from the temporary memory according to the first access address. If the target data is not obtained from the temporary memory, determining a second access address corresponding to the target data according to the first access address, where the second access address represents a storage location of the target data in the main memory;

[0009] S3, obtaining target data from the main memory according to the second access address;

[0010] S4, storing the target data in the temporary register according to the target storage address, where the target storage address represents the storage address of the target data in the temporary register.

[0011] The method for improving CPU execution efficiency provided by the present invention has the following beneficial effects: by adding a group of temporary registers between the main memory and the CPU, the temporary registers can perform read operations with the main memory and store operations with the CPU at the same time; when the CPU fails to obtain target data, the temporary register determines a second access address based on the first access address, and then directly reads the target data from the main memory using the second access address, and simultaneously stores the obtained target data into the temporary register according to the target storage address; while the temporary register reads the target data obtained from the main memory, the target data can be directly sent to the CPU, i.e., the CPU does not need to wait for the temporary register to read all the data in the main memory before reading the target data, thereby solving the problem of low CPU execution efficiency when the CPU fails to obtain data in the temporary register.

[0012] On the basis of the above technical solution, the method for improving CPU execution efficiency of the present invention can also be improved as follows.

[0013] Furthermore, the temporary memory includes a plurality of first buffer areas, the main memory includes a plurality of second buffer areas, each first buffer area corresponds to a first storage address, each second buffer area corresponds to a second storage address, and each first storage address includes a target storage address;

[0014] According to the target storage address, the target data is stored in the temporary register, including:

[0015] The target storage address corresponding to the target data is determined from each second storage address according to the target storage address and the first corresponding relationship, where the first corresponding relationship is a corresponding relationship between each first storage address and each second storage address.

[0016] The beneficial effect of adopting the above further scheme is: when the CPU fails to obtain the target data, it determines the storage location of the missing target data in the main memory based on the first corresponding relationship and the target storage address, and then directly obtains the target data from the corresponding storage location in the main memory and stores it in the corresponding storage location of the temporary register.

[0017] Furthermore, the method further comprises:

[0018] Taking any one of the second buffer areas as a first starting buffer area, and the second buffer area preceding the first starting buffer area as a first ending buffer area;

[0019] Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, and ending at the first ending buffer area as a loop;

[0020] The second cache area corresponding to the second access address is used as a new first starting cache area. When a new access request is obtained and new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, the data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and according to the target storage address, the new target data of the first cache area is stored in the temporary register to obtain the new target data from the main memory.

[0021] The beneficial effect of adopting the above-mentioned further scheme is as follows: when the CPU executes the original access request, it is possible that the target data is not obtained for multiple times. When the CPU fails to obtain the target data for the first time, the main memory obtains the target data in a loop manner and stores all the obtained data in the first cache area of the corresponding temporary register, which is equivalent to overwriting the original old target data with the newly obtained target data. Therefore, when the CPU executes the operation that should read the original old target data, the target data will not be not obtained. The CPU can directly read the newly overwritten target data, which greatly improves the execution efficiency of the CPU.

[0022] In a second aspect, the present invention provides a system for improving CPU execution efficiency, comprising an access request acquisition module, a first data acquisition module, a second data acquisition module, and a storage module;

[0023] An access request acquisition module, configured to acquire an access request, the access request including a first access address of target data, the first access address representing a storage location of the target data in the temporary register;

[0024] a first data acquisition module, configured to acquire target data from the temporary memory according to the first access address, and if the target data is not acquired from the temporary memory, determine a second access address corresponding to the target data according to the first access address, wherein the second access address represents a storage location of the target data in the main memory;

[0025] A second data acquisition module, configured to acquire target data from the main memory according to the second access address;

[0026] The storage module is used to store the target data in the temporary register according to the target storage address, where the target storage address represents the storage address of the target data in the temporary register.

[0027] The beneficial effect of the system for improving CPU execution efficiency provided by the present invention is as follows: by adding a temporary register between the main memory and the CPU, the temporary register can perform read operations with the main memory and store operations with the CPU at the same time; when the CPU fails to obtain target data, the temporary register determines a second access address based on the first access address, and then directly reads the target data from the main memory using the second access address, and simultaneously stores the obtained target data into the temporary register according to the target storage address; while the temporary register reads the target data obtained from the main memory, the target data can be directly sent to the CPU, i.e., the CPU does not need to wait for the temporary register to read all the data in the main memory before reading the target data, thereby solving the problem of low CPU execution efficiency when the CPU fails to obtain data in the temporary register.

[0028] Furthermore, the first data acquisition module further includes a target storage address module;

[0029] The target storage address module is used to determine the target storage address corresponding to the target data from each second storage address according to the target storage address and the first corresponding relationship, where the first corresponding relationship is the corresponding relationship between each first storage address and each second storage address.

[0030] The beneficial effect of adopting the above further scheme is: when the CPU fails to obtain the target data, it determines the storage location of the missing target data in the main memory based on the first corresponding relationship and the target storage address, and then directly obtains the target data from the corresponding storage location in the main memory and stores it in the corresponding storage location of the temporary register.

[0031] Furthermore, the system also includes a loopback module and a fourth data acquisition module;

[0032] a loopback module, configured to use any one of the second buffer areas as a first starting buffer area and a second buffer area preceding the first starting buffer area as a first ending buffer area;

[0033] Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, and ending at the first ending buffer area as a loop;

[0034] The fourth data acquisition module is used to use the second cache area corresponding to the second access address as a new first starting cache area. When a new access request is obtained and the new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, the data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and the new target data of the first cache area is stored in the temporary register according to the target storage address to obtain the new target data from the main memory.

[0035] The beneficial effect of adopting the above-mentioned further scheme is as follows: when the CPU executes the original access request, it is possible that the target data is not obtained for multiple times. When the CPU fails to obtain the target data for the first time, the main memory obtains the target data in a loop manner and stores all the obtained data in the first cache area of the corresponding temporary register, which is equivalent to overwriting the original old target data with the newly obtained target data. Therefore, when the CPU executes the operation that should read the original old target data, the target data will not be not obtained. The CPU can directly read the newly overwritten target data, which greatly improves the execution efficiency of the CPU.

[0036] In a third aspect, the present invention further provides an electronic device comprising a memory, a processor, and a program stored in the memory and running on the processor, wherein when the processor executes the program, the steps of the method for improving CPU execution efficiency as described above are implemented.

[0037] In a fourth aspect, the present invention further provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a terminal device, the terminal device executes the steps of the method for improving CPU execution efficiency as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention is further described below with reference to the accompanying drawings and embodiments.

[0039] Figure 1 A flowchart of a method for improving CPU execution efficiency according to an embodiment of the present invention;

[0040] Figure 2 Schematic diagram of a loop structure in the second buffer area according to an embodiment of the present invention;

[0041] Figure 3 Schematic diagram of the structure of a system for improving CPU execution efficiency according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following examples are provided to further explain and supplement the present invention and do not constitute any limitation to the present invention.

[0043] The following describes a method, system, electronic device, and medium for improving CPU execution efficiency according to embodiments of the present invention with reference to the accompanying drawings.

[0044] like Figure 1 As shown, the method for improving CPU execution efficiency according to an embodiment of the present invention includes the following steps:

[0045] S1, obtaining an access request, where the access request includes a first access address of target data, and the first access address represents a storage location of the target data in a temporary register.

[0046] S2, obtaining target data from the temporary register according to the first access address. If the target data is not obtained from the temporary register, determining a second access address corresponding to the target data according to the first access address, where the second access address represents the storage location of the target data in the main memory.

[0047] The access request indicates a request from a user to request target data.

[0048] In addition, when the CPU obtains the target data from the memory, it can directly obtain the target data from the memory.

[0049] Optionally, the temporary memory includes a plurality of first buffer areas, the main memory includes a plurality of second buffer areas, each first buffer area corresponds to a first storage address, each second buffer area corresponds to a second storage address, and each first storage address includes a target storage address;

[0050] According to the target storage address, the target data is stored in the temporary register, including:

[0051] The target storage address corresponding to the target data is determined from each second storage address according to the target storage address and the first corresponding relationship, where the first corresponding relationship is a corresponding relationship between each first storage address and each second storage address.

[0052] Optionally, any one of the second buffer areas is used as the first starting buffer area, and the second buffer area before the first starting buffer area is used as the first ending buffer area;

[0053] Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, and ending at the first ending buffer area as a loop;

[0054] The second cache area corresponding to the second access address is used as a new first starting cache area. When a new access request is obtained and new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, the data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and according to the target storage address, the new target data of the first cache area is stored in the temporary register to obtain the new target data from the main memory.

[0055] Optionally, the main memory sends data to the temporary register in a loopback manner, such as Figure 2As shown, the first row is the second cache area of the main memory, and the second row is the first cache area of the temporary register. Every time the main memory traverses 8 second cache areas, it corresponds to a loop. For example, the main memory obtains the target data in the second cache area 7 according to the second access address, and then stores the target data in the first cache area 7 in the temporary register according to the first corresponding relationship and the target storage address.

[0056] S3, obtaining target data from the main memory according to the second access address.

[0057] S4, storing the target data in the temporary register according to the target storage address, where the target storage address represents the storage address of the target data in the temporary register.

[0058] Specifically, if Figure 2 As shown, for example, when the main memory locates the first cache area 3 according to the second access address and obtains the target data, the main memory starts to execute a loop according to the first corresponding relationship and the target storage address, that is, reading the new target data from the second cache area 3 until the end of the second cache area 7. Since the temporary register can perform read and store operations at the same time, when the main memory reads the second cache area 3, the new target data of the second cache area 3 can be directly stored in the first cache area 3 of the temporary register and then the new target data of the second cache area can be read. At the same time, the CPU reads the new target data from the first cache area 3 of the temporary register. At this time, the main memory also reads the second cache area 4. -7 are stored in the corresponding first cache area in sequence. Finally, when the CPU receives a new access request, the target data will not be not obtained. For example, the CPU needs to obtain the target data from the original second cache area 5 according to the second access request, but in the previous loop, the target data in the second cache area 5 has been stored in the first cache area 5 in the temporary register. Therefore, the CPU can directly read the target data in the first cache area 5 in the temporary register. If the CPU needs to obtain the target data in the second cache area 2, that is, the previous loop did not obtain the target data in the second cache area 2, then S1-S4 can be re-executed.

[0059] Optionally, data can be exchanged between registers. For example, the register stores the read target data into a corresponding storage location in the register according to the fourth access address. The fourth access address represents the location of the target data obtained by the register from the main memory in the register. When the CPU obtains a new access request, it can directly obtain the newly obtained target data in the register.

[0060] like Figure 3 As shown, the system for improving CPU execution efficiency according to the embodiment of the present invention includes an access request acquisition module 202, a first data acquisition module 203, a second data acquisition module 204 and a storage module 205;

[0061] An access request obtaining module 202 is configured to obtain an access request, wherein the access request includes a first access address of target data, and the first access address represents a storage location of the target data in the temporary register;

[0062] A first data acquisition module 203 is configured to acquire target data from the temporary memory based on the first access address. If the target data is not acquired from the temporary memory, a second access address corresponding to the target data is determined based on the first access address, where the second access address represents a storage location of the target data in the main memory.

[0063] A second data acquisition module 204 is configured to acquire target data from the main memory according to the second access address;

[0064] The storage module 205 is configured to store the target data in the temporary register according to the target storage address, where the target storage address represents the storage address of the target data in the temporary register.

[0065] Optionally, the first data acquisition module 203 further includes a target storage address module;

[0066] The target storage address module is used to determine the target storage address corresponding to the target data from each second storage address according to the target storage address and the first corresponding relationship, where the first corresponding relationship is the corresponding relationship between each first storage address and each second storage address.

[0067] The system also includes a loopback module and a fourth data acquisition module;

[0068] a loopback module, configured to use any one of the second buffer areas as a first starting buffer area and a second buffer area preceding the first starting buffer area as a first ending buffer area;

[0069] Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, and ending at the first ending buffer area as a loop;

[0070] The fourth data acquisition module is used to use the second cache area corresponding to the second access address as a new first starting cache area. When a new access request is obtained and the new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, the data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and the new target data of the first cache area is stored in the temporary register according to the target storage address to obtain the new target data from the main memory.

[0071] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a program stored in the memory and running on the processor. When the processor executes the program, some or all steps of a method for improving CPU execution efficiency are implemented.

[0072] Among them, the electronic device can be a computer, and correspondingly, its program is computer software. The above-mentioned parameters and steps in an electronic device of the present invention can refer to the parameters and steps in the embodiment of the method for improving CPU execution efficiency above, and will not be repeated here.

[0073] A specific application of this embodiment:

[0074] like Figure 2 As shown, the CPU obtains the access request and obtains the target data from the temporary register according to the first access address. If the CPU does not obtain the target data, it executes a loop starting from the second cache area 3 of the main memory according to the second access address, that is, reading the new target data from the second cache area 3 until the end of the second cache area 7. Since the temporary register can perform read and store operations at the same time, when the temporary register reads the second cache area 3, the new target data of the second cache area 3 can be directly stored in the first cache area 3 in the temporary register according to the target storage address and the first corresponding relationship. At the same time, the CPU reads the new target data from the first cache area 3 in the temporary register.

[0075] Those skilled in the art will appreciate that the present invention may be implemented as a system, method, or computer program product. Therefore, the present disclosure may be specifically implemented in the following forms, namely: in the form of complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, the present invention may also be implemented in the form of a computer program product in one or more computer-readable media, the computer-readable media containing computer-readable program code. Computer-readable storage media may be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof.

[0076] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0077] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for improving CPU execution efficiency, characterized in that: The following steps are involved: S1, obtaining an access request, wherein the access request includes a first access address of target data, and the first access address represents a storage location of the target data in a temporary register; S2, obtaining the target data from the temporary memory according to the first access address. If the target data is not obtained from the temporary memory, determining a second access address corresponding to the target data according to the first access address, where the second access address represents a storage location of the target data in the main memory; S3, acquiring the target data from the main memory according to the second access address; S4, storing the target data in a temporary register according to a target storage address, where the target storage address represents a storage address of the target data in the temporary register; Among them, the temporary register is set between the main memory and the CPU; The temporary memory includes a plurality of first buffer areas, the main memory includes a plurality of second buffer areas, each first buffer area corresponds to a first storage address, each second buffer area corresponds to a second storage address, and each first storage address includes the target storage address; Storing the target data in a temporary register according to the target storage address includes: The target storage address corresponding to the target data is determined from each of the second storage addresses according to the target storage address and a first corresponding relationship, wherein the first corresponding relationship is a corresponding relationship between each of the first storage addresses and each of the second storage addresses.

2. The method according to claim 1, characterized in that The method further comprises: Taking any one of the second buffer areas as a first starting buffer area, and the second buffer area preceding the first starting buffer area as a first ending buffer area; Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, to the first ending buffer area as a loop; The second cache area corresponding to the second access address is used as a new first starting cache area. When a new access request is obtained and new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and according to the target storage address, the new target data of the first cache area is stored in the temporary register to obtain the new target data from the main memory.

3. A system for improving CPU execution efficiency, characterized in that: It includes an access request acquisition module, a first data acquisition module, a second data acquisition module and a storage module; The access request acquisition module is configured to acquire an access request, wherein the access request includes a first access address of target data, and the first access address represents a storage location of the target data in the temporary register; The first data acquisition module is configured to acquire the target data from the temporary memory according to the first access address, and if the target data is not acquired from the temporary memory, determine a second access address corresponding to the target data according to the first access address, wherein the second access address represents a storage location of the target data in the main memory; The second data acquisition module is used to acquire the target data from the main memory according to the second access address; A storage module, configured to store the target data in a temporary register according to a target storage address, wherein the target storage address represents a storage address of the target data in the temporary register; The first data acquisition module also includes a target storage address module; The target storage address module is used to determine the target storage address corresponding to the target data from each second storage address according to the target storage address and a first corresponding relationship, where the first corresponding relationship is a corresponding relationship between each first storage address and each second storage address.

4. The system according to claim 3, characterized in that The system also includes a loopback module and a fourth data acquisition module; The loopback module is configured to use any one of the second buffer areas as a first starting buffer area and a second buffer area preceding the first starting buffer area as a first ending buffer area; Determine a path formed from the first starting buffer area, sequentially passing through each second buffer area after the first starting buffer area, to the first ending buffer area as a loop; The fourth data acquisition module is used to use the second cache area corresponding to the second access address as a new first starting cache area. When a new access request is obtained and new target data corresponding to the new access request is not obtained from the temporary register according to the new access request, starting from the new first starting cache area, the data in each second cache area after the new first starting cache area is stored in the corresponding first cache area, and the new target data of the first cache area is stored in the temporary register according to the target storage address to obtain the new target data from the main memory.

5. An electronic device comprising a memory, a processor, and a program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the steps of the method for improving CPU execution efficiency as described in any one of claims 1 to 2 are implemented.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device executes the steps of the method for improving CPU execution efficiency as described in any one of claims 1 to 2.

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