Memory device

Abstract

The embodiments provide a storage device capable of improving performance. The storage device of the embodiments includes: a storage cell comprising a storage element and a switching element; and a circuit that applies a first write pulse having a first polarity to the storage cell when writing first data to the storage cell, and applies a second write pulse having a second polarity different from the first polarity to the storage cell when writing second data to the storage cell, wherein the switching element has a polarity dependence corresponding to the first polarity and the second polarity.

Description

[0001] This application enjoys priority to Japanese Patent Application No. 2021-040502 (filed March 12, 2021) and U.S. Patent Application No. 17 / 470867 (filed September 9, 2021). This application incorporates the entire contents of the basic applications by reference to them. Technical Field

[0002] Embodiments of the present invention relate to storage devices. Background Technology

[0003] Memory devices that use variable resistive elements (such as magnetoresistive elements) as storage elements are known. To improve the characteristics of memory devices, research and development of various technologies have been advanced. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a storage device that can improve performance.

[0005] The storage device of the embodiment includes: a storage cell including a storage element and a switching element; and a circuit that applies a first write pulse having a first polarity to the storage cell when writing first data to the storage cell, and applies a second write pulse having a second polarity different from the first polarity to the storage cell when writing second data to the storage cell, wherein the switching element has a polarity dependence corresponding to the first polarity and the second polarity. Attached Figure Description

[0006] Figure 1 This is a diagram showing an example of the configuration of the storage device according to the first embodiment.

[0007] Figure 2 This is a circuit diagram of the memory cell array of the memory device according to the first embodiment.

[0008] Figure 3 and Figure 4 This is a cross-sectional view showing a structural example of the memory cell array of the memory device according to the first embodiment.

[0009] Figure 5 This is a cross-sectional view showing a structural example of the storage cell of the storage device according to the first embodiment.

[0010] Figure 6 This is a diagram used to explain an example of the operation of the storage device in the first embodiment.

[0011] Figure 7 as well as Figure 8 This is a diagram used to explain the storage device of the first embodiment.

[0012] Figure 9 as well as Figure 10 This is a diagram used to illustrate the storage device of the second embodiment.

[0013] Figure 11 This is a diagram used to illustrate the storage device of the third embodiment.

[0014] Label Explanation

[0015] 1: Storage device; 20: Switching element; 201, 203: Electrodes; 202: Switching layer; 21: Storage element. Detailed Implementation

[0016] Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having the same function and structure will be assigned the same reference numerals.

[0017] In the following embodiments, for the same multiple components (e.g., circuits, wiring, various voltages, and signals), numbers / letters are sometimes added to the end of the reference numerals for differentiation.

[0018] When the constituent elements that are assigned reference labels at the end for differentiation can also be indistinguishable from each other, the record with the final numbers / letters omitted (reference label) is used.

[0019] [Implementation Method]

[0020] Reference Figures 1 to 11 The storage device of the implementation method and its design method are described.

[0021] (1) First Embodiment

[0022] Reference Figures 1 to 8 The storage device of the first embodiment and its design method will be described.

[0023] (a) Example of composition

[0024] (a-1) Overall Composition

[0025] Reference Figures 1-5 The configuration of the storage device in the first embodiment will be described.

[0026] Figure 1 This is a diagram illustrating an example of the configuration of the storage device in this embodiment.

[0027] like Figure 1As shown, in this embodiment, the storage device 1 is connected to an external device (hereinafter referred to as an external device) 9. The external device 9 sends commands CMD, address ADR, and control signals CNT to the storage device 1. Data DT is transferred between the storage device 1 and the external device 9. During a write operation, the external device 9 sends data to be written into the storage device 1 (hereinafter referred to as write data). During a read operation, the external device 9 receives data read from the storage device 1 (hereinafter referred to as read data).

[0028] The storage device 1 in this embodiment includes a storage cell array 10, a row control circuit 11, a column control circuit 12, a write circuit 13, a read circuit 14, a voltage generation circuit 15, an input / output circuit 16, and a control circuit 17.

[0029] The storage cell array 10 includes multiple storage cells MC, multiple word lines WL, and multiple bit lines BL.

[0030] Multiple memory cells (MCs) are associated with multiple rows and columns within the memory cell array 10. Each memory cell (MC) is connected to a corresponding word line (WL). Each memory cell (MC) is connected to a corresponding bit line (BL).

[0031] Row control circuit 11 is connected to memory cell array 10 via word lines WL. The row address (or the decoded result of the row address) of memory cell array 10 in address ADR is provided to row control circuit 11. Based on the decoded result of the row address, row control circuit 11 controls multiple word lines WL. Thus, row control circuit 11 sets multiple word lines WL (multiple rows) to a selected state or a non-selected state respectively. Hereinafter, word lines WL set to the selected state are referred to as selected word lines WL, and word lines WL other than selected word lines WL are referred to as non-selected word lines WL.

[0032] Column control circuit 12 is connected to memory cell array 10 via bit lines BL. The column address (or the decoded result of the column address) of memory cell array 10 in address ADR is provided to column control circuit 12. Based on the decoded result of column address ADR, column control circuit 12 controls multiple bit lines BL. Thus, column control circuit 12 sets multiple bit lines BL (multiple columns) to either a selected state or a non-selected state. Hereinafter, the bit lines BL set to the selected state are referred to as selected bit lines BL, and the bit lines BL other than selected bit lines BL are referred to as non-selected bit lines BL.

[0033] The write circuit 13 writes data to the memory cell MC. The write circuit 13 supplies voltages for writing data to the select word line WL and the select bit line BL, respectively. Thus, a write voltage (or write current) is supplied to the selected memory cell MC. The write circuit 13 can supply any one of a plurality of write voltages corresponding to the written data to the selected memory cell MC. For example, the plurality of write voltages each have a polarity (bias direction) corresponding to the written data. For example, the write circuit 13 includes a write driver (not shown).

[0034] The readout circuit 14 reads data from the memory cell MC. The readout circuit 14 amplifies the signal output from the selected memory cell MC to the select bit line BL. Based on the amplified signal, the readout circuit 14 identifies the data within the memory cell MC. For example, the readout circuit 14 includes a preamplifier (not shown) and a sense amplifier (not shown).

[0035] The voltage generation circuit 15 uses the power supply voltage provided from the external device 9 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 15 generates various voltages used in the write operation. The voltage generation circuit 15 outputs the generated voltages to the write circuit 13. For example, the voltage generation circuit 15 generates various voltages used in the read operation. The voltage generation circuit 15 outputs the generated voltages to the read circuit 14.

[0036] Input / output circuit 16 functions as an interface circuit for various signals (ADR, CMD, CNT, DT) between storage device 1 and external device 9. Input / output circuit 16 transmits the address (ADR) from external device 9 to control circuit 17. Input / output circuit 16 transmits the command (CMD) from external device 9 to control circuit 17. Input / output circuit 16 transmits various control signals (CNT) between external device 9 and control circuit 17. Input / output circuit 16 transmits write data (DT) from external device 9 to write circuit 13. Input / output circuit 16 transmits data (DT) from read circuit 14 to external device 9 as read data.

[0037] The control circuit (also known as a sequencer, state machine, or internal controller) 17 decodes the command CMD. Based on the decoding result of the command CMD and the control signal CNT, the control circuit 17 controls the operation of the row control circuit 11, column control circuit 12, write circuit 13, read circuit 14, voltage generation circuit 15, and input / output circuit 16 within the storage device 1. The control circuit 17 also decodes the address ADR. The control circuit 17 sends the address decoding result to the row control circuit 11 and column control circuit 12, etc. Furthermore, the circuit for decoding commands (command decoder) and the circuit for decoding addresses (address decoder) can also be externally located within the storage device 1.

[0038] (a-2) Storage cell array

[0039] Reference Figures 2-4 Here, an example of the configuration of the memory cell array in the memory device of this embodiment will be described.

[0040] Figure 2 This is an equivalent circuit diagram illustrating an example of the configuration of a memory cell array of the memory device according to this embodiment.

[0041] like Figure 2 As shown, multiple memory cells MC are arranged in a matrix within the memory cell array 10. Each memory cell MC is connected to a corresponding bit line BL (BL<0>, BL<1>, ..., BL<i-1>) and a corresponding word line WL (WL<0>, WL<1>, ..., WL<j-1>). i and j are integers greater than or equal to 2.

[0042] Each storage cell MC includes a switching element 20 and a storage element (variable resistor element) 21.

[0043] The switching element 20 functions as a selection element for the storage cell MC. The switching element 20 has the following functions: when writing and reading data to the corresponding storage cell 21, it controls the voltage (or current) supply to the storage cell 21.

[0044] For example, when the voltage applied to a certain polarity of a memory cell MC is lower than the threshold voltage of the switching element 20 within that polarity, the switching element 20 is set to a cutoff state (high resistance state, non-conducting state). In this case, the switching element 20 disconnects the voltage (or current) supplied to the memory element 21. When the voltage applied to a certain polarity of a memory cell MC is higher than the threshold voltage of the switching element 20 within that polarity, the switching element 20 is set to a ON state (low resistance state, conducting state). In this case, the switching element 20 supplies voltage (or current) to the memory element 21.

[0045] The switching element 20 can switch whether current flows in the storage cell MC based on the magnitude of the voltage applied to the storage cell MC, regardless of the direction of current flow within the storage cell.

[0046] For example, the switching element 20 is a two-terminal type element.

[0047] Storage element 21 is a variable resistor. The resistance state of storage element 21 changes to multiple resistance states (e.g., low resistance state and high resistance state) depending on the voltage (or current) supplied. Storage element 21 can store data by associating the resistance state of element 21 with data (e.g., data "0" and data "1").

[0048] Figure 3 and Figure 4 This is a diagram illustrating an example of the structure of the memory cell array of the memory device in this embodiment. Figure 3 It is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array along the X direction (axis). Figure 4 It is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array along the Y direction (axis).

[0049] like Figure 3 and Figure 4 As shown, the memory cell array 10 is disposed above the upper surface of the substrate 100.

[0050] Hereinafter, the plane parallel to the upper surface of the substrate 100 is called the X-Y plane. The direction (axis) perpendicular to the X-Y plane is called the Z direction (Z axis).

[0051] Multiple conductive layers 50 are disposed above the upper surface of the substrate 100 in the Z direction, separated by an insulating layer 90. The multiple conductive layers 50 are arranged along the Y direction. Each conductive layer 50 extends along the X direction. The multiple conductive layers 50 function, for example, as word lines WL.

[0052] Multiple conductive layers 51 are disposed above multiple conductive layers 50 in the Z direction. The multiple conductive layers 51 are arranged along the X direction. Each conductive layer 51 extends along the Y direction. The multiple conductive layers 51 function, for example, as bit lines BL.

[0053] Multiple memory cells MC are disposed between multiple conductive layers 50 and multiple conductive layers 51. The multiple memory cells MC are arranged in a matrix in the X-Y plane.

[0054] Multiple memory cells MC arranged in the X direction are disposed on a conductive layer 50. The multiple memory cells MC arranged in the X direction are connected to a common word line WL.

[0055] Multiple memory cells MC arranged in the Y direction are disposed under a conductive layer 51. The multiple memory cells MC arranged in the Y direction are connected to a common bit line BL.

[0056] For example in Figure 2 In the memory cell array 10 composed of circuits, a switching element 20 is disposed below the memory element 21 in the Z direction. The switching element 20 is disposed between the memory element 21 and the conductive layer (word line) 50. The memory element 21 is disposed between the conductive layer 51 and the switching element 20.

[0057] In addition, it has Figure 2 The structure of the memory cell array 10 composed of circuits is not limited to Figure 3 and Figure 4 For example, the switching element 20 may also be positioned above the storage element 21 in the Z direction. In this case, the conductive layer 50 is used as the bit line BL, and the conductive layer 51 is used as the word line WL.

[0058] Storage unit MC sometimes as Figure 3 and Figure 4 As shown by the dashed line TP, it has a tapered cross-sectional shape depending on the process used in forming the memory cell array 10. For example, in the tapered memory cell MC, the size of the bottom of the memory cell MC in the direction parallel to the surface of the substrate 100 (the portion on the conductive layer 50 side of the memory cell MC in this embodiment) is larger than the size of the top of the memory cell MC in the direction parallel to the surface of the substrate 100 (the portion on the conductive layer 51 side of the memory cell MC in this embodiment).

[0059] exist Figure 3 and Figure 4 An example is shown where an insulating layer 90 is disposed between the plurality of conductive layers 50 and the substrate 100. When the substrate 100 is a semiconductor substrate, field-effect transistors (not shown) may also be disposed on the upper surface of the substrate 100. The field-effect transistors are covered by the insulating layer 90. The field-effect transistors on the substrate 100 are constituent elements of circuits such as the row control circuit 11. The field-effect transistors are connected to the memory cell array 10 via contact plugs (not shown) and wiring (not shown) within the insulating layer 90. Thus, circuitry for controlling the operation of the memory cell array 10 may be disposed below the memory cell array 10 in the Z direction. Furthermore, if the substrate 100 is an insulating substrate, the plurality of conductive layers 50 may be disposed directly on the upper surface of the substrate 100 without the insulating layer 90.

[0060] The circuit configuration and structure of the stacked memory cell array 10 are not limited to... Figures 2-4The example shown illustrates this. The circuit configuration and structure of the memory cell array can be appropriately modified based on the connection relationship between the switching element 20 and the storage element 21 relative to the bit line BL and the word line WL.

[0061] (a-3) storage unit

[0062] Figure 5 This is a cross-sectional view showing an example of the structure of a storage cell in the storage device of this embodiment.

[0063] like Figure 5 As shown, the storage cell MC is a stack including switching elements 20 and storage elements 21. Within each storage cell MC, the switching elements 20 and storage elements 21 are arranged in the Z direction.

[0064] In the above Figures 2-4 In the example, within each storage cell MC, the storage element (variable resistor element) 21 is disposed on the switching element 20 in the Z direction.

[0065] For example, the variable resistor element 21 is a magnetoresistive element. In this case, the storage device of this embodiment is a magnetic memory such as MRAM (Magnetoresistive Random Access memory).

[0066] For example, the magnetoresistive element 21 includes at least two magnetic layers 211 and 213 and a non-magnetic layer 212. The non-magnetic layer 212 is disposed between the two magnetic layers 211 and 213 in the Z direction. Figures 2-4 In the example, multiple layers 211, 212, and 213 are arranged in the Z direction from the word line WL side to the bit line BL side in the order of magnetic layer 211, non-magnetic layer 212, and magnetic layer 213.

[0067] Two magnetic layers 211 and 213 and a non-magnetic layer 212 form a magnetic tunnel junction (MTJ). Hereinafter, the magnetoresistive element 21 including the magnetic tunnel junction is referred to as the MTJ element 21. The non-magnetic layer 212 in the MTJ element 21 is referred to as the tunnel barrier layer.

[0068] Magnetic layers 211 and 213 are, for example, ferromagnetic layers containing cobalt, iron, and / or boron. Magnetic layers 211 and 213 can be either single-layer or multilayer films (e.g., artificial lattice films). Tunnel barrier layer 212 is, for example, an insulating layer containing oxygen and magnesium, or essentially an insulating layer containing magnesium oxide. Tunnel barrier layer can be either a single-layer or multilayer film.

[0069] In this embodiment, the MTJ element 21 is a perpendicularly magnetized magnetoresistive element. For example, each magnetic layer 211, 213 has perpendicular magnetic anisotropy. The easy magnetization axis of each magnetic layer 211, 213 is perpendicular to the layer (film surface) of the magnetic layers 211, 213. The magnetization direction of each magnetic layer 211, 213 is parallel to the alignment direction (Z direction) of the magnetic layers 211, 213. Each magnetic layer 211, 213 has magnetization perpendicular to the layer of the magnetic layers 211, 213.

[0070] The magnetization direction of one of the two magnetic layers 211 and 213 can be variable, while the magnetization direction of the other magnetic layer remains constant. The MTJ element 21 can have multiple resistance states (resistance values) depending on the relative relationship (magnetization arrangement) between the magnetization directions of one magnetic layer and the other magnetic layer.

[0071] exist Figure 5 In this example, the magnetization direction of magnetic layer 213 is variable. The magnetization direction of magnetic layer 211 remains constant (fixed state). Hereinafter, magnetic layer 213 with variable magnetization direction is referred to as a storage layer. Hereinafter, magnetic layer 211 with constant magnetization direction (fixed state) is referred to as a reference layer. Furthermore, storage layer 213 is sometimes also referred to as a free layer, a magnetized free layer, or a magnetized variable layer. Reference layer 211 is sometimes also referred to as a pin layer, a pinned layer, a magnetized constant layer, or a magnetized fixed layer.

[0072] In this embodiment, "the magnetization direction of the reference layer (magnetic layer) remains unchanged" or "the magnetization direction of the reference layer (magnetic layer) is fixed" means that when a current or voltage used to change the magnetization direction of the storage layer is supplied to the magnetoresistive element, the magnetization direction of the reference layer does not change before or after the supply of current / voltage.

[0073] When the magnetization direction of the storage layer 213 is the same as that of the reference layer 211 (when the magnetization arrangement of the MTJ element 21 is in a parallel arrangement), the resistance state of the MTJ element 21 is the first resistance state.

[0074] When the magnetization direction of the storage layer 213 is different from that of the reference layer 211 (when the magnetization arrangement of the MTJ element 21 is antiparallel), the resistance state of the MTJ element 21 is a second resistance state, which is different from the first resistance state. The resistance value of the MTJ element 21 in the second resistance state (antiparallel arrangement) is higher than the resistance value of the MTJ element 21 in the first resistance state (parallel arrangement).

[0075] The following describes the magnetization arrangement of MTJ elements: the parallel arrangement is referred to as the P state, and the antiparallel arrangement is referred to as the AP state.

[0076] For example, the MTJ element 21 includes two electrodes 219A and 219B. Magnetic layers 211 and 213 and a tunnel barrier layer 212 are disposed between the two electrodes 219A and 219B in the Z direction. A reference layer 211 is disposed between electrode 219A and tunnel barrier layer 212. A storage layer 213 is disposed between electrode 219B and tunnel barrier layer 212.

[0077] For example, a shift cancel layer (not shown) can also be provided within the MTJ element 21. The shift cancel layer is disposed between the reference layer 211 and the electrode 219A. The shift cancel layer is a magnetic layer used to mitigate the effects of leakage magnetic fields in the reference layer 211.

[0078] In the case where the MTJ element 21 includes a transition elimination layer, a non-magnetic layer (not shown) is disposed between the transition elimination layer and the reference layer 211. The non-magnetic layer is, for example, a metal layer such as a Ru layer.

[0079] The transition elimination layer is coupled to the reference layer 211 via a non-magnetic layer in an antiferromagnetic manner. Thus, the stack including the reference layer 211 and the transition elimination layer forms a SAF (Synthetic Antiferromagnetic) structure. In the SAF structure, the magnetization direction of the transition elimination layer is opposite to the magnetization direction of the reference layer 211. Through the SAF structure, the magnetization direction of the reference layer 211 is set to a fixed state.

[0080] For example, the MTJ element 21 may also include at least one of a substrate layer (not shown) and a capping layer (not shown). The substrate layer is disposed between the magnetic layer (reference layer in this case) 211 and the electrode 219A. The substrate layer is a non-magnetic layer (e.g., a conductive compound layer). The substrate layer is used to improve the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 211 in contact with the substrate layer. The capping layer is disposed between the magnetic layer (storage layer in this case) 213 and the electrode 219B. The capping layer is a non-magnetic layer (e.g., a conductive compound layer). The capping layer is used to improve the properties (e.g., crystallinity and magnetic properties) of the magnetic layer 213 in contact with the capping layer. Furthermore, the substrate layer and the capping layer may also be considered as components of the electrodes 219 (219A, 219B).

[0081] When the switching element 20 is a two-terminal type element, the switching element 20 includes at least two electrodes (conductive layers) 201, 203 and a switching layer 202. The switching layer 202 is disposed between the two electrodes 201, 203 in the Z direction. The switching layer 202 is a variable resistance layer.

[0082] Depending on the voltage applied to the switching element 20 (memory cell MC), the resistance state of the switching layer 202 becomes either a high resistance state (non-conducting state) or a low resistance state (conducting state).

[0083] When the resistance of the switching layer 202 is high, the switching element 20 is off. When the resistance of the switching layer 202 is low, the switching element 20 is on.

[0084] When the memory cell MC is set to the selected state, the resistance of the switch layer 202 is in a low resistance state in order to turn on the switch element 20. When the memory cell MC is set to the non-selected state, the resistance of the switch layer 202 is in a high resistance state in order to turn off the switch element 20.

[0085] Furthermore, depending on the material of the switching layer 202, the change in the resistance state of the switching layer 202 sometimes also depends on the current flowing within the switching element 20 (memory cell) (e.g., the magnitude of the current).

[0086] The material of the switching layer 202 is, for example, an insulator containing dopants. An example of an insulator used in the switching layer 202 is oxygen and silicon, or substantially silicon oxide. When the material of the switching layer 202 is silicon oxide, the dopant added to the silicon oxide is arsenic (As) or germanium (Ge). For example, the dopant is added to the switching layer 202 by ion implantation.

[0087] The material of the switching layer 202 can also be other materials, such as conductive or insulating oxides, conductive or insulating nitrides, or semiconductors. Depending on the material used in the switching layer 202, the type of dopant added to the switching layer 202 can be varied. The type of dopant added to the silicon oxide used as the switching layer 202 is not limited to the examples described above.

[0088] The materials for electrodes 201 and 203 can be selected from metals, conductive compounds, and semiconductors. Alternatively, the materials for electrodes 201 and 203 can be selected based on the material of the switch layer 202.

[0089] Hereinafter, in the two electrodes 201 and 203 of the switching element 20, the electrode 201 on the substrate side is referred to as the lower electrode. The electrode 203 that is disposed above the lower electrode 201 in the Z direction (the electrode on the side opposite to the substrate side) is referred to as the upper electrode. Figure 5 In this example, the switching element 20 is connected to the MTJ element 21 via the upper electrode 203.

[0090] In the MRAM1 including the stacked memory cell array 10, a voltage of first polarity or a voltage of second polarity is applied to the selection cell according to the action performed in the memory cell of the object being acted (hereinafter also referred to as the selection cell). The second polarity is different from the first polarity. The current flowing in the selection cell also has a polarity corresponding to the polarity of the applied voltage.

[0091] In the MRAM1 of this embodiment, the switching element 20 has a polarity dependence corresponding to the polarity of the applied voltage (e.g., write voltage) and / or the polarity of the supply current (e.g., write current) to the memory cell MC.

[0092] For example, the threshold voltage (absolute value) Vth1 of the switching element 20 with the applied voltage for the first polarity is different from the threshold voltage (absolute value) Vth2 of the switching element 20 with the applied voltage for the second polarity.

[0093] For example, in this embodiment, the resistance value Rp1 of the switching element 20 when the first polarity applied voltage is applied to the memory cell MC is different from the resistance value Rp2 of the switching element 20 when the second polarity applied voltage is applied to the memory cell MC.

[0094] (b) Example of an action

[0095] Reference Figure 6 An example of the operation of the MRAM in this embodiment will be described.

[0096] External device 9 sends a command CMD corresponding to a user request, the address of the action object (hereinafter also referred to as the selection address) ADR, and a control signal CNT to MRAM1 in this embodiment. When data writing is requested, external device 9 sends the write data DT along with the command and address to MRAM1 in this embodiment.

[0097] In this embodiment, MRAM1 accepts commands CMD, address selection ADR, and control signals CNT. When write data is being sent, MRAM1 accepts the write data.

[0098] In MRAM1, the control circuit 17 controls the operation of each circuit 11 to 16 in MRAM1 based on the decoding results of the command CMD and the decoding results of the selection address ADR.

[0099] Row control circuit 11 selects one word line from multiple word lines WL based on the decoding result of selection address ADR. Column control circuit 12 selects one bit line from multiple bit lines BL based on the decoding result of selection address ADR. The memory cell between the selection word line and the selection bit line is selected as the memory cell (selection cell) of the action object.

[0100] In the following, storage cells other than the selected cells in a set of storage cells (MCs) are referred to as non-selected cells.

[0101] Row control circuit 11 applies a voltage of a certain value to the select word line. Column control circuit 12 applies a voltage of a certain value to the select bit line.

[0102] The potential difference between the select word line and the select bit line is supplied to the select unit as the applied voltage (operation voltage) for the operation of the select unit. The voltage values ​​applied to the select word line and the select bit line have magnitudes corresponding to the operation being performed.

[0103] The memory cell array 10 contains multiple memory cells other than the selection cell (hereinafter referred to as non-selection cells). Each non-selection cell is connected to at least one of a non-selection word line and a non-selection bit line. In the cascaded memory cell array 10, during the operation of the selection cell, the memory cell array 10 contains non-selection cells connected to both the selection word line and the selection bit line, as well as non-selection cells connected to both the selection word line and the selection bit line. Hereinafter, non-selection cells connected to both the selection word line and the selection bit line, as well as non-selection cells connected to both the selection word line and the selection bit line, are also referred to as half-selection cells.

[0104] In order to suppress malfunctions of non-selection and half-selection units during the operation of the selection unit, a voltage of a certain magnitude (hereinafter referred to as the non-selection voltage) is applied to the non-selection word line and non-selection bit line.

[0105] When the command is a write command, the data is written to the selection unit. For example, if the storage unit MC stores 1 bit of data, the first data (e.g., data "0") or the second data (e.g., data "1") is written to the storage unit (selection unit) MC.

[0106] In MRAM1, the magnetization arrangement state of MTJ element 21 is controlled according to the data written to the selection unit.

[0107] For example, when MRAM1 performs a write operation (STT) in the form of data, a write current flowing from the reference layer 211 side to the storage layer 213 side or a write current flowing from the storage layer 213 side to the reference layer 211 side is supplied to the MTJ element 21, depending on the data to be written to the selected cell.

[0108] In MRAM1, the relationship between the potentials of the select word line and the select bit line (the polarity of the applied voltage) is controlled according to the data to be written to the select cell.

[0109] Figure 6 This is a schematic diagram used to illustrate the write operation in the MRAM of this embodiment.

[0110] Figure 6 (a) indicates a write operation for the first data in the memory cell. For example, the first data (data "0") is associated with the parallel alignment state in the magnetization alignment state of the MTJ element 21.

[0111] like Figure 6 As shown in (a), when writing data "0", with the magnetization alignment state of MTJ element 21 set to parallel alignment state (P state), the write current IwAPP is supplied to the selection cell MC-s in a manner that flows from storage layer 213 toward reference layer 211. The write current IwAPP has a current value that is higher than or equal to the magnetization reversal threshold of MTJ element 21. More specifically, the current value of write current IwAPP is higher than or equal to the magnetization reversal threshold of storage layer 213, but lower than the magnetization reversal threshold of reference layer 211.

[0112] In order to generate the write current IwAPP, in MTJ element 21, the potential on the storage layer 213 side is set to be higher than the potential on the reference layer 211 side.

[0113] In this case, a first selection voltage Vsel1 is applied to wiring 51 on the memory layer 213 side (select bit line BL-s in this embodiment), and a second selection voltage Vsel2 is applied to wiring 50 on the reference layer 211 side (select word line WL-s in this embodiment). The voltage value of the first selection voltage Vsel1 is higher than the voltage value of the second selection voltage Vsel2. The selection voltage Vsel1 has, for example, a positive voltage value. The selection voltage Vsel2 is, for example, 0V.

[0114] The potential difference (Vsel1-Vsel2) between the select bit line BL-s and the select word line WL-s is applied to the select cell MC-s as the application voltage VwAPP for the write operation. Hereinafter, the operating voltage applied to the select cell for the write operation is referred to as the write voltage.

[0115] In this embodiment, the polarity of the write voltage VwAPP applied to the memory cell MC to make the potential on the memory layer 213 side of the MTJ element 21 higher than the potential on the reference layer 211 side of the MTJ element 21 is referred to as the first polarity. In the memory cell array 10 having Figures 2-5 In the case of the configuration, when the write voltage VwAPP of the first polarity is applied, the potential of the upper wiring 51 of the MTJ element 21 is higher than the potential of the lower wiring 50 of the MTJ element 21.

[0116] Based on the potential difference (write voltage) VwAPP between the select bit line BL-s and the select word line WL-s, the switching element 20 in the select unit MC-s is turned on. For the select unit to which the first polarity write voltage VwAPP is applied, the threshold voltage (absolute value) of the switching element 20 is below the write voltage (absolute value) VwAPP.

[0117] For example, when writing data "0", the switch element 20 in the ON state has a resistance value Rp1.

[0118] A write current IwAPP with a polarity corresponding to the polarity of the write voltage VwAPP is generated by using a write voltage VwAPP with a first polarity to write the data "0". The write current IwAPP generated by the write voltage VwAPP with the first polarity is called the write current IwAPP with the first polarity.

[0119] A write current IwAPP with the first polarity flows from the storage layer 213 to the reference layer 211 within the MTJ element 21.

[0120] The spin torque is generated within the MTJ element 21 due to the write current IwAPP. Through the spin torque, the magnetization direction of the storage layer 213 is reversed from the direction opposite to the magnetization direction of the reference layer 211 to the direction of the magnetization direction of the reference layer 211.

[0121] As a result, the magnetization arrangement state of MTJ element 21 changes from AP state to P state.

[0122] As a result, the data "0" is written into the selection unit MC-s. The selection unit MC-s is able to store the written data "0" in a substantially non-volatile manner until the data "1" is written to the selection unit MC-s.

[0123] Furthermore, when the write current IwAPP is supplied, and the magnetization arrangement of the MTJ element 21 is in the P state (data "0" holding state), even if the write current IwAPP for writing data "0" flows within the MTJ element 21, the magnetization reversal of the storage layer 213 does not occur. Therefore, when writing data "0", no data rewriting occurs in the storage cell storing data "0".

[0124] Figure 6 (b) is a schematic diagram illustrating the write operation of the second data for the storage unit.

[0125] For example, the second data (data "1") is associated with the antiparallel alignment state in the magnetization alignment state of MTJ element 21.

[0126] like Figure 6As shown in (b), when writing data "1", with the magnetization alignment state of MTJ element 21 set to antiparallel alignment state (AP state), the write current IwPAP is supplied to the select cell MC-s in a direction flowing from the reference layer 211 toward the storage layer 213. In order to generate the write current IwPAP, in MTJ element 21, the potential on the reference layer 211 side is set to be higher than the potential on the storage layer 213 side.

[0127] In this case, a third selection voltage Vsel3 is applied to wiring 50 on the reference layer 211 side (select word line WL-s in this embodiment), and a fourth selection voltage Vsel4 is applied to wiring 51 on the memory layer 213 side (select bit line BL-s in this embodiment). The voltage value of the third selection voltage Vsel3 is higher than the voltage value of the fourth selection voltage Vsel4. The selection voltage Vsel3 has a positive voltage value. The selection voltage Vsel4 is, for example, 0V.

[0128] The potential difference (|Vsel3-Vsel4|) between the select word line WL-s and the select bit line BL-s is applied to the select cell MC-s as the write voltage VwPAP.

[0129] In this embodiment, the polarity of the write voltage VwPAP applied to the memory cell MC to make the potential on the reference layer 211 side of the MTJ element 21 higher than the potential on the memory layer 213 side of the MTJ element 21 is referred to as the second polarity. In the memory cell array 10 having Figures 2-5 In the case of the configuration, when the write voltage VwPAP of the second polarity is applied, the potential of the wiring 50 below the MTJ element 21 is higher than the potential of the wiring 51 above the MTJ element 21.

[0130] If the polarities of the write voltages VwPAP and VwAPP are different, then the absolute value of the write voltage VwPAP can be the same as or different from the absolute value of the write voltage VwPPA. Similarly, the voltage value of voltage Vsel3 can be the same as or different from the voltage value of voltage Vsel1. Likewise, the voltage value of voltage Vsel4 can be the same as or different from the voltage value of voltage Vsel2.

[0131] The switching element 20 within the selection unit MC-s is turned on by the write voltage VwPAP. For the selection unit to which the second polarity write voltage VwPAP is applied, the threshold voltage (absolute value) of the switching element 20 is below the write voltage (absolute value) VwPAP.

[0132] For example, when writing the data "1", the switch element 20 in the ON state has a resistance value Rp2. The value of resistance Rp2 is different from the value of resistance Rp1.

[0133] A write current IwPAP with a polarity corresponding to the polarity of the write voltage VwPAP is generated by using a write voltage VwPAP with a second polarity to write the data "1". The write current IwPAP generated by the write voltage VwPAP with a second polarity is called the write current IwPAP with a second polarity.

[0134] A write current IwPAP with a second polarity flows from the reference layer 211 to the storage layer 213 within the MTJ element 21. The write current IwPAP has a current value above the magnetization reversal threshold of the MTJ element 21.

[0135] The spin torque is generated within the MTJ element 21 due to the write current IwPAP. This spin torque reverses the magnetization direction of the storage layer 213 from the same direction as the magnetization direction of the reference layer 211 to the opposite direction.

[0136] As a result, the magnetization arrangement of MTJ element 21 changes from the P state to the AP state.

[0137] As a result, the data "1" is written into the selection unit MC-s. The selection unit MC-s is able to store the written data "1" in a substantially non-volatile manner until the data "0" is written to the selection unit MC-s.

[0138] Furthermore, when the write current IwPAP is supplied, and the magnetization arrangement of the MTJ element 21 is in the AP state (data "1" holding state), even if the write current IwPAP for writing data "1" flows within the MTJ element 21, the magnetization reversal of the storage layer 213 does not occur. Therefore, when writing the second data, no data rewriting occurs in the storage cell storing the second data.

[0139] Under the bias state of the applied voltage of the selection cell MC-s, the second polarity is different from the first polarity. Hereinafter, the first polarity is referred to as the negative polarity, and the second polarity is referred to as the positive polarity. The write current IwAPP caused by the negative polarity write voltage VwAPP is called the negative polarity write current. The write current IwPAP caused by the positive polarity write voltage VwPAP is called the positive polarity write current.

[0140] The bias state of the select cell MC-s voltage when a negative write voltage VwAPP is applied is called the negative bias state. The bias state of the select cell MC-s voltage when a positive write voltage VwPAP is applied is called the positive bias state.

[0141] In the following, to indicate the different polarities of the write voltages VwAPP and VwPAP, the write voltage VwAPP is sometimes described as "-VwAPP (or VwAPP(-))" and the write voltage VwPAP is sometimes described as "+VwPAP (or VwPAP(+))". Furthermore, if the potential difference between the select word line and the select bit line, as well as the polarity of the write voltage (write current), are set so that predetermined write data is written to the select unit, a select voltage with a negative voltage value can also be applied to the select word line or the select bit line.

[0142] For example, depending on the polarity dependence of MTJ element 21, the absolute value of the write voltage VwPAP (|+VwPAP|) can be larger than the absolute value of the write voltage VwAPP (|-VwAPP|). Therefore, the write error rate (WER) in the MTJ element (memory cell) is reduced. Furthermore, characteristics of MTJ element 21, such as those related to time-dependent dielectric breakdown (TDDB), are improved.

[0143] Hereinafter, the write voltage and write current used to write data to the memory cell are collectively referred to as write pulses.

[0144] Figure 6 (c) is a schematic diagram used to illustrate the electrical state of the non-selected cell during a write operation.

[0145] like Figure 6 As shown in (c), during the write operation, the non-select voltage Vusel1 is applied to the non-select word line WL-z, and the non-select voltage Vusel2 is applied to the non-select bit line BL-z.

[0146] The non-selective voltages Vusel1 and Vusel2 are, for example, voltage values ​​above 0V.

[0147] The potential difference (hereinafter referred to as the off voltage) Voff between the non-select word line WL-z and the non-select bit line BL-z is smaller than the write voltage (absolute value). No current exceeding the magnetization reversal threshold current of the MTJ element 21 flows within the non-select cell MC-z where the voltage Voff is applied. When the off voltage Voff is applied to the non-select cell MC-z, the switching element 20 is off.

[0148] As described above, when performing an action on a selection cell, a half-selection cell exists in the storage cell array 10.

[0149] Set the voltage values ​​of non-selection voltages Vusel1 and Vusel2 to prevent malfunctions of the half-selection unit.

[0150] In writing the first data (“0”), the voltage values ​​of the non-selection voltages Vusel1 and Vusel2 are set as follows.

[0151] The voltage value of the non-selection voltage Vusel1 is set such that the potential difference between the non-selection voltage Vusel1 and the selection voltage Vsel2 is smaller than the write voltage VwAPP. For example, the voltage value of the non-selection voltage Vusel1 has a voltage value between the voltage values ​​of the selection voltage Vsel1 and the selection voltage Vsel2.

[0152] For example, when the voltage value of the non-selection voltage Vusel1 is the same as half the potential difference between the voltage values ​​of the selection voltage Vsel1 and the selection voltage Vsel2, a voltage VwAPP / 2 with half the voltage value of the write voltage VwAPP is applied to the half-selection cell connected to the selection bit line BL-s.

[0153] In this case, in the MTJ element 21 within the half-select cell connected to the select bit line BL-s, the potential on the storage layer 213 side is higher than the potential on the reference layer 211 side.

[0154] The voltage value of the non-selection voltage Vusel2 is set such that the potential difference between the non-selection voltage Vusel2 and the selection voltage Vsel1 is smaller than the write voltage VwAPP. For example, the voltage value of the non-selection voltage Vusel2 has the voltage value between the selection voltage Vsel1 and the selection voltage Vsel2.

[0155] For example, when the voltage value of the non-selection voltage Vusel2 is the same as half the potential difference between the voltage values ​​of the selection voltages Vsel1 and Vsel2, a voltage VwAPP / 2 is applied to the half-selection unit connected to the selection word line WL-s.

[0156] In this case, in the MTJ element 21 within the half-select unit connected to the select word line WL-s, the potential on the storage layer 213 side is higher than the potential on the reference layer 211 side.

[0157] When writing data "0", if the voltage values ​​of the non-selection voltages Vusel1 and Vusel2 are set as described above, the polarity of the voltage applied to the half-selection unit is the same as the polarity (negative polarity) of the write voltage VwAPP.

[0158] When writing data "0", the switching elements in the non-selection unit and the half-selection unit are turned off, which suppresses malfunctions of the non-selection unit and the half-selection unit and / or noise to the selection unit, and is therefore preferred.

[0159] The threshold voltage (absolute value) Vth1 of the switching element when writing data "0" is set to be higher than the voltage (absolute value) VwAPP / 2 and lower than the write voltage VwAPP.

[0160] When writing the second data (“1”), the voltage values ​​of the non-selected voltages Vusel1 and Vusel2 are set as follows.

[0161] The voltage value of the non-selection voltage Vusel1 is set such that the absolute value of the potential difference between the non-selection voltage Vusel1 and the selection voltage Vsel4 is smaller than the absolute value of the write voltage VwPAP. For example, the voltage value of the non-selection voltage Vusel1 has a voltage value between the voltage values ​​of the selection voltage Vsel3 and the selection voltage Vsel4.

[0162] For example, if the voltage value of the non-selection voltage Vusel1 is the same as half the potential difference between the voltage values ​​of the selection voltages Vsel3 and Vsel4, a voltage VwPAP / 2 with half the value of the write voltage VwAPP is applied to the half-selection cell connected to the selection bit line BL-s.

[0163] In this case, in the MTJ element 21 within the half-select cell connected to the select bit line BL-s, the potential on the storage layer 213 side is lower than the potential on the reference layer 211 side.

[0164] The voltage value of the non-selection voltage Vusel2 is set such that the potential difference between the non-selection voltage Vusel2 and the selection voltage Vsel3 is smaller than the write voltage VwPAP. For example, the voltage value of the non-selection voltage Vusel2 has the voltage value between the selection voltage Vsel3 and the selection voltage Vsel4.

[0165] For example, when the voltage value of the non-selection voltage Vusel2 is the same as half the potential difference between the voltage values ​​of the selection voltages Vsel3 and Vsel4, a voltage VwPAP / 2 is applied to the half-selection unit connected to the selection word line WL-s.

[0166] In this case, in the MTJ element 21 within the half-select unit connected to the select word line WL-s, the potential on the storage layer 213 side is lower than the potential on the reference layer 211 side.

[0167] When writing data "1", if the voltage values ​​of the non-selection voltages Vusel1 and Vusel2 are set as described above, the polarity of the voltage applied to the half-selection unit is in the same direction as the polarity (positive polarity) of the write voltage VwPAP.

[0168] When writing data "1", the switching elements in the non-selection unit and the half-selection unit are turned off, which suppresses malfunctions of the non-selection unit and the half-selection unit and / or noise to the selection unit, and is therefore preferred.

[0169] When writing data "1", the threshold voltage (absolute value) Vth2 of the switching element is set to be higher than the voltage (absolute value) VwAPP / 2 and lower than the write voltage VwAPP.

[0170] As described above, during the write operation of the selection cell, non-selection voltages Vusel1 and Vusel2 with certain voltage values ​​are applied to the non-selection word line WL-z and the non-selection bit line BL-z.

[0171] Therefore, when writing to a selected cell, erroneous operations on non-selected cells can be suppressed.

[0172] Furthermore, the read operation of MRAM1 in this embodiment is performed using well-known techniques. Therefore, the description of the read operation of MRAM1 is omitted in this embodiment.

[0173] In the MRAM1 of this embodiment, the switching element 20 has a dependence on the polarity of the applied voltage (e.g., write voltage). Thus, in the MRAM1 of this embodiment, the switching element 20, to which a voltage is applied, exhibits different characteristics depending on the polarity of the applied voltage.

[0174] As a result, the MRAM1 of this embodiment can suppress the shrinkage of the operating margin of the MRAM1 (memory cell MC).

[0175] (c) Design Example

[0176] Reference Figures 7-11 A design example (design method) of a switching element in the MRAM1 of this embodiment that is polarity dependent on the applied voltage will be described.

[0177] Figure 7 This is a graph used to illustrate the relationship between the threshold voltage and the write voltage of the switching element of the memory cell in the MRAM1 of this embodiment.

[0178] Figure 7 The horizontal axis corresponds to voltage (voltage value). Figure 7 The vertical axis corresponds to the number of components.

[0179] exist Figure 7 In this system, the voltage (voltage value) when writing data "0" is represented by negative polarity (negative value), and the voltage (voltage value) when writing data "1" is represented by positive polarity (positive value).

[0180] Hereinafter, the threshold voltage of the switching element 20 when writing data "0" is recorded as "-Vth1". The threshold voltage of the switching element 20 when writing data "1" is recorded as "+Vth2". Hereinafter, when the threshold voltages "-Vth1" and "+Vth2" are not distinguished, the threshold voltage is recorded as "Vth".

[0181] exist Figure 7 In this context, "VwAPP" and "VwPAP" represent the write voltages of different polarities mentioned above, and represents the voltage value of that voltage.

[0182] Hereinafter, without distinguishing between write voltages VwAPP and VwPAP, the write voltage will be referred to as "Vw".

[0183] like Figure 7 As shown, the distribution Da of the threshold voltage "-Vth1" of the switching element 20 in writing data "0" is set in the voltage range between the voltage value "-VwAPP" and the voltage value "-VwAPP / 2".

[0184] The distribution Db of the threshold voltage "+Vth2" of the switching element 20 during the writing of data "1" is set within the voltage range between the voltage value "+VwPAP / 2" and the voltage value "+VwPAP".

[0185] As mentioned above, when the write voltages VwAPP and VwPAP are set according to the polarity dependence of the MTJ element, the absolute values ​​of the write voltages VwAPP and VwPAP have the relationship of "|-VwAPP|<|+VwPAP|". However, |-VwAPP| can also be the same as |+VwPAP|.

[0186] The median value of the threshold voltage of the switching element 20 in the threshold voltage distribution Da is recorded as "-medVth1". The median value of the threshold voltage of the switching element 20 in the threshold voltage distribution Db is recorded as "+medVth2".

[0187] Hereinafter, without distinguishing between "-medVth1" and "+medVth2", the central value of the threshold voltage is recorded as "medVth".

[0188] For example, the threshold voltage distributions Da and Db have a normal distribution.

[0189] The standard deviation of “Vth” (σ) Vth This can be expressed as a percentage (s%) of “medVth”. Vth and medVth have "σ Vth The relationship is "=medVth×s / 100". "s" has values ​​greater than 0 and less than 100.

[0190] For example, the normal distribution of threshold voltages Da and Db is represented as "Vth ~ N(medVth, (medVth×(s / 100)). 2 ))".

[0191] The motion margin in MRAM1 is determined by "n×σ". Vth In the case of “n×σ”, Vth This can be represented as "medVth×n×s / 100". Here, "n" is the number of samples (a positive integer). Furthermore, "n×σ" Vth "It can also be regarded as a value associated with the write error rate of MRAM1."

[0192] Based on the action margin (n×σ) in the write action Vth The relationship between the write voltage “Vw” and the threshold voltage of the normally distributed switching element is expressed by the following equations (A) and (B).

[0193] Vw / 2 <medVth-n×σ Vth =medVth×(1-n×s / 100)···(A)

[0194] medVth×(1+n×s / 100) <Vw···(B)

[0195] Equation (A) is equivalent to: the relationship between the voltage value "-Vth1a" (absolute value) of the upper limit of the threshold voltage distribution Da (the upper tail of the distribution) and the voltage value "-Vw / 2 (=-VwAPP / 2)" (absolute value), and the relationship between the voltage value "+Vth2a" (absolute value) of the lower limit of the threshold voltage distribution Db (the lower tail of the distribution) and the voltage value "Vw / 2 (=+VwPAP / 2)" (absolute value).

[0196] In addition, as mentioned above, the non-select voltage values ​​that can be applied to the non-select word lines and bit lines are as follows: the voltage value "Vw / 2" is equivalent to the voltage value applied to the half-select cell during a write operation.

[0197] Equation (B) is equivalent to: the relationship between the voltage value "-Vth1b" (absolute value) of the lower limit (lower tail of the distribution) of the threshold voltage distribution Da and the writing voltage "Vw (=-VwAPP)" (absolute value), and the relationship between the voltage value "+Vth2b" (absolute value) of the upper limit (upper tail of the distribution) of the threshold voltage distribution Db and the writing voltage "Vw (=+VwPAP)" (absolute value).

[0198] Equation (C) can be obtained based on equations (A) and (B).

[0199] medVth×(1+n×s / 100) <Vw<medVth×2×(1-n×s / 100)···(C)

[0200] When the absolute values ​​of the negative write voltage VwAPP and the positive write voltage VwPAP have a relationship of "VwAPP < VwPAP", equation (C) can be expressed as equation (D) below.

[0201] medVth×(1+n×s / 100) <VwAPP<VwPAP<medVth×2×(1-n×s / 100)···(D)

[0202] Here, the magnitudes of the write voltages VwAPP and VwPAP, which are set according to the polarity dependence of the MTJ element (the polarity dependence of the write voltage), are assumed to use the coefficient "a" as in the following equation (E).

[0203] VwPAP = a × VwAPP···(E)

[0204] In equation (E), "a" has a value greater than 1.

[0205] Furthermore, the coefficient "a" represents the polarity dependence of the MTJ element 21 on write voltages VwAPP and VwPAP (or write currents IwAPP and IwPAP) with different polarities (hereinafter also referred to as the polarity dependence coefficient of the MTJ element). "a" can be represented by the voltage ratio of write voltages VwAPP and VwPAP (or the current ratio of write currents IwAPP and IwPAP).

[0206] The polarity dependence of the threshold voltage of the switching element 20 during the write operation is assumed using the central value of the threshold voltage as shown in the following equation (F).

[0207] medVth2=b×medVth1···(F)

[0208] “medVth1” represents the central value of the threshold voltage Vth1 of the switching element 20 when the negative polarity write voltage VwAPP(-) is applied to the selection cell (when writing data “0”).

[0209] “medVth2” represents the midpoint of the threshold voltage Vth2 of the switching element 20 when the positive write voltage VwPAP(+) is applied to the selection cell (when writing data “1”). “medVth1” and “medVth2” are represented by absolute values.

[0210] In equation (F), "b" is a value greater than or equal to 1 (b≥1).

[0211] Furthermore, the coefficient "b" represents the polarity dependence of the switching element 20 on write voltages VwAPP and VwPAP (or write currents IwAPP and IwPAP) with different polarities. "b" can be represented by the voltage ratio of the threshold voltage of the switching element 20 to the write voltages VwAPP and VwPAP (or the ratio of the threshold voltage of the switching element 20 to the write currents IwAPP and IwPAP).

[0212] In the following, the central values ​​medVth1 and medVth2 in the threshold voltage distribution of the switching element 20 are sometimes also regarded as representative values ​​(reference values) of the threshold voltage of the switching element 20 for each write voltage VwAPP and VwPAP, and are considered as the threshold voltage of the switching element 20.

[0213] In this embodiment, the polarity dependence of the switching element 20 is verified based on the coefficient “a” in Equation (E) and the coefficient “b” in Equation (F).

[0214] <<Case where the switching element has no polarity dependence related to the applied voltage>>

[0215] When the switching element has no polarity dependence related to the applied voltage, "b" in equation (F) is 1. In this case, the median value of the threshold voltage of the switching element 20 related to the write voltage VwPAP, medVth2, is equal to the median value of the threshold voltage of the switching element 20 related to the write voltage VwAPP, medVth1. Here, "medVth1" and "medVth2" are referred to as "medVth".

[0216] Based on equation (E), equation (D) can be expressed as equation (G0) below.

[0217] medVth×(1+n×s / 100) <VwAPP<medVth×2×(1-n×s / 100) / a···(G0)

[0218] In this case, based on equation (G0), we can obtain the following equation (G1).

[0219] (1+n×s / 100)<2×(1-n×s / 100) / a···(G1)

[0220] Equation (G1) is expressed as Equation (G2) below.

[0221] 0<2×(1-n×s / 100) / a-(1+n×s / 100)···(G2)

[0222] Equation (G2) is expressed as Equation (G3) below.

[0223] 0<2×(1-n×s / 100)-a×(1+n×s / 100)···(G3)

[0224] Furthermore, equation (G3) is expressed as equation (G4) below.

[0225] 0<(2-a)-(2+a)×n×s / 100···(G4)

[0226] Based on equation (G4), we can obtain the following equation (H).

[0227] n×s / 100<(2-a) / (2+a)···(H)

[0228] Based on Equation (H), the deviation of the threshold voltage of the switching element 20, “n×s / 100”, is smaller than “(2-a) / (2+a)”.

[0229] The range of the value “a” that satisfies equation (H) is “1 < a < 2”.

[0230] Figure 8 This is a graph showing the relationship between the operating margin of the MRAM in this embodiment and the value "a".

[0231] Line P1 represents the relationship between coefficient "a" and the operating margin of the MRAM when the threshold voltage of the switching element 20 is not dependent on the polarity of the write voltage. This coefficient "a" represents the voltage ratio of two write voltages VwAPP and VwPAP with different polarities.

[0232] Line P1 (the line containing the quadrilateral plot) represents the relationship between the coefficient “a” based on equation (H) and the action margin “n×s / 100”.

[0233] For example, when the polarity dependence coefficient (the voltage ratio of the write voltage |VwPAP / VwAPP|) "a" of the MTJ element is 1.2, the operating margin D1 becomes a value about 5% higher with respect to the threshold voltage of the switching element, relative to the operating margin of the reference value of 0.2.

[0234] <<Case where switching elements exhibit polarity dependence related to applied voltage>>

[0235] When the switching element has a polarity dependence related to the applied voltage (in the case that b≠1 in equation (F), “a” and “b” are represented by the following relationship.

[0236] Regarding the write voltage VwAPP, the above equation (C) is expressed as the following equation (I1).

[0237] medVth1×(1+n×s / 100) <VwAPP<medVth1×2×(1-n×s / 100)···(I1)

[0238] Regarding the write voltage VwPAP, the above equation (C) is expressed as the following equation (I2).

[0239] medVth2×(1+n×s / 100) <VwPAP<medVth2×2×(1-n×s / 100)···(I2)

[0240] Based on the relationship shown in equations (E) and (F) above, the following equation (J) can be obtained from equation (I2).

[0241] medVth1×(1+n×s / 100)×b / a <VwAPP<medVth1×2×(1-n×s / 100)×b / a···(J)

[0242] As shown in equation (J), the negative polarity write voltage VwAPP (absolute value) can be expressed by a relation using "a" and "b".

[0243] In the case where b / a > 1 (b > a), the following equation (K1) can be obtained from equation (I1) and equation (J).

[0244] medVth1×(1+n×s / 100)×b / a <medVth1×2×(1-n×s / 100)···(K1)

[0245] The left side of equation (K1) is the left side of equation (J), and the right side of equation (K1) is the right side of equation (I1).

[0246] Equation (K1) is expressed as Equation (K2) below.

[0247] (1+n×s / 100)×b / a<2×(1-n×s / 100)···(K2)

[0248] Equation (K2) is expressed as Equation (K3) below.

[0249] 0<(2-2×n×s / 100)-(1+n×s / 100)×b / a···(K3)

[0250] Equation (K3) is expressed as Equation (K4) below.

[0251] 0<(2a-b)-(2a+b)×n×s / 100···(K4)

[0252] Based on equation (K4), the deviation of the threshold voltage of the switching element is expressed as equation (K5) below.

[0253] n×s / 100<(2a-b) / (2a+b)···(K5)

[0254] Furthermore, the above equations (H) and (K5) have the following relationship as shown in equation (L).

[0255] (2-a) / (2+a)<(2a-b) / (2a+b)···(L)

[0256] Based on equation (L), we can obtain "b < a 2 The relationship between them.

[0257] Therefore, in the case where b > a, we have "b < a" through "b" and "a". 2 Due to the relationship between "", the operating margin of MRAM1 in this embodiment becomes larger.

[0258] In the case of "b / a < 1" (b < a), the operating margin of the MRAM in this embodiment is expressed by formula (I1) and formula (J) as the following formula (M1).

[0259] medVth1×(1+n×s / 100) <medVth1×2×(1-n×s / 100)×b / a···(M1)

[0260] The left side of equation (M1) is the left side of equation (I1), and the right side of equation (M) is the right side of equation (J).

[0261] Equation (M1) is expressed as Equation (M2) below.

[0262] 1+n×s / 100<2×(1-n×s / 100)×b / a···(M2)

[0263] Equation (M2) is expressed as Equation (M3) below.

[0264] 0<2b-2b×n×s / 100-aa×n×s / 100···(M3)

[0265] Equation (M2) is expressed as Equation (M3) below.

[0266] 0<(2b-a)-(2b+a)×n×s / 100···(M4)

[0267] Based on equation (M4), the deviation of the threshold voltage of the switching element is expressed as the following equation (L).

[0268] n×s / 100<(2b-a) / (2b+a)···(M5)

[0269] The above equations (H) and (M5) have the following relationship as shown in equation (N).

[0270] (2-a) / (2+a)<(2b-a) / (2b+a)···(N)

[0271] Based on equation (N), the relationship "b > a" can be obtained.

[0272] Based on the above, when b > a, and when "b" has a relationship of "1 < b", the operating margin of MRAM1 in this embodiment becomes larger.

[0273] exist Figure 8 In the diagram, lines P2 and P3 represent the relationship between the coefficient "a" and the operating margin of the MRAM when the threshold voltage of the switching element 20 is dependent on the polarity of the write voltage. The coefficient "a" represents the voltage ratio of two write voltages VwAPP and PAP with different polarities.

[0274] Line P2 (the line containing the triangle plot) represents the relationship between the coefficient "a" based on equation (L) and the action margin "n×s / 100". Line P2 indicates that "b" and "a" are "b=a". 0.5 The shift of action margin under the condition of "".

[0275] Line P3 (the line plotted with a circle) represents the relationship between the coefficient "a" based on equation (N) and the motion margin. Line P3 shows the shift in motion margin when "b" and "a" are both "b = a".

[0276] like Figure 8 As shown, the motion margin values ​​associated with line P2 and line P3 are higher than the motion margin values ​​associated with line P1.

[0277] In this way, the operating margin of MRAM can be improved by making the threshold voltage of the switching element polarity dependent on the write voltage.

[0278] For example, when comparing the operating margin values ​​when the polarity dependence coefficient (voltage ratio of write voltage) "a" of the MTJ element is "1.2", the operating margin D2 based on formula (L) is improved by about 13% compared to the operating margin D1 based on formula (H) (operating margin when the switching element has no polarity dependence) compared to the reference value of 0.2.

[0279] As shown in line P3, when the value of “b” is equal to the value of “a”, the action margin based on equation (N) can be maintained at a value of 0.3 or higher without depending on the value of “a”.

[0280] In this case, the action margin based on equation (N) can achieve the highest value.

[0281] Furthermore, the relationship between the operating margin of MRAM and the polarity dependence of switching elements was explained using write voltages VwPAP and VwAPP with different polarities.

[0282] However, the relationship between the operating margin of MRAM and the polarity dependence of the switching element has the same relationship with respect to write currents IwAPP and IwPAP with different polarities.

[0283] (d) Summary

[0284] The MRAM of this embodiment includes a storage element (e.g., an MTJ element) 21 and a switching element 20 within the storage cell MC.

[0285] In the MRAM of this embodiment, a write pulse (write voltage and / or write current) of the first polarity or a write pulse of the second polarity is supplied to the memory cell according to the write data to the memory cell.

[0286] In the MRAM of this embodiment, the switching element has a polarity dependence corresponding to write pulses with different polarities. Depending on the polarity dependence for the write pulse, the characteristics of the switching element (e.g., at least one of the threshold voltage and resistance value) when a write pulse of the first polarity is supplied are different from the characteristics of the switching element when a write pulse of the second polarity is supplied.

[0287] Therefore, the MRAM of this embodiment can improve the operating margin of the memory cell.

[0288] In this embodiment, the switching element has a polarity-dependent magnitude as follows.

[0289] The MTJ element 21 exhibits a polarity dependence with respect to two write voltages of different polarities, represented by a coefficient “a”. “a” is the value of the ratio of the absolute value of the positive polarity write voltage VwPAP to the absolute value of the negative polarity write voltage VwAPP (the polarity dependence coefficient of the MTJ element).

[0290] The switching element 20 has a polarity dependence with respect to two write voltages of different polarities, represented by a coefficient “b”. “b” is the value of the ratio (the central value of the threshold voltage distribution) of the switching element when a positive write voltage VwPAP is applied to the threshold voltage (the central value of the threshold voltage distribution) of the switching element when a negative write voltage VwAPP is applied (the polarity dependence coefficient of the switching element).

[0291] In the MRAM of this embodiment, "a" and "b" have the following relationship: "1 < b < a". 2 The relationship between "and" is established. Therefore, the MRAM of this embodiment can improve the operating margin.

[0292] For example, when the value of "b" is the same as the value of "a", the magnitude of the action margin will be the maximum.

[0293] Thus, as in the MRAM of this embodiment, when the switching elements within the memory cell are polarity-dependent on the polarity of the write voltage, the operating margin can be improved.

[0294] Therefore, the storage device of this embodiment can improve the characteristics of the storage device.

[0295] (2) Second implementation method

[0296] Reference Figure 9 and Figure 10 The storage device of the second embodiment and its design method will be described.

[0297] As follows, in the memory device (e.g., MRAM) of this embodiment, the polarity dependence of the switching element on write voltages of different polarities can be controlled.

[0298] <<Materials of Switching Components>>

[0299] In the MRAM1 of this embodiment, the polarity dependence of the switching element 20 of the memory cell MC can be controlled based on the selection of materials of the multiple layers used in the switching element 20.

[0300] For example, the polarity dependence of the switching element 20 on the polarity of the applied write voltages VwAPP and VwPAP can be controlled based on the combination of the materials of the switching layer 202 and the materials of the electrodes 201 and 203.

[0301] Due to the difference between the work function of the materials of electrodes 201 and 203 and the work function of the material of switch layer 202, a potential barrier will be generated between electrodes 201 and 203 and switch layer 202.

[0302] In a two-terminal switching element 20, when the work function of the material of one electrode (e.g., the lower electrode 201) is different from the work function of the material of the other electrode (e.g., the upper electrode 203), the magnitude of the potential barrier between the lower electrode 201 and the switching layer 202 is different from the magnitude of the potential barrier between the upper electrode 203 and the switching layer 202.

[0303] Depending on the polarity of the voltage applied to the switching element 20, the potential barrier on the upper electrode 203 side and the potential barrier on the lower electrode 201 side are modulated (changed).

[0304] As a result, the threshold voltage of the switching element 20 varies depending on the polarity of the write voltages VwAPP and VwPAP.

[0305] Thus, when the upper electrode 203 and the lower electrode 201 are made of different materials, the characteristics of the switching element 20 have a polarity dependence corresponding to the polarity of the write voltage. Depending on the materials used for electrodes 201 and 203, the magnitude of the polarity dependence of the switching element 20 (e.g., the value of "b" in the above formula (F)) can be controlled.

[0306] For example, if the material of the switching layer 202 is silicon oxide, the materials of the electrodes 201 and 203 can be tantalum (Ta), tungsten (W), copper (Cu), hafnium (Hf), and titanium nitride (TiN), etc. One of these materials is used as the material of one electrode, and a material different from the material of the selected electrode is used as the material of the other electrode.

[0307] The work function of the material used in the electrode has a value corresponding to the crystal structure and crystal planes of the layer formed by the material.

[0308] The work function of tantalum ranges from 4.0 eV to 4.8 eV. The work function of tungsten ranges from 4.32 eV to 5.22 eV. The work function of copper ranges from 4.53 eV to 5.10 eV. The work function of hafnium ranges from 3.5 eV to 3.9 eV. The work function of titanium nitride is, for example, 4.7 eV.

[0309] The materials of electrodes 201 and 203 are not limited to the materials mentioned above, and can be appropriately changed according to the material of the switching layer 202.

[0310] Furthermore, the polarity dependence of the switching element 20 can be controlled not only by the materials of the switching layer 202 and the electrodes 201 and 203, but also by the surface roughness of each layer at the boundary (interface) between the switching layer 202 and the electrodes 201 and 203, the film thickness of the switching layer 202 and the electrodes 201 and 203, and the crystallinity (crystal structure) of the switching layer 202 and the electrodes 201 and 203.

[0311] Figure 9 This is a diagram illustrating an example of controlling the polarity dependence of switching elements in the MRAM of this embodiment.

[0312] exist Figure 9 The diagram shows the relationship between the resistance values ​​RTE and RBE of the switching element, which are related to the materials of the lower electrode BE and the upper electrode TE.

[0313] The resistance value RTE represents a bias state where the potential of the upper electrode is higher than that of the lower electrode (e.g., based on...). Figure 6 The resistance value of the switching element during the write operation of the positive polarity write voltage shown in (b).

[0314] The resistance value RBE represents a bias state where the potential of the lower electrode is higher than that of the upper electrode (e.g., based on...). Figure 6 The resistance value of the switching element during the write operation of the negative polarity write voltage shown in (a).

[0315] Figure 9 The vertical axis of the graph corresponds to the ratio (R / RTE) of the resistance value R of the switching element to the resistance value RTE. Figure 9 The vertical axis of the chart is represented by the log scale.

[0316] exist Figure 9 The horizontal axis of the graph shows the resistance values ​​RBE and RTE as samples. However, Figure 9 The horizontal axis of the chart does not represent the relationship between the resistance values ​​RBE and RTE.

[0317] according to Figure 9 The polarity dependence of the switching element is represented by standardization using the resistance value RTE as a reference. Therefore, as... Figure 9 As shown at point Q0, when “R” is “RTE”, the value of “R / RTE” is “1”.

[0318] When the polarity dependence of the switching element is controlled according to the materials of the upper and lower electrodes, the value of "R / RTE = RBE / RTE" will change depending on the combination of materials used for the electrodes.

[0319] Figure 9Point Q1 represents the value of "RBE / RTE" when both the material of the lower electrode and the material of the upper electrode are silicon nitride (SiN).

[0320] When silicon nitride is used as the material for both the lower and upper electrodes, as in point Q1, the value of "RBE / RTE" is "1".

[0321] This means that the switching elements using silicon nitride on both the lower and upper electrodes are essentially polarity-independent with respect to the applied voltage (or supplied current).

[0322] Figure 9 Point Q2 represents the value of "RBE / RTE" when the material of the lower electrode is titanium nitride (TiN) and the material of the upper electrode is SiN.

[0323] When titanium nitride is used as the lower electrode and silicon nitride is used as the upper electrode, as in point Q2, the value of "RBE / RTE" becomes less than 1.

[0324] This means that the switching element, in which titanium nitride is used in the lower electrode and silicon nitride is used in the upper electrode, has a polarity dependence with respect to the applied voltage (or supplied current).

[0325] When "RBE / RTE" is less than 1, as in point Q2, the resistance value RBE of the switching element is lower than the resistance value RTE of the switching element.

[0326] Furthermore, when silicon nitride is used in the lower electrode and titanium nitride is used in the upper electrode, the value of "RBE / RTE" becomes greater than 1.

[0327] Figure 9 Point Q3 represents the "RBE / RTE" value when both the material of the lower electrode and the material of the upper electrode are titanium nitride.

[0328] When titanium nitride is used in both the lower and upper electrodes, as in point Q3, the value of "RBE / RTE" becomes greater than 1.

[0329] This means that the switching element in which titanium nitride is used in both the lower and upper electrodes has a polarity dependence with respect to the applied voltage (or supplied current). Thus, even when the materials of the lower and upper electrodes are the same, the switching element may sometimes have a polarity dependence with respect to the applied voltage (supply current) depending on the materials used in the electrodes.

[0330] When "RBE / RTE" is greater than 1, as in point Q3, the resistance value RBE of the switching element is higher than the resistance value RTE of the switching element.

[0331] As with points Q2 and Q3, the resistance values ​​RBE and RTE of the switching element relative to the applied voltage (or supplied current) will change depending on the materials of the upper and lower electrodes of the switching element.

[0332] In addition, as with points Q2 and Q3, depending on the materials of the upper and lower electrodes of the switching element, the direction of the polarity dependence of the switching element on the applied voltage (or supplied current) (the relationship between the resistance values ​​RBE and RTE) will change.

[0333] In addition, Figure 9 In some examples, the SiN or TiN layer used as the electrode can also be disposed between the switching layer and the metal layer.

[0334] If used Figure 9 As explained, the degree to which a switching element depends on the polarity of the applied voltage can be controlled according to the material used in the switching element.

[0335] <<Conditions for the Formation of Switching Elements>>

[0336] In the MRAM of this embodiment, the polarity dependence of the switching element on the applied voltage (or supplied current) can be controlled by controlling the formation conditions of the switching layer. In order to control the polarity dependence of the switching element, for example, the composition of the switching layer (the composition ratio of the added elements), the types of added elements in the switching layer, and / or the injection conditions of the added elements are controlled.

[0337] Figure 10 This is a diagram illustrating an example of controlling the polarity dependence of switching elements in the MRAM of this embodiment.

[0338] exist Figure 10 The diagram shows the relationship between the resistance values ​​RTE and RBE of a switching element, which are related to the conditions under which the switching element is formed.

[0339] Figure 10 The vertical axis of the graph corresponds to the ratio (R / RTE) of the resistance value R of the switching element to the resistance value RTE. Figure 10 The vertical axis of the chart is represented by the log scale. Figure 10 The horizontal axis of the graph shows the resistance values ​​RBE and RTE as samples. However, Figure 10 The horizontal axis of the chart does not represent the relationship between the resistance values ​​RBE and RTE.

[0340] exist Figure 10 The diagram illustrates the relationship between ion implantation conditions for a switching layer (e.g., a silicon oxide layer) and the polarity dependence of the switching element.

[0341] and Figure 9 Similarly, in cases where the polarity dependence of a switching element is expressed by normalizing the resistance value RTE as a reference, such as... Figure 10 As with point Q10, the value of "R / RTE" related to "RTE" is "1".

[0342] Figure 10 Point Q11 represents the value of "RBE / RTE" in the case where arsenic (As) is implanted into the switching layer of the switching element via ion implantation.

[0343] When arsenic is injected into the switching layer as in point Q11, the value of "RBE / RTE" becomes greater than 1.

[0344] This means that a switching element with an arsenic-implanted switching layer is polarity dependent with respect to the applied voltage (or supplied current).

[0345] In cases like point Q11 where "RBE / RTE" is greater than 1, the resistance value RBE of the switching element is higher than the resistance value RTE of the switching element.

[0346] Figure 10 Point Q12 represents the value of “RBE / RTE” when germanium (Ge) is implanted into the switch layer via ion implantation.

[0347] As with point Q12, when germanium is injected into the switching layer, the value of "RBE / RTE" becomes less than 1.

[0348] This means that a switching element with a germanium-infused switching layer is polarity dependent with respect to the applied voltage (or supplied current).

[0349] In cases where "RBE / RTE" is less than 1, such as at point Q12, the resistance value RBE of the switching element is lower than the resistance value RTE of the switching element.

[0350] As shown in the examples of points Q11 and Q12, the direction of the polarity dependence of the switching element (the relationship between the resistance values ​​RBE and RTE) can be changed depending on the type of ions injected into the switching layer.

[0351] Figure 10 Point Q13 represents the "RBE / RTE" value when germanium (Ge) is implanted into the switch layer at a relatively high dose via ion implantation. For example, the dose of germanium at point Q13 is higher than the dose of germanium at point Q12.

[0352] Similar to point Q12, when germanium is injected into the switching layer, the value of "RBE / RTE" becomes less than 1.

[0353] As in point Q13, the RBE / RTE value is larger when germanium is implanted into the switch layer under relatively high dose ion implantation conditions than in point Q12.

[0354] The relationship between points Q12 and Q13 shows that the magnitude of "RBE / RTE" changes with the dose of germanium.

[0355] For example, as the dose of germanium increases, the resistance value RBE increases compared to the change in resistance value RTE.

[0356] Therefore, regarding the conditions of ion implantation, the polarity dependence of the switching element on the applied voltage (or supplied current) can be controlled by controlling the dosage of ions in the switching layer.

[0357] Figure 10 Point Q14 represents the "RBE / RTE" value when germanium (Ge) is implanted into the switch layer at a relatively high acceleration energy via ion implantation. For example, the acceleration energy of ion implantation at point Q14 is higher than that of ion implantation at point Q12.

[0358] As with point Q14, and similarly with point Q12, when germanium is injected into the switching layer, the value of "RBE / RTE" becomes less than 1.

[0359] As in point Q14, the "RBE / RTE" value is smaller when germanium is implanted into the switch layer under relatively high acceleration energies of ion implantation than in point Q12.

[0360] The relationship between points Q12 and Q14 shows that the magnitude of the resistance value RBE relative to the acceleration energy of ion implantation changes with the change of acceleration energy.

[0361] For example, as the acceleration energy of ions increases, the resistance value RBE decreases compared to the change in resistance value RTE.

[0362] Therefore, regarding the conditions of ion implantation, the polarity dependence of the switching element on the applied voltage (or supplied current) can be controlled by controlling the acceleration energy of the ions in the switching layer.

[0363] Thus, regarding ion implantation of the switching layer, the polarity dependence of the switching element on the applied voltage (or supplied current) can be controlled according to the type of ions implanted, the dose, and the acceleration energy.

[0364] If used Figure 10As explained, the degree of dependence of a switching element on the polarity of the applied voltage can be controlled by controlling the formation conditions of the switching element (e.g., the impurity injection conditions of the switching layer).

[0365] In addition, regarding the use Figure 9 and Figure 10 The polarity control of the switching element, as explained above, even when a write current with a polarity corresponding to the write voltage is supplied to the switching element, the polarity dependence control of the switching element tends to correspond to the polarity of the supplied write current.

[0366] As described above, the memory device (e.g., MRAM) of this embodiment can control the polarity dependence of the switching element on the applied voltage of multiple polarities. As a result, the memory device of this embodiment can improve the operating margin of the memory device.

[0367] Therefore, the storage device of the second embodiment can improve the operating characteristics of the storage device.

[0368] (3) Third implementation

[0369] Reference Figure 11 The storage device of the third embodiment and its design method will be described.

[0370] In the memory devices (e.g., MRAM) of the first and second embodiments, the switching elements are polarity dependent with respect to write voltages having multiple polarities.

[0371] In the MRAM of this embodiment, the storage element (here, the MTJ element) exhibits polarity dependence with respect to write voltages (or write currents) having multiple polarities. As described above, the polarity dependence of the switching element on the write voltage is related to the polarity dependence of the MTJ element on the write voltage regarding the operating margin of the MRAM. Therefore, the acceptable range of polarity dependence of the switching element varies depending on the control of the polarity dependence (polarity dependence coefficient) of the MTJ element.

[0372] As follows, the polarity dependence of the MTJ element on the write voltage with multiple polarities is controlled. Furthermore, in the MRAM of this embodiment, the polarity dependence of both the MTJ element and the switching element can be controlled, or only the polarity dependence of the MTJ element can be controlled.

[0373] Figure 11 This is a diagram illustrating several examples of polarity dependence control for MTJ elements in the MRAM of this embodiment.

[0374] Figure 11(a) is a graph showing the relationship between the composition of the storage layer of an MTJ element and the polarity dependence of the magnetization reversal threshold of the MTJ element.

[0375] exist Figure 11 In (a), the horizontal axis of the graph corresponds to the percentage (%) of iron (Fe) composition within the storage layer. Figure 11 In (a), the vertical axis of the graph corresponds to the values ​​representing the polarity dependence of the MTJ element. The value representing polarity dependence is the ratio of the magnetization reversal threshold (IcAPP) of the MTJ element when a write voltage VwAPP is applied to the magnetization reversal threshold (IcPAP) of the MTJ element when a write voltage VwPAP is applied (Ic ratio = IcAPP / IcPAP). A large Ic ratio means that the MTJ element is highly polarity dependent on the write voltage (write current). A small Ic ratio means that the MTJ element is less polarity dependent on the write voltage.

[0376] like Figure 11 As shown in (a), it is shown that the Ic ratio tends to increase as the iron composition ratio within the storage layer increases.

[0377] Figure 11 (b) is a graph showing the relationship between the composition of the storage layer of the MTJ element and the polarity dependence of the magnetization reversal threshold of the MTJ element.

[0378] exist Figure 11 In (b), the horizontal axis of the graph corresponds to the composition ratio of boron (B) within the storage layer. Figure 11 In (b), the vertical axis of the graph corresponds to the Ic ratio (IcAPP / IcPAP) of the MTJ component.

[0379] like Figure 11 As shown in (b), the Ic ratio tends to increase as the boron composition ratio within the storage layer increases.

[0380] However, the tendency of the Ic ratio to change by controlling the boron composition ratio is different from the tendency of the Ic ratio to change by controlling the iron composition ratio.

[0381] When the iron content within the storage layer is controlled, the Ic ratio increases relatively gradually with increasing iron content. Conversely, when the boron content within the storage layer is controlled, the Ic ratio increases more sharply when the boron content exceeds a certain value.

[0382] like Figure 11As in (a) and (b), the polarity dependence of the MTJ element on the write voltage (or write current) can be controlled by controlling the components constituting the memory layer (e.g., the composition of the elements). Furthermore, the tendency for the polarity dependence to change can be controlled based on the element among the multiple elements constituting the memory layer that controls the composition.

[0383] Figure 11 (c) is a graph showing the relationship between the thickness of the storage layer (film thickness) of the MTJ element and the polarity dependence of the magnetization reversal threshold of the MTJ element.

[0384] exist Figure 11 In (c), the horizontal axis of the graph corresponds to the film thickness of the storage layer. Figure 11 In (c), the vertical axis of the graph corresponds to the Ic ratio (IcAPP / IcPAP) of the MTJ component.

[0385] like Figure 11 As shown in (c), the Ic ratio tends to decrease as the thickness of the storage layer increases.

[0386] In this way, by controlling the thickness of the storage layer, the polarity dependence of the MTJ element on the write voltage can be controlled.

[0387] As in this embodiment, the polarity dependence of the memory cell on the write voltage (write current) can be controlled as a result of controlling the polarity dependence of the MTJ element on the write voltage (write current).

[0388] Therefore, the MRAM of this embodiment can improve the operating margin of the storage device.

[0389] Therefore, the storage device of the third embodiment can improve the operating characteristics of the storage device.

[0390] (4) Other

[0391] In the above embodiments, MRAM is exemplified as the storage device of this embodiment. However, the storage device of this embodiment may also be a magnetic memory other than MRAM, as long as a magnetoresistive element (e.g., an MTJ element) is used as the storage element.

[0392] The memory device in this embodiment can be a memory device other than a magnetic memory, as long as it includes a switching element that is polarity-dependent for a write voltage having multiple polarities. For example, the memory device in this embodiment can also be a memory device that uses a variable resistance element (e.g., a transition metal oxide element) as a storage element (e.g., a resistive random access memory such as ReRAM), a memory device that uses a phase change element as a storage element (e.g., a phase change memory such as PCRAM), or a memory device that uses a ferroelectric element as a storage element (e.g., a ferroelectric memory such as FeRAM).

[0393] Even if the storage device in this embodiment is a storage device other than MRAM, the effects described in the above embodiments can be obtained.

[0394] Several embodiments of the present invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: A storage cell, comprising storage elements and switching elements; and The circuit applies a first write pulse with a first polarity to the memory cell when writing first data to the memory cell, and applies a second write pulse with a second polarity different from the first polarity to the memory cell when writing second data to the memory cell. The switching element has a polarity dependency corresponding to the first polarity and the second polarity. When the first write pulse is represented by "VwAPP", the second write pulse by "VwPAP", the ratio of the first write pulse to the second write pulse by "a", and the polarity dependence of the switching element by "b", "a" has the following relationship as shown in equation (1), and "b" has the following relationship as shown in equation (2). a=VwPAP / VwAPP···(1) 1<b<a 2 ···(2)。 2. The storage device according to claim 1, The first threshold voltage of the switching element when the first write pulse is applied is different from the second threshold voltage of the switching element when the second write pulse is applied.

3. The storage device according to claim 1, b is equal to a.

4. The storage device according to claim 1, The first resistance value of the switching element when the first write pulse is applied is different from the second resistance value of the switching element when the second write pulse is applied.

5. The storage device according to claim 1, The switching element includes a first electrode, a second electrode, and a first layer between the first electrode and the second electrode. The material of the first electrode is different from the material of the second electrode.

6. The storage device according to claim 1, The polarity dependence of the switching element is set based on the formation conditions of the switching element.

7. The storage device according to claim 1, The storage element has a polarity dependency corresponding to the first polarity and the second polarity.

8. The storage device according to claim 1, The storage element is a magnetoresistive element. The magnetoresistive effect element includes: A first magnetic layer with variable magnetization direction; A second magnetic layer with an invariant magnetization direction; as well as The insulating layer between the first magnetic layer and the second magnetic layer, The polarity dependence of the magnetoresistive element on the first write pulse and the second write pulse is set by controlling at least one of the size of the first magnetic layer and the composition of the constituent elements of the first magnetic layer.

9. A storage device comprising: A storage cell, comprising storage elements and switching elements; and The circuit applies a first write pulse with a first polarity to the memory cell when writing first data to the memory cell, and applies a second write pulse with a second polarity different from the first polarity to the memory cell when writing second data to the memory cell. The first resistance value of the switching element when the first write pulse is applied is different from the second resistance value of the switching element when the second write pulse is applied.

10. The storage device according to claim 9, The first threshold voltage of the switching element when the first write pulse is applied is different from the second threshold voltage of the switching element when the second write pulse is applied.

11. The storage device according to claim 9, The switching element has a polarity dependency corresponding to the first polarity and the second polarity.

12. The storage device according to claim 11, When the first write pulse is represented by "VwAPP", the second write pulse by "VwPAP", the ratio of the first write pulse to the second write pulse by "a", and the polarity dependence of the switching element by "b", "a" has the following relationship as shown in equation (1), and "b" has the following relationship as shown in equation (2). a=VwPAP / VwAPP···(1) 1<b<a 2 ···(2)。 13. The storage device according to claim 12, b is equal to a.

14. The storage device according to claim 9, The switching element includes a first electrode, a second electrode, and a first layer between the first electrode and the second electrode. The material of the first electrode is different from the material of the second electrode.

15. The storage device according to claim 9, The difference between the first resistance value and the second resistance value of the switching element is set based on the formation conditions of the switching element.

16. The storage device according to claim 9, The storage element has a polarity dependency corresponding to the first polarity and the second polarity.

17. The storage device according to claim 9, The storage element is a magnetoresistive element. The magnetoresistive effect element includes: A first magnetic layer with variable magnetization direction; A second magnetic layer with an invariant magnetization direction; as well as The insulating layer between the first magnetic layer and the second magnetic layer, The polarity dependence of the magnetoresistive element on the first write pulse and the second write pulse is set by controlling at least one of the size of the first magnetic layer and the composition of the constituent elements of the first magnetic layer.

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