Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes providing a substrate including an insulating region, an active region, and a first upper surface, the active region being adjacent to the insulating region, wherein the insulating region has an insulating trench filled with a dielectric material, and the active region has a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and the gate electrode material exposed by the hard mask, thereby forming a second upper surface of the dielectric material and a third upper surface of the gate electrode material, wherein the second upper surface and the third upper surface are substantially on the same plane and substantially lower than the first upper surface.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 201,587, filed March 15, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor structure. In particular, it relates to a semiconductor structure having a plurality of buried word lines. Background Technology

[0003] An embedded word line is a structure formed in a dynamic random access memory (DRAM) to increase the integration density of a transistor in a memory cell, simplify a manufacturing process, and improve a device characteristic, such as leakage current characteristics. Generally, a trench is formed and a word line is embedded in the trench to form an embedded word line.

[0004] When forming multiple buried character lines, a single etch-back process is important because it creates space in the trenches to fill with a conductive material. However, in a single etch-back process, etching selectivity often causes variations in the material height forming the buried character lines.

[0005] Therefore, there is a need to improve the etch process that forms the embedded character lines.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate comprising an insulating region, an active region, and a first upper surface, the active region being adjacent to the insulating region, wherein the insulating region includes an insulating trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove the dielectric material and the gate electrode material exposed by the hard mask, thereby forming a second upper surface of the dielectric material and a third upper surface of the gate electrode material; wherein the second upper surface and the third upper surface are substantially on the same plane and substantially lower than the first upper surface.

[0008] In some embodiments, the preparation method further includes depositing a gate conductive material to cover the dielectric material and the gate electrode material.

[0009] In some embodiments, the preparation method further includes removing a portion of the gate conductive material on the first upper surface of the substrate, so that the gate conductive material in the insulating trench is recessed below the first upper surface.

[0010] In some embodiments, forming the hard mask includes forming a cover layer on the substrate, the dielectric material, and the gate electrode material; forming a mask layer on the cover layer; forming an anti-reflective coating (ARC) layer on the mask layer; and forming a photoresist pattern on the anti-reflective coating layer, wherein the photoresist pattern includes a plurality of photoresist features.

[0011] In some embodiments, the photoresist feature is used as an etch mask to etch the mask layer to form a mask pattern that includes a plurality of mask features.

[0012] In some embodiments, the masking features are used as an etch mask to etch the cover layer to form a cover pattern that includes a plurality of cover features.

[0013] In some embodiments, the cover pattern is formed together with the mask pattern on the hard mask on the substrate.

[0014] In some embodiments, the etching method includes using a first plasma in a first operating phase, wherein the first plasma has a first etching selectivity of the gate electrode material to the dielectric material; changing the first plasma to a second plasma in a second operating phase, wherein the second plasma has a second etching selectivity of the gate electrode material to the dielectric material; and changing the second plasma to a third plasma in a third operating phase, wherein the third plasma has a third etching selectivity of the gate electrode material to the dielectric material.

[0015] In some embodiments, the first working phase, the second working phase, and the third working phase are performed in situ within a single etching chamber.

[0016] In some embodiments, the first operating phase includes a first interval in which the first plasma is turned on and maintained at a first high power, then adjusted to a low power and maintained at the low power; a second interval in which the first plasma is adjusted to the first high power and maintained at the high power, then adjusted to the low power and maintained at the low power; and a third interval in which the second interval is repeated, wherein after the third interval, a first switching step is performed to terminate the first operating phase.

[0017] In some embodiments, after the first switching step, a first stabilization period is used to change the first plasma to the second plasma.

[0018] In some embodiments, the second operating phase includes a fourth interval in which the second plasma is maintained at a second high power, then adjusted to a low power and maintained at the low power; a fifth interval in which the second plasma is adjusted to the second high power and maintained at the second high power, then adjusted to the low power and maintained at the low power; and a sixth interval in which the fifth interval is repeated, wherein after the sixth interval, a second switching step is performed to terminate the second operating phase.

[0019] In some embodiments, after the second switching step, a second stabilization period is used to change the second plasma to the third plasma.

[0020] In some embodiments, the third operating phase includes maintaining the third plasma at a third high power.

[0021] In some embodiments, the second high power is different from the first high power.

[0022] In some embodiments, the third high power is lower than the first high power or the second high power.

[0023] In some embodiments, the first high power, the second high power, and the third high power represent the primary etching phases.

[0024] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate comprising an insulating region, an active region, a first upper surface, an insulating trench, and a gate trench. The active region is adjacent to the insulating region. The insulating trench is recessed into the first upper surface and disposed within the insulating region. The gate trench is recessed into the first upper surface and disposed within the active region. A dielectric material is deposited in a lower portion of the insulating trench, wherein the dielectric material has a second upper surface below the first upper surface. A gate electrode material is deposited in a lower portion of the gate trench, wherein the gate electrode material has a third upper surface substantially on the same plane as the second upper surface. A gate conductive material is deposited in an upper portion of the insulating trench to cover the dielectric material and in an upper portion of the gate trench to cover the gate electrode material.

[0025] In some embodiments, the dielectric material and the gate conductive material formed thereon, as well as the gate electrode material and the gate conductive material formed thereon, form a plurality of buried word line structures.

[0026] In some embodiments, the embedded character line structure has a fourth upper surface that is substantially on the same bit plane as the first upper surface of the substrate.

[0027] The etching method provided in this disclosure includes varying the combination of multiple etchants used as plasma in an in-situ etch-back process. The etching method includes three working stages performed in a single etching chamber. The plasma may have different etching selectivity for polysilicon in the gate electrode material relative to silicon dioxide in the dielectric material during the three working stages. Furthermore, the plasma power is adjusted at different intervals during the first and second working stages. The primary etching phase is a period during which the plasma is at high power, while at low power it removes the etching byproducts. Therefore, during the etch-back process, the dielectric material in the insulating trench and the gate electrode material in the gate trench can be recessed into the upper surface of the substrate. Furthermore, according to the etching method provided in this disclosure, during the buried word line formation, the upper surface of the etched dielectric material and the upper surface of the etched gate electrode material can be maintained on substantially the same octagon.

[0028] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0029] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1 This is a structural schematic diagram illustrating an etching system according to some embodiments of the present disclosure.

[0031] Figure 2 This is a top view schematic diagram illustrating a semiconductor structure having multiple embedded character line structures in some embodiments of this disclosure.

[0032] Figure 3 It is along Figure 2A cross-sectional view along line A-A' illustrates some embodiments of this disclosure prior to the formation of the embedded character lines. Figure 2 Semiconductor structure in.

[0033] Figure 4 This is a cross-sectional schematic diagram illustrating the semiconductor structure after one etching process according to some embodiments of the present disclosure.

[0034] Figure 5 This is a cross-sectional schematic diagram illustrating a semiconductor structure after a gate conductive material deposition, according to some embodiments of the present disclosure.

[0035] Figure 6 This is an enlarged top view schematic diagram illustrating some embodiments of this disclosure. Figure 2 One of the embedded character line structures.

[0036] Figure 7 This is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0037] Figure 8 This is a flowchart illustrating some embodiments of this disclosure. Figure 7 Methods for preparing semiconductor structures.

[0038] Figures 9 to 24 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure based on... Figure 8 The preparation method in the process involves each manufacturing stage in sequence.

[0039] Figure 25 This is a graph illustrating the relationship between plasma power and etching time, showing some embodiments of this disclosure used in applications... Figure 22 The plasma etching method in the back etching process described in the paper.

[0040] The reference numerals in the attached figures are explained as follows:

[0041] 10: Base

[0042] 12: Dielectric materials

[0043] 14: Gate electrode material

[0044] 16: Gate conductive material

[0045] 20: Semiconductor stacking

[0046] 22: Gas Inlet

[0047] 24: Plasma

[0048] 26: Vacuum System

[0049] 100: Base

[0050] 110: First photoresist pattern

[0051] 120: Dielectric material

[0052] 130: Second photoresist pattern

[0053] 140: Gate electrode material

[0054] 150: Cover pattern

[0055] 150A: Cover Features

[0056] 150B: Opening

[0057] 150L: Cover layer

[0058] 160: Masking Pattern

[0059] 160A: Masking Feature

[0060] 160B: Opening

[0061] 160L: Masking layer

[0062] 170: Anti-reflective coating pattern

[0063] 170A: Anti-reflective coating characteristics

[0064] 170B: Opening

[0065] 170L: Anti-reflective coating

[0066] 180: Photoresist pattern

[0067] 180A: Photoresist characteristics

[0068] 180B: Opening

[0069] 180L: Photoresist layer

[0070] 190: Gate conductive material

[0071] 200: Multilayer film

[0072] 500: Preparation method

[0073] 1000: Etching Method

[0074] AA: Active Zone

[0075] BB: Insulation Zone

[0076] BWL1: Embedded character line structure

[0077] BWL2: Embedded character line structure

[0078] D1: First Direction

[0079] D2: Second Direction

[0080] E1: Electrode

[0081] E2: Electrode

[0082] ES1: Etching System

[0083] HM1: Hard Mask

[0084] Hv1: Radiation

[0085] I11: Interval

[0086] I12: Interval

[0087] I13: Interval

[0088] I21: Interval

[0089] I22: Interval

[0090] I23: Interval

[0091] HP1: First High Power

[0092] HP2: Second Highest Power

[0093] HP3: Third High Power

[0094] MA1: Light Mask

[0095] O1: Opaque area

[0096] P1: Part 1

[0097] P2: Part Two

[0098] PL: Low Power

[0099] R1: Array area

[0100] RF: Power Supply

[0101] S1: Upper surface

[0102] S2: Upper surface

[0103] S3: Upper surface

[0104] S101: Steps

[0105] S103: Steps

[0106] S105: Steps

[0107] S107: Steps

[0108] S109: Steps

[0109] S111: Steps

[0110] SP1: First Stable Period

[0111] SP2: Second Stable Period

[0112] ST1: Semiconductor Structure

[0113] ST3: Semiconductor Structure

[0114] SW1: First Switching Step

[0115] T1: Transparent area

[0116] TA: Insulation trench

[0117] TB: Gate Trench

[0118] W1: Width

[0119] W2: Width

[0120] WS1: First Working Phase

[0121] WS2: Second Working Phase

[0122] WS3: Third Working Phase

[0123] θ: Angle Detailed Implementation

[0124] The embodiments or examples of this disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0125] It should be understood that while the terms "first," "second," "third," etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second device, component, region, layer, or part without departing from the teachings of this text.

[0126] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, the terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0127] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0128] An etching process typically uses an ionized gas (such as plasma) to etch a semiconductor stack. Multiple plasma etching processes are particularly useful for etching multiple adjacent structures with multiple fine features. However, with increasingly stringent requirements for feature size and spacing, the limitations of this plasma etching process become apparent. For example, reactive ion etching (RIE) is an etching technique that uses chemically reactive plasma to remove material deposited on a semiconductor stack. This plasma is generated at low pressure by an electromagnetic field. The high-energy ions from this plasma attack the material of the semiconductor stack and react with it.

[0129] Figure 1This is a schematic diagram illustrating an etching system according to some embodiments of this disclosure. In some embodiments, the etching system ES1 is a reactive ion etching (RIE) system. The etching system ES1 includes at least a power supply RF and a pair of electrodes E1, E2. In a RIE process, firstly, a semiconductor stack 20 is placed on a wafer holder (not shown). Next, a plurality of gases are introduced via a gas inlet 22. A plasma 24 is used to bombard the gas mixture using the power supply RF, breaking the gas mixture into a plurality of energetic ions. The energetic ions are directed toward and react on the surface of the semiconductor stack 20, forming other gaseous byproducts. Next, the gaseous byproducts are discharged via a vacuum system 26 to complete the reactive ion etching.

[0130] A plurality of buried word line structures in a semiconductor device includes a plurality of gate electrodes and a plurality of buried word lines, wherein the gate electrodes and the buried word lines are established in a plurality of trenches in a plurality of active regions and a plurality of insulating regions. Generally, the buried word line structure is processed after the active regions are defined, for example after a shallow trench isolation (STI) process.

[0131] Figure 2 This is a top-view schematic diagram illustrating a semiconductor structure ST1 having multiple buried character line structures according to some embodiments of the present disclosure. The semiconductor structure ST1 includes an array region R1 and a surrounding region (not shown), with the array region R1 and the surrounding region disposed on a substrate 10. For simplicity, only the elements in the array region R1 are shown. In the array region R1, the semiconductor structure ST1 includes multiple insulating regions BB and multiple active regions AA, with the active regions AA and the insulating regions BB configured together. In some embodiments, the active regions AA may be repeatedly configured at multiple predetermined intervals and are insulated from each other by the insulating regions BB. In some embodiments, such as Figure 2As shown, the active regions AA are arranged parallel to each other and extend along a first direction D1. In some embodiments, the active regions AA are doped with various dopants to adjust electronic characteristics and form multiple source regions (not shown) and multiple drain regions (not shown). The source regions and the drain regions can construct a significant portion of the array region R1. In some embodiments, multiple buried word line structures BWL1 are disposed on the substrate 10 and pass through the active regions AA and the insulating region BB. In some embodiments, the average width of each buried word line structure BWL1 is approximately 0.5.0 nm. In some embodiments, the buried word line structures BWL1 are equidistantly arranged (with the same spacing) and extend along a second direction D2. In some embodiments, the second direction D2 is substantially different from the first direction D1. In some embodiments, the second direction D2 forms a predetermined angle θ relative to the first direction D1, wherein the predetermined angle θ is preferably 90 degrees. In other words, the active regions AA are diagonally arranged relative to the buried word line structures BWL1.

[0132] Figure 3 It is along Figure 2 A cross-sectional view along line A-A' illustrates some embodiments of this disclosure prior to the formation of the embedded character lines. Figure 2 The semiconductor structure ST1 is described. In some embodiments, after the formation of the active region AA in the substrate 10, the formation of a plurality of buried word lines begins. In some embodiments, firstly, a plurality of insulating trenches TA are formed in the substrate 10. The insulating trenches TA are completely filled with a dielectric material 12 to form a plurality of insulating regions BB, and the dielectric material 12 is, for example, silicon dioxide (SiO2). The insulating regions BB divide the substrate 10 into a plurality of active regions AA, wherein the active regions AA and the insulating regions BB are alternately arranged. Next, a plurality of gate trenches TB are formed in the active regions AA. The gate trenches TB are completely filled with a gate electrode material 14, and the gate electrode material 14 is, for example, polysilicon.

[0133] Figure 4 This is a cross-sectional schematic diagram illustrating the semiconductor structure ST1 after one etching process, according to some embodiments of this disclosure. Please refer to... Figure 4In some embodiments, the upper surfaces of the dielectric material 12 and the upper surfaces of the gate electrode material 14 are etched to create a plurality of recesses on the dielectric material 12 within the insulating trench TA and a plurality of recesses on the gate electrode 14 within the gate trench TB. In a first comparative embodiment, after this etch-back process, the upper surfaces of the dielectric material 12 and the upper surfaces of the gate electrode material 14 have different heights. This problem can arise due to the difference in etch selectivity between the dielectric material 12, which is primarily silicon dioxide, and the gate electrode material 14, which is primarily polysilicon. Generally, silicon dioxide is consumed faster than polysilicon when a particular etchant is used in this etch-back process. Therefore, the different etch rates of the dielectric material 12 and the gate electrode material 14 result in different heights of their upper surfaces.

[0134] Figure 5 This is a cross-sectional schematic diagram illustrating a semiconductor structure ST1 after a gate conductive material deposition, according to some embodiments of this disclosure. Please refer to... Figure 5 In some embodiments, after the etch-back process, a gate conductive material 16 is deposited to fill the recesses within the insulating trench TA and the gate trench TB to form the buried word line. The dielectric material 12, the gate electrode material 14, and the gate conductive material 16 deposited thereon can form as follows: Figure 2 The buried word line structure BWL1 is shown. During the formation of the buried word line structure BWL1, the etch-back process is important because the thickness of the dielectric material 12 or the gate electrode material 14 determines the volume of the recess within the insulating trench TA or the gate trench TB, which in turn determines the amount of trench gate conductive material 16 that can be deposited to fill the recess. In this first comparative embodiment, the amount of gate conductive material 16 that can be deposited in the gate trench TB is greatly limited because after the etch-back process, only a small amount of usable space remains in the gate trench TB.

[0135] Figure 6 This is an enlarged top view schematic diagram illustrating some embodiments of this disclosure. Figure 2 One of the embedded character line structures is BWL1. In a second comparative embodiment, the embedded character line structure BWL1 has a non-uniform width, wherein some portions of the embedded character line structure BWL1 are narrow, while some portions are wide. In some embodiments, the embedded character line structure BWL1 includes a plurality of first portions P1 and a plurality of second portions P2, wherein the first portions P1 are where the embedded character line structure BWL1 spatially overlaps the active region AA, and the second portions P2 are where the embedded character line structure BWL1 spatially overlaps the insulating region BB. Generally, the width W1 of the first portions P1 is smaller than the width W2 of the second portions P2.

[0136] Similar to the first comparative embodiment, the problem in this second comparative embodiment may be due to the difference in etching rates between the silicon dioxide corresponding to the first part P1 and the polysilicon corresponding to the second part P2 during the fabrication of the buried character line structure BWL1. Therefore, there is a strong need to improve the etch-back process in the formation of the buried character line.

[0137] One object of this disclosure is to provide a semiconductor structure having multiple buried character lines. Figure 7 This is a cross-sectional schematic diagram illustrating the semiconductor structure ST3 of some embodiments of this disclosure. Please refer to... Figure 7 The semiconductor structure ST3 includes a substrate 100, a plurality of insulating regions BB, and a plurality of active regions AA. The insulating regions BB are disposed in the substrate 100, and the active regions AA are surrounded by the insulating regions BB. In some embodiments, the substrate 100 has a generally flat upper surface S1. The active regions AA and the insulating regions BB are staggered. In some embodiments, the active regions AA may be disposed in the substrate 100 at multiple predetermined intervals.

[0138] In some embodiments, an insulating trench TA is recessed into the upper surface S1 and disposed in each insulating region BB. A dielectric material 120 is deposited in a lower portion of the insulating trench TA. In some embodiments, the dielectric material 120 has an upper surface S2, which is located below the upper surface S1 of the substrate 100. Furthermore, a gate trench TB is recessed into the upper surface S1 and disposed in each active region AA. A gate electrode material 140 is deposited in a lower portion of the gate trench TB. In some embodiments, the gate electrode material 140 has an upper surface S3, which is located below the upper surface S1 of the substrate 100. In some embodiments, the upper surface S2 of the dielectric material 120 and the upper surface S3 of the gate electrode material 140 are substantially on the same plane.

[0139] A gate conductive material 190 fills an upper portion of an insulating trench TA to cover a dielectric material 120, and fills an upper portion of a gate trench TB to cover a gate electrode material 140. The dielectric material 120 and the gate conductive material 190 formed thereon, and the gate electrode material 140 and the gate conductive material 190 formed thereon, form a plurality of buried word line structures BWL2 embedded in the substrate 100. Each buried word line structure BWL2 has an upper surface that is substantially coplanar with the upper surface S1 of the substrate 100.

[0140] Another object of this disclosure is to provide a method for fabricating a semiconductor structure having a plurality of buried character lines. Figure 8 This is a flowchart illustrating some embodiments of this disclosure. Figure 7 Method 500 for fabricating the semiconductor structure ST3. Figures 9 to 24 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure based on... Figure 8 The preparation method in the 500 refers to the sequential manufacturing stages.

[0141] Please refer to Figures 9 to 11 ,in accordance with Figure 8 Step S101 involves performing an insulating process on a substrate. In some embodiments, the insulating process is a shallow trench isolation (STI) process that defines at least one active region AA. In some embodiments, the STI process includes a lithography process, an etching process, and a deposition process. First, please refer to... Figure 9 A substrate 100 is provided, and the substrate 100 has an upper surface S1. In some embodiments, the substrate 100 may include Si, SiGe, GaAs, or other suitable semiconductor materials. A first photoresist pattern 110 is formed on the upper surface S1 of the substrate 100. In some embodiments, the first photoresist pattern 110 may define the locations for forming a plurality of insulating structures.

[0142] Next, please refer to Figure 10 The substrate 100 is etched using a first photoresist pattern 110 as an etching mask to form a plurality of insulating trenches TA. After the insulating trenches TA are formed in the substrate 100, an ashing process or a wet stripping process is used.

[0143] Next, please refer to Figure 11 A dielectric material 120 is deposited to fill the insulating trench TA. In some embodiments, the dielectric material 120 may include silicon dioxide or other suitable materials, and its fabrication technology may include a CVD process or a spin coating (SOC) process. In some embodiments, a chemical mechanical polishing is performed to remove the dielectric material 120 on the upper surface S1 of the substrate 100. After the insulating trench TA is filled with the dielectric material 120, a plurality of insulating regions BB are formed. In some embodiments, an active region AA is surrounded by the insulating region BB. Furthermore, the active region AA and the insulating region BB are staggered. In some embodiments, the active regions AA are disposed in the substrate 100 at a plurality of predetermined intervals.

[0144] Please refer to Figures 12 to 14 According to Figure 8 In step S103, a gate electrode formation process is performed on the substrate 100. In some embodiments, the gate electrode formation process includes at least a photolithography process, an etching process, and a deposition process. First, please refer to... Figure 12 A second photoresist pattern 130 is formed on the upper surface S1 of the substrate 100. In some embodiments, the second photoresist pattern 130 defines the location where the gate trench is formed.

[0145] Next, please refer to Figure 13 The substrate 100 is etched using a second photoresist pattern 130 as an etch mask to form a plurality of gate trenches TB. After the gate trenches TB are formed in the substrate 100, the second photoresist pattern 130 is removed using an ashing process or a wet stripping process. In some embodiments, the gate trenches TB are staggered with the insulating region TA.

[0146] Next, please refer to Figure 14 A gate electrode material 140 is deposited to fill the gate trench TB. In some embodiments, the gate electrode material 140 may comprise polysilicon or other suitable materials, and its fabrication technique may include a CVD process or an atomic layer deposition (ALD) process. In some embodiments, a CMP process is performed to remove the gate electrode material 140 above the upper surface S1 of the substrate 100. In some embodiments, the gate trench TB filled with the gate electrode material 140 serves as a gate electrode. In some embodiments, the gate electrodes may be disposed in the substrate 100 at predetermined intervals.

[0147] Please refer to Figures 15 to 21 According to Figure 8 In step S105, a hard mask formation process is performed on the substrate 100. Please refer to... Figure 15 In some embodiments, multiple layers may be sequentially formed on the substrate 100. First, a capping layer 150L is formed on the upper surface S1. In some embodiments, the capping layer 150L completely covers the dielectric material 120 in the insulating trench TA and the gate electrode material 140 in the gate trench TB. In some embodiments, the capping layer 150L comprises a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0148] Next, a mask layer 160L is formed on the cover layer 150L. In some embodiments, the mask layer 160L primarily comprises a plurality of carbon materials and serves as a hard mask. Subsequently, an antireflective coating (ARC) layer 170L is optionally formed on the mask layer 160L, followed by a photoresist layer 180L formed on the antireflective coating layer 170L. In some embodiments, the antireflective coating layer 170L minimizes light reflection when the photoresist layer 180L is irradiated. In some embodiments, the antireflective coating layer 170L is formed using a spin coating process. In some embodiments, the photoresist layer 180L is a positive photoresist (positive photoresist), meaning that the exposed area will be removed by a developer. In some embodiments, the photoresist layer 180L includes a chemical amplifier (CA) photoresist. This chemical amplifier photoresist includes a photoacid generator (PAG), which can be decomposed during the lithography exposure process to form an acid. Due to a catalytic reaction, more acid can be generated. At this time, the capping layer 150L, ​​the masking layer 160L, the anti-reflective coating layer 170L, and the photoresist layer 180L are together formed on the substrate 100 to form a multilayer film 200.

[0149] Please refer to Figure 16 A lithography process is performed on a photoresist layer 180L. The photoresist layer 180L is exposed to radiation hv1 using a photomask MA1 and a lithography system (not shown). In some embodiments, the radiation hv1 may include, but is not limited to, deep ultraviolet (DUV) radiation. The photomask MA1 includes a plurality of transparent portions T1 and a plurality of opaque portions O1. In some embodiments, the photomask MA1 may be a binary mask, a phase-shift mask, or any other type of mask suitable for use in a lithography system. The exposure includes a photochemical reaction that alters the chemical properties of some portions of the photoresist layer 180L. For example, the photoresist layer 180L corresponding to the transparent portions T1 is exposed and becomes more reactive in a development process. In some embodiments, a post-exposure baking (PEB) may be performed after the exposure of the photoresist layer 180L.

[0150] Please refer to Figure 17A suitable developer is used to wash away the exposed photoresist layer 180L. In some embodiments, the exposed portion of the photoresist layer 180L reacts with the developer and can be easily removed. After the exposed photoresist layer 190L is developed, a photoresist pattern 180 is formed, which includes a plurality of photoresist features 180A and a plurality of openings 180B, wherein the openings 180B are disposed together with the photoresist features 180A. In some embodiments, the photoresist features 180A and the openings 180B correspond to the opaque portion O1 and the transparent portion T1 of the light mask MA1, respectively. In some embodiments, a portion of the antireflective coating layer 170L is covered by the photoresist features 180A.

[0151] Please refer to Figure 18 A first etching is performed on the antireflective coating layer 170L. In some embodiments, the first etching may be a RIE process that anisotropically etches portions of the antireflective coating layer 170L exposed by the openings 180B. Thus, an antireflective coating pattern 170 is formed, comprising a plurality of antireflective coating features 170A and a plurality of openings 170B, wherein the openings 170B are disposed together with the antireflective coating features 170A. In some embodiments, the antireflective coating features 170A and the openings 170B are respectively connected to the photoresist feature 180A and the openings 180B. In some embodiments, portions of the mask layer 160L are covered by the antireflective coating features 170A.

[0152] Please refer to Figure 19 A second etching is performed on the mask layer 160L. In some embodiments, the mask layer 160L is etched using the photoresist feature 180A as an etching mask. In some embodiments, the second etching may be a RIE process that anisotropically removes portions of the mask layer 160L exposed by the opening 170B. Thus, a mask pattern 160 is formed, which includes a plurality of mask features 160A and a plurality of openings 160B disposed together with the mask features 160A. In some embodiments, the mask features 160A and the openings 160B are respectively connected to the antireflective coating feature 170A and the openings 170B. In some embodiments, portions of the cover layer 150L are covered by the mask features 160A.

[0153] Please refer to Figure 20 Prior to the next process, the photoresist pattern 180 and the antireflective coating pattern 170 are removed. In some embodiments, this removal may be performed using an ashing process or a wet stripping process.

[0154] Please refer to Figure 21A third etching is performed on the capping layer 150L. In some embodiments, the capping layer 150L is etched using the masking feature 160A as an etching mask. In some embodiments, the third etching may be a RIE process that anisotropically removes portions of the capping layer 150L exposed by the opening 160B. Thus, a capping pattern 150 is formed, comprising a plurality of capping features 150A and a plurality of openings 150B, wherein the openings 150B are disposed together with the capping features 150A. In some embodiments, the capping features 150A and the openings 150B are respectively connected to the masking feature 160A and the openings 160B. In some embodiments, the dielectric material 120 and the gate electrode material 140 are exposed by the openings 150B. In some embodiments, the capping pattern 150 and the masking pattern 160 may be together formed on the substrate 100 to form a hard mask HM1.

[0155] Please refer to Figure 22 ,in accordance with Figure 8 In step S107, an etching process is performed on the substrate 100. In some embodiments, using... Figure 25 An etching method 1000 described herein partially removes dielectric material 120 and gate electrode material 140. In some embodiments, etching of dielectric material 120 and gate electrode material 140 exposes portions thereof by means of a hard mask HM1. Please still refer to... Figure 22 After the etch-back process, the upper surfaces S2 of the etched dielectric material 120 and the upper surfaces S3 of the etched gate electrode material 140 are all lower than the upper surface S1 of the substrate 10. At this time, the depressions in the insulating trench TA and the gate trench TB are generated again. In some embodiments, the depressions are filled with a plurality of subsequently formed buried word lines.

[0156] Compared to Figure 4 In the first comparative embodiment, with the use of etching method 1000, the upper surfaces S2 of the etched dielectric material 120 and the etched gate electrode material 140 are substantially on the same plane. The etching method 1000 according to an embodiment of the present disclosure can balance the unbalanced etching of the gate electrode material 140 and the dielectric material 120 during the etch-back process.

[0157] Please refer to Figure 23 ,in accordance with Figure 8 In step S109, the hard mask HM1 is removed from the substrate 100. In some embodiments, the hard mask HM1 is removed using an ashing process or a wet stripping process prior to the formation of the embedded character lines.

[0158] Please refer to Figure 24 ,in accordance with Figure 8In step S111, an embedded word line formation process is performed. In some embodiments, a gate conductive material 190 is deposited to completely cover the dielectric material 120 and the gate electrode material 140. Therefore, the insulating trench TA and the gate trench TB are filled with the gate conductive material 190. In some embodiments, the fabrication technique of the gate conductive material 190 includes using a CVD process, a physical vapor deposition (PVD) process, or an ALD process. In some embodiments, the gate conductive material 190 may include any one or more of the following: TiN, WN, TaN, TiSiN, TaSiN, WSiN, and WSiN. In some embodiments, the gate conductive material 190 is polished using a CMP process or a dry etching process to remove a portion of the gate conductive material 190 on the upper surface S1 of the substrate 100.

[0159] After the gate conductive material 190 is completely deposited in the insulating trench TA and the gate trench TB, a plurality of buried word lines are formed. In some embodiments, the dielectric material 120, the gate electrode material 140, and the gate conductive material 190 disposed thereon may form a plurality of buried word line structures BWL2. In some embodiments, each buried word line structure BWL2 has an upper surface that is coplanar with the upper surface S1 of the substrate 100. At this time, a semiconductor structure ST3 with a plurality of buried word lines is typically formed.

[0160] Figure 25 This is a graph illustrating the relationship between plasma power and etching time, showing some embodiments of this disclosure used in applications... Figure 22 The plasma in the etching method 1000 of the back etching process described herein. The X-axis represents the etching time t (seconds), and the Y-axis represents the plasma power P (watts). In some embodiments, the etching method 1000 includes a first working stage WS1, a second working stage WS2, and a third working stage WS3, which are performed in situ in a single etching chamber.

[0161] During the first operating phase WS1, a first plasma is used, wherein the first plasma comprises a first etchant combination. In some embodiments, the first plasma may have a first etch selectivity of approximately 1:2 for polysilicon to silicon dioxide. Therefore, the etch ratio of the gate electrode material 140 to the dielectric material 120 is approximately 1:2. In some embodiments, the first operating phase WS1 comprises two or four intervals. In a preferred embodiment, the first operating phase WS1 comprises three intervals I11, I12, and I13. In interval I11, the first plasma is turned on and maintained at a first high power HP1 for 5 seconds. Then, the first plasma is adjusted to a low power PL and maintained at the low power PL for 5 seconds to complete interval I11. In interval I12, the first plasma is adjusted to a first high power HP1 and maintained at the first high power HP1 for 5 seconds. Then, the first plasma is adjusted to a low power PL and maintained at the low power PL for 5 seconds to complete interval I12. In some embodiments, subsequent intervals repeat as in interval I12. In the final interval, after the first plasma is maintained at low power PL for 5 seconds, a first switching step SW1 is performed to terminate the first working phase WS1.

[0162] Please refer to the following: Figure 25 Following the first switching step SW1, there is a first stabilization period SP1 for changing the first etchant combination to a second etchant combination to form a second plasma. Then, the second operating phase WS2 begins with the use of this second plasma. In some embodiments, the second etchant combination differs from the first etchant combination. In some embodiments, the second plasma has a second etch selectivity of approximately 2:1 for polysilicon to silicon dioxide. Therefore, the etch ratio of the gate electrode material 140 to the dielectric material 120 is approximately 2:1. In some embodiments, the second operating phase WS2 also includes two or four intervals. In a preferred embodiment, the second operating phase WS2 includes three intervals I21, I22, and I23. In interval I21, the second plasma is maintained at a second high power HP2 for 5 seconds. Then, the second plasma is adjusted to a low power PL and maintained at low power PL for 5 seconds to complete interval I21. In some embodiments, the second high power HP2 may differ from the first high power HP1. In other embodiments, the second high power HP2 may be the same as the first high power HP1. In some embodiments, the low-power PL is in an on state, meaning that the power supply for the first or second plasma is always on. In some embodiments, the subsequent intervals I22 and I23 are repeated as in interval I21. In the final interval, after the second plasma is maintained at low power PL for 5 seconds, a second switching step SW2 is performed to terminate the second operating phase WS2.

[0163] Please refer to the following: Figure 25 Following the second switching step SW2, there is a second stabilization period SP2 for changing the second etchant combination to a third etchant combination to form a third plasma. Then, the third operating phase WS3 begins with the use of this third plasma. In some embodiments, the third etchant combination differs from the first or second etchant combination. In some embodiments, the third plasma may have a third etch selectivity of approximately 3:1 for polysilicon versus silicon dioxide. Therefore, the etch ratio of the gate electrode material 140 to the dielectric material 120 is approximately 3:1. In some embodiments, during the third operating phase WS3, one of a pair of electrodes in an etch system (not shown) used to perform the etch-back process is turned off. In the third operating phase WS3, the third plasma is maintained at a third high power HP3 for 5 to 20 seconds. Next, the third plasma is turned off to complete the etch-back process. In some embodiments, the third high power HP3 is lower than the first high power HP1 or the second high power HP2. In some embodiments, high-power modes (HP1, HP2, HP3) represent multiple primary etch phases, and low-power modes (PL) represent phases removed by etching multiple byproducts.

[0164] This disclosure provides an etching method comprising three working stages performed in situ within a single etching chamber. The three working stages include different combinations of etchants acting as plasmas. By varying the etchant combinations, the plasma can exhibit different etching selectivity in the three working stages for polysilicon in the gate electrode material corresponding to silicon dioxide in the dielectric material. Furthermore, the power applied to the plasma is adjusted at different intervals in the first and second working stages. During the primary etching phase, the plasma is at a high power. When the plasma is at a low power, the etching byproducts are removed. Thus, during the etch-back process, the dielectric material in the insulating trench and the gate electrode material in the gate trench can be recessed into the upper surface of the substrate. Moreover, according to the etching method provided in this disclosure, during the buried word line formation, the upper surface of the etched dielectric material and the upper surface of the etched gate electrode material can be maintained at substantially the same plane.

[0165] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0166] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor structure, comprising: A substrate is provided, the substrate including an insulating region, an active region and a first upper surface, the active region being adjacent to the insulating region, wherein the insulating region includes an insulating trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material. A hard mask is formed on the substrate; as well as An etching process is performed to partially remove the dielectric material and the gate electrode material exposed by the hard mask, so as to form a second upper surface of the dielectric material and a third upper surface of the gate electrode material. The second upper surface and the third upper surface are on the same plane, and the second upper surface is lower than the first upper surface. The etching process includes: A first plasma is used in a first working stage, wherein the first plasma has a first etching selectivity of the gate electrode material to the dielectric material; In a second working stage, the first plasma is transformed into a second plasma, wherein the second plasma has a second etching selectivity of the gate electrode material for the dielectric material; and In a third working stage, the second plasma is transformed into a third plasma, wherein the third plasma has a third etching selectivity of the gate electrode material for the dielectric material.

2. The preparation method according to claim 1 further includes depositing a gate conductive material to cover the dielectric material and the gate electrode material.

3. The preparation method of claim 2 further includes removing a portion of the gate conductive material on the first upper surface of the substrate, so that the gate conductive material in the insulating trench is recessed below the first upper surface.

4. The preparation method according to claim 1, wherein the formation of the hard mask comprises: A capping layer is formed on the substrate, the dielectric material, and the gate electrode material; A masking layer is formed on the cover layer; An anti-reflective coating is formed on the mask layer; and A photoresist pattern is formed on the antireflective coating layer, wherein the photoresist pattern includes multiple photoresist features.

5. The preparation method of claim 4, wherein the photoresist feature is used as an etch mask to etch the mask layer to form a mask pattern, the mask pattern comprising a plurality of mask features.

6. The preparation method of claim 5, wherein the masking feature is used as an etch mask to etch the cover layer to form a cover pattern comprising a plurality of cover features.

7. The preparation method of claim 6, wherein the cover pattern and the mask pattern are formed together on the substrate in the hard mask.

8. The preparation method of claim 1, wherein the first working stage, the second working stage and the third working stage are performed in situ in a single etching chamber.

9. The preparation method according to claim 1, wherein the first working stage includes: The first interval, wherein the first plasma is turned on and maintained at a first high power, then adjusted to a low power and maintained at that low power; A second interval, wherein the first plasma is adjusted to and maintained at the first high power, then adjusted to and maintained at the low power; and A third interval is followed by a repetition of the second interval, wherein after the third interval, a first switching step is performed to terminate the first working phase.

10. The preparation method of claim 9, wherein after the first switching step, a first stabilization period is used to change the first plasma to the second plasma.

11. The preparation method according to claim 10, wherein the second working stage includes: A fourth interval, wherein the second plasma is maintained at a second high power, then adjusted to the low power and maintained at the low power; A fifth interval, wherein the second plasma is adjusted to the second high power and maintained at the second high power, then adjusted to the low power and maintained at the low power; and A sixth interval is followed by the fifth interval, wherein after the sixth interval, a second switching step is performed to terminate the second working phase.

12. The preparation method of claim 11, wherein after the second switching step, a second stabilization period is used to change the second plasma to the third plasma.

13. The preparation method of claim 12, wherein the third working stage includes maintaining the third plasma at a third high power.

14. The preparation method of claim 13, wherein the second high power is different from the first high power.

15. The preparation method of claim 13, wherein the third high power is lower than the first high power or the second high power.

16. The preparation method of claim 13, wherein the first high power, the second high power, and the third high power represent the main etching phase.

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