Capacitor and method of manufacturing the same

Abstract

The present invention provides a capacitor and a manufacturing method thereof, including a capacitor unit, wherein the capacitor unit has a first side and a second side relative to each other, and on the first side of the capacitor unit, the sidewalls of the second conductive layer located in an even-numbered layer are aligned with the sidewalls of the second conductive layer located in an odd-numbered layer below it, and a portion of the upper surface of the second conductive layer located in an even-numbered layer below it is exposed; and / or, on the second side of the capacitor unit, the sidewalls of the second conductive layer located in an odd-numbered layer are aligned with the sidewalls of the second conductive layer located in an even-numbered layer below it, and a portion of the upper surface of the second conductive layer located in an odd-numbered layer below it is exposed, thereby reducing the use of masks and lowering manufacturing costs; or, without reducing the number of masks, more layers of the second conductive layer can be exposed to lead out wiring, thereby improving the capacitance density of the capacitor; or, the process requirements for the subsequently formed contact conductive structure can be reduced, thereby improving the reliability of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitor and a manufacturing method thereof. Background Art

[0002] Capacitors are widely used in a large number of electronic products. Common capacitors include MLCCs (Multi-layer Ceramic Capacitors), tantalum capacitors, and high-voltage capacitors. Their basic uses include storing voltage, isolating DC signals, bypassing high-frequency noise, and ensuring the integrity of power supply signals.

[0003] While widely used, MLCCs offer low cost, but their capacitance becomes significantly reduced if their thickness is reduced below 100μm. This thinness also leads to stress and reliability issues. Consequently, they cannot be used in advanced 2.5D and 3D integrated circuits and module packaging, nor are they suitable for ultra-small, ultra-thin, and high-reliability products.

[0004] Silicon-based capacitors are ideal for ultra-small, ultra-thin, and high-reliability products. For example, in the demanding testing requirements of automotive electronics, their reliability is 10 times that of MLCCs, and their temperature resistance can reach 200°C. Furthermore, silicon-based capacitors can be less than 40μm thick, while the thinnest MLCC is only 120μm. Their ultra-thin form factor is also well-suited for advanced integrated packaging applications such as CoWoS (Chipon Wafer on Substrate), WoW (Wafer on Wafer), and InFo (Integrated Fan-Out).

[0005] However, in order to increase the capacitance density of silicon-based capacitors, the number of conductive layers needs to be increased, which also requires increasing the number of photolithography processes for the corresponding conductive layers. For example, three conductive layers require three photolithography and etching processes to expose each conductive layer for lead-out. If seven conductive layers are needed to increase capacitance, seven photolithography and etching processes are required to expose each conductive layer for lead-out, resulting in increased manufacturing costs. Therefore, how to reduce costs and increase capacitance density is a decisive factor in the promotion of capacitors. Summary of the Invention

[0006] An object of the present invention is to provide a capacitor and a method for manufacturing the same, so as to reduce manufacturing costs, increase capacitance density or improve capacitor reliability.

[0007] In order to achieve the above object, the present invention provides a capacitor, comprising:

[0008] a substrate having a groove formed therein; and

[0009] a capacitor unit located on the substrate, the capacitor unit comprising a first conductive layer and N capacitor layers located on the first conductive layer, the first conductive layer covering the inner wall of the groove and extending to cover the surface of the substrate, each capacitor layer comprising a stacked dielectric layer and a second conductive layer, wherein N is a natural number greater than 1;

[0010] The capacitor unit has a first side and a second side relative to each other, and on the first side of the capacitor unit, the side wall of the second conductive layer located in the even-numbered layer is aligned with the side wall of the second conductive layer located in the next odd-numbered layer, and a portion of the upper surface of the second conductive layer located in the next even-numbered layer is exposed; and / or, on the second side of the capacitor unit, the side wall of the second conductive layer located in the odd-numbered layer is aligned with the side wall of the second conductive layer located in the next even-numbered layer, and a portion of the upper surface of the second conductive layer located in the next odd-numbered layer is exposed.

[0011] Optionally, in the capacitor, the capacitor further includes a first protective structure and a second protective structure, the first protective structure covers the side wall of at least one layer of the second conductive layer on the first side of the capacitor unit, and the second protective structure covers the side wall of at least one layer of the second conductive layer on the second side of the capacitor unit.

[0012] Optionally, in the capacitor, the capacitor further includes at least one first contact conductive structure and at least one second contact conductive structure, and on the first side of the capacitor unit, each of the second conductive layers located in the even-numbered layers is connected to a different first contact conductive structure, or at least part of the second conductive layers located in the even-numbered layers are connected to the same first contact conductive structure; on the second side of the capacitor unit, each of the second conductive layers located in the odd-numbered layers is connected to a different second contact conductive structure, or at least part of the second conductive layers located in the odd-numbered layers are connected to the same second contact conductive structure; the first conductive layer is connected to the first contact conductive structure or the second contact conductive structure.

[0013] Optionally, in the capacitor, the capacitor further includes at least one wiring layer, each wiring layer includes at least one first wiring structure and at least one second wiring structure, the first contact conductive structure is connected to the first wiring structure, and the second contact conductive structure is connected to the second wiring structure.

[0014] Optionally, in the capacitor, the capacitor includes at least two wiring layers, the first contact conductive structure is connected to the first wiring structure in the wiring layer located at the bottom layer, and the second contact conductive structure is connected to the second wiring structure in the wiring layer located at the bottom layer; the first wiring structure and the second wiring structure in the wiring layer of the upper layer are correspondingly connected to the first wiring structure and the second wiring structure in the wiring layer of the lower layer.

[0015] Optionally, in the capacitor, the capacitor further includes at least one first lead-out electrode and at least one second lead-out electrode, the first wiring structure in the top wiring layer is connected to the first lead-out electrode, and the second wiring structure in the top wiring layer is connected to the second lead-out electrode.

[0016] Optionally, in the capacitor, the capacitor includes a plurality of the capacitor units.

[0017] Optionally, in the capacitor, the capacitor includes a plurality of the capacitor units, and in all the capacitor units, at least one of the first lead-out electrode or the second lead-out electrode is connected to only one of the capacitor units.

[0018] Optionally, in the capacitor, a plurality of the grooves are formed in the substrate, and each of the capacitor units covers at least one of the grooves.

[0019] Optionally, in the capacitor, the material of the substrate includes ceramic, glass, plastic or semiconductor silicon wafer.

[0020] The present invention also provides a method for manufacturing a capacitor, the method comprising:

[0021] providing a substrate having a groove formed therein;

[0022] forming a first conductive layer on the substrate, wherein the first conductive layer covers the inner wall of the groove and extends to cover the surface of the substrate;

[0023] forming N capacitor layers on the first conductive layer in sequence, each capacitor layer including a stacked dielectric layer and a second conductive layer, wherein N is a natural number greater than 1; and

[0024] An exposure area is formed using a mask combination, and an etching process is performed on the N-layer capacitor layer in the exposure area to form a capacitor unit, wherein the capacitor unit has a first side and a second side relative to each other, and on the first side of the capacitor unit, the sidewalls of the second conductive layer located in the even-numbered layer are aligned with the sidewalls of the second conductive layer located in the next odd-numbered layer, and a portion of the upper surface of the second conductive layer located in the next even-numbered layer is exposed; and / or, on the second side of the capacitor unit, the sidewalls of the second conductive layer located in the odd-numbered layer are aligned with the sidewalls of the second conductive layer located in the next even-numbered layer, and a portion of the upper surface of the second conductive layer located in the next odd-numbered layer is exposed.

[0025] Optionally, in the method for manufacturing the capacitor, forming an exposure area using a mask combination, and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit at least includes:

[0026] Using a first photomask to form a first exposure area, the first exposure area exposing a portion of the surface of the first capacitor layer in the N-layer capacitor layer, and etching away the first capacitor layer exposed in the first exposure area, or etching away the first capacitor layer and the capacitor layer next to it exposed in the first exposure area; and

[0027] Using a second photomask to form a second exposure area, the second exposure area exposing a portion of the surface of the second capacitor layer in the N-layer capacitor layer, and etching away the second capacitor layer and the capacitor layer next to it exposed in the second exposure area, or etching away the second capacitor layer exposed in the second exposure area;

[0028] wherein, the first exposure region is formed by using the first photomask first and then the second exposure region is formed by using the second photomask; or, the second exposure region is formed by using the second photomask first and then the first exposure region is formed by using the first photomask;

[0029] The first capacitor layer and the second capacitor layer are the same capacitor layer or different capacitor layers.

[0030] Optionally, in the method for manufacturing the capacitor, forming an exposure area using a mask combination, and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit further comprises:

[0031] Using the first photomask to form a third exposure area, the third exposure area exposing a portion of the surface of the third capacitor layer in the N-layer capacitor layer, and etching and removing the third capacitor layer exposed in the third exposure area, or etching and removing the third capacitor layer and the capacitor layer next to it exposed in the third exposure area; wherein the third capacitor layer and the first capacitor layer are different capacitor layers;

[0032] Alternatively, a fourth exposure area is formed using the second photomask, wherein the fourth exposure area exposes a portion of the surface of the fourth capacitor layer in the N-layer capacitor layer, and the fourth capacitor layer and the capacitor layer below it exposed in the fourth exposure area are etched away, or the fourth capacitor layer exposed in the fourth exposure area is etched away; wherein the fourth capacitor layer and the second capacitor layer are different capacitor layers;

[0033] Alternatively, a third photomask is used to form a fifth exposure area and a sixth exposure area, wherein the fifth exposure area exposes a portion of the surface of the fifth capacitor layer in the N-layer capacitor layer, and the fifth capacitor layer and the capacitor layer of the next layer exposed in the fifth exposure area are etched away, and the sixth exposure area exposes a portion of the surface of the sixth capacitor layer in the N-layer capacitor layer, and the sixth capacitor layer and the capacitor layer of the next layer exposed in the sixth exposure area are etched away; wherein the fifth capacitor layer and the sixth capacitor layer are capacitor layers of different layers.

[0034] Optionally, in the method for manufacturing the capacitor, the method for manufacturing the capacitor further includes:

[0035] A first protection structure and a second protection structure are formed, wherein the first protection structure covers the sidewall of at least one layer of the second conductive layer on the first side of the capacitor unit, and the second protection structure covers the sidewall of at least one layer of the second conductive layer on the second side of the capacitor unit.

[0036] Optionally, in the method for manufacturing the capacitor, the method for manufacturing the capacitor further includes:

[0037] At least one first contact conductive structure and at least one second contact conductive structure are formed. On the first side of the capacitor unit, each of the second conductive layers located in the even-numbered layers is connected to a different first contact conductive structure, or at least part of the second conductive layers located in the even-numbered layers are connected to the same first contact conductive structure; on the second side of the capacitor unit, each of the second conductive layers located in the odd-numbered layers is connected to a different second contact conductive structure, or at least part of the second conductive layers located in the odd-numbered layers are connected to the same second contact conductive structure; the first conductive layer is connected to the first contact conductive structure or the second contact conductive structure.

[0038] Optionally, in the method for manufacturing the capacitor, the method for manufacturing the capacitor further includes:

[0039] At least one wiring layer is formed, each wiring layer includes at least one first wiring structure and at least one second wiring structure, the first contact conductive structure is connected to the first wiring structure, and the second contact conductive structure is connected to the second wiring structure.

[0040] Optionally, in the manufacturing method of the capacitor, at least two wiring layers are formed, the first contact conductive structure is connected to the first wiring structure in the wiring layer located at the bottom layer, and the second contact conductive structure is connected to the second wiring structure in the wiring layer located at the bottom layer; the first wiring structure and the second wiring structure in the upper wiring layer are correspondingly connected to the first wiring structure and the second wiring structure in the lower wiring layer.

[0041] Optionally, in the method for manufacturing the capacitor, the method for manufacturing the capacitor further includes:

[0042] At least one first extraction electrode and at least one second extraction electrode are formed, the first wiring structure in the top wiring layer is connected to the first extraction electrode, and the second wiring structure in the top wiring layer is connected to the second extraction electrode.

[0043] Optionally, in the method for manufacturing the capacitor, an exposure area is formed by using a mask combination, and an etching process is performed on the N-layer capacitor layer in the exposure area to form a plurality of capacitor units at the same time.

[0044] Optionally, in the manufacturing method of the capacitor, an exposure area is formed using a mask combination, and an etching process is performed on the N-layer capacitor layer in the exposure area to simultaneously form a plurality of capacitor units. Among all the capacitor units, at least one of the first lead-out electrode or the second lead-out electrode is only connected to one of the capacitor units.

[0045] The capacitor and its manufacturing method provided by the present invention include a capacitor unit, which has a first side and a second side relative to each other. On the first side of the capacitor unit, the second conductive layer located in the even-numbered layer is aligned with the side wall of the second conductive layer located in the next odd-numbered layer, and a portion of the upper surface of the second conductive layer located in the next even-numbered layer is exposed; and / or, on the second side of the capacitor unit, the second conductive layer located in the odd-numbered layer is aligned with the side wall of the second conductive layer located in the next even-numbered layer, and a portion of the upper surface of the second conductive layer located in the next odd-numbered layer is exposed, thereby reducing the use of masks and thus reducing manufacturing costs; or without reducing the number of masks, more layers of second conductive layers can be exposed to lead out wiring, thereby improving the capacitance density of the capacitor; or the process requirements for the subsequently formed contact conductive structure can be reduced, thereby improving the reliability of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of the correspondence between a three-layer capacitor and the three required photomasks in the prior art.

[0047] Figures 2 to 13 3 is a schematic structural diagram of a device formed by executing the capacitor manufacturing method according to the first embodiment of the present invention.

[0048] Figure 14 1 is a schematic diagram of the correspondence between the three-layer capacitor and the two required photomasks in the second embodiment of the present invention.

[0049] Figure 15 1 is a schematic diagram of the correspondence between the four-layer capacitor and the three required photomasks in the third embodiment of the present invention.

[0050] Figure 16 1 is a schematic diagram of the correspondence between a capacitor with a four-layer structure and the three required photomasks in the fourth embodiment of the present invention.

[0051] Figure 17 1 is a schematic diagram of the correspondence between the four-layer capacitor and the three required photomasks in the fifth embodiment of the present invention.

[0052] Figure 18 1 is a schematic diagram of the correspondence between a capacitor with a four-layer structure and the three required photomasks in the sixth embodiment of the present invention.

[0053] Figure 19 1 is a schematic diagram of the correspondence between a five-layer capacitor and the three required photomasks in the seventh embodiment of the present invention.

[0054] Figure 20 1 is a schematic diagram of the correspondence between the capacitor with a seven-layer structure and the four required photomasks in the eighth embodiment of the present invention.

[0055] Figure 21 It is a structural diagram of a three-layer capacitor in Example 9 of the present invention.

[0056] Figure 22 Schematic diagram of the structure of a three-layer capacitor in the tenth embodiment of the present invention.

[0057] Figure 23 1 is a schematic structural diagram of a three-layer capacitor in the eleventh embodiment of the present invention.

[0058] Figure 24 This is a circuit diagram of a three-layer capacitor in the eleventh embodiment of the present invention.

[0059] The description of the accompanying drawings is as follows:

[0060] Figure markings in the prior art: 10-first light mask; 11-second light mask; 12-third light mask; 100-first conductive layer; 101-first capacitor layer; 102-second capacitor layer; 103-third capacitor layer; 104-substrate; 1010-first dielectric layer; 1011-first second conductive layer; 1020-second dielectric layer; 1021-second second conductive layer; 1030-third dielectric layer; 1031-third second conductive layer.

[0061] Reference numerals in the first embodiment: 20 - first photomask; 21 - second photomask; 200 - substrate; 201 - groove; 202 - first conductive layer; 203 - first capacitor layer; 204 - second capacitor layer; 205 - third capacitor layer; 2030 - first dielectric layer; 2031 - first second conductive layer; 2040 - second dielectric layer; 2041 - second second conductive layer; 2050 - third dielectric layer; 2051 - third second conductive layer; 206 - first mask layer; 207 - second An exposure area; 208-a second mask layer; 209-a second exposure area; 210-a third exposure area; 211-a first protection structure; 212-a second protection structure; 213-a metal silicide layer; 214-a first contact conductive structure; 215-a second contact conductive structure; 216-a first dielectric layer; 217-a wiring layer; 2170-a first wiring structure; 2171-a second wiring structure; 218-an extraction electrode; 2180-a first extraction electrode; 2181-a second extraction electrode; 219-a second dielectric layer.

[0062] Figure marks in Example 2: 22-first light mask; 23-second light mask; 220-first conductive layer; 221-first capacitor layer; 222-second capacitor layer; 223-third capacitor layer; 2210-first dielectric layer; 2211-first second conductive layer; 2220-second dielectric layer; 2221-second second conductive layer; 2230-third dielectric layer; 2231-third second conductive layer; 2240-first contact conductive structure; 2241-second contact conductive structure.

[0063] Figure marks in Example 3: 24-first light mask; 25-second light mask; 26-third light mask; 230-first conductive layer; 231-first capacitor layer; 232-second capacitor layer; 233-third capacitor layer; 234-fourth capacitor layer; 2310-first dielectric layer; 2311-first second conductive layer; 2320-second dielectric layer; 2321-second second conductive layer; 2330-third dielectric layer; 2331-third second conductive layer; 2340-fourth dielectric layer; 2341-fourth second conductive layer; 2350-first contact conductive structure; 2351-second contact conductive structure.

[0064] Figure markings in Example 4: 27-first light mask; 28-second light mask; 29-third light mask; 240-first conductive layer; 241-first capacitor layer; 242-second capacitor layer; 243-third capacitor layer; 244-fourth capacitor layer; 2410-first dielectric layer; 2411-first second conductive layer; 2420-second dielectric layer; 2421-second second conductive layer; 2430-third dielectric layer; 2431-third second conductive layer; 2440-fourth dielectric layer; 2441-fourth second conductive layer.

[0065] Figure markings in Example 5: 30-first light mask; 31-second light mask; 32-third light mask; 250-first conductive layer; 251-first capacitor layer; 252-second capacitor layer; 253-third capacitor layer; 254-fourth capacitor layer; 2510-first dielectric layer; 2511-first second conductive layer; 2520-second dielectric layer; 2521-second second conductive layer; 2530-third dielectric layer; 2531-third second conductive layer; 2540-fourth dielectric layer; 2541-fourth second conductive layer.

[0066] Figure markings in Example 6: 33-first light mask; 34-second light mask; 35-third light mask; 260-first conductive layer; 261-first capacitor layer; 262-second capacitor layer; 263-third capacitor layer; 264-fourth capacitor layer; 2610-first dielectric layer; 2611-first second conductive layer; 2620-second dielectric layer; 2621-second second conductive layer; 2630-third dielectric layer; 2631-third second conductive layer; 2640-fourth dielectric layer; 2641-fourth second conductive layer.

[0067] Figure markings in Example 7: 36-first light mask; 37-second light mask; 38-third light mask; 270-first conductive layer; 271-first capacitor layer; 272-second capacitor layer; 273-third capacitor layer; 274-fourth capacitor layer; 275-fifth capacitor layer; 2710-first dielectric layer; 2711-first second conductive layer; 2720-second dielectric layer; 2721-second second conductive layer; 2730-third dielectric layer; 2731-third second conductive layer; 2740-fourth dielectric layer; 2741-fourth second conductive layer; 2750-fifth dielectric layer; 2751-fifth second conductive layer.

[0068] Reference numerals in the eighth embodiment: 39 - first light mask; 40 - second light mask; 41 - third light mask; 42 - fourth light mask; 280 - first conductive layer; 281 - first capacitor layer; 282 - second capacitor layer; 283 - third capacitor layer; 284 - fourth capacitor layer; 285 - fifth capacitor layer; 286 - sixth capacitor layer; 287 - seventh capacitor layer; 2810 - first dielectric layer; 2811 - first second conductive layer layer; 2820-second dielectric layer; 2821-second second conductive layer; 2830-third dielectric layer; 2831-third second conductive layer; 2840-fourth dielectric layer; 2841-fourth second conductive layer; 2850-fifth dielectric layer; 2851-fifth second conductive layer; 2860-sixth dielectric layer; 2861-sixth second conductive layer; 2870-seventh dielectric layer; 2871-seventh second conductive layer.

[0069] Figure markings in Example 9: 290-first contact conductive structure; 291-second contact conductive structure; 292-first conductive layer; 293-first second conductive layer; 294-second second conductive layer; 295-third second conductive layer; 296-first wiring layer; 297-second wiring layer; 2960, 2970-first wiring structure; 2961, 2971-second wiring structure; 298-dielectric layer; 2990-first lead-out electrode; 2991-second lead-out electrode.

[0070] Reference numerals in the tenth embodiment: 300 - substrate; 301 - groove; 302 - capacitor unit.

[0071] Reference numerals in the eleventh embodiment: 400 - capacitor unit; 4000 - first capacitor unit; 4001 - second capacitor unit; 4002 - third capacitor unit; 401 - first conductive layer; 402 - wiring layer. DETAILED DESCRIPTION

[0072] The following is a detailed description of the capacitor and its manufacturing method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0073] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the invention. Unless otherwise defined herein, technical or scientific terms used herein shall have the ordinary meaning as understood by persons of ordinary skill in the art to which the invention pertains. The terms "first," "second," and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are simply used to distinguish one component from another. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. "Multiple" or "several" refer to two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the invention to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or items preceding the term "include" or "comprising" include the elements or items listed after the term and their equivalents, and do not exclude other elements or items. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and may include electrical connections, whether direct or indirect. As used in the present description and the appended claims, the singular forms "a," "an," "said," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0074] In addition, it should be noted that the terms "first mask" and "first mask" appear in the terminology of this application, where "first mask" refers to the first mask used in a certain sequence; and "first mask" is only for the convenience of description, used to distinguish it from other masks, which can be the first mask used, or the second, third, ..., mask used; similarly, "second mask" and "second mask" are also used. The terms "first capacitor layer" and "first capacitor layer" also appear in the terminology of this application, where "first capacitor layer" refers to the first capacitor layer formed in a stacked structure; and "first capacitor layer" is only for the convenience of description, used to distinguish it from other capacitor layers, which can be the first capacitor layer, or the second, third, ..., capacitor layer; similarly, "second capacitor layer" and "second capacitor layer" are also used. The terminology of this application also includes multiple first exposure areas, multiple second exposure areas... etc., among which multiple first exposure areas are usually exposure areas of different sizes or positions, etc., and usually they only appear in the same order in specific situations. For example, they appear for the first time in the claims, Example 1, Example 2..., respectively. For the convenience of description, the above arrangement is made.

[0075] In the prior art, if a capacitor with an M-layer structure is to be formed, M photomasks need to be used and M photolithography and etching processes need to be performed to expose the conductive layers serving as capacitor plates for lead-out. For example, in order to form a three-layer capacitor, the existing technology requires three photomasks and three photolithography and etching processes to expose the conductive layers serving as the capacitor plates for lead-out wiring, thereby forming a corresponding three-layer capacitor; in order to form a four-layer capacitor, the existing technology requires four photomasks and four photolithography and etching processes to expose the conductive layers serving as the capacitor plates for lead-out wiring, thereby forming a corresponding four-layer capacitor; and in order to form a five-layer capacitor, the existing technology requires five photomasks and five photolithography and etching processes to expose the conductive layers serving as the capacitor plates for lead-out wiring, thereby forming a corresponding five-layer capacitor; for another example, in order to form a seven-layer capacitor, the existing technology requires seven photomasks and seven photolithography and etching processes to expose the conductive layers serving as the capacitor plates for lead-out wiring, thereby forming a corresponding seven-layer capacitor.

[0076] That is, in the prior art, if a capacitor with an M-layer structure is to be formed, M photomasks are required, which increases the mask cost and the manufacturing cost accordingly; or, under limited manufacturing costs, more photomasks cannot be used, thereby failing to increase the capacitance density.

[0077] Here, we take the prior art method of forming a three-layer capacitor using three photomasks as an example to further illustrate its formation method. Figure 1 , which is a schematic diagram of the correspondence between a three-layer capacitor and the three required masks in the prior art.

[0078] like Figure 1 As shown, in the prior art, after forming the first conductive layer 100 and the three capacitor layers on the substrate 104, a first mask 10 is used to form a first exposure area ( Figure 1 ). The three-layer capacitor layer includes a stacked first capacitor layer 101, a second capacitor layer 102, and a third capacitor layer 103, each capacitor layer including a stacked dielectric layer and a second conductive layer, that is, the three-layer capacitor layer includes a stacked first dielectric layer 1010, a first second conductive layer 1011, a second dielectric layer 1020, a second second conductive layer 1021, a third dielectric layer 1030, and a third second conductive layer 1031. The first exposure area exposes the third capacitor layer 103, specifically, exposes a portion of the surface of the third second conductive layer 1031 (that is, the topmost conductive layer here). Then, the third second conductive layer 1031 and the third dielectric layer 1030 are etched from the exposed third second conductive layer 1031 to expose the second second conductive layer 1021.

[0079] The specific method of etching the third second conductive layer 1031 and the third dielectric layer 1030 to expose the second second conductive layer 1021 may include: first forming a mask layer ( Figure 1 (not shown); then, the mask layer is exposed using a first photomask 10, and the exposed mask layer is developed to form a first exposure region, which exposes a portion of the third second conductive layer 1031; the exposed third second conductive layer 1031 and the underlying third dielectric layer 1030 are etched to expose a portion of the surface of the second second conductive layer 1021; finally, the mask layer is removed. Conventional exposure, development, and etching processes are employed, and will not be further described in this application.

[0080] Please continue to refer to Figure 1 Then, the second exposure area ( Figure 1 (not shown), the second exposure area exposes a portion of the second second conductive layer 1021, and then, the exposed second second conductive layer 1021 and the second dielectric layer 1020 thereunder are etched to expose the first second conductive layer 1011.

[0081] Next, a third photomask 12 is used to form a third exposure area, which exposes a portion of the first second conductive layer 1011. Next, the first second conductive layer 1011 and the first dielectric layer 1010 are etched to expose the first conductive layer 100. Thus, by using three photomasks, the conductive layers serving as capacitor plates are exposed, namely, the first conductive layer 100, the first second conductive layer 1011, the second second conductive layer 1021, and the third second conductive layer 1031.

[0082] Here, the first conductive layer 100, the first dielectric layer 1010, the first second conductive layer 1011, the second dielectric layer 1020, the second second conductive layer 1021, the third dielectric layer 1030, and the third second conductive layer 1031 stacked in sequence constitute a three-layer capacitor unit. At two opposing sides of the three-layer capacitor unit, which may be referred to herein as a first side and a second side, the upper surface of the second second conductive layer 1021, the upper surface of the first second conductive layer 1011, and the upper surface of the first conductive layer 100 are all exposed; simultaneously, the entire upper surface of the third second conductive layer 1031 is exposed. Then, a contact conductive structure can be formed to connect the exposed third-layer second conductive layer 1031, the second-layer second conductive layer 1021, the first-layer second conductive layer 1011 and the first conductive layer 100, thereby leading out the first conductive layer 100, the first-layer second conductive layer 1011, the second-layer second conductive layer 1021 and the third-layer second conductive layer 1031.

[0083] like Figure 1 As shown, in the prior art, for forming a three-layer capacitor unit, the first mask 10, the second mask 11, and the third mask 12 each have two mask areas, and the two mask areas of the second mask 11 are respectively located within the range of the two mask areas of the first mask 10 (that is, the projections of the two mask areas of the second mask 11 on the substrate 104 are respectively located within the projections of the two mask areas of the first mask 10 on the substrate 104), and the two mask areas of the third mask 12 are respectively located within the range of the two mask areas of the second mask 11. The three-layer capacitor unit is formed by exposure, development, and etching processes, exposing portions of the upper surfaces of the first conductive layer 100, the first second conductive layer 1011, the second second conductive layer 1021, and the third second conductive layer 1031 located on both sides of the capacitor unit.

[0084] Please continue to refer to Figure 1In the prior art, the even-numbered second conductive layer and the odd-numbered second conductive layer are exposed on both sides of the capacitor unit, that is, the second second conductive layer 1021, the first second conductive layer 1011, and the first conductive layer 100 are all exposed on both sides of the capacitor unit. Therefore, when forming the contact conductive structure connecting the second second conductive layer 1021 and the first conductive layer 100, care must be taken to avoid a short circuit with the first second conductive layer 1011, which could cause capacitor failure. Similarly, when forming the contact conductive structure connecting the third second conductive layer 1031 and the first second conductive layer 1011, care must be taken to avoid a short circuit with the second second conductive layer 1021 and the first conductive layer 100, which could cause capacitor failure. Accordingly, when forming the metal silicide, it is also easy to cause capacitor failure due to short circuits between the third second conductive layer 1031 and the second second conductive layer 1021, between the second second conductive layer 1021 and the first second conductive layer 1011, and between the first second conductive layer 1011 and the first conductive layer 100. Therefore, the existing technology will have higher process requirements and is more likely to cause device reliability problems due to incorrect connections.

[0085] As can be seen from the above, in the prior art, at least three photomasks are required to form a three-layer capacitor, and the process requirements are very high. Misconnection of the conductive structure must not occur, otherwise the capacitor will fail and cause defects.

[0086] Accordingly, in the prior art, to form a four-layer capacitor, four photomasks are required, and four photolithography and etching processes are performed to expose the conductive layers serving as the capacitor plates for wiring, wherein each photolithography and etching process exposes one conductive layer. Similarly, to form a five-layer capacitor, five photomasks are required, and five photolithography and etching processes are performed to expose the conductive layers serving as the capacitor plates for wiring, wherein each photolithography and etching process exposes one conductive layer. That is, to form an M-layer capacitor, M photomasks are required, and M photolithography and etching processes are performed to expose the conductive layers serving as the capacitor plates for wiring, wherein each photolithography and etching process exposes only one layer of the second conductive layer.

[0087] The capacitors and their manufacturing methods provided in the embodiments of the present application overcome this limitation of the prior art. For example, in a seven-layer capacitor unit, only four photomasks are required to complete the lead-out of each conductive layer. This means that to form an N-layer (N is a natural number greater than 2) capacitor, only N-1 photomasks are required at most. This means that compared to the prior art, at least one photomask can be reduced to expose each conductive layer that serves as the capacitor plate, thereby facilitating lead-out wiring and forming a corresponding N-layer capacitor.

[0088] Furthermore, in the capacitor and its manufacturing method provided in the embodiments of the present application, all even-numbered second conductive layers are led out on the first side of the capacitor unit, and all odd-numbered second conductive layers are led out on the second side of the capacitor unit. This successfully avoids the capacitor failure problem caused by short circuits that can occur when the odd-numbered and even-numbered second conductive layers are led out on the same side, thereby resolving the device reliability issues that are common in the prior art and reducing the manufacturing process requirements for the device.

[0089] The core idea of ​​the present invention is to provide a capacitor, which includes: a substrate having a groove formed therein; and a capacitor unit located on the substrate, wherein the capacitor unit includes a first conductive layer and N capacitor layers located on the first conductive layer, the first conductive layer covering the inner wall of the groove and extending to cover the surface of the substrate, each capacitor layer including a stacked dielectric layer and a second conductive layer, and N is a natural number greater than 1; wherein the capacitor unit has a first side and a second side opposite to each other, and on the first side of the capacitor unit, the second conductive layer located in the even-numbered layer is aligned with the sidewall of the second conductive layer located in the next odd-numbered layer, and exposes a portion of the upper surface of the second conductive layer located in the next even-numbered layer; and / or, on the second side of the capacitor unit, the second conductive layer located in the odd-numbered layer is aligned with the sidewall of the second conductive layer located in the next even-numbered layer, and exposes a portion of the upper surface of the second conductive layer located in the next odd-numbered layer. This can reduce the use of masks, thereby reducing manufacturing costs; or, without reducing the number of masks, more layers of the second conductive layer can be exposed to lead out wiring, thereby increasing the capacitance density of the capacitor; or, the process requirements for the subsequently formed contact conductive structure and / or metal silicide can be reduced, thereby improving the reliability of the capacitor.

[0090] Accordingly, the manufacturing method of the capacitor includes: providing a substrate having a groove formed therein; forming a first conductive layer on the substrate, the first conductive layer covering the inner wall of the groove and extending to cover the surface of the substrate; sequentially forming N capacitor layers on the first conductive layer, each capacitor layer including a stacked dielectric layer and a second conductive layer, wherein N is a natural number greater than 1; and using a mask combination to form an exposure area, and performing an etching process on the N capacitor layers in the exposure area to form a capacitor unit, wherein the capacitor unit has a first side and a second side relative to each other, and on the first side of the capacitor unit, the second conductive layer located in the even layer is aligned with the side wall of the second conductive layer located in the next odd layer, and a portion of the upper surface of the second conductive layer located in the next even layer is exposed; and / or, on the second side of the capacitor unit, the second conductive layer located in the odd layer is aligned with the side wall of the second conductive layer located in the next even layer, and a portion of the upper surface of the second conductive layer located in the next odd layer is exposed.

[0091] Specifically, using a mask combination to form an exposure area, and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit at least includes: using a first mask to form a first exposure area, the first exposure area exposes a portion of the surface of the first capacitor layer in the N-layer capacitor layer, and etching and removing the first capacitor layer exposed in the first exposure area, or etching and removing the first capacitor layer and the capacitor layer of the next layer exposed in the first exposure area; and using a second mask to form a second exposure area, the second exposure area exposes a portion of the surface of the second capacitor layer in the N-layer capacitor layer, and etching and removing the second capacitor layer and the capacitor layer of the next layer exposed in the second exposure area, or etching and removing the second capacitor layer exposed in the second exposure area; wherein, the first exposure area is first formed by using the first mask and then the second exposure area is formed by using the second mask, or the second exposure area is first formed by using the second mask and then the first exposure area is formed by using the first mask; the first capacitor layer and the second capacitor layer are the same capacitor layer or different capacitor layers.

[0092] Among them, the first light mask can be, for example, the first light mask executed, the second light mask can be, for example, the second light mask executed, the first capacitor layer and the second capacitor layer can be, for example, both the Nth capacitor layer; the first light mask can also be, for example, the second light mask executed, the second light mask can be, for example, the first light mask executed, the second capacitor layer can be, for example, the Nth capacitor layer, and the first capacitor layer can be, for example, the N-1th capacitor layer.

[0093] Furthermore, the second exposure area can be located within the range of the first exposure area, or the second exposure area can be located outside the range of the first exposure area (that is, here, the projection of the second exposure area on the corresponding substrate is separated from the projection of the first exposure area on the corresponding substrate, or there is no overlap).

[0094] Furthermore, using a mask combination to form an exposure area, and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit also includes: using the first mask to form a third exposure area, the third exposure area exposes a portion of the surface of the third capacitor layer in the N-layer capacitor layer, and etching away the third capacitor layer exposed in the third exposure area, or etching away the third capacitor layer exposed in the third exposure area and the capacitor layer of the next layer; wherein the third capacitor layer and the first capacitor layer are different layers of capacitor layers; or using the second mask to form a fourth exposure area, the fourth exposure area exposes a portion of the surface of the fourth capacitor layer in the N-layer capacitor layer, and etching away the exposed portion of the fourth capacitor layer in the fourth exposure area. The fourth capacitor layer and the capacitor layer of the next layer are exposed by etching, or the fourth capacitor layer exposed in the fourth exposure area is removed; wherein the fourth capacitor layer and the second capacitor layer are different capacitor layers; or, a fifth exposure area and a sixth exposure area are formed by using a third mask, the fifth exposure area exposes a portion of the surface of the fifth capacitor layer in the N-layer capacitor layer, and the fifth capacitor layer and the capacitor layer of the next layer exposed in the fifth exposure area are removed by etching, the sixth exposure area exposes a portion of the surface of the sixth capacitor layer in the N-layer capacitor layer, and the sixth capacitor layer and the capacitor layer of the next layer exposed in the sixth exposure area are removed by etching; wherein the fifth capacitor layer and the sixth capacitor layer are different capacitor layers.

[0095] It is easy to know that according to the capacitor and the manufacturing method thereof provided in the embodiments of the present invention, there are many variations when forming the capacitor unit, which are only illustrative in the embodiments of the present application.

[0096] Next, the structure of the capacitor and the method for forming the capacitor in the embodiment of the present application will be described in detail through specific embodiments.

[0097] [Example 1]

[0098] Please refer to Figures 2 to 13 , which is a schematic diagram of the structure of a device formed by executing the method for manufacturing a capacitor according to the first embodiment of the present invention. In the first embodiment, two photomasks are used to expose the conductive layers serving as capacitor plates, thereby forming a three-layer capacitor.

[0099] First, please refer to Figure 2, providing a substrate 200, wherein the material of the substrate 200 may include ceramic, glass, plastic or semiconductor silicon wafer, etc. In the embodiment of the present application, the substrate 200 is a semiconductor silicon wafer. The thickness of the substrate 200 is between 100μm and 5000μm, that is, its thickness is greater than or equal to 100μm and less than or equal to 5000μm. In the embodiment of the present application, the thickness of the substrate 200 is 700μm. Furthermore, a groove 201 is formed in the substrate 200. In the embodiment of the present application, a groove 201 is formed in the substrate 200.

[0100] Specifically, a flat substrate 200 may be provided first. The flat substrate 200 may be made of a semiconductor silicon wafer. Then, a patterned photoresist layer or a patterned hard mask layer ( Figure 2 (not shown) to expose a portion of the surface of the flat substrate 200; then, an etching process is performed on the exposed flat substrate 200 to form a groove 201 in the substrate 200. After the groove 201 is formed, the patterned photoresist layer or the patterned hard mask layer is removed.

[0101] The groove 201 extends from the surface of the substrate 200 into the substrate 200. In the embodiment of the present application, the groove 201 is a deep groove. Preferably, its depth is between 2μm and 40μm, that is, its depth is greater than or equal to 2μm and less than or equal to 40μm. The aspect ratio of the groove 201 can be 20:1 to 100:1. Furthermore, the width of the groove 201 is between 0.1μm and 2μm, that is, its width is greater than or equal to 0.1μm and less than or equal to 2μm. Here, the width of the groove 201 refers to the dimension in the left-right direction in the figure; the length of the groove 201 is between 1μm and 10μm, that is, its length is greater than or equal to 1μm and less than or equal to 10μm. Here, the length of the groove 201 refers to the dimension in the front-back direction perpendicular to the paper surface in the figure.

[0102] Please refer to Figure 3In the embodiment of the present application, an ion implantation process is then performed on the substrate 200 to form a first conductive layer 202 (named as the first conductive layer herein for the convenience of describing the conductive layer) on the surface of the substrate 200, and the first conductive layer 202 covers the inner wall of the groove 201 and the surface of the substrate 200. That is, here, the material of the first conductive layer 202 is doped single crystal silicon or polycrystalline silicon. In other embodiments of the present application, the first conductive layer 202 can also be formed by depositing a conductive material, and the first conductive layer 202 covers the inner wall of the groove 201 and the surface of the substrate 200. The material of the first conductive layer 202 can be a metal-containing material such as aluminum, copper, gold, silver, titanium nitride, tantalum, tantalum nitride, titanium nitride, titanium aluminum nitride (TiAlN), etc.

[0103] Next, please refer to Figure 4 , N capacitor layers are sequentially formed on the first conductive layer 202. In the embodiment of the present application, three capacitor layers are formed on the first conductive layer 202, and each capacitor layer includes a stacked dielectric layer and a second conductive layer (for ease of description of the conductive layer, referred to herein as the second conductive layer), that is, each capacitor layer includes a dielectric layer and a second conductive layer located on the dielectric layer.

[0104] like Figure 4 As shown, a first capacitor layer 203 covering the first conductive layer 202 is formed from bottom to top, the first capacitor layer 203 includes a first dielectric layer 2030 covering the first conductive layer 202 and a first second conductive layer 2031 covering the first dielectric layer 2030; a second capacitor layer 204 covering the first capacitor layer 203, the second capacitor layer 204 includes a second dielectric layer 2040 covering the first second conductive layer 2031 and a second second conductive layer 2041 covering the second dielectric layer 2040; a third capacitor layer 205 covering the second capacitor layer 204, the third capacitor layer 205 includes a third dielectric layer 2050 covering the second second conductive layer 2041 and a third second conductive layer 2051 covering the third dielectric layer 2050. Preferably, the third second conductive layer 2051, the second second conductive layer 2041 and the first second conductive layer 2031 have the same thickness, and the third dielectric layer 2050, the second dielectric layer 2040 and the first dielectric layer 2030 have the same thickness.

[0105] In an embodiment of the present application, the material of the dielectric layer may be one or more of silicon dioxide, silicon nitride and high-K materials. The high-K material may include, for example, hafnium oxide, zirconium oxide, zinc oxide and / or barium titanate. The material of the second conductive layer may be metal-containing materials such as aluminum, copper, gold, silver, titanium nitride, tantalum, tantalum nitride, titanium nitride, and titanium aluminum nitride (TiAlN). Among them, the materials of the third dielectric layer 2050, the second dielectric layer 2040 and the first dielectric layer 2030 may be the same or different (including partially different or completely different), and the third second conductive layer 2051, the second second conductive layer 2041 and the first second conductive layer 2031 may also be the same or different (including partially different or completely different). Preferably, the thickness of the dielectric layer is between The dielectric layer can be formed by an oxidation process or a deposition process. For example, the first dielectric layer 2030 can be formed by performing an oxidation process on a portion of the thickness of the first conductive layer 202. Next, the first second conductive layer 2031 can be formed by depositing a conductive material; or, the first second conductive layer 2031 can be formed by depositing doped or undoped single crystal silicon or polycrystalline silicon. Next, the second dielectric layer 2040 can be formed by depositing silicon dioxide, silicon nitride, or a high-K material; or, the second dielectric layer 2040 can be formed by performing an oxidation process on a portion of the thickness of the first second conductive layer 2031. Similarly, the second capacitor layer 204 and the third capacitor layer 205 are formed.

[0106] Next, a first mask layer 206 is formed on the surface of the third second conductive layer 2051. The first mask layer 206 may be a photoresist layer or a hard mask layer. Figure 5 As shown, a first photomask 20 is used to perform a photolithography process on the first mask layer 206, which includes performing an exposure and development process on the first mask layer 206 to form a first exposure area 207, where a first opening is formed in the first mask layer 206, and the first exposure area 207 exposes a portion of the third second conductive layer 2051, that is, exposes a portion of the third capacitor layer 205.

[0107] like Figure 6 As shown, in the embodiment of the present application, the third second conductive layer 2051 and the third dielectric layer 2050 are then etched from the surface of the exposed third second conductive layer 2051, i.e., the third capacitor layer 205 is etched to expose the second second conductive layer 2041. Specifically, a wet or dry etching process can be used to etch the third capacitor layer 205. Next, the first mask layer 206 is removed.

[0108] A second mask layer 208 is formed, and the second mask layer 208 covers the exposed surfaces of the third second conductive layer 2051 and the second second conductive layer 2041. The second mask layer 208 can be a photoresist layer or a hard mask layer, such as Figure 7 As shown. Next, a photolithography process is performed on the second mask layer 208 using a second photomask 21 to form a second exposure area 209. The second exposure area 209 exposes a portion of the third second conductive layer 2051. In the embodiment of the present application, the second photomask 21 is also used to form a third exposure area 210. The third exposure area 210 exposes a portion of the second second conductive layer 2041. In the embodiment of the present application, the third exposure area 210 is located within the first exposure area 207, while the second exposure area 209 is located outside the first exposure area 207.

[0109] Please refer to Figure 8 The third second conductive layer 2051, the third dielectric layer 2050, the second second conductive layer 2041, and the second dielectric layer 2040 are etched from the surface of the third second conductive layer 2051 exposed from the second exposure area 209 to expose the first second conductive layer 2031. In the embodiment of the present application, the second second conductive layer 2041, the second dielectric layer 2040, the first second conductive layer 2031, and the first dielectric layer 2030 are also etched from the surface of the second second conductive layer 2041 exposed from the third exposure area 210 to expose the first conductive layer 202. Next, the second mask layer 208 is removed.

[0110] At this point, by using two photomasks, the first conductive layer 202, the first second conductive layer 2031, the second second conductive layer 2041, and the third second conductive layer 2051 are exposed, forming a capacitor unit. The capacitor unit includes the stacked first conductive layer 202, the first dielectric layer 2030, the first second conductive layer 2031, the second dielectric layer 2040, the second second conductive layer 2041, the third dielectric layer 2050, and the third second conductive layer 2051.

[0111] On the first side of the capacitor unit, the sidewalls of the second-layer second conductive layer 2041 and the first-layer second conductive layer 2031 are aligned, and portions of the surface of the second-layer second conductive layer 2041 and the first conductive layer 202 are exposed. On the second side of the capacitor unit, the sidewalls of the third-layer second conductive layer 2051 and the second-layer second conductive layer 2041 are aligned, and portions of the surface of the first-layer second conductive layer 2031 are exposed. The first side and the second side are opposite sides of the capacitor unit, and can also be referred to as one side and the other side. At the same time, the entire upper surface of the third-layer second conductive layer 2051 is exposed.

[0112] On the first side of the capacitor unit, the side walls of the second-layer second conductive layer 2041 and the first-layer second conductive layer 2031 are aligned, which means that the side walls of the second-layer second conductive layer 2041 and the first-layer second conductive layer 2031 are basically flush; similarly, on the second side of the capacitor unit, the side walls of the third-layer second conductive layer 2051 and the second-layer second conductive layer 2041 are aligned, which means that the side walls of the third-layer second conductive layer 2051 and the second-layer second conductive layer 2041 are basically flush.

[0113] like Figure 9 As shown, in the embodiment of the present application, a first protective structure 211 and a second protective structure 212 are then formed. The first protective structure 211 covers the sidewall of at least one layer of the second conductive layer on the first side of the capacitor unit, and the second protective structure 212 covers the sidewall of at least one layer of the second conductive layer on the second side of the capacitor unit. Specifically, a dielectric material layer ( Figure 9 (not shown in the figure), the dielectric material layer can be a single-layer structure or a multi-layer structure, for example, a two-layer stacked structure, which can include silicon oxide and silicon nitride located on the silicon oxide; then, the dielectric material layer is etched to form the first protective structure 211 and the second protective structure 212.

[0114] Specifically, in the embodiment of the present application, the first protective structure 211 includes two parts, namely a first protective structure portion and a second protective structure portion. The first protective structure portion covers the sidewalls of the third second conductive layer 2051 and the third dielectric layer 2050. The second protective structure portion covers the sidewalls of the second second conductive layer 2041 and the first second conductive layer 2031, and also covers the sidewalls of the second dielectric layer 2040 and the first dielectric layer 2030. The second protective structure 212 covers the sidewalls of the third second conductive layer 2051 and the second second conductive layer 2041, and also covers the sidewalls of the third dielectric layer 2050 and the second dielectric layer 2040.

[0115] The first protection structure 211 and the second protection structure 212 can protect the sidewalls of each second conductive layer to prevent undesired connection in the subsequent process of forming a contact conductive structure, thereby improving the reliability of the formed capacitor.

[0116] Please refer to Figure 10 In the embodiment of the present application, a metal silicide layer 213 is then formed. The metal silicide layer 213 covers the exposed surfaces of the conductive layers, including the exposed surfaces of the first conductive layer 202, the first second conductive layer 2031, the second second conductive layer 2041, and the third second conductive layer 2051, to improve the electrical connection performance between each of the conductive layers and the subsequently formed contact conductive structure. In other embodiments of the present application, the metal silicide layer may not be formed, and the contact conductive structure may be directly formed.

[0117] Next, please refer to Figure 11 , forming at least one first contact conductive structure 214 and at least one second contact conductive structure 215, wherein the first contact conductive structure 214 is connected to the capacitor unit at the first side of the capacitor unit, and the second contact conductive structure 215 is connected to the capacitor unit at the second side of the capacitor unit. Specifically, a first dielectric layer 216 may be formed first; then, the first dielectric layer 216 may be etched to form a plurality of first openings ( Figure 11 (not shown), the plurality of first openings expose a portion of the surface of each of the conductive layers; the plurality of first openings are filled to form the first contact conductive structure 214 and the second contact conductive structure 215. In the embodiment of the present application, two first contact conductive structures 214 and two second contact conductive structures 215 are formed.

[0118] In which, the first contact conductive structure 214 is connected to the spaced conductive layers on the first side of the capacitor unit, specifically, connected to each of the second conductive layers located in the even layers, and here the first contact conductive structure 214 connects the first conductive layer 202 and the second-layer second conductive layer 2041; the second contact conductive structure 215 is connected to the spaced conductive layers on the second side of the capacitor unit, specifically, connected to each of the second conductive layers located in the odd layers, and here the second contact conductive structure 215 connects the first-layer second conductive layer 2031 and the third-layer second conductive layer 2051.

[0119] In the embodiment of the present application, each conductive layer is connected to a different contact conductive structure. Figure 11The first conductive layer 202 is connected to a first contact conductive structure 214 , the second conductive layer 2041 is connected to another first contact conductive structure 214 , the first conductive layer 2031 is connected to a second contact conductive structure 215 , and the third conductive layer 2051 is connected to another second contact conductive structure 215 .

[0120] like Figure 12 As shown, then, at least one wiring layer 217 is formed, each of the wiring layers 217 includes at least one first wiring structure 2170 and at least one second wiring structure 2171, and the first contact conductive structure 214 and the second contact conductive structure 215 are connected to the first wiring structure 2170 and the second wiring structure 2171 respectively. Here, a wiring layer 217 is formed, the wiring layer 217 includes a first wiring structure 2170 and a second wiring structure 2171, the two first contact conductive structures 214 are connected to the first wiring structure 2170, and the two second contact conductive structures 215 are connected to the second wiring structure 2171. Specifically, a wiring material layer ( Figure 12 (not shown), the material of the wiring material layer is, for example, metal. Then, the wiring material layer is etched to form the wiring layer 217.

[0121] Please refer to Figure 13 In an embodiment of the present application, the capacitor manufacturing method further includes: forming at least one first extraction electrode 2180 and at least one second extraction electrode 2181, wherein the wiring structure in the wiring layer 217 located on the top layer is connected to the extraction electrode 218. Here, a first extraction electrode 2180 and a second extraction electrode 2181 are formed, wherein the first wiring structure 2170 is connected to the first extraction electrode 2180, and the second wiring structure 2171 is connected to the second extraction electrode 2181. The extraction electrode 218 is, for example, a copper pillar.

[0122] Specifically, a second dielectric layer 219 can be formed first, covering the wiring layer 217. Next, an etching process is performed on the second dielectric layer 219 to form a plurality of second openings (not shown) in the second dielectric layer 219. The plurality of second openings expose portions of the wiring layer 217, specifically, portions of the first wiring structure 2170 and the second wiring structure 2171. Subsequently, the plurality of second openings can be filled with electroplated metal material, such as electroplated copper, to form the extraction electrodes 218.

[0123] In summary, in this embodiment, two photomasks are used to expose the conductive layers serving as capacitor plates to form a three-layer capacitor, thereby reducing the number of photomasks used and thus lowering manufacturing costs.

[0124] Furthermore, the first conductive layer 202 and the second conductive layer 2041 exposed on the first side of the capacitor unit are both connected to the same contact conductive structure (here, the first contact conductive structure 214), and are connected to the same electrode through the contact conductive structure, the wiring layer 217, and the lead-out electrode 218, that is, they are simultaneously connected to the power electrode or the ground electrode; while the first conductive layer 202 and the second conductive layer 2041 are connected to different contact conductive structures and ultimately connected to different electrodes. The first conductive layer 2031 is only exposed on the second side of the capacitor unit. That is, except for the topmost second conductive layer, the exposed surfaces of the conductive layers used to connect to different electrodes are separated, and the conductive layers exposed on the same side of the capacitor unit are all used to connect to the same electrode. Therefore, when forming the contact conductive structure, there is no need to pay special attention to avoid connection with other conductive layers, thereby reducing the process requirements for the contact conductive structure and improving the reliability of the capacitor.

[0125] In addition, since the side walls of the second second conductive layer 2041, the second dielectric layer 2040, the first second conductive layer 2031, and the first dielectric layer 2030 are aligned on the first side of the capacitor unit, and the side walls of the third second conductive layer 2051, the third dielectric layer 2050, the second second conductive layer 2041, and the second dielectric layer 2040 are aligned on the second side of the capacitor unit, the length of the second conductive layer can be reduced by reducing the exposed upper surface of the second conductive layer, thereby reducing the area occupied by the capacitor unit in the substrate. Accordingly, on a substrate of the same area, more capacitor units can be prepared and more / larger capacitors can be formed, thereby improving the utilization rate of the substrate and reducing manufacturing costs.

[0126] [Example 2]

[0127] In this second embodiment, two photomasks are also used to expose the conductive layers that serve as capacitor plates, thereby forming a three-layer capacitor. This differs from the first embodiment in that the conductive layers are exposed using different steps / sequences, as described below. Furthermore, the same / similar parts of this second embodiment to those of the first embodiment are not further described; reference is made to the description of the first embodiment for the corresponding parts.

[0128] Specifically, such as Figure 14 As shown, after forming the first conductive layer 220 and the three capacitor layers, a first exposure area ( Figure 14). The three-layer capacitor layer includes a stacked first capacitor layer 221, a second capacitor layer 222, and a third capacitor layer 223, each capacitor layer including a stacked dielectric layer and a second conductive layer, that is, the three-layer capacitor layer includes a stacked first dielectric layer 2210, a first second conductive layer 2211, a second dielectric layer 2220, a second second conductive layer 2221, a third dielectric layer 2230, and a third second conductive layer 2231. The first exposure area exposes the third capacitor layer 223, specifically, exposes a portion of the surface of the third second conductive layer 2231 (i.e., the topmost conductive layer here). Then, the third second conductive layer 2231, the third dielectric layer 2230, the second second conductive layer 2221, and the second dielectric layer 2220 are etched from the exposed third second conductive layer 2231 to expose the first second conductive layer 2211.

[0129] Here, for forming a capacitor including one capacitance unit, the first mask 22 has one mask area, thereby forming a first exposure area.

[0130] Please continue to refer to Figure 14 Then, a second mask 23 is used to form two exposure areas (not shown in the figure), which are the second exposure area and the third exposure area. The second exposure area exposes a portion of the third second conductive layer 2231, and the third exposure area exposes a portion of the first second conductive layer 2211. Figure 14 As shown, a mask area of ​​the second mask 23 (ie Figure 14 The mask area on the left side of the middle) is within the range of the mask area of ​​the first mask 22, and another mask area of ​​the second mask 23 (ie Figure 14 The mask area on the right side of the middle mask is outside the range of the mask area of ​​the first mask 22.

[0131] Next, etching can be performed downward from the exposed third-second conductive layer 2231 and the exposed first-second conductive layer 2211. Here, the third-second conductive layer 2231 and the third dielectric layer 2230 are etched downward from the exposed third-second conductive layer 2231, exposing a portion of the second-second conductive layer 2221. Simultaneously, the first-second conductive layer 2211 and the first dielectric layer 2210 are etched downward from the exposed first-second conductive layer 2211, exposing the first conductive layer 220. This results in the third-second conductive layer 2231, the third dielectric layer 2230, the second-second conductive layer 2221, and the second dielectric layer 2220, all of which have aligned sidewalls. That is, here, on the second side of the capacitor unit, the sidewalls of the third second conductive layer 2231 in the odd-numbered layer are aligned with the sidewalls of the second second conductive layer 2221 in the even-numbered layer below it, and a portion of the upper surface of the first second conductive layer 2211 in the odd-numbered layer below it is exposed. It should be noted that the first side and the second side of the capacitor unit are merely for convenience of description. As the two opposite sides of the capacitor unit, they can be respectively referred to as the first side and the second side, or as the second side and the first side, or as one side and the other side.

[0132] like Figure 14 As shown, a three-layer capacitor unit is formed by two photomasks. The three-layer capacitor unit includes: a first conductive layer 220, a first dielectric layer 2210, a first second conductive layer 2211, a second dielectric layer 2220, a second second conductive layer 2221, a third dielectric layer 2230, and a third second conductive layer 2231 stacked in sequence. On one side of the three-layer capacitor unit, the upper surface of the first second conductive layer 2211 is exposed, and the upper surface of the first conductive layer 220 on this side is also exposed; on the other side of the three-layer contact conductive structure, the upper surface of the second second conductive layer 2221 is exposed; and at the same time, the entire upper surface of the third second conductive layer 2231 is exposed. Then, a contact conductive structure is formed to connect the exposed third second conductive layer 2231, the second second conductive layer 2221, the first second conductive layer 2211, and the first conductive layer 220, thereby leading out the first conductive layer 220, the first second conductive layer 2211, the second second conductive layer 2221, and the third second conductive layer 2231. Thus, a three-layer capacitor can be obtained using two photomasks, thereby saving the use of photomasks and reducing manufacturing costs.

[0133] Please continue to refer to Figure 14In the second embodiment of the present application, the first second conductive layer 2211 and the first conductive layer 220 exposed on the second side of the capacitor unit are respectively connected to different contact conductive structures, wherein the first second conductive layer 2211 is connected to the second contact conductive structure 2241, and the first conductive layer 220 is connected to the first contact conductive structure 2240. Furthermore, the third second conductive layer 2231 is connected to the second contact conductive structure 2241, and the second second conductive layer 2221 is connected to the first contact conductive structure 2240. Therefore, compared to the first embodiment, in the second embodiment, when forming the contact conductive structure, it is necessary to avoid the connection between the first second conductive layer 2211 and the first conductive layer 220. That is, the capacitor in the first embodiment has lower process requirements for the contact conductive structure than the capacitor in the second embodiment, and the capacitor has higher reliability.

[0134] In addition, it should be noted that Figure 14 In the capacitor unit, the second contact conductive structure 2241 is located behind the first contact conductive structure 2240 in the vertical direction of the paper, and is therefore blocked by the first contact conductive structure 2240. Figure 14 , the second contact conductive structure 2241 is shown on another capacitor unit at the left side of the figure.

[0135] [Example 3]

[0136] In this third embodiment, three photomasks are used to expose the conductive layers serving as capacitor plates to form a four-layer capacitor. The steps of providing a substrate, forming a first conductive layer, and forming N capacitor layers (four capacitor layers in this example) are similar to those in the first embodiment, and reference may be made to the first embodiment accordingly. This third embodiment will not be described in detail. This third embodiment primarily describes the process of using three photomasks to form exposure areas, exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, and the fourth second conductive layer, respectively. The details are described below.

[0137] For details, please refer to Figure 15 After forming the first conductive layer 230 and the four capacitor layers, a first exposure area ( Figure 15(not shown). The four capacitor layers include a stacked first capacitor layer 231, a second capacitor layer 232, a third capacitor layer 233, and a fourth capacitor layer 234. Each capacitor layer includes a stacked dielectric layer and a second conductive layer. That is, the four capacitor layers include a stacked first dielectric layer 2310, a first second conductive layer 2311, a second dielectric layer 2320, a second second conductive layer 2321, a third dielectric layer 2330, a third second conductive layer 2331, a fourth dielectric layer 2340, and a fourth second conductive layer 2341. The first exposure area exposes the fourth capacitor layer 234, specifically, exposes a portion of the surface of the fourth second conductive layer 2341 (i.e., the topmost conductive layer here). Next, the fourth second conductive layer 2341 , the fourth dielectric layer 2340 , the third second conductive layer 2331 and the third dielectric layer 2330 are etched from the exposed fourth second conductive layer 2341 to expose a portion of the second second conductive layer 2321 .

[0138] Here, for forming a capacitor including one capacitance unit, the first mask 24 has one mask area, thereby forming a first exposure area.

[0139] Next, a second photomask 25 is used to form a second exposure area, which exposes a portion of the fourth second conductive layer 2341. Then, the fourth second conductive layer 2341 and the fourth dielectric layer 2340 are etched from the exposed fourth second conductive layer 2341 to expose a portion of the third second conductive layer 2331. Here, the mask area of ​​the second photomask 25 is outside the mask area of ​​the first photomask 24, and accordingly, the second exposure area is outside the range of the first exposure area.

[0140] Please continue to refer to Figure 15 , using the third mask 26 to form two exposure areas, which are the third exposure area and the fourth exposure area, wherein the third exposure area exposes a portion of the second second conductive layer 2321, and the fourth exposure area exposes a portion of the third second conductive layer 2231. Further, as Figure 15 As shown, a mask area of ​​the third mask 26 (ie Figure 15 The mask area on the left in the middle) is located within the range of the mask area of ​​the first mask 24, and accordingly, the third exposure area is located within the range of the first exposure area; another mask area of ​​the third mask 26 (ie Figure 15 The mask area on the right side of the middle is located within the range of the mask area of ​​the second mask 25, and correspondingly, the fourth exposure area is located within the range of the second exposure area.

[0141] Then, the second-layer second conductive layer 2321, the second-layer dielectric layer 2320, the first-layer second conductive layer 2311 and the first-layer dielectric layer 2310 can be etched from the exposed partial surface of the second-layer second conductive layer 2321 to align the side walls of the second-layer second conductive layer 2321, the second-layer dielectric layer 2330, the first-layer second conductive layer 2311 and the first-layer dielectric layer 2310, and expose the first conductive layer 230; at the same time, the third-layer second conductive layer 2331, the third-layer dielectric layer 2330, the second-layer second conductive layer 2321 and the second-layer dielectric layer 2320 can be etched from the exposed partial surface of the third-layer second conductive layer 2331 to obtain the third-layer second conductive layer 2331, the third-layer dielectric layer 2330, the second-layer second conductive layer 2321 and the second-layer dielectric layer 2320 with aligned side walls, and expose the first-layer second conductive layer 2311.

[0142] like Figure 15 As shown, a four-layer capacitor unit is formed by three photomasks. The four-layer capacitor unit includes: a first conductive layer 230, a first dielectric layer 2310, a first second conductive layer 2311, a second dielectric layer 2320, a second second conductive layer 2321, a third dielectric layer 2330, a third second conductive layer 2331, a fourth dielectric layer 2340, and a fourth second conductive layer 2341 stacked in sequence. On one side of the four-layer capacitor unit, the upper surface of the second second conductive layer 2321 is exposed, and the upper surface of the first conductive layer 230 on this side is also exposed; on the other side of the four-layer capacitor unit, the upper surfaces of the first second conductive layer 2311 and the third second conductive layer 2331 are exposed; and at the same time, the upper surface of the fourth second conductive layer 2341 is exposed. Then, a contact conductive structure can be formed to connect the exposed fourth-layer second conductive layer 2341, the third-layer second conductive layer 2331, the second-layer second conductive layer 2321, the first-layer second conductive layer 2311 and the first conductive layer 230, thereby leading out the first conductive layer 230, the first-layer second conductive layer 2311, the second-layer second conductive layer 2321, the third-layer second conductive layer 2331 and the fourth-layer second conductive layer 2341.

[0143] Please continue to refer to Figure 15In the third embodiment, on the first side of the capacitor unit, each of the second conductive layers located in the even-numbered layers and the first conductive layer 230 are connected to the first contact conductive structure 2350. On the second side of the capacitor unit, each of the second conductive layers located in the odd-numbered layers is connected to the second contact conductive structure 2351. Therefore, the four-layer capacitor obtained by this embodiment of the application also does not need to pay special attention to avoiding connection with other conductive layers, thereby reducing the process requirements for the contact conductive structure and improving the reliability of the capacitor.

[0144] As can be seen, compared to the prior art, the capacitor provided by this embodiment can reduce the use of at least one photomask, resulting in a four-layer capacitor structure. Furthermore, the substrate area occupied by the capacitor units can be reduced. On a substrate of the same area, more capacitor units can be fabricated, resulting in more / larger capacitors, thereby increasing substrate utilization and reducing manufacturing costs.

[0145] [Example 4]

[0146] The fourth embodiment also uses three photomasks to expose the conductive layers that serve as capacitor plates, thereby forming a four-layer capacitor. The steps of providing a substrate, forming a first conductive layer, and forming N capacitor layers (here, four capacitor layers) are similar to those of the first embodiment, and can be referred to in the first embodiment accordingly. The fourth embodiment will not be described in detail. The fourth embodiment mainly describes the process of using three photomasks to form an exposure area, respectively exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, and the fourth second conductive layer. The difference from the third embodiment is that each conductive layer is exposed through different steps / sequences. Please refer to the following description for details.

[0147] For details, please refer to Figure 16 After forming the first conductive layer 240 and the four capacitor layers, a first exposure area ( Figure 16). The four capacitor layers include a stacked first capacitor layer 241, a second capacitor layer 242, a third capacitor layer 243, and a fourth capacitor layer 244, each capacitor layer including a stacked dielectric layer and a second conductive layer, that is, the four capacitor layers include a stacked first dielectric layer 2410, a first second conductive layer 2411, a second dielectric layer 2420, a second second conductive layer 2421, a third dielectric layer 2430, a third second conductive layer 2431, a fourth dielectric layer 2440, and a fourth second conductive layer 2441. The first exposure area exposes the fourth capacitor layer 244, specifically, exposes a portion of the surface of the fourth second conductive layer 2441 (i.e., the topmost conductive layer here). Then, the fourth second conductive layer 2441 and the fourth dielectric layer 2440 are etched from the exposed fourth second conductive layer 2441, and the third second conductive layer 2431 is exposed.

[0148] Here, for forming a capacitor including one capacitance unit, the first mask 27 has one mask area, thereby forming a first exposure area.

[0149] Next, a second exposure area is formed using a second mask 28, and the second exposure area exposes a portion of the fourth second conductive layer 2441. Then, the fourth second conductive layer 2441, the fourth dielectric layer 2440, the third second conductive layer 2431 and the third dielectric layer 2430 are etched from the exposed fourth second conductive layer 2441 to expose a portion of the second second conductive layer 2421.

[0150] Please continue to refer to Figure 16 , using the third mask 29 to form two exposure areas, which are the third exposure area and the fourth exposure area, wherein the third exposure area exposes a portion of the third second conductive layer 2431, and the fourth exposure area exposes a portion of the second second conductive layer 2421. Further, as Figure 16 As shown, a mask area of ​​the third mask 29 (ie Figure 16 The mask area on the right side of the middle) is located within the range of the mask area of ​​the first mask 27. Correspondingly, the third exposure area is located within the range of the first exposure area; another mask area of ​​the third mask 29 (i.e. Figure 16 The mask area on the left in the middle is located within the range of the second mask 28. Correspondingly, the fourth exposure area is located within the range of the second exposure area; the mask area position of the second mask 28 is located outside the range of the mask area of ​​the first mask 27.

[0151] Then, the third-layer second conductive layer 2431, the third-layer dielectric layer 2430, the second-layer second conductive layer 2421 and the second-layer dielectric layer 2420 can be etched from the exposed partial surface of the third-layer second conductive layer 2431 to align the side walls of the third-layer second conductive layer 2431, the third-layer dielectric layer 2430, the second-layer second conductive layer 2421 and the second-layer dielectric layer 2420, and expose the first-layer second conductive layer 2411; at the same time, the second-layer second conductive layer 2421, the second-layer dielectric layer 2420, the first-layer second conductive layer 2411 and the first-layer dielectric layer 2410 are etched from the exposed partial surface of the second-layer second conductive layer 2421 to obtain the second-layer second conductive layer 2421, the second-layer dielectric layer 2420, the first-layer second conductive layer 2411 and the first-layer dielectric layer 2410 with aligned side walls, and expose the first conductive layer 240.

[0152] like Figure 16 As shown, a four-layer capacitor unit is formed by the same three masking steps. The four-layer capacitor unit includes: a first conductive layer 240, a first dielectric layer 2410, a first second conductive layer 2411, a second dielectric layer 2420, a second second conductive layer 2421, a third dielectric layer 2430, a third second conductive layer 2431, a fourth dielectric layer 2440, and a fourth second conductive layer 2441 stacked in sequence. On one side of the four-layer capacitor unit, the top surfaces of the first second conductive layer 2411 and the third second conductive layer 2431 are exposed; on the other side of the four-layer capacitor unit, the top surface of the second second conductive layer 2421 is exposed, and the top surface of the first conductive layer 240 on this side is also exposed; and at the same time, the top surface of the fourth second conductive layer 2441 is exposed. Next, a contact conductive structure is formed to connect the exposed fourth second conductive layer 2441, third second conductive layer 2431, second second conductive layer 2421, first second conductive layer 2411, and first conductive layer 240, thereby leading out the first conductive layer 240, first second conductive layer 2411, second second conductive layer 2421, third second conductive layer 2431, and fourth second conductive layer 2441. Thus, a four-layer capacitor can be obtained using three photomasks, reducing the process requirements for the contact conductive structure and improving the reliability of the capacitor.

[0153] [Example 5]

[0154] The fifth embodiment also uses three photomasks to expose the conductive layers that serve as capacitor plates, thereby forming a four-layer capacitor. The steps of providing a substrate, forming a first conductive layer, and forming N-layer capacitor layers (here, four-layer capacitor layers) are similar to those of the first embodiment, and can be referred to in the first embodiment accordingly. The fifth embodiment will not be repeated. The fifth embodiment mainly describes the process of using three photomasks to form an exposure area, respectively exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, and the fourth second conductive layer. The difference between the third embodiment and the fourth embodiment is that the conductive layers are exposed through different steps / sequences. Please refer to the following description for details.

[0155] For details, please refer to Figure 17 After forming the first conductive layer 250 and the four capacitor layers, a first exposure area ( Figure 17 ). The four capacitor layers include a stacked first capacitor layer 251, a second capacitor layer 252, a third capacitor layer 253, and a fourth capacitor layer 254, each capacitor layer including a stacked dielectric layer and a second conductive layer, that is, the four capacitor layers include a stacked first dielectric layer 2510, a first second conductive layer 2511, a second dielectric layer 2520, a second second conductive layer 2521, a third dielectric layer 2530, a third second conductive layer 2531, a fourth dielectric layer 2540, and a fourth second conductive layer 2541. The first exposure area exposes the fourth capacitor layer 254, specifically, exposes a portion of the surface of the fourth second conductive layer 2541 (i.e., the topmost conductive layer here). Then, the fourth second conductive layer 2541 and the fourth dielectric layer 2540 are etched from the exposed fourth second conductive layer 2541, and the third second conductive layer 2531 is exposed.

[0156] Here, for forming a capacitor including one capacitor unit, the first mask 30 has one mask area, thereby forming a first exposure area.

[0157] Next, a second photomask 31 is used to form two exposure areas, which are the second exposure area and the third exposure area. The second exposure area exposes a portion of the fourth second conductive layer 2541, while the third exposure area exposes a portion of the third second conductive layer 2531. Figure 17 As shown, a mask area of ​​the second mask 31 (ie Figure 17 The mask area on the right side of the middle) is located within the range of the mask area of ​​the first mask 30, and accordingly, the third exposure area is located within the range of the first exposure area; another mask area of ​​the second mask 31 (i.e. Figure 17 The mask area on the left side of the mask is located outside the range of the mask area of ​​the first mask 30.

[0158] Next, the fourth second conductive layer 2541, the fourth dielectric layer 2540, the third second conductive layer 2531 and the third dielectric layer 2530 are etched from the exposed surface of the fourth second conductive layer 2541 so that one side of the fourth second conductive layer 2541, the fourth dielectric layer 2540, the third second conductive layer 2531 and the third dielectric layer 2530 are aligned and the second second conductive layer 2521 is exposed; at the same time, the third second conductive layer 2531, the third dielectric layer 2530, the second second conductive layer 2521 and the second dielectric layer 2520 are etched from the exposed surface of the third second conductive layer 2531 so that one side wall of the third second conductive layer 2531, the third dielectric layer 2530, the second second conductive layer 2521 and the second dielectric layer 2520 are aligned and the first second conductive layer 2511 is exposed.

[0159] Please continue to refer to Figure 17 Then, a third mask 32 is used to form a fourth exposure area, wherein the fourth exposure area exposes a portion of the second conductive layer 2521. Figure 17 As shown, the mask area of ​​the third mask 32 is located in a mask area of ​​the second mask 31 (here Figure 17 Correspondingly, the fourth exposure area is located within the range of the second exposure area.

[0160] Then, the second-layer second conductive layer 2521, the second-layer dielectric layer 2520, the first-layer second conductive layer 2511 and the first-layer dielectric layer 2510 can be etched from the exposed portion of the surface of the second-layer second conductive layer 2521 to obtain the second-layer second conductive layer 2521, the second-layer dielectric layer 2520, the first-layer second conductive layer 2511 and the first-layer dielectric layer 2510 with one side wall aligned, and expose the first conductive layer 250.

[0161] like Figure 17As shown, a four-layer capacitor unit is formed by the same three masking steps. The four-layer capacitor unit includes: a first conductive layer 250, a first dielectric layer 2510, a first second conductive layer 2511, a second dielectric layer 2520, a second second conductive layer 2521, a third dielectric layer 2530, a third second conductive layer 2531, a fourth dielectric layer 2540, and a fourth second conductive layer 2541 stacked in sequence. On one side of the four-layer capacitor unit, the upper surfaces of the first second conductive layer 2511 and the third second conductive layer 2531 are exposed; on the other side of the four-layer capacitor unit, the upper surface of the second second conductive layer 2521 is exposed, and the upper surface of the first conductive layer 250 on this side is also exposed; at the same time, the upper surface of the fourth second conductive layer 2541 is exposed. Next, a contact conductive structure is formed to connect the exposed fourth second conductive layer 2541, third second conductive layer 2531, second second conductive layer 2521, first second conductive layer 2511, and first conductive layer 250, thereby leading out the first conductive layer 250, first second conductive layer 2511, second second conductive layer 2521, third second conductive layer 2531, and fourth second conductive layer 2541. Thus, a four-layer capacitor can be obtained using three photomasks, which reduces the process requirements for the contact conductive structure and improves the reliability of the capacitor.

[0162] [Example 6]

[0163] This embodiment six also uses three photomasks to expose the conductive layers that serve as capacitor plates, thereby forming a four-layer capacitor. Among them, the steps of providing a substrate, forming a first conductive layer, and forming N-layer capacitor layers (here, four-layer capacitor layers) are similar to those in embodiment one, and can be referred to embodiment one accordingly. This embodiment six will not be repeated. This embodiment six mainly describes the process of using three photomasks to form an exposure area, respectively exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, and the fourth second conductive layer. The difference between this embodiment six and embodiment three, embodiment four, and embodiment five is that each conductive layer is exposed through different steps / sequences. Please refer to the following description for details.

[0164] Please refer to Figure 18 Specifically, after forming the first conductive layer 260 and the four capacitor layers, a first exposure area ( Figure 18(not shown in the figure). The four capacitor layers include a stacked first capacitor layer 261, a second capacitor layer 262, a third capacitor layer 263, and a fourth capacitor layer 264. Each capacitor layer includes a stacked dielectric layer and a second conductive layer. That is, the four capacitor layers include a stacked first dielectric layer 2610, a first second conductive layer 2611, a second dielectric layer 2620, a second second conductive layer 2621, a third dielectric layer 2630, a third second conductive layer 2631, a fourth dielectric layer 2640, and a fourth second conductive layer 2641. The first exposure area exposes the fourth capacitor layer 264, specifically, exposes a portion of the surface of the fourth second conductive layer 2641 (i.e., the topmost conductive layer here). Then, the fourth second conductive layer 2641, the fourth dielectric layer 2640, the third second conductive layer 2631, the third dielectric layer 2630, the second second conductive layer 2621, the second dielectric layer 2620, the first second conductive layer 2611 and the first dielectric layer 2610 are etched from the exposed fourth second conductive layer 2641 to expose the first conductive layer 260.

[0165] Here, for forming a capacitor including one capacitance unit, the first mask 33 has one mask area, thereby forming a first exposure area.

[0166] Next, a second exposure area is formed using a second mask 34, which exposes a portion of the fourth second conductive layer 2641. Then, the fourth second conductive layer 2641 and the fourth dielectric layer 2640 are etched from the exposed fourth second conductive layer 2641 to expose a portion of the third second conductive layer 2631.

[0167] Please continue to refer to Figure 18 , using the third mask 35 to form two exposure areas, which are the third exposure area and the fourth exposure area, wherein the third exposure area exposes a portion of the fourth second conductive layer 2641, and the fourth exposure area exposes a portion of the third second conductive layer 2631. Further, as Figure 18 As shown, a mask area of ​​the third mask 35 (ie Figure 18 The mask area on the left in the middle) is located within the range of the mask area of ​​the first mask 33, or more precisely, the mask area of ​​the first mask 33 is located within a mask area of ​​the third mask (i.e. Figure 18 The third mask 35 of another mask area (ie Figure 18 The mask area on the right side of the middle mask is located within the range of the mask area of ​​the second mask 34, and the range of the mask area of ​​the second mask 34 and the range of the mask area of ​​the first mask 33 are separated from each other.

[0168] Then, the fourth-layer second conductive layer 2641, the third-layer dielectric layer 2640, the third-layer second conductive layer 2631 and the third-layer dielectric layer 2630 can be etched from the exposed portion of the fourth-layer second conductive layer 2641 to expose the second-layer second conductive layer 2621, and align one side wall of the fourth-layer second conductive layer 2641, the fourth-layer dielectric layer 2640, the third-layer second conductive layer 2631 and the third-layer dielectric layer 2630; at the same time, the third-layer second conductive layer 2631, the third-layer dielectric layer 2630, the second-layer second conductive layer 2621 and the second-layer dielectric layer 2620 can be etched from the exposed portion of the third-layer second conductive layer 2631 to expose the first-layer second conductive layer 2611, and align one side wall of the third-layer second conductive layer 2631, the third-layer dielectric layer 2630, the second-layer second conductive layer 2621 and the second-layer dielectric layer 2620.

[0169] like Figure 18 As shown, a four-layer capacitor unit is formed by the same three masking steps. The four-layer capacitor unit includes: a first conductive layer 260, a first dielectric layer 2610, a first second conductive layer 2611, a second dielectric layer 2620, a second second conductive layer 2621, a third dielectric layer 2630, a third second conductive layer 2631, a fourth dielectric layer 2640, and a fourth second conductive layer 2641 stacked in sequence. On one side of the four-layer capacitor unit, the top surfaces of the first second conductive layer 2611 and the third second conductive layer 2631 are exposed; on the other side of the four-layer capacitor unit, the top surface of the second second conductive layer 2621 is exposed, and the top surface of the first conductive layer 260 on this side is also exposed; and at the same time, the top surface of the fourth second conductive layer 2641 is exposed. Next, a contact conductive structure is formed to connect the exposed fourth second conductive layer 2641, third second conductive layer 2631, second second conductive layer 2621, first second conductive layer 2611, and first conductive layer 260, thereby leading out the first conductive layer 260, first second conductive layer 2611, second second conductive layer 2621, third second conductive layer 2631, and fourth second conductive layer 2641. Thus, a four-layer capacitor can be obtained using three photomasks, which reduces the process requirements for the contact conductive structure and improves the reliability of the capacitor.

[0170] [Example 7]

[0171] In this embodiment 7, three photomasks are used to expose the conductive layers serving as capacitor plates, thereby forming a five-layer capacitor. The steps of providing a substrate, forming a first conductive layer, and forming N capacitor layers (here, five capacitor layers) are similar to those in the first embodiment, and reference may be made to the first embodiment accordingly. This embodiment 7 will not be described in detail. This embodiment 7 primarily describes the process of using three photomasks to form exposure areas, exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, the fourth second conductive layer, and the fifth second conductive layer, respectively. For details, refer to the following description.

[0172] For details, please refer to Figure 19 After forming the first conductive layer 270 and the five capacitor layers, a first exposure area ( Figure 19 ). The five capacitor layers include a stacked first capacitor layer 271, a second capacitor layer 272, a third capacitor layer 273, a fourth capacitor layer 274, and a fifth capacitor layer 275. Each capacitor layer includes a stacked dielectric layer and a second conductive layer. That is, the five capacitor layers include a stacked first dielectric layer 2710, a first second conductive layer 2711, a second dielectric layer 2720, a second second conductive layer 2721, a third dielectric layer 2730, a third second conductive layer 2731, a fourth dielectric layer 2740, a fourth second conductive layer 2741, a fifth dielectric layer 2750, and a fifth second conductive layer 2751. The first exposure area exposes the fifth capacitor layer 275, specifically, exposes a portion of the surface of the fifth second conductive layer 2751 (i.e., the topmost conductive layer here). Next, the fifth second conductive layer 2751 and the fifth dielectric layer 2750 are etched from the exposed fifth second conductive layer 2751 to expose a portion of the fourth second conductive layer 2741 .

[0173] Here, for forming a capacitor including one capacitor unit, the first photomask has a photomask region, thereby forming a first exposure region.

[0174] Next, a second photomask 37 is used to form two exposure areas, which are the second exposure area and the third exposure area. The second exposure area exposes a portion of the fifth second conductive layer 2751, while the third exposure area exposes a portion of the fourth second conductive layer 2741. Figure 19 As shown, a mask area of ​​the second mask 37 (ie Figure 19 The mask area on the left in the middle) is located within the range of the mask area of ​​the first mask 36, and correspondingly, the third exposure area is located within the range of the first exposure area; another mask area of ​​the second mask 37 (i.e. Figure 19 The mask area on the right side of the middle is outside the range of the mask area of ​​the first mask 36.

[0175] Then, the fifth second conductive layer 2751, the fifth dielectric layer 2750, the fourth second conductive layer 2741 and the fourth dielectric layer 2740 can be etched from the partial surface of the exposed fifth second conductive layer 2751 to align the side walls of the fifth second conductive layer 2751, the fifth dielectric layer 2750, the fourth second conductive layer 2741 and the fourth dielectric layer 2740, and expose the third second conductive layer 2731. At the same time, the fourth second conductive layer 2741, the fourth dielectric layer 2740, the third second conductive layer 2731 and the third dielectric layer 2730 are etched from the partial surface of the exposed fourth second conductive layer 2741 to form the fourth second conductive layer 2741, the fourth dielectric layer 2740, the third second conductive layer 2731 and the third dielectric layer 2730 with aligned side walls, and expose a portion of the second second conductive layer 2721.

[0176] Please continue to refer to Figure 19 Then, a third mask 38 is used to form two exposure areas, which are the fourth exposure area and the fifth exposure area. The fourth exposure area exposes a portion of the third second conductive layer 2731, and the fifth exposure area exposes a portion of the second second conductive layer 2721. Figure 19 As shown, a mask area of ​​the third mask 38 (ie Figure 19 The mask area on the right side of the middle) is located in a mask area of ​​the second mask 37 (ie Figure 19 The fourth exposure area is located within the range of the second exposure area; the other mask area of ​​the third mask 38 (ie Figure 19 The mask area on the left side of the middle) is located in another mask area of ​​the second mask 37 (i.e. Figure 19 Correspondingly, the fifth exposure area is located within the range of the third exposure area. Here, the fifth exposure area is also located within the range of the first exposure area.

[0177] Then, the third-layer second conductive layer 2731, the third-layer dielectric layer 2730, the second-layer second conductive layer 2721 and the second-layer dielectric layer 2720 can be etched from the partial surface of the exposed third-layer second conductive layer 2731 to expose the first-layer second conductive layer 2711 and align the side walls of the third-layer second conductive layer 2731, the third-layer dielectric layer 2730, the second-layer second conductive layer 2721 and the second-layer dielectric layer 2720; at the same time, the second-layer second conductive layer 2721, the second-layer dielectric layer 2720, the first-layer second conductive layer 2711 and the first-layer dielectric layer 2710 are etched from the partial surface of the exposed second-layer second conductive layer 2721 to form the second-layer second conductive layer 2721, the second-layer dielectric layer 2720, the first-layer second conductive layer 2711 and the first-layer dielectric layer 2710 with aligned side walls and expose the first conductive layer 270.

[0178] Thus, a five-layer capacitor unit is formed by the same three masking steps. The five-layer capacitor unit includes: a first conductive layer 270, a first dielectric layer 2710, a first second conductive layer 2711, a second dielectric layer 2720, a second second conductive layer 2721, a third dielectric layer 2730, a third second conductive layer 2731, a fourth dielectric layer 2740, a fourth second conductive layer 2741, a fifth dielectric layer 2750, and a fifth second conductive layer 2751, stacked in sequence. On one side of the five-layer capacitor unit, the upper surfaces of the second second conductive layer 2721 and the fourth second conductive layer 2741 are exposed, and the upper surface of the first conductive layer 270 is also exposed on this side. On the other side of the five-layer capacitor unit, the upper surfaces of the first second conductive layer 2711 and the third second conductive layer 2731 are exposed. At the same time, the upper surface of the fifth second conductive layer 2751 is exposed. Then, a contact conductive structure can be formed to connect the exposed fifth-layer second conductive layer 2751, the fourth-layer second conductive layer 2741, the third-layer second conductive layer 2731, the second-layer second conductive layer 2721, the first-layer second conductive layer 2711 and the first conductive layer 270, thereby leading out the first conductive layer 270, the first-layer second conductive layer 2711, the second-layer second conductive layer 2721, the third-layer second conductive layer 2731, the fourth-layer second conductive layer 2741 and the fifth-layer second conductive layer 2751.

[0179] Thus, compared with the prior art, at least two photomasks can be reduced, and a five-layer capacitor can be obtained. Similarly, the five-layer capacitor obtained by the embodiment of the present application does not need to pay special attention to avoid connection with other conductive layers, thereby reducing the process requirements for contacting the conductive structure and improving the reliability of the capacitor. Furthermore, the area of ​​the substrate occupied by the capacitor unit can be reduced. On a substrate of the same area, more capacitor units can be prepared and more / larger capacitors can be formed, thereby increasing the utilization rate of the substrate and reducing manufacturing costs.

[0180] [Embodiment 8]

[0181] In the eighth embodiment, four photomasks are used to expose the conductive layers serving as capacitor plates, thereby forming a seven-layer capacitor. The steps of providing a substrate, forming a first conductive layer, and forming N capacitor layers (seven capacitor layers in this example) are similar to those in the first embodiment, and reference may be made to the first embodiment accordingly. This eighth embodiment will not be described in detail. This eighth embodiment mainly describes the process of using four photomasks to form an exposure area, exposing the first conductive layer, the first second conductive layer, the second second conductive layer, the third second conductive layer, the fourth second conductive layer, the fifth second conductive layer, the sixth second conductive layer, and the seventh second conductive layer, respectively. For details, refer to the following description.

[0182] For details, please refer to Figure 20 After forming the first conductive layer 280 and the seven capacitor layers, a first exposure area ( Figure 20 ). The seven capacitor layers include a stacked first capacitor layer 281, a second capacitor layer 282, a third capacitor layer 283, a fourth capacitor layer 284, a fifth capacitor layer 285, a sixth capacitor layer 286, and a seventh capacitor layer 287. Each capacitor layer includes a stacked dielectric layer and a second conductive layer. That is, the seven capacitor layers include a stacked first dielectric layer 2810, a first second conductive layer 2811, a second dielectric layer 2820, a second second conductive layer 2821, a third dielectric layer 2830, a third second conductive layer 2831, a fourth dielectric layer 2840, a fourth second conductive layer 2841, a fifth dielectric layer 2850, a fifth second conductive layer 2851, a sixth dielectric layer 2860, a sixth second conductive layer 2861, a seventh dielectric layer 2870, and a seventh second conductive layer 2871. The first exposure region exposes the seventh capacitor layer 287, specifically, a portion of the surface of the seventh second conductive layer 2871 (i.e., the uppermost conductive layer in this embodiment). Next, the seventh second conductive layer 2871 and the seventh dielectric layer 2870 are etched from the exposed seventh second conductive layer 2871, exposing a portion of the sixth second conductive layer 2861.

[0183] Here, for forming a capacitor including one capacitor unit, the first photomask has a photomask region, thereby forming a first exposure region.

[0184] Next, a second photomask 40 is used to form two exposure areas, which are the second exposure area and the third exposure area. The second exposure area exposes a portion of the seventh second conductive layer 2871, while the third exposure area exposes a portion of the sixth second conductive layer 2861. Figure 20 As shown, a mask area of ​​the second mask 40 (ie Figure 20 The mask area on the left side of the middle) is within the range of the mask area of ​​the first mask 39, and another mask area of ​​the second mask 40 (ie Figure 20 The mask area on the right side of the middle is located outside the range of the mask area of ​​the first mask 39.

[0185] Then, the seventh-layer second conductive layer 2871, the seventh-layer dielectric layer 2870, the sixth-layer second conductive layer 2861 and the sixth-layer dielectric layer 2860 can be etched from the exposed portion of the seventh-layer second conductive layer 2871 to align the side walls of the seventh-layer second conductive layer 2871, the seventh-layer dielectric layer 2870, the sixth-layer second conductive layer 2861 and the sixth-layer dielectric layer 2860, and expose the fifth-layer second conductive layer 2851. At the same time, the sixth-layer second conductive layer 2861, the sixth-layer dielectric layer 2860, the fifth-layer second conductive layer 2851 and the fifth-layer dielectric layer 2850 are etched from the exposed portion of the sixth-layer second conductive layer 2861 to form the sixth-layer second conductive layer 2861, the sixth-layer dielectric layer 2860, the fifth-layer second conductive layer 2851 and the fifth-layer dielectric layer 2850 with aligned side walls, and expose a portion of the fourth-layer second conductive layer 2841.

[0186] Please continue to refer to Figure 20 Then, a third mask 41 is used to form two exposure areas, which are the fourth exposure area and the fifth exposure area. The fourth exposure area exposes a portion of the fifth second conductive layer 2851, while the fifth exposure area exposes a portion of the fourth second conductive layer 2841. Figure 20 As shown, a mask area of ​​the third mask 41 (ie Figure 20 The mask area on the left side of the middle) is located in a mask area of ​​the second mask 40 (ie Figure 20 Within the range of the mask area on the left side of the middle), another mask area of ​​the third mask 41 (ie Figure 20 The mask area on the right side of the middle) is located in another mask area of ​​the second mask 40 (ie Figure 20 within the range of the mask area on the left side of the center).

[0187] Then, the fifth second conductive layer 2851, the fifth dielectric layer 2850, the fourth second conductive layer 2841 and the fourth dielectric layer 2840 can be etched from the exposed portion of the fifth second conductive layer 2851 to expose the third second conductive layer 2831 and align one side wall of the fifth second conductive layer 2851, the fifth dielectric layer 2850, the fourth second conductive layer 2841 and the fourth dielectric layer 2840; at the same time, the fourth second conductive layer 2841, the fourth dielectric layer 2840, the third second conductive layer 2831 and the third dielectric layer 2830 can be etched from the exposed portion of the fourth second conductive layer 2841 to form a fourth second conductive layer 2841, the fourth dielectric layer 2840, the third second conductive layer 2831 and the third dielectric layer 2830 with aligned one side wall and expose the second second conductive layer 2821.

[0188] Please continue to refer to Figure 20 Then, a fourth mask 42 is used to form two exposure areas, which are the sixth exposure area and the seventh exposure area. The sixth exposure area exposes a portion of the third second conductive layer 2831, and the seventh exposure area exposes a portion of the second second conductive layer 2821. Figure 20 As shown, a mask area of ​​the fourth mask 42 (ie Figure 20 The mask area on the left side of the middle) is located in a mask area of ​​the third mask 41 (ie Figure 20 Within the range of the mask area on the left side of the middle), another mask area of ​​the fourth mask 42 (ie Figure 20 The mask area on the right side of the middle) is located in another mask area of ​​the third mask 41 (ie Figure 20 within the range of the mask area on the right side of the center).

[0189] Then, the third-layer second conductive layer 2831, the third-layer dielectric layer 2830, the second-layer second conductive layer 2821 and the second-layer dielectric layer 2820 can be etched from the exposed portion of the third-layer second conductive layer 2831 to expose the first-layer conductive layer 2811 and align one side wall of the three-layer second conductive layer 2831, the third-layer dielectric layer 2830, the second-layer second conductive layer 2821 and the second-layer dielectric layer 2820; at the same time, the second-layer second conductive layer 2821, the second-layer dielectric layer 2820, the first-layer second conductive layer 2811 and the first-layer dielectric layer 2810 are etched from the exposed portion of the second-layer second conductive layer 2821 to form a second-layer second conductive layer 2821, the second-layer dielectric layer 2820, the first-layer second conductive layer 2811 and the first-layer dielectric layer 2810 with aligned one side wall and expose the first conductive layer 280.

[0190] Thus, a seven-layer capacitor unit can be formed through four photomasks, and the seven-layer capacitor unit includes: a first conductive layer 280, a first dielectric layer 2810, a first second conductive layer 2811, a second dielectric layer 2820, a second second conductive layer 2821, a third dielectric layer 2830, a third second conductive layer 2831, a fourth dielectric layer 2840, a fourth second conductive layer 2841, a fifth dielectric layer 2850, a fifth second conductive layer 2851, a sixth dielectric layer 2860, a sixth second conductive layer 2861, a seventh dielectric layer 2870 and a seventh second conductive layer 2871 stacked in sequence. Among them, on one side of the capacitor unit of the seven-layer structure, the upper surfaces of the second-layer second conductive layer 2821, the fourth-layer second conductive layer 2841 and the sixth-layer second conductive layer 2861 are exposed, and the upper surface of the first conductive layer 280 on this side is also exposed; on the other side of the capacitor unit of the seven-layer structure, the upper surfaces of the first-layer second conductive layer 2811, the third-layer second conductive layer 2831 and the fifth-layer second conductive layer 2851 are exposed; at the same time, the upper surface of the seventh-layer second conductive layer 2871 is exposed. Then, a contact conductive structure can be formed to connect the exposed seventh-layer second conductive layer 2871, the sixth-layer second conductive layer 2861, the fifth-layer second conductive layer 2851, the fourth-layer second conductive layer 2841, the third-layer second conductive layer 2831, the second-layer second conductive layer 2821, the first-layer second conductive layer 2811 and the first conductive layer 280, thereby leading out the first conductive layer 280, the first-layer second conductive layer 2811, the second-layer second conductive layer 2821, the third-layer second conductive layer 2831, the fourth-layer second conductive layer 2841, the fifth-layer second conductive layer 2851, the sixth-layer second conductive layer 2861 and the seventh-layer second conductive layer 2871.

[0191] Thus, compared with the prior art, at least three photomasks can be reduced, and a seven-layer capacitor can be obtained. Similarly, the seven-layer capacitor obtained by the embodiment of the present application does not need to pay special attention to avoid connection with other conductive layers, thereby reducing the process requirements for contacting the conductive structure and improving the reliability of the capacitor. Furthermore, the area of ​​the substrate occupied by the capacitor unit can be reduced. On a substrate of the same area, more capacitor units can be prepared and more / larger capacitors can be formed, thereby increasing the utilization rate of the substrate and reducing manufacturing costs.

[0192] [Example 9]

[0193] In the ninth embodiment, two photomasks are also used to expose the conductive layers serving as capacitor plates, thereby forming a three-layer capacitor. The steps of providing a substrate, forming a first conductive layer, forming three capacitor layers, forming an exposure area using a combination of photomasks, and etching the three capacitor layers in the exposure area to form a three-layer capacitor unit are similar to those in the first embodiment, and reference may be made to the first embodiment accordingly. This ninth embodiment will not be further described.

[0194] Please refer to Figure 21 , and compared with the reference example 1 Figure 13 The main difference between the ninth embodiment and the first embodiment is that, for one capacitor unit, only one first contact conductive structure 290 and one second contact conductive structure 291 are formed to connect the first conductive layer 292, the first second conductive layer 293, the second second conductive layer 294 and the third second conductive layer 295.

[0195] Furthermore, the first contact conductive structure 290 and the second contact conductive structure 291 are formed simultaneously with the first wiring layer (ie, the bottom wiring layer). Figure 21 Specifically, after forming the capacitor unit, a metal material layer (not shown) is then formed. The metal material layer fills the openings exposing the first conductive layer 292, the first second conductive layer 293, and the second second conductive layer 294, and extends to cover the surface of the third second conductive layer 295. Next, the metal material layer is etched using a single photomask to simultaneously form the first contact conductive structure 290, the second contact conductive structure 291, and the first wiring layer 296. Compared to a process in which the first wiring layer and the contact conductive structure are formed separately, this process can save one photomask, thereby further reducing manufacturing costs.

[0196] In the embodiment of the present application, a second wiring layer 297 (also referred to as the top wiring layer in the embodiment of the present application) is further formed. Figure 21 As shown, specifically, a dielectric layer 298 is first formed, and the dielectric layer 298 covers the first wiring layer 296; then, an etching process is performed on the dielectric layer 298 using a mask to form a plurality of openings in the dielectric layer 298 that expose the first wiring layer 296 (not shown in the figure); then, a metal material layer is formed to fill the openings and extend to cover the dielectric layer 298; and the metal material layer is etched to form a second wiring layer 297.

[0197] The second wiring layer 297 is connected to the first wiring layer 296. Specifically, the first wiring structure 2970 in the second wiring layer 297 is connected to the first wiring structure 2960 in the first wiring layer 296, and the second wiring structure 2971 in the second wiring layer 297 is connected to the second wiring structure 2961 in the first wiring layer 296. Meanwhile, the first wiring structure 2970 and the second wiring structure 2971 in the second wiring layer 297 are not connected to each other, the first wiring structure 2960 and the second wiring structure 2961 in the first wiring layer 296 are not connected to each other, and the first wiring structure 2970 and the second wiring structure 2961, as well as the second wiring structure 2971 and the first wiring structure 2960, are also not connected to each other.

[0198] In the embodiment of the present application, a first extraction electrode 2990 and a second extraction electrode 2991 are then formed on the second wiring layer 297, wherein the first extraction electrode 2990 is connected to the first wiring structure 2970 in the second wiring layer 297, and the second extraction electrode 2991 is connected to the second wiring structure 2971 in the second wiring layer 297. Furthermore, in the embodiment of the present application, two first extraction electrodes 2990 are connected to the same first wiring structure 2970, and two second extraction electrodes 2991 are connected to the same second wiring structure 2971, thereby achieving connections to electrodes with different voltages.

[0199] [Example 10]

[0200] In the tenth embodiment, two photomasks are also used to expose the conductive layers serving as capacitor plates, thereby forming a three-layer capacitor.

[0201] Please refer to Figure 22 , and compared with the reference example 1 Figure 2 and Figure 13 The main difference between this embodiment 10 and the embodiment 1 is that a substrate 300 is provided, wherein a plurality of grooves 301 are formed in the substrate 300, and a capacitor unit 302 is formed to cover at least two of the grooves 301. Thus, the capacitance density of the formed capacitor can be increased without increasing the planar area of ​​the substrate occupied by the capacitor unit. The steps of forming the following steps after providing the substrate 300 are basically similar to those of the embodiment 1, including forming a first conductive layer, forming three capacitor layers, and forming an exposure area using a mask combination, and performing an etching process on the three capacitor layers in the exposure area to form the three-layer capacitor unit. The steps are similar to those of the embodiment 1, and can be referred to in the embodiment 1 accordingly. This embodiment 10 will not be repeated.

[0202] [Example 11]

[0203] In the eleventh embodiment, two photomasks are also used to expose the conductive layers serving as capacitor plates, thereby forming a three-layer capacitor.

[0204] Please refer to Figure 23 , and compared with the reference example 1 Figure 2 and Figure 13 , and can also be compared with the reference embodiment 10 Figure 22 The capacitor unit formed in the eleventh embodiment is the same as that in the first embodiment, except that a plurality of capacitor units 400 are formed simultaneously in the eleventh embodiment. The plurality of capacitor units 400 are formed simultaneously through the same process steps. Figure 23 Only three capacitor units 400 are schematically shown, namely the first capacitor unit 4000, the second capacitor unit 4001, and the third capacitor unit 4002. In practice, far more than three capacitor units 400 can be formed. The specific formation method of the capacitor unit can be referred to in Example 1, and will not be repeated in this Example 11.

[0205] Furthermore, in the embodiment of the present application, the first conductive layer 401 of the second capacitor unit 4001 is integrally connected to the first conductive layer 401 of the first capacitor unit 4000, and is disconnected from the first conductive layer 401 of the third capacitor unit 4002. Thus, multiple capacitor units can be formed into different capacitor unit combinations, thereby forming capacitors with diversified structures to meet different needs. In addition, the connection relationship between each capacitor unit can also be adjusted by the wiring layer 402, thereby forming different capacitor unit combinations. The number of layers of the wiring layer 402 is preferably multiple layers ( Figure 23 Only one layer is shown as an example).

[0206] For further information, please refer to Figure 24 , which is a circuit diagram of a three-layer capacitor according to an embodiment of the present invention. Figure 24In the capacitor circuit structure diagram shown, the capacitor includes four three-layer capacitor units, namely, a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, and a fourth capacitor unit C4, that is, formed by a first conductive layer, a first second conductive layer, a second second conductive layer, and a third second conductive layer. The three-layer capacitor unit formed by the four conductive layers includes four plates, namely, a first plate t1, a second plate t2, a third plate t3, and a fourth plate t4. Further, the four capacitor units form different capacitor unit combinations by connecting to different electrodes. Specifically, the first capacitor unit C1 and the second capacitor unit C2 are both connected to the (power) electrode P1 and the (ground) electrode G1, the third capacitor unit C3 is connected to the (power) electrode P2 and the (ground) electrode G1, and the fourth capacitor unit is connected to the (power) electrode P3 and the (ground) electrode G2. This allows for convenient combination of different capacitor capacitances to form the desired capacitor.

[0207] In summary, it can be seen that in the capacitor and the manufacturing method thereof provided in the embodiment of the present invention, the capacitor unit has a first side and a second side relative to each other, and on the first side of the capacitor unit, the side wall of the second conductive layer located in the even layer is aligned with the side wall of the second conductive layer located in the next odd layer, and a portion of the upper surface of the second conductive layer located in the next even layer is exposed; and / or, on the second side of the capacitor unit, the side wall of the second conductive layer located in the odd layer is aligned with the side wall of the second conductive layer located in the next even layer, and a portion of the upper surface of the second conductive layer located in the next odd layer is exposed, thereby reducing the use of masks and thus reducing manufacturing costs, or more layers of conductive layers can be exposed to lead out wiring without reducing the number of masks, thereby improving the capacitance density of the capacitor.

[0208] Furthermore, the conductive layers exposed on one side of the capacitor unit can be connected to the same contact conductive structure to connect to the same electrode, such as a power electrode or a ground electrode; the conductive layers exposed on the other side of the capacitor unit can also be connected to the same contact conductive structure to connect to the same electrode. That is, except for the top second conductive layer, the exposed surfaces of the conductive layers used to connect to different electrodes are separated, and the conductive layers exposed on the same side of the capacitor unit are all used to connect to the same electrode. Therefore, when forming the contact conductive structure, there is no need to pay special attention to avoid connection with other conductive layers, thereby reducing the process requirements for the contact conductive structure and improving the reliability of the capacitor.

[0209] Furthermore, since at least one second conductive layer on at least one side of the capacitor unit is aligned with the sidewalls of the second conductive layer of the first layer below it, the exposed upper surface of the second conductive layer is reduced, thereby reducing the length of the second conductive layer, thereby reducing the area occupied by the capacitor unit. Accordingly, on a substrate of the same area, more capacitor units can be prepared and more / larger capacitors can be formed, thereby improving the utilization rate of the substrate and reducing manufacturing costs.

[0210] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a capacitor, characterized in that: The method for manufacturing the capacitor includes: providing a substrate having a groove formed therein; forming a first conductive layer on the substrate, wherein the first conductive layer covers the inner wall of the groove and extends to cover the surface of the substrate; forming N capacitor layers on the first conductive layer in sequence, each capacitor layer including a stacked dielectric layer and a second conductive layer, wherein N is a natural number greater than 1; and An exposure area is formed using a mask combination, and an etching process is performed on the N-layer capacitor layer in the exposure area to form a capacitor unit, wherein the capacitor unit has a first side and a second side opposite to each other, and on the first side of the capacitor unit, the sidewalls of the second conductive layer in the even-numbered layer are aligned with the sidewalls of the second conductive layer in the next odd-numbered layer, and a portion of the upper surface of the second conductive layer in the next even-numbered layer is exposed; and / or, on the second side of the capacitor unit, the sidewalls of the second conductive layer in the odd-numbered layer are aligned with the sidewalls of the second conductive layer in the next even-numbered layer, and a portion of the upper surface of the second conductive layer in the next odd-numbered layer is exposed; The step of forming an exposure area by using a mask combination and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit at least includes: Using a first photomask to form a first exposure area, the first exposure area exposing a portion of the surface of the first capacitor layer in the N-layer capacitor layer, and etching away the first capacitor layer exposed in the first exposure area, or etching away the first capacitor layer and the capacitor layer next to it exposed in the first exposure area; and Using a second photomask to form a second exposure area, the second exposure area exposing a portion of the surface of the second capacitor layer in the N-layer capacitor layer, and etching away the second capacitor layer and the capacitor layer next to it exposed in the second exposure area, or etching away the second capacitor layer exposed in the second exposure area; wherein, the first exposure region is formed by using the first photomask first and then the second exposure region is formed by using the second photomask; or, the second exposure region is formed by using the second photomask first and then the first exposure region is formed by using the first photomask; The first capacitor layer and the second capacitor layer are the same capacitor layer or different capacitor layers.

2. The method for manufacturing a capacitor according to claim 1, wherein: The method further comprises: forming an exposure area by using a mask combination, and performing an etching process on the N-layer capacitor layer in the exposure area to form a capacitor unit; Using the first photomask to form a third exposure area, the third exposure area exposing a portion of the surface of the third capacitor layer in the N-layer capacitor layer, and etching and removing the third capacitor layer exposed in the third exposure area, or etching and removing the third capacitor layer and the capacitor layer next to it exposed in the third exposure area; wherein the third capacitor layer and the first capacitor layer are different capacitor layers; Alternatively, a fourth exposure area is formed using the second photomask, wherein the fourth exposure area exposes a portion of the surface of the fourth capacitor layer in the N-layer capacitor layer, and the fourth capacitor layer and the capacitor layer below it exposed in the fourth exposure area are etched away, or the fourth capacitor layer exposed in the fourth exposure area is etched away; wherein the fourth capacitor layer and the second capacitor layer are different capacitor layers; Alternatively, a third photomask is used to form a fifth exposure area and a sixth exposure area, wherein the fifth exposure area exposes a portion of the surface of the fifth capacitor layer in the N-layer capacitor layer, and the fifth capacitor layer and the capacitor layer of the next layer exposed in the fifth exposure area are etched away, and the sixth exposure area exposes a portion of the surface of the sixth capacitor layer in the N-layer capacitor layer, and the sixth capacitor layer and the capacitor layer of the next layer exposed in the sixth exposure area are etched away; wherein the fifth capacitor layer and the sixth capacitor layer are capacitor layers of different layers.

3. The method for manufacturing a capacitor according to claim 1 or 2, wherein: The method for manufacturing the capacitor further includes: A first protection structure and a second protection structure are formed, wherein the first protection structure covers the sidewall of at least one layer of the second conductive layer on the first side of the capacitor unit, and the second protection structure covers the sidewall of at least one layer of the second conductive layer on the second side of the capacitor unit.

4. The method for manufacturing a capacitor according to claim 3, wherein: The method for manufacturing the capacitor further includes: At least one first contact conductive structure and at least one second contact conductive structure are formed. On the first side of the capacitor unit, each of the second conductive layers located in the even-numbered layers is connected to a different first contact conductive structure, or at least part of the second conductive layers located in the even-numbered layers are connected to the same first contact conductive structure; on the second side of the capacitor unit, each of the second conductive layers located in the odd-numbered layers is connected to a different second contact conductive structure, or at least part of the second conductive layers located in the odd-numbered layers are connected to the same second contact conductive structure; the first conductive layer is connected to the first contact conductive structure or the second contact conductive structure.

5. The method for manufacturing a capacitor according to claim 4, wherein: The method for manufacturing the capacitor further includes: At least one wiring layer is formed, each wiring layer includes at least one first wiring structure and at least one second wiring structure, the first contact conductive structure is connected to the first wiring structure, and the second contact conductive structure is connected to the second wiring structure.

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