Micro light emitting diode display chip and manufacturing method thereof

Abstract

The application discloses a micro light emitting diode display chip and a manufacturing method thereof. The micro light emitting diode display chip comprises a driving substrate with opposite first and second surfaces, an LED epitaxial layer bonded to the first surface of the driving substrate, and a stress compensation layer bonded to the second surface of the driving substrate. The stress of the LED epitaxial layer and the stress compensation layer acting on the driving substrate are offset. The application sets the stress compensation layer on the other side of the driving substrate opposite to the LED epitaxial layer, balances the stress of the LED epitaxial layer on the driving substrate, completely eliminates the warping problem caused by bonding, has no limitation on the bonding temperature and the process temperature after bonding, greatly improves the yield, the manufacturability and the device reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular, to a micro light emitting diode display chip (LED chip or micro LED chip) and a manufacturing method thereof. BACKGROUND

[0002] In the manufacturing process of a vertical structure LED chip, an epitaxial layer grown on a sapphire substrate or other substrate needs to be transferred to another substrate, and the original epitaxial substrate is removed, so as to achieve better performance. The substrate transfer technology is critical, and a mature high-reliability metal bonding process is generally used to achieve this. The mature high-reliability metal bonding process is generally at 300 DEG C or above. Due to the large difference in the thermal expansion coefficient between the epitaxial material (generally GaN) and the driving substrate, the new wafer formed after bonding will have a large warpage, which will cause great problems in subsequent process procedures, resulting in a decrease in yield, poor production consistency, frequent device alarms, and the like.

[0003] With the further development of micro display applications, the pixel size of micro LED is required to be smaller and smaller (<5 um). If the traditional flip chip method is used to bond the micro LED chip with the CMOS driving substrate, the alignment accuracy exceeds the limit of the equipment. Therefore, people generally bond the micro LED epitaxial layer with the CMOS first, and then complete the chip manufacturing by using a semiconductor process. Due to the large difference in the thermal expansion coefficient between the GaN epitaxial layer and the bonded CMOS substrate (the thermal expansion coefficient of the CMOS substrate is 2.6E-6 / K, and the thermal expansion coefficient of GaN in the horizontal direction is 5.59E-6 / K), after bonding, the bonded wafer will have a large warpage after the epitaxial substrate is removed, which will have a great impact on subsequent process procedures, resulting in a decrease in yield, poor production consistency, frequent device alarms, and the like.

[0004] Some existing technologies introduce a low-melting-point metal as an intermediate bonding layer to reduce the bonding temperature, thereby reducing the warpage after bonding. To some extent, the warpage problem introduced by bonding can be alleviated, but the warpage problem caused by bonding cannot be eliminated. At the same time, the device reliability is poor when a low-melting-point metal is introduced, and the temperature of the subsequent production process is also limited (generally cannot exceed the bonding temperature)

[0005] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be regarded as an acknowledgment or any form of suggestion that this information forms prior art that is publicly known. SUMMARY

[0006] The present application aims to provide a micro light emitting diode display chip and a manufacturing method thereof, which can overcome the warpage problem introduced by bonding in the prior art.

[0007] To achieve the above object, the embodiment of the present application provides a micro light emitting diode display chip, comprising:

[0008] a driving substrate having opposite first and second surfaces;

[0009] an LED epitaxial layer bonded to the first surface of the driving substrate; and

[0010] a stress compensation layer bonded to the second surface of the driving substrate, the stress of the LED epitaxial layer and the stress compensation layer acting on the driving substrate respectively offset.

[0011] In one or more embodiments, the thermal expansion coefficient of the stress compensation layer is the same as or close to the thermal expansion coefficient of the LED epitaxial layer, the temperature c1 at which the LED epitaxial layer is bonded to the first surface of the driving substrate is 300-500℃, and the temperature c2 at which the stress compensation layer is bonded to the second surface of the driving substrate is 300-500℃.

[0012] In one or more embodiments, the stress compensation layer and the LED epitaxial layer are made of the same material.

[0013] In one or more embodiments, the stress compensation layer is made of GaN material.

[0014] In one or more embodiments, the LED epitaxial layer and the driving substrate have a first metal bonding layer therebetween, the stress compensation layer and the driving substrate have a second metal bonding layer therebetween, and the material of the first metal bonding layer and the second metal bonding layer is selected from one or more of Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0015] In one or more embodiments, the LED epitaxial layer forms a plurality of LED light emitting units arranged in an array through an isolation groove or ion implantation isolation material, the driving substrate includes a driving circuit and a plurality of contacts electrically connected to the driving circuit, each LED light emitting unit corresponds to one contact, and the contact drives the LED light emitting unit.

[0016] In one or more embodiments, each LED light emitting unit comprises:

[0017] a first doped semiconductor layer formed on the first surface of the driving substrate;

[0018] a light emitting layer formed on the first doped semiconductor layer;

[0019] a second doped semiconductor layer formed on the light emitting layer,

[0020] a passivation layer formed on the second doped semiconductor layer, the passivation layer having a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; and

[0021] an electrode layer formed on the passivation layer, the electrode layer being electrically connected to the second doped semiconductor layer through the first opening and being electrically connected to the contact through the second opening.

[0022] In one or more embodiments, the contact is electrically connected to the second doped semiconductor layer of each LED light emitting unit, and the contact is located between adjacent LED units.

[0023] In one or more embodiments, further comprising: a plurality of through holes penetrating the LED epitaxial layer and the first metal bonding layer, each through hole corresponding to one of the contacts, the bottom of the through hole exposing the contact,

[0024] the electrode layer being electrically connected to the second doped semiconductor layer and the contact through the through hole, respectively.

[0025] To achieve the above object, an embodiment of the present application provides a manufacturing method of a micro light emitting diode display chip, comprising:

[0026] forming an LED epitaxial layer on a growth substrate;

[0027] providing a driving substrate, the driving substrate having opposite first and second surfaces;

[0028] bonding the LED epitaxial layer and the first surface of the driving substrate;

[0029] providing a dummy substrate, forming a stress compensation layer on the dummy substrate, bonding the stress compensation layer and the second surface of the driving substrate, the stress of the LED epitaxial layer and the stress compensation layer acting on the driving substrate being offset;

[0030] stripping the growth substrate and the dummy substrate;

[0031] separating the LED epitaxial layer to form a plurality of arrayed LED light emitting units, the plurality of LED light emitting units being independently driven.

[0032] In one or more embodiments, the temperature c1 for bonding the LED epitaxial layer and the first surface of the driving substrate is 300-500℃, and the temperature c2 for bonding the stress compensation layer and the second surface of the driving substrate is 300-500℃.

[0033] In one or more embodiments, the temperature c2 is less than or equal to the temperature cl, or the temperature cl is less than or equal to the temperature c2, when the LED epitaxial layer is bonded to the first surface of the driving substrate first and the stress compensation layer is bonded to the second surface of the driving substrate second, or the stress compensation layer is bonded to the second surface of the driving substrate first and the LED epitaxial layer is bonded to the first surface of the driving substrate second. In one or more embodiments, the stress compensation layer has a thermal expansion coefficient that is the same as or close to the thermal expansion coefficient of the LED epitaxial layer.

[0034] In one or more embodiments, the stress compensation layer and the LED epitaxial layer are made of the same material.

[0035] In one or more embodiments, the stress compensation layer is made of GaN material.

[0036] In one or more embodiments, the method of bonding the LED epitaxial layer to the first surface of the driving substrate comprises:

[0037] forming a first bonding layer on the surface of the LED epitaxial layer;

[0038] forming a second bonding layer on the first surface of the driving substrate;

[0039] bonding the LED epitaxial layer and the driving substrate together through the first bonding layer and the second bonding layer, the first bonding layer and the second bonding layer being made of one or more of Au, Sn, Cu, Ti, Ni, or alloys thereof.

[0040] In one or more embodiments, the method of bonding the stress compensation layer to the second surface of the driving substrate comprises:

[0041] forming a third bonding layer on the surface of the stress compensation layer;

[0042] forming a fourth bonding layer on the second surface of the driving substrate;

[0043] bonding the stress compensation layer and the driving substrate together through the third bonding layer and the fourth bonding layer, the third bonding layer and the fourth bonding layer being made of one or more of Au, Sn, Cu, Ti, Ni, or alloys thereof.

[0044] In one or more embodiments, the method of separating the LED epitaxial layer to form a plurality of arrayed LED light emitting units comprises:

[0045] etching an isolation groove between adjacent LED light emitting units, or

[0046] ion implanting an isolation material between adjacent LED light emitting units.

[0047] In one or more embodiments, the method of separating the LED epitaxial layer to form a plurality of arrayed LED light emitting units comprises: etching to form isolation grooves between adjacent LED light emitting units; and thinning the stress compensation layer to balance the stress variation of the LED epitaxial layer.

[0048] In one or more embodiments, the method of forming an LED epitaxial layer on a growth substrate comprises:

[0049] forming a first doped semiconductor layer on the first surface of the driving substrate;

[0050] forming a light emitting layer on the first doped semiconductor layer;

[0051] forming a second doped semiconductor layer on the light emitting layer.

[0052] In one or more embodiments, the driving substrate comprises a driving circuit and a plurality of contacts electrically connected to the driving circuit, each LED light emitting unit corresponding to one contact,

[0053] the contact is electrically connected to the second doped semiconductor layer of each LED light emitting unit, and the contact is located between adjacent LED units.

[0054] In one or more embodiments, the method further comprises:

[0055] etching the LED epitaxial layer to form a plurality of through holes, each through hole corresponding to one of the contacts, the bottom of the through hole exposing the contact;

[0056] forming a passivation layer on the second doped semiconductor layer and the sidewall of the through hole, the passivation layer having a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; and

[0057] forming an electrode layer on the passivation layer, the electrode layer being electrically connected to the second doped semiconductor layer through the first opening and being electrically connected to the contact through the second opening.

[0058] In one or more embodiments, the LED epitaxial layer and the stress compensation layer are respectively faced to the first surface and the second surface of the driving substrate, so that the LED epitaxial layer and the stress compensation layer are simultaneously bonded with the driving substrate.

[0059] Compared with the prior art, the present invention can balance the stress of the LED epitaxial layer on the driving substrate by setting a stress compensation layer on the other side of the driving substrate relative to the LED epitaxial layer, which can completely eliminate the warping problem caused by bonding. At the same time, there are no restrictions on the bonding temperature and the process temperature after bonding, which greatly improves the yield, manufacturability and device reliability. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of a miniature light-emitting diode display chip according to Embodiment 1 of the present invention;

[0061] Figures 2a-2h This is a schematic diagram of the intermediate structure of a micro light-emitting diode display chip according to Embodiment 2 of the present invention;

[0062] Figures 3a-3g This is a schematic diagram of the intermediate structure of a micro light-emitting diode display chip according to Embodiment 3 of the present invention. Detailed Implementation

[0063] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0064] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0065] Generally, terms can be understood at least in part based on their usage in the context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood at least in part based on the context to convey either a singular or a plural usage.

[0066] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and that “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.

[0067] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an extent that is less than the underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can include multiple layers.

[0068] Embodiment 1

[0069] In combination Figure 1 As shown in the drawings, an embodiment of the present application provides a micro light emitting diode display chip 100, comprising a driving substrate 10, an LED epitaxial layer 20 and a stress compensation layer 30. Wherein, the driving substrate 10 has opposite first surface 11 and second surface 12; the LED epitaxial layer 20 is bonded to the first surface 11 of the driving substrate 10; the stress compensation layer 30 is bonded to the second surface 12 of the driving substrate 10.

[0070] In order to avoid the deformation of the driving substrate 10, the LED epitaxial layer 20 and the stress compensation layer 30 respectively act on the stress of the driving substrate 10 to offset.

[0071] In the technical solution, the LED epitaxial layer 20 and the stress compensation layer 30 respectively generate opposite stress effects on both sides of the driving substrate 10, and offset the stress to avoid the warping of the driving substrate 10 caused by the difference in the thermal expansion coefficient.

[0072] In an embodiment, the thermal expansion coefficient of the LED epitaxial layer 20 is greater than the thermal expansion coefficient of the driving substrate 10, the LED epitaxial layer 20 acts on the first surface 11 of the driving substrate 10, which will generate a first force to make the driving substrate 10 warp to the direction of the LED epitaxial layer 20; the thermal expansion coefficient of the stress compensation layer 30 is greater than the thermal expansion coefficient of the driving substrate 10, the stress compensation layer 30 acts on the second surface 12 of the driving substrate 10, which will generate a second force to make the driving substrate 10 warp to the direction of the stress compensation layer 30, the first force and the second force are approximately the same in size, and offset each other to prevent the deformation of the driving substrate 10.

[0073] In a preferred embodiment, the thermal expansion coefficient and the thickness of the LED epitaxial layer 20 are close to the stress compensation layer 30, in other embodiments, the LED epitaxial layer 20 and the stress compensation layer 30 can also be selected from materials with inconsistent thermal expansion coefficients, but the thickness required for stress compensation needs to be changed to satisfy the stress offset of the LED epitaxial layer 20 and the stress compensation layer 30 acting on the driving substrate 10.

[0074] In one embodiment, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer 30 is made of Ge (CTE = 5.9E-6 / K) with a thickness of 0.95 um, which is thinner than the LED epitaxial layer 20.

[0075] In one embodiment, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer 30 is made of Ge (CTE = 5.9E-6 / K) with a thickness of 0.95 um, which is thinner than the LED epitaxial layer 20.

[0076] In one embodiment, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer 30 is made of Ge (CTE = 5.9E-6 / K) with a thickness of 0.95 um, which is thinner than the LED epitaxial layer 20.

[0077] In a preferred embodiment, a metal bonding process is used between the LED epitaxial layer 20 and the driving substrate 10. The bonding layer 40 is an adhesive material formed between the LED epitaxial layer 20 and the driving substrate 10, and in some embodiments, the material of the bonding layer 40 is Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0078] In other embodiments, the bonding layer 40 can also be made of non-metallic materials, such as polyimide (PI), polydimethylsiloxane (PDMS), photoresist, etc.

[0079] In one embodiment, the bonding layer 40 includes a first bonding layer 41 and a second bonding layer 42 bonded to the epitaxial function 20 and the driving substrate 10, respectively, and the first bonding layer 41 and the second bonding layer 42 are bonded under certain temperature and pressure conditions. The materials of the first bonding layer 41 and the second bonding layer 42 can be the same or different.

[0080] In this technical solution, since the driving substrate 10 does not warp under the balance of the epitaxial function 20 and the stress compensation layer 30, the selection window of the bonding material and the bonding temperature of the bonding layer 40 is larger, such as the bonding process can be carried out at a high temperature of 300-500℃ without easy warping, and this temperature condition also meets the temperature window of the process after bonding, thereby reducing the difficulty of subsequent processes while ensuring yield, and the product obtained by the bonding method of the present application can be applied to high temperature environment and has high reliability.

[0081] In a preferred embodiment, a metal bonding process is used between the stress compensation layer 30 and the driving substrate 10. The bonding layer 50 is an adhesive material formed between the stress compensation layer 30 and the driving substrate 10, and in some embodiments, the material of the bonding layer 50 is Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0082] In other embodiments, the bonding layer 50 can also employ non-metallic materials, such as polyimide (PI), polydimethylsiloxane (PDMS), photoresist, etc.

[0083] In one embodiment, the bonding layer 50 includes a third bonding layer 51 and a fourth bonding layer 52 bonded to the stress compensation layer 30 and the driving substrate 10, respectively, and the third bonding layer 51 and the fourth bonding layer 52 are bonded under certain temperature and pressure conditions. The materials of the third bonding layer 51 and the fourth bonding layer 52 can be the same or different.

[0084] In this technical solution, since the driving substrate 10 does not warp under the balancing effect of the epitaxial functional layer 20 and the stress compensation layer 30, the selection window of the bonding material and the bonding temperature of the bonding layer 50 is larger, and the yield is greatly improved.

[0085] In one embodiment, the LED epitaxial layer 20 is arranged in an array of a plurality of LED light emitting units 21 in a boss structure through an isolation groove 210 formed between adjacent LED light emitting units 21, so that the LED light emitting units 21 are independent of each other.

[0086] In another embodiment, the separation of different LED light emitting units 21 can also be achieved by ion implantation of isolation materials. In some embodiments, an ion implantation region (not shown in the figure) can be formed by implanting H+, He+, N+, O+, F+, Mg+, Si+, or Ar+ions, etc. in the LED epitaxial layer 20. In some embodiments, the LED epitaxial layer 20 can be implanted with one or more ions to form an ion implantation region. The ion implantation region has electrically insulating physical properties after implanting the ions.

[0087] The driving substrate 10 includes a driving circuit and a plurality of contacts 13 electrically connected to the driving circuit, and each LED light emitting unit 21 corresponds to one contact 13, and the contact 13 drives the LED light emitting unit.

[0088] Each LED light emitting unit 21 includes a first doped semiconductor layer 213, a light emitting layer 212, a second doped semiconductor layer 211, and a passivation layer 214 formed in sequence on the first surface 11 of the driving substrate 10. The passivation layer 214 has a first opening 2141 exposing the second doped semiconductor layer 211 and a second opening 2142 exposing the contact 13. Each LED light emitting unit 21 further includes an electrode layer 215 formed on the passivation layer 214. The electrode layer 215 contacts the second doped semiconductor layer 211 through the first opening 2141 of the passivation layer 214 and is electrically connected to the contact 13 through the second opening 2142 of the passivation layer 214. The contact 13 is located at a gap between adjacent LED units 21 and is electrically connected to the second doped semiconductor layer 211 of one of the LED light emitting units 21 through the electrode layer 215. In some embodiments of the present application, the second doped semiconductor layer 211 forms a cathode of each LED light emitting unit 21, and thus the contact 13 provides a driving voltage for each LED unit 21 to the second doped semiconductor layer 211 through the electrode layer 215.

[0089] In some embodiments, the first doped semiconductor layer 213 can be a p-type GaN. In some embodiments, the first doped semiconductor layer 213 can be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213 can be a p-type InGaN. In some embodiments, the first doped semiconductor layer 213 can also be a p-type AlInGaP.

[0090] In some embodiments, the second doped semiconductor layer 211 can be an n-type semiconductor layer and forms a cathode of each LED light emitting unit. In some embodiments, the second doped semiconductor layer 211 can be an n-type GaN. In some embodiments, the second doped semiconductor layer 211 can be an n-type InGaN. In some embodiments, the second doped semiconductor layer 211 can also be an n-type AlInGaP. The second doped semiconductor layers 211 of different LED light emitting units are electrically isolated, and thus each LED light emitting unit can have a cathode with a different voltage level from other units.

[0091] The light emitting layer 212 is an active region of the LED light emitting unit and has a multi-quantum well structure, for example, composed of gallium nitride / indium gallium nitride / aluminum gallium nitride materials. In some embodiments, the thickness of the first doped semiconductor layer 213 and the second doped semiconductor layer 211 can be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the first doped semiconductor layer 213, the light emitting layer 212, and the second doped semiconductor layer 211 can be between about 0.4 μm and about 4 μm.

[0092] The passivation layer 214 can be used to protect and isolate the LED light-emitting unit. The passivation layer 214 may contain polyimide, SU-8 photoresist or other photo-patternable polymers.

[0093] The electrode layer 215 can be made of conductive materials such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge or Ni.

[0094] To facilitate the electrical connection of the electrode layer 215 to the second doped semiconductor layer 211 and the contact 13, the LED epitaxial layer 20 and the bonding layer 40 are also perforated with vias 22. Each via 22 corresponds to one contact 13, and the bottom of the via 22 exposes the contact 13. The electrode layer 215 is electrically connected to the second doped semiconductor layer 211 and the contact 13 through the vias 22.

[0095] In this case, each contact 13 is connected to the second doped semiconductor layer 211 of an LED light-emitting unit 21, enabling independent control of each LED light-emitting unit 21. The first doped semiconductor layer 213 extends between multiple LED light-emitting units 21, realizing a common electrode.

[0096] Example 2

[0097] According to a method for fabricating a micro light-emitting diode display chip according to an embodiment of the present invention, an LED epitaxial layer and a stress compensation layer are sequentially bonded to a driving substrate to fabricate the chip. Figure 1 Taking the light-emitting diode structure shown as an example, the specific steps include the following.

[0098] Step S110: Refer Figure 2a A growth substrate 60 is provided, on which an LED epitaxial layer 20 is formed. The LED epitaxial layer 20 includes a second doped semiconductor layer 211, a light-emitting layer 212, and a first doped semiconductor layer 213 sequentially grown on the growth substrate 60.

[0099] The growth substrate 60 includes, but is not limited to, a mirror-finished or micron / nano-scale patterned sapphire substrate, and may also be a gallium arsenide, indium phosphide, gallium phosphide, gallium oxide, silicon carbide, silicon, zinc oxide, lithium gallium oxide single crystal substrate, or a high-temperature resistant metal substrate.

[0100] The first doped semiconductor layer 213 may be p-type GaN. In some embodiments, the first doped semiconductor layer 213 may be formed by doping GaN with magnesium (Mg). In some embodiments, the first doped semiconductor layer 213 may be p-type InGaN. In some embodiments, the first doped semiconductor layer 213 may also be p-type AlInGaP.

[0101] The light emitting layer 212, as an active region, adopts a multi-quantum well structure, for example, composed of gallium nitride / indium gallium nitride / gallium aluminum nitride. In some embodiments, the thickness of the first doped semiconductor layer 213 and the second doped semiconductor layer 211 can be between about 0.3 μm and about 5 μm. In some other embodiments, the thickness of the first doped semiconductor layer 213, the light emitting layer 212 and the second doped semiconductor layer 211 can be between about 0.4 μm and about 4 μm.

[0102] The second doped semiconductor layer 211 can be an n-type semiconductor layer and forms a cathode of each LED light emitting unit. In some embodiments, the second doped semiconductor layer 211 can be an n-type GaN. In some embodiments, the second doped semiconductor layer 211 can be an n-type InGaN. In some embodiments, the second doped semiconductor layer 211 can also be an n-type AlInGaP.

[0103] Step 120: referring to Figure 2b A first bonding layer 41 is formed on the surface of the LED epitaxial layer 20.

[0104] The material of the first bonding layer 41 adopts Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0105] Step 130: referring to Figure 2c A driving substrate 10 is provided, which has opposite first and second surfaces 11 and 12, and a second bonding layer 42 is formed on the first surface 11 of the driving substrate 10.

[0106] The driving substrate 10 includes a driving circuit (not shown) and a plurality of contacts 13 electrically connected to the driving circuit.

[0107] The material of the second bonding layer 42 adopts Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0108] Step 140: referring to Figure 2d The first bonding layer 41 and the second bonding layer 42 are bonded, and the metal surface bonding is performed under heating and a certain pressure. The bonding adopts high-temperature bonding, and the bonding temperature is controlled at 300-500 °C.

[0109] In the process after the bonding, in order to ensure the yield, the temperature of other processes needs to be less than the bonding temperature. In the present case, since the bonding adopts high-temperature bonding and the bonding temperature reaches 300 °C or above, in the process after the bonding, other processes have a larger temperature selection window and are less limited in temperature, thereby greatly improving the device yield, manufacturability and device reliability.

[0110] Meanwhile, the bonding temperature should not be too high, such as greater than 500°C, which will affect the yield of the device. In some preferred embodiments, the bonding temperature can be 300°C, 350°C, 400°C, 450°C, 500°C, etc.

[0111] Step 150: referring to FIG. 1C, a fourth bonding layer 52 is formed on the second surface 12 of the driving substrate 10. Figure 2e , the fourth bonding layer 52 is formed on the second surface 12 of the driving substrate 10.

[0112] The material of the fourth bonding layer 52 can be Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0113] Step 160: referring to FIG. 1D, a stress compensation layer 30 and a third bonding layer 51 are formed on a wafer substrate 70. Figure 2f , the stress compensation layer 30 and the third bonding layer 51 are formed on the wafer substrate 70.

[0114] The wafer substrate 70 can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the wafer substrate 70 can be made of a non-conductive material, such as glass, plastic or sapphire wafer, etc.

[0115] The stress compensation layer 30 has a thermal expansion coefficient and a thickness close to the LED epitaxial layer 20. In other embodiments, the LED epitaxial layer 20 and the stress compensation layer 30 can also be made of materials with different thermal expansion coefficients, but the thickness required for stress compensation needs to be changed to satisfy the stress offset of the LED epitaxial layer 20 and the stress compensation layer 30 acting on the driving substrate 10.

[0116] In a specific example, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer is made of GaN material with a thickness consistent with the LED epitaxial layer 20, i.e. 1 um.

[0117] In another specific example, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer 30 is made of Ge (CTE = 5.9E-6 / K) with a thickness of 0.95 um, which is thinner than the LED epitaxial layer 20.

[0118] In another specific example, the LED epitaxial layer 20 is made of GaN material with a thickness of 1 um, and the stress compensation layer 30 is made of InSb (CTE = 5.37E-6 / K) with a thickness of 1.04 um, which is thicker than the LED epitaxial layer 20.

[0119] The material of the third bonding layer 51 can be Au, Sn, Cu, Ti, Ni or an alloy thereof.

[0120] Step 170: referring to FIG. 1E, the wafer substrate 70 is bonded to the driving substrate 10. Figure 2gThe third bonding layer 51 and the fourth bonding layer 52 are bonded together, and metal-to-metal bonding is performed under heating and certain pressure conditions. High-temperature bonding is used, with the bonding temperature controlled between 300℃ and 500℃, and the bonding temperature in this step is less than or equal to the bonding temperature in step 140.

[0121] Step 180: Refer Figure 2h The growth substrate 60 and the co-film substrate 70 are then peeled off.

[0122] Step 190: Refer Figure 1 Multiple boss structures are formed on the LED epitaxial layer 20, and a passivation layer 214 and an electrode layer 215 are fabricated on the second doped semiconductor layer 211. The multiple boss structures divide the LED epitaxial layer 20 to form multiple arrayed LED light-emitting units 21, which can be driven independently.

[0123] The method of forming multiple boss structures on the LED epitaxial layer 20 can be to form isolation grooves 210 by etching. The isolation grooves 210 are formed between adjacent LED light-emitting units 21, so that the LED light-emitting units 21 are independent of each other.

[0124] Since the stress of the LED epitaxial layer is prone to change during the etching of the isolation trench 210 or other chip processes, the present invention can match the stress change of the front LED epitaxial layer by reducing the thickness of the stress compensation layer, thereby ensuring that the bonding wafer does not warp and improving the product yield.

[0125] Another method for forming multiple boss structures on the LED epitaxial layer 20 is by ion implantation of an insulating material. In some embodiments, ion-implanted regions (not shown) can be formed by implanting H+, He+, N+, O+, F+, Mg+, Si+, or Ar+ ions into the LED epitaxial layer 20. In some embodiments, the LED epitaxial layer 20 can be implanted with one or more ions to form ion-implanted regions. After ion implantation, the ion-implanted regions possess electrically insulating physical properties.

[0126] The electrode layer 215 contacts the second doped semiconductor layer 211 through an opening in the passivation layer 214.

[0127] The passivation layer 214 can be used to protect and isolate the LED light-emitting unit. The passivation layer 214 may contain polyimide, SU-8 photoresist or other photo-patternable polymers.

[0128] The electrode layer 215 can be made of conductive materials such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge or Ni.

[0129] In the LED chip manufacturing process, the stress of the LED epitaxial layer changes due to the manufacturing process, and the stress of the front LED epitaxial layer can be matched by reducing the thickness of the stress compensation layer, so as to ensure that the wafer bonding does not produce warping.

[0130] Embodiment 3

[0131] The micro light emitting diode display chip manufacturing method according to an embodiment of the present application adopts the bonding mode of LED epitaxial layer and stress compensation layer in sequence with the driving substrate to manufacture Figure 1 The light emitting diode structure shown is taken as an example.

[0132] In this embodiment, the driving substrate 10 and the wafer substrate 70 are first bonded by metal, and then the driving substrate 10 and the LED epitaxial layer 20 are bonded. Except for the sequence of this step, the rest is the same as embodiment 2, which will not be repeated here.

[0133] Embodiment 4

[0134] The micro light emitting diode display chip manufacturing method according to an embodiment of the present application adopts the bonding mode of LED epitaxial layer and stress compensation layer in sequence with the driving substrate to manufacture Figure 1 The light emitting diode structure shown is taken as an example, which specifically includes the following steps.

[0135] Step S210: providing a growth substrate 60', and forming an LED epitaxial layer 20' on the growth substrate 60'. Figure 3a The growth substrate 60' includes but is not limited to one of a mirror or a micron / nanometer patterned sapphire substrate, and can also be a gallium arsenide, indium phosphide, gallium phosphide, gallium oxide, silicon carbide, silicon, zinc oxide, lithium gallate single crystal substrate or high-temperature resistant metal substrate.

[0136] The first doped semiconductor layer 213' can be a p-type GaN. In some embodiments, the first doped semiconductor layer 213' can be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213' can be a p-type InGaN. In some embodiments, the first doped semiconductor layer 213' can also be a p-type AlInGaP.

[0137] The first doped semiconductor layer 213' can be a p-type GaN. In some embodiments, the first doped semiconductor layer 213' can be formed by doping magnesium (Mg) in GaN. In some embodiments, the first doped semiconductor layer 213' can be a p-type InGaN. In some embodiments, the first doped semiconductor layer 213' can also be a p-type AlInGaP.

[0138] The light-emitting layer 212′ serves as the active region and employs a multi-quantum-well structure, which may be composed of gallium nitride / indium gallium nitride / aluminum gallium nitride materials. In some embodiments, the thickness of the first doped semiconductor layer 213′ and the second doped semiconductor layer 211′ can be between approximately 0.3 μm and approximately 5 μm. In some other embodiments, the thickness of the first doped semiconductor layer 213′, the light-emitting layer 212′, and the second doped semiconductor layer 211′ can be between approximately 0.4 μm and approximately 4 μm.

[0139] The second doped semiconductor layer 211' may be an n-type semiconductor layer and form the cathode of each LED light-emitting unit. In some embodiments, the second doped semiconductor layer 211' may be n-type GaN. In some embodiments, the second doped semiconductor layer 211' may be n-type InGaN. In some embodiments, the second doped semiconductor layer 211' may also be n-type AlInGaP.

[0140] Step 220: Refer Figure 3b A first bonding layer 41' is formed on the surface of the LED epitaxial layer 20'.

[0141] The first bonding layer 41′ is made of Au, Sn, Cu, Ti, Ni or their alloys.

[0142] Step 230: Refer Figure 3c A driving substrate 10' is provided, the driving substrate 10' having a first surface 11' and a second surface 12' opposite to each other, a second bonding layer 42' being formed on the first surface 11' of the driving substrate 10', and a fourth bonding layer 52' ​​being formed on the second surface 12' of the driving substrate 10'.

[0143] The driving substrate 10' includes a driving circuit (not shown) and a plurality of contacts 13' electrically connected to the driving circuit.

[0144] The driving substrate 10' is selected from one of silicon, copper, molybdenum, tungsten, molybdenum-copper alloy, tungsten-copper alloy, and aluminum-silicon alloy substrates. For manufacturing micro LED displays, the driving substrate 10' can also be a display substrate of a CMOS backplane or a TFT glass substrate.

[0145] The material of the second bonding layer 42′ is Au, Sn, Cu, Ti, Ni or their alloys.

[0146] The fourth bonding layer 52′ is made of Au, Sn, Cu, Ti, Ni or their alloys.

[0147] Step 240: Refer Figure 3d A secondary substrate 70' is provided, on which a stress compensation layer 30' and a third bonding layer 51' are formed.

[0148] The wafer substrate 70' can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide. In some embodiments, the wafer substrate 70' can be made of a non-conductive material, such as glass, plastic or sapphire wafer, etc.

[0149] The stress compensation layer 30' has a thermal expansion coefficient close to that of the LED epitaxial layer 20'. In other embodiments, the LED epitaxial layer 20' and the stress compensation layer 30' can also be made of materials with different thermal expansion coefficients, but the thickness required to compensate for stress needs to be changed to meet the stress balance between the LED epitaxial layer 20' and the stress compensation layer 30' acting on the driving substrate 10'.

[0150] In a specific example, the LED epitaxial layer 20' is made of GaN material with a thickness of 1 um, and the stress compensation layer 30' is also made of GaN material with a thickness of 1 um, the same as the LED epitaxial layer 20'.

[0151] In another specific example, the LED epitaxial layer 20' is made of GaN material with a thickness of 1 um, and the stress compensation layer 30' is made of Ge (CTE = 5.9E-6 / K) with a thickness of 0.95 um, thinner than the LED epitaxial layer 20'.

[0152] In another specific example, the LED epitaxial layer 20' is made of GaN material with a thickness of 1 um, and the stress compensation layer 30' is made of InSb (CTE = 5.37E-6 / K) with a thickness of 1.04 um, thicker than the LED epitaxial layer 20'.

[0153] The third bonding layer 51' is made of Au, Sn, Cu, Ti, Ni or their alloys.

[0154] Step 250: participate Figure 3e The first bonding layer 41' and the second bonding layer 42' are bonded, and the third bonding layer 51' and the fourth bonding layer 52' are bonded, and the bonding between the driving substrate 10' and the LED epitaxial layer 20', and the bonding between the driving substrate 10' and the stress compensation layer 30' are simultaneously realized under the conditions of heating and certain pressure.

[0155] In this step, the bonding between the first bonding layer 41' and the second bonding layer 42', and the bonding between the third bonding layer 51' and the fourth bonding layer 52' are carried out simultaneously, and the bonding temperature is the same, which is 300-500°C.

[0156] In order to ensure yield, the temperature of other processes needs to be less than the bonding temperature. In the present application, since high-temperature bonding is adopted, the bonding temperature reaches 300 DEG C or above, so that the other processes have a larger temperature selection window in the process after bonding, and the temperature limit is small, thereby reducing the difficulty of subsequent processes while ensuring yield, and the product obtained by the bonding method of the present application can be applied to high-temperature environments and has high reliability.

[0157] Step 260: referring to Figure 3f , the growth substrate 60' and the wafer substrate 70' are peeled off.

[0158] Step 370: referring to Figure 3g A plurality of boss structures are formed on the LED epitaxial layer 20', and a passivation layer 214' and an electrode layer 215' are made on the second doped semiconductor layer 211'. The plurality of boss structures separate the LED epitaxial layer 20' to form a plurality of array-arranged LED light-emitting units 21', which can be independently driven.

[0159] The method of forming a plurality of boss structures on the LED epitaxial layer 20' can be to form isolation grooves 210' by etching, which are formed between adjacent LED light-emitting units 21' so that the LED light-emitting units 21' are independent of each other.

[0160] Since the stress of the LED epitaxial layer is prone to change during etching of the isolation grooves 210 or other chip processes, the stress change of the front LED epitaxial layer can be matched by thinning the stress compensation layer thickness, so as to ensure that the bonded wafer does not warp.

[0161] The method of forming a plurality of boss structures on the LED epitaxial layer 20' can also be by ion implantation of isolation materials. In some embodiments, an ion implantation region (not shown in the figure) can be formed by implanting H+, He+, N+, O+, F+, Mg+, Si+ or Ar+ ions in the LED epitaxial layer 20'. In some embodiments, the LED epitaxial layer 20' can be implanted with one or more ions to form an ion implantation region. The ion implantation region has electrically insulating physical properties after implanting the ions.

[0162] The electrode layer 215' is in contact with the second doped semiconductor layer 211' through an opening in the passivation layer 214'.

[0163] The passivation layer 214' can be used to protect and isolate the LED light-emitting units, and the passivation layer 214' can include polyimide, SU-8 photoresist or other photo-patternable polymers.

[0164] The electrode layer 215′ can be made of conductive materials such as indium tin oxide (ITO), Cr, Ti, Pt, Au, Al, Cu, Ge or Ni.

[0165] During the LED chip manufacturing process, the stress in the LED epitaxial layer varies due to the manufacturing process. This can be addressed by thinning the stress compensation layer to match the stress variation in the front-side LED epitaxial layer, thereby ensuring that the bonded wafer does not warp.

[0166] In summary, in the LED chip structure of this embodiment, the presence of the stress compensation layer on the back of the driving substrate ensures that the bonded wafer is always in a state of stress balance, completely eliminating wafer warpage caused by bonding, greatly improving device manufacturability and yield, while not changing the original high-reliability bonding method, ensuring that device reliability is not affected.

[0167] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for fabricating a micro light emitting diode display chip, characterized in that, The application relates to a method for manufacturing a light-emitting diode (LED) array, comprising the following steps: providing an LED epitaxial layer formed on a growth substrate; providing a driving substrate with opposite first and second surfaces; bonding the LED epitaxial layer and the first surface of the driving substrate, wherein a first metal bonding layer is formed between the LED epitaxial layer and the driving substrate, and the bonding temperature c1 of the LED epitaxial layer and the first surface of the driving substrate is 300-500 DEG C; providing a wafer substrate, forming a stress compensation layer on the wafer substrate, and bonding the stress compensation layer and the second surface of the driving substrate, wherein a second metal bonding layer is formed between the stress compensation layer and the driving substrate, and the bonding temperature c2 of the stress compensation layer and the second surface of the driving substrate is 300-500 DEG C; the stress of the LED epitaxial layer and the stress compensation layer respectively acting on the driving substrate are offset; peeling off the growth substrate and the wafer substrate; separating the LED epitaxial layer to form a plurality of array-arranged LED light-emitting units, and the plurality of LED light-emitting units can be independently driven.

2. The method of claim 1, wherein the method further comprises: The bonding temperature c2 of the stress compensation layer and the second surface of the driving substrate is less than or equal to the bonding temperature c1 of the LED epitaxial layer and the first surface of the driving substrate, or the bonding temperature c1 of the LED epitaxial layer and the first surface of the driving substrate is less than or equal to the bonding temperature c2 of the stress compensation layer and the second surface of the driving substrate.

3. The method of claim 1, wherein the method further comprises: The thermal expansion coefficient of the stress compensation layer is the same as the thermal expansion coefficient of the LED epitaxial layer.

4. The method of claim 1, wherein the method further comprises: The method for bonding the LED epitaxial layer and the first surface of the driving substrate comprises the following steps: forming a first bonding layer on the surface of the LED epitaxial layer; forming a second bonding layer on the first surface of the driving substrate; bonding the LED epitaxial layer and the driving substrate through the first bonding layer and the second bonding layer, and the material of the first bonding layer and the second bonding layer is selected from one or more of Au, Sn, Cu, Ti, Ni or alloys thereof.

5. The method of claim 1, wherein the method further comprises: The method for bonding the stress compensation layer and the second surface of the driving substrate comprises the following steps: forming a third bonding layer on the surface of the stress compensation layer; forming a fourth bonding layer on the second surface of the driving substrate; bonding the stress compensation layer and the driving substrate through the third bonding layer and the fourth bonding layer, and the material of the third bonding layer and the fourth bonding layer is selected from one or more of Au, Sn, Cu, Ti, Ni or alloys thereof.

6. The method of claim 1, wherein the method further comprises: The method for separating the LED epitaxial layer to form a plurality of array-arranged LED light-emitting units comprises the following steps: etching isolation grooves between adjacent LED light-emitting units, or ion implanting isolation materials between adjacent LED light-emitting units.

7. The method of claim 1, wherein the method further comprises: forming a plurality of micro-LEDs on the substrate; and forming a plurality of micro-LED display chips by cutting the substrate along the plurality of scribe lines. The method for separating the LED epitaxial layer to form a plurality of array-arranged LED light-emitting units comprises the following steps: etching isolation grooves between adjacent LED light-emitting units; thinning the stress compensation layer to balance the stress change of the LED epitaxial layer.

8. The method of claim 1, wherein the method further comprises: Each of the LED light-emitting units comprises: a first doped semiconductor layer on the first surface of the driving substrate; a light-emitting layer formed on the first doped semiconductor layer; A second doped semiconductor layer is formed on the light emitting layer; The driving substrate comprises a driving circuit and a plurality of contacts electrically connected with the driving circuit, each LED light emitting unit corresponds to one contact, and the contact drives the LED light emitting unit.

9. The method of claim 8, wherein the method further comprises: forming a plurality of micro-LEDs on the substrate; and forming a plurality of micro-LED display chips by cutting the substrate along the plurality of scribe lines. The first doped semiconductor layers of adjacent LED light emitting units are connected with each other, The contact is electrically connected with the second doped semiconductor layer of the corresponding LED light emitting unit, and the contact is located between adjacent LED units; A plurality of through holes are etched in the LED epitaxial layer, each through hole corresponds to one contact, and the bottom of the through hole exposes the contact; A passivation layer is formed on the second doped semiconductor layer, the passivation layer is provided with a first opening exposing the second doped semiconductor layer and a second opening exposing the contact; And An electrode layer is formed on the passivation layer, the electrode layer is electrically connected with the second doped semiconductor layer through the first opening and is electrically connected with the contact through the second opening.

10. The method of claim 1, wherein the method further comprises: The LED epitaxial layer and the stress compensation layer are respectively faced to the first surface and the second surface of the driving substrate, so that the LED epitaxial layer and the stress compensation layer are simultaneously bonded with the driving substrate.

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