Display substrate and display device

Abstract

The display substrate and the display device are provided. The display substrate comprises a substrate, a display area and a peripheral area at least partially surrounding the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of gate lines located in the display area and the peripheral area and electrically connected with the plurality of sub-pixels; a plurality of gate driving circuits located in the peripheral area and electrically connected with the plurality of gate lines; at least one control line located in the peripheral area and electrically connected with the plurality of gate driving circuits; the at least one control line comprises a first segment and a second segment arranged at intervals along a first direction, and the two opposite end faces of the first segment and the second segment each have at least one protruding tip; and a first conductive adapter, which is located on the side of the at least one control line away from the substrate and is electrically connected with the first segment and the second segment through a first via. The protruding tip arranged on the two opposite end faces of the first segment and the second segment can form a tip discharge structure to effectively release the accumulated static electricity.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to display substrates and display devices. Background Technology

[0002] OLED devices are self-emissive devices that rely on driving their own organic light-emitting materials to emit light. They have advantages such as high brightness, low power consumption, and high resolution, and have attracted much attention from users.

[0003] However, current display substrates and display devices still need improvement. Summary of the Invention

[0004] This disclosure is based on the inventors' discoveries and understanding of the following facts and problems:

[0005] The inventors discovered that during the fabrication of OLED substrates, significant static electricity accumulates during dry etching or exposure of the interlayer dielectric layer in the GOA (Gate Driver on Array) region. This static electricity can cause breakdown at some points in the interlayer dielectric layer, leading to problems such as line breaks and short circuits between some source / drain electrode lines and the gate layer during subsequent source / drain electrode layer deposition. These issues result in display defects in OLED products, such as dark lines or interlaced displays. To alleviate or resolve these technical problems to some extent, the inventors discovered through extensive experimentation that a tip discharge structure can be placed at the edge of the traces in the peripheral area to effectively release the accumulated static electricity, thereby preventing display defects caused by line breaks or short circuits.

[0006] This disclosure aims to at least partially address one of the technical problems in the related art. In view of this, in one aspect of this disclosure, a display substrate is provided, the display substrate comprising: a substrate including a display area and a peripheral area at least partially surrounding the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of gate lines located in the display area and the peripheral area and electrically connected to the plurality of sub-pixels; a plurality of gate driving circuits located in the peripheral area and electrically connected to the plurality of gate lines; at least one control line located in the peripheral area and electrically connected to the plurality of gate driving circuits; the at least one control line includes a first segment and a second segment spaced apart along a first direction, each of the first segment and the second segment having at least one protruding tip on its opposite end faces; a first conductive transition portion located on the side of the at least one control line away from the substrate, and the first conductive transition portion being electrically connected to the first segment and the second segment through a first via. Thus, by providing protruding tips on the opposite end faces of the first segment and the second segment, a tip discharge structure can be formed to effectively release accumulated static electricity, thereby avoiding display defects caused by broken lines or short circuits due to static discharge.

[0007] According to an embodiment of the present disclosure, the at least one control line further comprises a third segment, the second segment and the third segment are arranged in the first direction with a spacing, and opposite two end surfaces of the second segment and the third segment are respectively provided with at least one protruding tip, and the display substrate further comprises a second conductive adapter, the second conductive adapter is located on a side of the at least one control line away from the substrate, and the second conductive adapter is electrically connected with the second segment and the third segment through a second via. Thus, the protruding tips of the opposite two end surfaces of the second segment and the third segment can also form a tip discharge structure, which is conducive to further effectively releasing accumulated static electricity.

[0008] According to an embodiment of the present disclosure, the display substrate further comprises a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and the second semiconductor portion are located on a side of the at least one control line close to the substrate, a projection of the first semiconductor portion on the substrate is located in a projection of the first conductive adapter on the substrate, and a projection of the second semiconductor portion on the substrate is located in a projection of the second conductive adapter on the substrate. Thus, when the amount of static electricity is small, the static electricity at the protruding tips can be conducted out through the first semiconductor portion and the second semiconductor portion.

[0009] According to an embodiment of the present disclosure, the number of the at least one control line is two, and the two control lines are respectively located on opposite two sides of the display area. Thus, the overall performance of the display substrate can be further improved.

[0010] According to an embodiment of the present disclosure, the number of the at least one control line is four, and the four control lines are located on opposite two sides of the display area, and each of the opposite two sides has two control lines. Thus, the overall performance of the display substrate can be further improved.

[0011] According to an embodiment of the present disclosure, the at least one control line is a power line. Thus, the control line can provide a power signal.

[0012] According to an embodiment of the present disclosure, the display substrate further comprises a connection line, the connection line is located in the peripheral area, the connection line is electrically connected with the gate line, and a projection of the connection line on the substrate overlaps a projection of the at least one control line on the substrate. Thus, the transmission of the gate signal is facilitated.

[0013] According to an embodiment of the present disclosure, the connection line comprises a first connection part and a second connection part, the first connection part is located on a side of the second connection part away from the substrate, the first connection part and the second connection part are electrically connected, and a projection of the first connection part on the substrate and a projection of the second connection part on the substrate at least partially overlap. In this way, the first connection part and the second connection part can form a double-layer wiring structure, even if there are a few electrostatic discharge-induced layer-to-layer dielectric layer breakdown points, so that the first connection part is partially ramped and broken, but the first connection part and the second connection part can still form a complete signal transmission path, thereby ensuring normal signal transmission, and further facilitating improvement of display effect.

[0014] According to an embodiment of the present disclosure, the first connection part is electrically connected to both ends of the second connection part through a third via hole and a fourth via hole, the third via hole is located on a side of the at least one control line close to the display area, and the fourth via hole is located on a side of the at least one control line away from the display area. In this way, it is beneficial to further ensure normal signal transmission.

[0015] According to an embodiment of the present disclosure, the first connection part, the second connection part, and the gate line extend along a second direction, and the first direction and the second direction intersect. In this way, it is beneficial to arrange the wiring, thereby facilitating improvement of product yield.

[0016] According to an embodiment of the present disclosure, the at least one control line has a plurality of holes penetrating the at least one control line, and a projection of the first connection part and the second connection part on the substrate intersects with a projection of the holes on the substrate. In this way, the overall performance of the display substrate can be further improved.

[0017] According to an embodiment of the present disclosure, the plurality of sub-pixels comprise a pixel circuit, the pixel circuit comprises: a light shielding layer located on a side of the substrate; a semiconductor layer located on a side of the light shielding layer away from the substrate; a gate electrode located on a side of the semiconductor layer away from the substrate; and a source electrode and a drain electrode located on a side of the gate electrode away from the substrate. In this way, it is beneficial to further improve the display effect of the display substrate.

[0018] According to an embodiment of the present disclosure, the first conductive adapter and the second conductive adapter are disposed in the same layer as the first connection part, and are disposed in the same layer as the source electrode and the drain electrode. In this way, the above-mentioned multiple structures can be formed by the same process and the same step, which is beneficial to reduce the process steps and improve the product yield.

[0019] According to an embodiment of the present disclosure, the display substrate further comprises: a buffer layer covering part of the surface of the substrate and the surface of the second connecting portion away from the substrate; an interlayer dielectric layer disposed on the side of the buffer layer away from the substrate and covering at least one of the control lines, wherein the third via hole and the fourth via hole both penetrate the buffer layer and the interlayer dielectric layer; and a gate insulating layer between the buffer layer and the at least one control line. Thus, the overall performance of the display substrate can be further improved.

[0020] In another aspect of the present disclosure, a display device is provided, which comprises the display substrate as described above. Thus, the display device has all the features and advantages of the display substrate as described above, which will not be repeated here. In general, the display device has good display effect, which is beneficial to improve the user experience. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A structural schematic diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0022] Figure 2 A structural schematic diagram of a display substrate according to another embodiment of the present disclosure is shown;

[0023] Figure 3 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0024] Figure 4 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0025] Figure 5 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0026] Figure 6 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0027] Figure 7 A partial structural schematic diagram of a control line according to an embodiment of the present disclosure is shown;

[0028] Figure 8 A physical diagram of electrostatic discharge at the protruding tip of a display substrate is shown;

[0029] Figure 9 A physical diagram of electrostatic discharge at the hole of a display substrate is shown;

[0030] Figure 10 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0031] Figure 11 A structural schematic diagram of a display substrate according to yet another embodiment of the present disclosure is shown;

[0032] Figure 12 A flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure is shown;

[0033] Figure 13 A flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure is shown;

[0034] Figure 14 A schematic diagram of electrostatic discharge of a display substrate is shown.

[0035] Explanation of reference signs:

[0036] 100: substrate; 110: display area; 120: peripheral area; 200: sub-pixel; 300: gate line; 400: control line; 410: first segment; 420: second segment; 430: protruding tip; 440: third segment; 450: hole; 500: buffer layer; 600: interlayer dielectric layer; 700: gate insulation layer; 800: passivation layer; 10: first conductive adapter; 20: second conductive adapter; 30: first semiconductor part; 40: second semiconductor part; 50: connection line; 51: first connection part; 52: second connection part; 1: first via hole; 2: second via hole; 3: third via hole; 4: fourth via hole; 5: fifth via hole. DETAILED DESCRIPTION

[0037] Embodiments of the present disclosure are described in detail below. The embodiments described below are exemplary only, and are not intended to be limiting of the present disclosure. Unless otherwise indicated, technical or scientific terms used in the embodiments have the same meaning as those commonly understood by one of ordinary skill in the art.

[0038] In an aspect of the present disclosure, the present disclosure provides a display substrate. According to an embodiment of the present disclosure, referring to Figures 1 to 6 , the display substrate includes a substrate 100, a plurality of sub-pixels 200, a plurality of gate lines 300, a plurality of gate driving circuits (such as Figure 3The GOA0, the GOA1, the GOA2, …, the GOAn, the at least one control line 400 and the first conductive transition part 10 shown in the figure, specifically, the substrate 100 includes a display area 110 and a peripheral area 120 at least partially surrounding the display area; a plurality of sub-pixels 200 are located on one side of the substrate 100 and in the display area 110; a plurality of gate lines 300 are located in the display area 110 and the peripheral area 120, and are electrically connected with the plurality of sub-pixels 200; a plurality of gate drive circuits are located in the peripheral area 120, and the plurality of gate drive circuits are electrically connected with the plurality of gate lines 300; the at least one control line 400 is located in the peripheral area 120, and the at least one control line 400 is electrically connected with the plurality of gate drive circuits, the at least one control line includes a first segment 410 and a second segment 420 which are arranged at intervals along a first direction (X direction), and the two opposite end faces of the first segment 410 and the second segment 420 respectively have at least one protruding tip 430; the first conductive transition part 10 is located on the side of the at least one control line 400 away from the substrate 100, and the first conductive transition part 10 is electrically connected with the first segment 410 and the second segment 420 through the first via 1. In this way, by arranging the protruding tips on the two opposite end faces of the first segment and the second segment, the oppositely arranged protruding tips can form a tip discharge structure, which can effectively release the accumulated static electricity in the dry etching or exposure process of the interlayer dielectric layer, thereby effectively avoiding the problems such as disconnection or short circuit caused by static electricity release, and further effectively avoiding display defects such as dark lines and interlaced display caused by disconnection or short circuit, which is beneficial to improve the yield of products.

[0039] According to embodiments of the present disclosure, referring to Figure 7 The protruding tips 430 are arranged on the two opposite end faces of the first segment 410 and the second segment 420, and the oppositely arranged protruding tips 430 can form a tip discharge structure, wherein a physical diagram of the tip discharge structure discharging can refer to Figure 8 The tip discharge structure can effectively release the accumulated static electricity, thereby avoiding the disconnection and short circuit caused by static electricity release.

[0040] According to some embodiments of the present disclosure, referring to Figure 1 And Figure 2 And Figure 6 The at least one control line 400 can further include a third segment 440, the second segment 420 and the third segment 440 are arranged at intervals along the first direction (X direction), and the two opposite end faces of the second segment 420 and the third segment 440 respectively have at least one protruding tip 430. In this way, the protruding tips arranged on the two opposite end faces of the second segment and the third segment can also constitute a tip discharge structure, and the accumulated static electricity can be more effectively released through the tip discharge structures at both ends of the control line, thereby more effectively avoiding display defects such as dark lines and interlaced display caused by disconnection or short circuit, and further improving the yield of products.

[0041] According to some embodiments of the present disclosure, referring to Figure 1 , Figure 2 and Figure 6 , the display substrate can further comprise a second conductive adapter 20, the second conductive adapter 20 is located on the side of the at least one control line 400 away from the substrate 100, and the second conductive adapter 20 is electrically connected with the second segment 420 and the third segment 440 through the second via 2. Thus, on the basis of setting the protruding tip, the second segment and the third segment can be electrically connected through the second conductive adapter, so as to ensure the normal transmission of the control line.

[0042] According to some embodiments of the present disclosure, referring to Figure 1 , Figure 2 and Figure 6 , wherein, Figure 6 may be regarded as Figure 1 a cross-sectional view along CC', the display substrate further comprises a first semiconductor part 30 and a second semiconductor part 40 (only the second semiconductor part 40 is shown in Figure 6 ), the first semiconductor part 30 and the second semiconductor part 40 are located on the side of the at least one control line 400 close to the substrate 100, the orthographic projection of the first semiconductor part 30 on the substrate 100 is in the orthographic projection of the first conductive adapter 10 on the substrate 100, and the orthographic projection of the second semiconductor part 40 on the substrate 100 is in the orthographic projection of the second conductive adapter 20 on the substrate 100. Thus, the control line and the first semiconductor part or the second semiconductor part corresponding thereto constitute a thin film transistor (TFT) structure, when a small amount of static electricity is accumulated, the gate insulating layer between the control line and the first semiconductor part and / or the second semiconductor part will be burned through at the protruding tip, and the static electricity will be conducted away through the first semiconductor part and / or the second semiconductor part.

[0043] According to some embodiments of the present disclosure, the number of the at least one control line 400 can be two, and the two control lines 400 are respectively located on the opposite sides of the display area 110. Thus, the two control lines can ensure the normal transmission of the signal.

[0044] According to some other embodiments of the present disclosure, referring to Figure 1 and Figure 2 , the number of the at least one control line 400 can be four, and the four control lines 400 are located on the opposite sides of the display area 110, and each of the opposite sides has two control lines. Thus, the four control lines can transmit more signals.

[0045] According to embodiments of the present disclosure, the at least one control line 400 can be a power line. Thus, the control line can input a control signal. According to some specific embodiments of the present disclosure, the control line 400 can be a low-level signal line (VGL); according to other specific embodiments of the present disclosure, the control line 400 can be a high-level signal line (VGH); according to still other specific embodiments of the present disclosure, the control line 400 can include both a low-level signal line and a high-level signal line.

[0046] According to some embodiments of the present disclosure, referring to Figure 3 , the display substrate can further include a first start voltage signal line GSTV, a first clock signal line GCK, a second clock signal line GCB, etc., and the gate driving circuit is electrically connected to the first start voltage signal line GSTV, the first clock signal line GCK and the second clock signal line GCB so as to generate a gate driving signal under the control thereof. According to embodiments of the present disclosure, referring to Figure 3 , the first start voltage signal line GSTV, the first clock signal line GCK and the second clock signal line GCB can also be distributed on opposite sides of the display area, specifically, one first start voltage signal line GSTV, one first clock signal line GCK and one second clock signal line GCB can be respectively arranged on opposite sides of the display area. In addition, referring to Figure 3 , each signal line can be integrated onto an IC (integrated circuit).

[0047] According to other embodiments of the present disclosure, referring to Figure 1 and Figure 2 , the display substrate further includes a connection line 50, the connection line 50 is located in the peripheral area 120, the connection line 50 is electrically connected to the gate line 300, and a projection of the connection line 50 on the substrate 100 overlaps with a projection of the at least one control line 400 on the substrate. The connection line can better ensure the normal transmission of signals.

[0048] According to some specific embodiments of the present disclosure, referring to Figure 1 , Figure 2 , Figure 4 and Figure 5 , wherein, Figure 4 may be regarded as Figure 1 a sectional view along AA’, Figure 5 may be regarded as Figure 2In the cross-sectional view along BB', the connection line 50 can include a first connection portion 51 and a second connection portion 52, the first connection portion 51 is located on the side of the second connection portion 52 away from the substrate 100, the first connection portion 51 and the second connection portion 52 are electrically connected, and the orthographic projection of the first connection portion 51 on the substrate 100 and the orthographic projection of the second connection portion 52 on the substrate 100 at least partially overlap. Thus, the first connection portion and the second connection portion can form a double-layer wiring structure, even if the static electricity accumulated during dry etching or exposure of the interlayer dielectric layer causes the interlayer dielectric layer to be partially broken down, causing the first connection portion 51 to be partially broken, the double-layer wiring structure formed by the first connection portion 51 and the second connection portion 52 can still ensure normal transmission of signals, thereby avoiding display defects such as dark lines and interlaced display, and is beneficial to improving the yield of products.

[0049] According to some embodiments of the present disclosure, with reference to Figure 1 , Figure 2 , Figure 4 and Figure 5 , the first connection portion 51 is electrically connected to both ends of the second connection portion 52 through a third via hole 3 and a fourth via hole 4, respectively, the third via hole 3 is located on the side of at least one control line 400 close to the display area 110, and the fourth via hole 4 is located on the side of at least one control line 400 away from the display area 110. Thus, the second connection portion 52 can span the arrangement area of the control lines on the side of the display area, thereby further facilitating the double-layer wiring structure formed by the second connection portion 52 and the first connection portion 51 to realize normal transmission of signals.

[0050] According to embodiments of the present disclosure, the first connection portion 51, the second connection portion 52, and the gate line 300 extend along a second direction (Y direction), and the first direction (X direction) and the second direction (Y direction) intersect. According to some embodiments of the present disclosure, with reference to Figure 1 and Figure 2 , the control line 400 extends along the first direction (i.e., the X direction shown in Figure 1 and Figure 2 ), the first connection portion 51, the second connection portion 52, and the gate line 300 (i.e., the Y direction shown in Figure 1 and Figure 2 ), the first direction (X direction) and the second direction (Y direction) intersect, and with reference to Figure 4 , Figure 4 may be regarded as Figure 1 In the cross-sectional view along AA', the orthographic projection of the second connection portion 52 on the substrate 100 and the orthographic projection of the first connection portion 51 on the substrate 100 have an overlapping area. Thus, it is beneficial for the double-layer wiring structure to be better connected through the third via hole and the fourth via hole, thereby ensuring normal transmission of signals, and facilitating the arrangement of the wiring.

[0051] According to some embodiments of the present disclosure, with reference toFigures 1 to 3 The first direction (X direction) and the second direction (Y direction) intersect, and the first direction and the second direction are different directions, which can be two substantially perpendicular directions as shown in Figures 1 to 3 , thereby being more conducive to the arrangement of the wires. It should be noted that substantially perpendicular means that the first direction (X direction) and the second direction (Y direction) can be difficult to be absolutely perpendicular due to precision problems in the manufacturing process.

[0052] According to some embodiments of the present disclosure, referring to Figure 1 and Figure 2 , the gate line 300 can be disposed in the same layer as the control line 400, and the gate line 300 can be electrically connected to the first connection part 51 through the fifth via hole 5, so that the gate line can be used to transmit a gate signal.

[0053] According to still another embodiment of the present disclosure, referring to Figure 2 and Figure 5 , the at least one control line 400 has a plurality of holes 450 penetrating the at least one control line 400, and the orthographic projection of the first connection part 51 and the second connection part 52 on the substrate 100 intersects the orthographic projection of the hole 450 on the substrate 100. According to some specific embodiments of the present disclosure, referring to Figure 5 , Figure 5 , the cross-sectional view along BB' can be seen as Figure 2 , the two control lines 400 and the two holes 450 are shown in Figure 5 , it can be seen that the orthographic projection of the second connection part 52 on the substrate 100 intersects the orthographic projection of the hole 450 on the substrate 100. Thus, the position where the control line is provided with the hole can also be subjected to tip discharge, effectively releasing part of the static electricity. It can be referred to the physical display substrate shown in Figure 9 , the static electricity at the hole position can be effectively released, and will not have a significant impact on the display effect; even if a small number of point positions of the interlayer dielectric layer are broken down during the static electricity release process at the position, the double-layer wire structure formed by the first connection part and the second connection part can also avoid the open-circuit type defect caused by the disconnection of the first connection part, thereby ensuring the normal transmission of the signal and improving the product yield.

[0054] According to embodiments of the present disclosure, referring to Figure 4 , Figure 5 and Figure 10The display substrate can further include a buffer layer 500, an interlayer medium layer 600, and a gate insulating layer 700. The buffer layer 500 covers part of the surface of the substrate 100 and the surface of the second connecting portion 52 away from the substrate 100. The interlayer medium layer 600 is arranged on the side of the buffer layer 500 away from the substrate 100 and covers at least one control line 400. The third via hole 3 and the fourth via hole 4 both penetrate the buffer layer 500 and the interlayer medium layer 600. The gate insulating layer 700 is located between the buffer layer 500 and the at least one control line 400. Thus, the overall performance of the display substrate can be further improved.

[0055] According to an embodiment of the present disclosure, referring to Figure 10 The display substrate can further include a passivation layer 800. The material of the passivation layer 800 can be silicon oxide, silicon nitride, silicon oxynitride, etc. The thickness of the passivation layer 800 can be 300-500 nanometers. Thus, the passivation layer has good insulation performance and a suitable thickness, which can improve the display effect of the display substrate and the thinness of the display substrate.

[0056] According to an embodiment of the present disclosure, referring to Figure 11 The plurality of sub-pixels 200 include a pixel circuit, Figure 11 Only one transistor of one pixel circuit is shown in the figure for illustration. The pixel circuit includes a light shielding layer 210 on one side of the substrate 100, a semiconductor layer 220 on the side of the light shielding layer 210 away from the substrate 100, a gate 230 on the side of the semiconductor layer 220 away from the substrate 100, and a source 240 and a drain 250 on the side of the gate 230 away from the substrate 100. Thus, the light shielding layer arranged in the display area can avoid the adverse effects caused by the laser irradiation on the pixel circuit on the substrate during the subsequent excimer laser annealing process. The material of the light shielding layer can be a metal material such as copper, aluminum, titanium, etc. The light shielding layer made of the metal material can better reduce the power consumption of the display substrate.

[0057] According to some embodiments of the present disclosure, the second connecting portion 52 can be arranged in the same layer as the light shielding layer 210. The second connecting portion can be arranged in the same layer as the light shielding layer in the display area. The material of the second connecting portion can be the same as that of the light shielding layer. Thus, the light shielding layer and the second connecting portion can be formed in the same process and in the same step, which can simplify the operation steps and reduce the operation difficulty. The second connecting portion has good conductivity, which can better ensure the normal transmission of signals.

[0058] According to some embodiments of the present disclosure, the first conductive adapter 10 and the second conductive adapter 20 are arranged in the same layer as the first connecting part 51 and in the same layer as the source electrode 240 and the drain electrode 250. Thus, the first conductive adapter 10, the second conductive adapter 20, the first connecting part 51, the source electrode 240 and the drain electrode 250 can be formed by the same process step, and can be made of the same material, such as copper or aluminum, which has good conductivity. Therefore, the manufacturing steps can be saved, the manufacturing difficulty can be reduced, and the above-mentioned materials have good conductivity, which can further ensure the normal transmission of signals and improve the display effect of the display product.

[0059] According to some embodiments of the present disclosure, the first semiconductor part 30 and the second semiconductor part 40 can be arranged in the same layer as the semiconductor layer 220, and can be made of indium gallium zinc oxide. Thus, the above-mentioned structure can be formed by the same step and the same process, which can further save the manufacturing steps and improve the overall performance of the display substrate.

[0060] The forming process of the double-layer wiring structure formed by the first connecting part 51 and the second connecting part 52 in the present disclosure will be described in detail below.

[0061] According to some embodiments of the present disclosure, referring to Figure 5 and Figure 12 , wherein, Figure 5 can be regarded as Figure 2 The cross-sectional view along BB' is taken as an example for illustrating that the control line 400 is provided with the hole 450. The second connecting part 52 is first formed on one side of the substrate 100, as shown in Fig. (a) of Figure 5 and Figure 12 . The substrate 100 can be made of glass. At this time, the substrate 100 is transparent, and thus the structure of the substrate 100 is not shown in Figure 12 . After the second connecting part 52 is formed, the buffer layer 500 and the gate insulating layer 700 are formed. The gate insulating layer 700 is arranged on the side of the buffer layer 500 away from the substrate 100. The buffer layer 500 and the gate insulating layer 700 are both transparent, and thus the buffer layer and the gate insulating layer are not shown in Figure 12 . Then, at least one control line 400 is formed. Figure 12 In Figure 5 and Figure 12 , two control lines are taken as an example for being formed on one side of the display area, and only part of the structure of the control line is shown. The control line 400 has the hole 450. The orthogonal projection of the hole 450 on the substrate intersects with the orthogonal projection of the second connecting part 52 on the substrate 100, as shown in Fig. (b) of Figure 5 and Figure 12 . Then, the interlayer dielectric layer 600 is formed, and the interlayer dielectric layer 600 is etched (specifically, a series of processes such as glue coating, exposure, etching and stripping can be adopted) to form the third via 3 and the fourth via 4, referring toFigure 5 and Figure 12 Figure (c) in the above-mentioned Figure 5 and Figure 12 Figure (c) in the above-mentioned Figure 5 and Figure 5 and Figure 12 Figure (d) in the above-mentioned Figure 5 and

[0062] According to some embodiments of the present disclosure, the material of the control line 400 in the present disclosure can be a metal material such as copper or aluminum. The control line can be formed by deposition, so that the control line has good conductivity and is more conducive to improving the overall performance of the display substrate.

[0063] The formation process of the sharp discharge structure at the end of the control line 400 is described as follows:

[0064] According to some embodiments of the present disclosure, the sharp discharge structure at the second segment 420 and the third segment 440 of the control line 400 is taken as an example. No second connection part is arranged at this position. Referring to Figure 6 and Figure 13 The buffer layer 500, the second semiconductor part 40, the gate insulating layer 700, the control line 400, and the first connection part 51 are formed on the substrate 100, Figure 6 Figure (a) in the above-mentioned Figure 13 and Figure 13 Figure (b) in the above-mentioned Figure 13 and Figure 13 Figure (b) in the above-mentioned Figure 13 Figure 6 Figure (b) in the above-mentioned Figure 13 Figure 13and Figure 13 Figure (c) in the figure, the interlayer dielectric layer 600 is formed, and the interlayer dielectric layer 600 is etched (specifically, a series of processes such as coating-exposure-etching-peeling can also be used) to form the second via 2. Since the interlayer dielectric layer is a transparent structure, Figure 6 Figure (c) in the figure only shows the corresponding position of the second via 2 on the control line 400; after the formation of the second via 2, refer to Figure 13 and Figure 6 Figure (d) in the figure, the second conductive adapter 20 is formed, and Figure 14 It can be seen that the second conductive adapter 40 is arranged in a different layer from the control line 400, and the second conductive adapter 40 is electrically connected with the second segment 420 and the third segment 440 through the second via 2. The formation steps of the sharp discharge structure at the first segment 410 and the second segment 420 of the control line 400 are the same as the formation steps of the sharp discharge structure at the second segment 420 and the third segment 440, and will not be repeated here.

[0065] Referring to Figure 14 , in the display substrate, static electricity is easy to gather and release in the gate drive circuit area, Figure 1 The two edges of the rectangular frame pointed by the two groups of arrows in the figure can be regarded as the gate drive circuit area, and the four corners of the rectangular frame can be regarded as Figure 2 or ​ the end of the control line. In the present disclosure, by arranging a protruding sharp end at the end of the control line, a sharp discharge structure is formed, which can serve as a static electricity release structure and a static electricity protection structure, can effectively guide the static electricity to the end of the control line, and make the static electricity effectively released through the sharp discharge structure, thereby further avoiding the adverse effects caused by static electricity, and ensuring the normal transmission of signals; further, by arranging a second connecting part in the gate drive circuit area, and forming a double-layer wiring structure with the first connecting part and the second connecting part, the adverse effects of the static electricity release in the gate drive circuit area on the display substrate can be avoided, thereby ensuring the normal transmission of signals and improving the yield of products.

[0066] In another aspect of the present disclosure, a display device is provided. According to the embodiments of the present disclosure, the display device comprises the display substrate as described above, and thus has all the features and advantages of the display substrate as described above, which will not be repeated here. In general, the display device has good display effect, which is beneficial to improve the user experience.

[0067] The specific type of display device in the present disclosure is not particularly required, and a person skilled in the art can flexibly select according to actual needs, such as a mobile phone, an iPad, a notebook computer, etc. A person skilled in the art can understand that the display device has the structures and components necessary for a conventional display device in addition to the display substrate described above. Taking a mobile phone as an example, in addition to the display substrate described above, the mobile phone also includes a battery back cover, a middle frame, a touch panel, an audio module, a mainboard, etc.

[0068] The terms "first", "second", "third", "fourth", "fifth" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or a specific number of the technical features indicated. Therefore, the features defined with "first", "second", "third", "fourth", "fifth" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0069] In the description of the present specification, the description of the terms "one embodiment", "another embodiment", "yet another embodiment", "some embodiments", "other embodiments", "yet some embodiments" or "some specific embodiments" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, a person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0070] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and a person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate comprising a display area and a peripheral area at least partially surrounding the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of gate lines located in the display area and the peripheral area and electrically connected to the plurality of sub-pixels; a plurality of gate driving circuits located in the peripheral area and electrically connected to the plurality of gate lines; at least one control line located in the peripheral area and electrically connected to the plurality of gate driving circuits; the at least one control line comprises a first segment and a second segment spaced apart along a first direction, and the two end faces of the first segment and the second segment opposite to each other respectively have at least one protruding tip; a first conductive adapter located on the side of the at least one control line away from the substrate, and the first conductive adapter is electrically connected to the first segment and the second segment through a first via.

2. The display substrate of claim 1, wherein, The at least one control line further comprises a third segment, the second segment and the third segment are spaced apart along the first direction, and the two end faces of the second segment and the third segment opposite to each other respectively have at least one protruding tip, The display substrate further comprises a second conductive adapter, the second conductive adapter is located on the side of the at least one control line away from the substrate, and the second conductive adapter is electrically connected to the second segment and the third segment through a second via. 3.The display substrate of claim 2, wherein, The display substrate further comprises a first semiconductor part and a second semiconductor part, the first semiconductor part and the second semiconductor part are located on the side of the at least one control line close to the substrate, the first semiconductor part is located in the projection of the first conductive adapter on the substrate, and the second semiconductor part is located in the projection of the second conductive adapter on the substrate.

4. The display substrate according to any one of claims 1-3, wherein, The number of the at least one control line is two, and the two control lines are respectively located on opposite sides of the display area.

5. The display substrate according to any one of claims 1-3, wherein, The number of the at least one control line is four, and the four control lines are located on opposite sides of the display area, and each of the opposite sides has two control lines.

6. The display substrate according to any one of claims 1-3, wherein, The at least one control line is a power line.

7. The display substrate according to any one of claims 1-3, wherein, The display substrate further comprises: a connection line located in the peripheral area, the connection line is electrically connected to the gate line, and the projection of the connection line on the substrate overlaps the projection of the at least one control line on the substrate. 8.The display substrate of claim 7, wherein, The connection line comprises a first connection part and a second connection part, the first connection part is located on the side of the second connection part away from the substrate, the first connection part and the second connection part are electrically connected, and the projection of the first connection part on the substrate and the projection of the second connection part on the substrate at least partially overlap. 9.The display substrate of claim 8, wherein, The first connection part is electrically connected to the two ends of the second connection part through a third via and a fourth via, the third via is located on the side of the at least one control line close to the display area, and the fourth via is located on the side of the at least one control line away from the display area. 10.The display substrate of claim 8 or 9, wherein, The first connection part, the second connection part and the gate line extend along a second direction, and the first direction and the second direction intersect. 11.The display substrate of claim 8 or 9, wherein, The at least one control line has a plurality of holes penetrating the at least one control line, and a projection of the first connection portion and the second connection portion on the substrate intersects with a projection of the holes on the substrate. 12.The display substrate of claim 9, wherein, The plurality of sub-pixels comprise a pixel circuit, the pixel circuit comprises: A light shielding layer located on one side of the substrate; A semiconductor layer located on a side of the light shielding layer away from the substrate; A gate electrode located on a side of the semiconductor layer away from the substrate; and A source electrode and a drain electrode located on a side of the gate electrode away from the substrate. 13.The display substrate of claim 12, wherein, The display substrate comprises a second conductive adapter located on a side of the at least one control line away from the substrate, the first conductive adapter and the second conductive adapter are arranged in the same layer as the first connection portion, and are arranged in the same layer as the source electrode and the drain electrode. 14.The display substrate of claim 12, wherein, The display substrate further comprises: A buffer layer covering part of the surface of the substrate and the surface of the second connection portion away from the substrate; An interlayer dielectric layer arranged on a side of the buffer layer away from the substrate and covering at least one of the control lines, wherein the third via hole and the fourth via hole both penetrate the buffer layer and the interlayer dielectric layer; A gate insulating layer located between the buffer layer and the at least one control line.

15. A display device comprising: The display substrate comprises any one of claims 1-14.

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