NiO / Ga2O3 JFET with vertical structure and preparation method thereof

Abstract

This invention proposes a vertically structured NiO / Ga2O3 JFET and its fabrication method. The device structure, from bottom to top, consists of a drain metal layer, an N2O3 layer, and a NiO / Ga2O3 JFET. + Type Ga2O3 substrate, N ‑ Type Ga2O3 drift layer, P-type NiO layer, gate metal layer, Al2O3 isolation layer, ion-implanted Si + Highly doped N + The gate control region consists of a Ni / NiO / Ga2O3 heterostructure and a source metal layer. A fin-shaped structure is etched into the Ga2O3 drift layer, with a P-type NiO layer and a gate metal layer located sequentially on either side. This invention uses a Ni / NiO / Ga2O3 heterostructure to form the gate control region, replacing existing MOS structures. This facilitates enhancement-mode implementation and has greater potential in subsequent circuit and power module applications. Furthermore, JFET devices are buried trench devices, less affected by interface defects, which improves carrier mobility and device response speed.

Description

TECHNICAL FIELD

[0001] The present application relates to a vertical structure NiO / Ga2O3 JFET and a preparation method thereof, and belongs to the technical field of semiconductor devices. BACKGROUND

[0002] Gallium oxide (Ga2O3) material has an ultra-wide band gap and is one of the third-generation semiconductor materials that are currently concerned by academia and industry. Ga2O3 has five isomers, i.e., alpha, beta, gamma, delta, and epsilon (kappa), among which beta-Ga2O3 has the best thermal stability and is the most stable phase that is currently studied most and has the most mature technology. Most device researches are also based on beta-Ga2O3 material. The band gap of beta-Ga2O3 is about 4.9 eV, which is much higher than that of Si (1.12 eV), SiC (3.3 eV), and GaN (3.4 eV). Moreover, beta-Ga2O3 can realize stable N-type doping in the range of 10 cm to 10 cm. The breakdown field strength of beta-Ga2O3 reaches 8 MV / cm, and the Baliga's Figure of Merit is as high as 3444, which can effectively improve the breakdown voltage of power devices and reduce energy loss. However, there are still some technical challenges in the current Ga2O3 material, and there is a lack of stable P-type doping, so there is a lack of PN junction structure in device research, which greatly limits the device research. 16 cm -3 to 10 19 cm -3 However, there are still some technical challenges in the current Ga2O3 material, and there is a lack of stable P-type doping, so there is a lack of PN junction structure in device research, which greatly limits the device research.

[0003] The existing Ga2O3 transistor device research focuses on horizontal structure MOSFET, and there are also some researches on vertical structure MOSFET. In order to obtain a higher breakdown voltage, the horizontal structure power device needs to increase the distance between the drain and the gate, and the device size increases. In addition, the horizontal structure MOSFET device is difficult to withstand a large current, and the reported horizontal structure Ga2O3 MOSFET is difficult to realize enhancement, and the gate control ability is weak. Therefore, in the field of power semiconductors, vertical structure devices are the mainstream of practical application. Due to the lack of PN structure of Ga2O3 material, in order to realize effective gate control, the existing vertical structure Ga2O3 MOSFET adopts current aperture structure and fin type channel structure. Although some researches report enhancement of vertical structure Ga2O3 MOSFET, the current of these devices is greatly reduced compared with the depletion type device with the same parameters, and the practical application is also limited. The channel of Ga2O3 MOSFET device is often present on the surface, which is greatly affected by the defects between the gate dielectric and the Ga2O3 interface, and the device consistency and stability are insufficient. JFET devices have the potential to solve the above problems of MOSFET devices, and there are many JFET devices based on other materials in the existing research, but the research on vertical structure Ga2O3 JFET is still blank. Summary of the Invention

[0004] To address the limitations of existing Ga2O3 power transistors, this invention proposes a vertically structured NiO / Ga2O3 JFET device. This device uses a Ni / NiO / Ga2O3 heterojunction as the gate control region of the transistor, achieving enhancement mode and enabling it to withstand high voltage and high current.

[0005] The solution adopted in this invention is as follows:

[0006] A vertically structured NiO / Ga2O3 JFET includes a drain metal layer, an N2O3 electrode, and an N2O3 electrode, arranged sequentially from bottom to top. + Type Ga2O3 substrate, N - Type Ga2O3 drift layer, P-type NiO layer, gate metal layer, Al2O3 isolation layer, highly doped N + The region and the source metal layer. Among them, N... - A vertical fin structure is etched into the Ga2O3 drift layer, and a P-type NiO layer and a gate metal layer are sequentially stacked on both sides of the vertical fin structure; highly doped N + The region forms an ohmic contact with the source metal layer, and the drain metal layer forms an ohmic contact with the N. + Both Ga2O3 substrates have ohmic contacts.

[0007] Furthermore, the N + Type Ga2O3 substrate and N - The Ga2O3 drift layers all use β-Ga2O3 crystals.

[0008] Furthermore, the fin structure has a depth of 1 μm and a width of 300 nm.

[0009] Furthermore, the gate metal layer is Ni metal, and the thickness of the gate metal layer is 20-50 nm.

[0010] Furthermore, Ni metal, P-type NiO layer and N are used. - The heterojunction formed by the type Ga2O3 drift layer (3) forms the gate control region; wherein, the thickness of the P-type NiO layer is 30-60nm.

[0011] The method for fabricating the vertically oriented NiO / Ga2O3 JFET includes the following steps:

[0012] In N - Si was ion-implanted onto the surface of the Ga2O3 drift layer, followed by annealing; subsequently, after selecting the fin structure size, a metal mask was used to implant Si onto the N2O3 drift layer. - Vertical fin-shaped channels were etched into the Ga2O3 drift layer; then, in the N... +Ti / Au is grown on the back of Ga2O3 substrate as drain metal by EBE; then rapid thermal annealing is performed to realize ohmic contact of drain metal; + NiO material and Ni metal are grown on both sides of the fin-shaped channel in sequence, and high-doped N

[0013] Further, the specific steps of the method are:

[0014] (1) N - Si is ion implanted on the surface of Ga2O3 drift layer + High-doped N + region is formed, and annealing is performed in N2.

[0015] (2) The size of the fin-shaped structure is selected by electron beam lithography (EBL), and Pt metal mask is evaporated on the Ga2O3 drift layer by electron beam evaporation (EBE), then vertical fin-shaped structure is etched by ICP to form conductive channel for the device;

[0016] (3) Ti / Au is grown on the back of the substrate by EBE to form drain, and rapid thermal annealing is performed to realize ohmic contact of the drain;

[0017] (4) NiO material is co-grown on both sides of the fin-shaped structure by magnetron sputtering technology;

[0018] (5) Ni metal is grown on the outside of NiO as gate by EBE;

[0019] (6) For the sample treated in step (5), after the photoresist planarization process, ICP etching is performed to remove the gate metal Ni and NiO near the high-doped N + region;

[0020] (7) Al2O3 layer is grown by ALD method to isolate gate-source metal;

[0021] (8) For the sample treated in step (7), after the photoresist planarization process, ICP etching is performed to remove the excess Al2O3 on the top of the high-doped N + region;

[0022] (9) Ti / Au is evaporated on the top of the high-doped N + region to form gate, and ICP technology is used to etch the excess part to realize device isolation.

[0023] Further, in step (1), the doping concentration of the high-doped N + region is higher than 2×10 19 cm -3 .

[0024] Further, in the step (3), the annealing temperature is 500 DEG C, and the time length is 1 minute.

[0025] Further, in the step (6), the temperature for ALD growth of Al2O3 is 250 DEG C.

[0026] The vertical structure NiO / Ga2O3 JFET device involved in the application has the beneficial effects of:

[0027] (1) The P-type NiO material is used to effectively solve the problem of lack of P-type doping of Ga2O3 material, and a heterojunction is introduced in the Ga2O3 device to replace the missing PN junction.

[0028] (2) The Ni / NiO / Ga2O3 heterojunction structure is used as a gate control region instead of the traditional Ga2O3 MOS structure, and due to the band characteristics, the device is more likely to be enhancement mode, and has higher value in subsequent circuit design and power semiconductor applications.

[0029] (3) The Ga2O3 JFET proposed in the application is a buried trench device, and the channel is inside the Ga2O3 channel layer, which is less affected by the gate dielectric / Ga2O3 interface defects, and can effectively improve the response speed of the device.

[0030] (4) The JFET involved in the application adopts a vertical structure, which can withstand higher voltage and larger current than the horizontal structure device.

[0031] The vertical structure device has smaller size than the horizontal structure device under the same voltage resistance characteristics, saving the cost and space of the power module. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 The figure is a structure diagram of the vertical structure NiO / Ga2O3 JFET proposed in the application. Wherein, 1-metal layer of drain, 2-N + type Ga2O3 substrate, 3-N - type Ga2O3 drift layer, 4-P type NiO layer, 5-gate metal layer, 6-Al2O3 isolation layer, 7-highly doped N + region, 8-source metal layer.

[0033] Figure 2 The figure is a linear coordinate and semi-logarithmic coordinate transfer characteristic curve diagram of the vertical structure NiO / Ga2O3 JFET involved in the application.

[0034] Figure 3 The figure is a preparation flow chart of the vertical structure NiO / Ga2O3 JFET of the application. Wherein, Figure 3 (a) Figure 3(i) are schematic diagrams of steps (1) to (9) of the embodiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The described embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0036] This embodiment is a vertical NiO / Ga2O3 JFET device based on β-Ga2O3. The device substrate is 650 μm thick and is highly doped Si, with a doping concentration higher than 2 × 10⁻⁶. 18 cm -3 The drift layer is 10 μm thick and is lightly doped Si with a doping concentration of approximately 2 × 10⁻⁶. 16 cm -3 .like Figure 1 As shown, the device structure proposed in this invention is as follows: with N + Type Ga2O3 substrate 2 and N - The Ga2O3 drift layer 3 serves as the substrate, and a fin-shaped structure is etched into it. The fin-shaped structure is topped with ion-implanted Si. + Highly doped N + Region 7. The p-type NiO layer 4 and the gate metal layer 5 are located on either side of the fin structure. The Al2O3 isolation layer 6 is located outside the gate metal layer 5, isolating the gate metal layer 5 and the source metal layer 8. The source metal layer 8 is located on the highly doped N... + At the top of region 7, drain metal layer 1 is located in N. + Back side of Ga2O3 substrate 2. Ion implanted Si. + Highly doped N + Region 7 forms an ohmic contact with the source metal layer 8, and the drain metal layer 1 forms an ohmic contact with the N. + Both Ga2O3 substrates have ohmic contacts.

[0037] Furthermore, this invention provides a feasible fabrication method for NiO / Ga2O3 JFET devices, such as... Figure 3 (a)- Figure 3 As shown in (i), the steps include:

[0038] (1) In N - Ga2O3 drift layer 3 surface ion implantation Si + Forming highly doped N + Zone 7 has a doping concentration higher than 2×1019 cm -3 . And then annealing at 1000℃ for 30 minutes in N2 to reduce the contact resistance.

[0039] (2) The fin type structure size is selected by electron beam lithography (EBL), and Pt metal mask is evaporated on the Ga2O3 drift layer 3 by electron beam evaporation (EBE), and then the vertical fin type structure is etched by ICP to form the conductive channel of the device, with a depth of 1 μm and a width of 300 nm.

[0040] (3) Ti / Au is grown on the back of the substrate by electron beam evaporation (EBE) to form the drain, and then rapid thermal annealing at 500℃ for 1 minute is performed to realize the ohmic contact of the drain.

[0041] (4) NiO material is co-grown on both sides of the fin type structure by magnetron sputtering technology.

[0042] (5) Ni metal is grown as the gate outside the NiO by electron beam evaporation (EBE) technology.

[0043] (6) For the sample treated by step (5), after the photoresist planarization process, ICP etching is used to remove the gate metal Ni and NiO near the high-doped N + region 7.

[0044] (7) Al2O3 layer is grown by ALD method to isolate the gate and source metal.

[0045] (8) For the sample treated by step (7), after the photoresist planarization process, ICP etching is used to remove the excess Al2O3 at the top of the high-doped N + region 7.

[0046] (9) Ti / Au is evaporated on the top of the high-doped N + region 7 to form the gate, and ICP technology is used to etch the excess part to realize the isolation between devices.

[0047] The electrical characteristics of the NiO / Ga2O3 JFET device in the embodiment are simulated by Silvaco TCAD simulation software, Figure 2 which is the device transfer characteristic curve in linear coordinates and semi-logarithmic coordinates, indicating that the threshold voltage of the device is 0.24 V, and it is an enhancement type device.

Claims

1. A method for fabricating a vertical NiO / Ga2O3 JFET, comprising: The vertical structure NiO / Ga2O3 JFET comprises, from bottom to top, a drain metal layer (1), an N+ type Ga2O3 substrate (2), an N- type Ga2O3 drift layer (3), a P type NiO layer (4), a gate metal layer (5), an Al2O3 isolation layer (6), a high-doped N+ region (7), and a source metal layer (8); wherein the N- type Ga2O3 drift layer (3) is etched into a vertical fin type structure, and the P type NiO layer (4) and the gate metal layer (5) are sequentially stacked on both sides of the vertical fin type structure; the high-doped N+ region (7) and the source metal layer (8) form an ohmic contact, and the drain metal layer (1) and the N+ type Ga2O3 substrate (2) also form an ohmic contact; the N+ type Ga2O3 substrate (2) and the N- type Ga2O3 drift layer (3) both adopt β-Ga2O3 crystals; the fin type structure has a depth of 1 μm and a width of 300 nm; the gate metal layer (5) is Ni metal, and the gate metal layer (5) has a thickness of 20-50 nm; The steps of the method are as follows: 1) ion implantation of Si+ on the surface of the N- type Ga2O3 drift layer (3) to form a high-doped N+ region (7), and then annealing in N2; 2) selection of the fin type structure size by electron beam lithography (EBL), and deposition of a Pt metal mask on the Ga2O3 drift layer (3) by electron beam evaporation (EBE); then, etching of a vertical fin type structure by ICP to form a conductive channel for the device; 3) growth of Ti / Au on the back of the substrate by EBE to form a drain, and then rapid thermal annealing to achieve ohmic contact of the drain; 4) co-growth of NiO material on both sides of the fin type structure by magnetron sputtering technology; 5) growth of Ni metal as a gate on the outside of the NiO by EBE; 6) for the sample treated in step (5), ICP etching after a photoresist planarization process to remove the gate metal Ni and NiO near the high-doped N+ region (7); 7) growth of an Al2O3 layer to isolate the gate and source metals by ALD; 8) for the sample treated in step (7), removal of the excess Al2O3 at the top of the high-doped N+ region (7) by ICP etching after a photoresist planarization process; 9) deposition of Ti / Au on the top of the high-doped N+ region (7) by EBE to form a gate, and etching of the excess part by ICP to achieve isolation between devices.

2. The production method according to claim 1, characterized by, In step 1), the doping concentration of the highly doped N+ region (7) is higher than 2 x 1018 cm-3. 19 cm -3 .

3. The preparation method according to claim 1, characterized in that, In step 3), the annealing temperature is 500℃, and the time length is 1 minute.

4. The production method according to claim 1, characterized by, In step 7), the ALD growth temperature of Al2O3 is 250℃.

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