P+ shield layer self-clamping trench type silicon carbide IGBT device and preparation method thereof

Abstract

The application provides a trench type silicon carbide IGBT device with P+ shielding layer self-clamping and a preparation method thereof, and realizes automatic clamping of the P+ shielding layer potential by introducing an enhanced P-channel MOSFET structure: in the forward blocking area, the enhanced P-channel MOSFET is turned on, and the P+ shielding layer is automatically clamped at the low potential protection gate oxide layer; in the saturation area, the enhanced P-channel MOSFET is turned off, the P+ shielding layer keeps a floating state, and the near-surface layer carrier concentration is improved; in the active area, the enhanced P-channel MOSFET is turned on, the shielding layer potential is clamped, the saturation current is reduced, and the short-circuit capability of the device is improved. The application keeps the advantages of low forward conduction voltage and low switching loss under the premise of ensuring the reliability of the trench type silicon carbide IGBT device gate oxide layer, and takes into account the EMI noise characteristics and short-circuit capability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically a P+ shielding layer self-clamping trench silicon carbide IGBT device. Background Technology

[0002] Silicon carbide (SiC) is a representative of third-generation wide-bandgap semiconductor materials, possessing characteristics such as a large bandgap, high critical avalanche breakdown field strength, high thermal conductivity, and strong radiation resistance, making it a promising candidate for high-voltage, high-power systems. IGBT devices combine the advantages of simple drive circuitry of MOS field-controlled structures and strong bipolar on-state conduction capability, resulting in low conduction losses, high blocking voltage, fast switching speed, good high-temperature performance, and strong radiation resistance. SiC IGBTs mainly come in two types: planar gate and trench gate. Planar gate SiC IGBTs exhibit a JFET effect in the adjacent P-well region, significantly increasing their forward conduction voltage; while trench gate SiC IGBTs eliminate the JFET effect, increasing channel density and further enhancing the near-surface carrier concentration.

[0003] Although trench-gate silicon carbide IGBTs are more effective at mitigating the trade-off between on-state voltage drop and switching losses, when the IGBT is in the forward blocking state, the blocking voltage is borne by the P-well region and the reverse-biased PN junction in the drift region. When the device is at critical breakdown, the electric field strength in the gate oxide layer is much higher than the peak electric field strength in silicon carbide, approximately 2.5 times that of silicon carbide, leading to a sharp increase in the risk of failure due to gate oxide layer degradation. To address the problem of excessive electric field strength in the gate oxide layer during the blocking state, a P+ shielding layer at the bottom of the trench is typically used to weaken the electric field strength of the gate oxide layer and improve its reliability.

[0004] The P+ shielding layer exists in two states: emitter short-circuited and floating. An emitter short-circuited P+ shielding layer effectively reduces the electric field strength of the trench gate oxide layer, but it accelerates the extraction of non-equilibrium minority carriers, leading to a weakened conductivity modulation effect and an increased forward conduction voltage. A floating P+ shielding layer achieves a stronger conductivity modulation effect and reduces the forward conduction voltage, but the IGBT saturation current is larger with a floating P+ shielding layer, reducing its short-circuit capability. Simultaneously, the floating P+ shielding layer weakens its shielding ability against the gate oxide electric field. Furthermore, during the initial IGBT turn-on stage, the gate potential is low, and holes accumulate near the gate oxide layer, generating a displacement current that charges the gate capacitance. This weakens the gate resistance Rg's control over the IGBT turn-on, increasing EMI noise during device turn-on. Summary of the Invention

[0005] To address the aforementioned issues, this invention combines the advantages of emitter shorting and a floating P+ shielding layer, proposing a trench-type silicon carbide IGBT device with a self-clamped P+ shielding layer and its fabrication method. Automatic clamping of the P+ shielding layer potential is achieved by introducing an enhancement-mode P-channel MOSFET structure: When the IGBT operates in the forward blocking region, the gate-emitter voltage is zero or negative. At this time, the potential of the P+ shielding layer and the N-type base region will increase with the increase of the blocking voltage. When the potential difference between the N-type base region potential and the virtual gate reaches the threshold voltage of the enhancement-mode P-channel MOSFET, the enhancement-mode P-channel MOSFET turns on, and the P+ shielding layer is automatically clamped at a low potential to protect the gate oxide layer. When the IGBT operates in the saturation region, the gate-emitter voltage is positive. At this time, the collector-emitter voltage is small, the enhancement-mode P-channel MOSFET is turned off, and the P+ shielding layer remains in a floating state, increasing the near-surface carrier concentration and achieving a lower on-state voltage drop. When the IGBT operates in the active region, the collector-emitter voltage is large, the enhancement-mode P-channel MOSFET turns on, and the shielding layer switches to a clamping state, achieving a lower saturation current and improving the device's short-circuit capability. Due to the clamping of the P+ shield at low potential and the introduction of the virtual gate structure, the displacement current generated by hole accumulation near the gate oxide layer is reduced in the initial stage of IGBT turn-on, thereby reducing the EMI noise generated when the device is turned on. The device has a smaller Miller capacitance. This invention maintains the advantages of low forward conduction voltage and low switching loss while ensuring the reliability of the gate oxide layer of the trench silicon carbide IGBT device, and takes into account EMI noise characteristics and short-circuit capability.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A P+ shielded self-clamping trench-type silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. A groove is provided on the upper left side of the interior of the N-drift region 4, containing a polysilicon gate 9, a virtual polysilicon gate 91 to the right of the polysilicon gate 9, and a gate dielectric 10 filling the groove. A P-type base region 3 is located to the left of the groove, and a P+ shielding layer 22 is located to the lower right of the groove. An N-type base region is located above the P+ shielding layer 22. 31; The upper left of the P-type base region 3 is the P+ ohmic contact region 2, and the upper right of the P-type base region 3 is the N+ source region 8; the upper part of the N-type base region 31 is the second P+ ohmic contact region 21; the upper part of the P+ ohmic contact region 2 and the N+ source region 8 is the first emitter metal 1; the upper part of the virtual polysilicon gate 91 is the second emitter metal 12; the upper part of the second P+ ohmic contact region 21 is the third emitter metal 11; the upper part of the polysilicon gate 9 is the gate metal 14, and the part of the P-type base region 3 near the gate dielectric 10 is the channel of the device.

[0008] As a preferred embodiment, the gate dielectric is SiO2.

[0009] As a preferred embodiment, the P+ ohmic contact region 2, N+ source region 8, second P+ ohmic contact region 21, P-type base region 3, N-type base region 31 and P+ shielding layer 22 are all formed by multiple ion implantations.

[0010] As a preferred embodiment, the materials of the P+ substrate 6, N-type buffer layer 5, N-drift region 4, P+ ohmic contact region 2, N+ source region 8, second P+ ohmic contact region 21, P-type base region 3, N-type base region 31 and P+ shielding layer 22 of the device are all silicon carbide.

[0011] To achieve the above-mentioned objectives, the present invention also provides a second type of P+ shielded self-clamping trench silicon carbide IGBT device, comprising a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5; a groove is provided on the upper left side inside the N-drift region 4, and a polysilicon gate 9, a virtual polysilicon gate 91 below the polysilicon gate 9, and a gate dielectric 10 filling the groove are provided in the groove; a P-type base region 3 is on the left side of the groove, and a P+ shield is on the lower right side of the groove. Layer 22; above the P+ shielding layer 22 is an N-type base region 31; above the left of the P-type base region 3 is a P+ ohmic contact region 2, and above the right of the P-type base region 3 is an N+ source region 8; above the N-type base region 31 is a second P+ ohmic contact region 21; above the P+ ohmic contact region 2 and the N+ source region 8 is a first emitter metal 1; above the second P+ ohmic contact region 21 is a third emitter metal 11; above the polysilicon gate 9 is a gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 is the channel of the device.

[0012] To achieve the above-mentioned objectives, this invention also provides a third type of P+ shielding layer self-clamping trench silicon carbide IGBT device, comprising a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5; a groove filled with a polysilicon gate 9 and a gate dielectric 10 is provided on the upper left side of the interior of the N-drift region 4, a P-type base region 3 is on the left side of the groove, and a P+ shielding layer 22 is on the lower right side of the groove; an N-type base region 31 is on the upper left side of the interior of the P+ shielding layer 22; the P-type base region 31... The upper left corner is the P+ ohmic contact region 2, and the upper right corner of the P-type base region 3 is the N+ source region 8; the upper left side inside the N-type base region 31 is the second P+ ohmic contact region 21; the first emitter metal 1 is above the P+ ohmic contact region 2 and the N+ source region 8; the second gate dielectric 15 is above the N-type base region 31 and the P+ shielding layer 22; the third emitter metal 11 is above the second P+ ohmic contact region 21 and the second gate dielectric 15; the gate metal 14 is above the polysilicon gate 9, and the portion of the P-type base region 3 near the gate dielectric 10 is the device channel.

[0013] To achieve the above-mentioned objectives, this invention also provides a fourth type of P+ shielding layer self-clamping trench silicon carbide IGBT device, comprising a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5; the upper left side of the interior of the N-drift region 4 is provided with a groove filled with a polysilicon gate 9 and a first gate dielectric 10, the left side of the groove is a P-type base region 3, and the lower right side of the groove is a P+ shielding layer 22; the P+ shielding layer 2... Above the P-type base region 3 is an N-type base region 31; above the left of the P-type base region 3 is a P+ ohmic contact region 2, and above the right of the P-type base region 3 is an N+ source region 8; above the N-type base region 31 is a second P+ ohmic contact region 21; above the P+ ohmic contact region 2 and the N+ source region 8 is a first emitter metal 1; above the second P+ ohmic contact region 21 is a third emitter metal 11; above the polysilicon gate 9 is a gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 is the channel of the device.

[0014] To achieve the above-mentioned objectives, this invention also provides a fifth type of P+ shielded self-clamping trench silicon carbide IGBT device, comprising a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5; a groove filled with a polysilicon gate 9 and a gate dielectric 10 is provided on the upper left side of the interior of the N-drift region 4, a P-type base region 3 is on the left side of the groove, and a P+ shielding layer 22 is on the lower right side of the groove; a P+ ohmic contact region 2 is on the upper left side of the P-type base region 3, and an N+ source region 8 is on the upper right side of the P-type base region 3; an N+ field cutoff layer 16 is above the P+ shielding layer 22; a first emitter metal 1 is above the P+ ohmic contact region 2 and the N+ source region 8; a third emitter metal 11 is above the N+ field cutoff layer 16; a gate metal 14 is above the polysilicon gate 9, and the portion of the P-type base region 3 near the gate dielectric 10 forms the device channel.

[0015] To achieve the above-mentioned objectives, this invention also provides a method for fabricating a P+ shielding layer self-clamping trench silicon carbide IGBT device, comprising the following steps:

[0016] Step 1: Clean the epitaxial wafer, and implant aluminum ions into the N- epitaxial layer using polysilicon as an implantation barrier layer to form a P+ shielding layer;

[0017] Step 2: Epitaxial formation of P-type base region;

[0018] Step 3: Nitrogen ion implantation to form the N-type base region;

[0019] Step 4: Aluminum ion implantation to form the P+ ohmic contact region;

[0020] Step 5: Inject nitrogen ions to form an N+ source region and activate annealing;

[0021] Step 6: Etch the gate trench and dry oxidize to form a gate oxide layer, followed by annealing in a nitrogen atmosphere;

[0022] Step 7: Deposit polysilicon, perform ion implantation and annealing, and pattern the polysilicon;

[0023] Step 8: Deposit emitter and gate metal;

[0024] Step 9: Etching the metal to form the emitter electrode and gate electrode;

[0025] Step 10: Deposit current collector metal to form an electrode.

[0026] The device has a gate dielectric layer end as the gate electrode, a P+ substrate end as the collector electrode, and a P+ ohmic contact region and an N+ source region as the emitter electrode.

[0027] This invention introduces an enhanced P-channel MOSFET structure to achieve automatic clamping of the P+ shielding potential, thereby effectively reducing the electric field strength of the gate oxide layer while ensuring good forward conduction characteristics of the device when the device is in a forward blocking state. This reduces the switching losses and EMI noise during the turn-on process, and improves the short-circuit capability of the device. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a traditional silicon carbide IGBT device with a P+ shielding layer.

[0029] Figure 2 This is a schematic diagram of the structure of the P+ shielding layer self-clamping trench type silicon carbide IGBT device according to Embodiment 1 of the present invention.

[0030] Figure 3 This is a schematic diagram of embodiment 6 of the present invention, in which aluminum ions are injected into an N-epitaxy layer using polysilicon as an injection barrier layer to form a P+ shielding layer;

[0031] Figure 4 This is a schematic diagram of the epitaxial formation of a P-type base region in Embodiment 6 of the present invention;

[0032] Figure 5 This is a schematic diagram of nitrogen ion implantation to form an N-type base region in Embodiment 6 of the present invention;

[0033] Figure 6 This is a schematic diagram of the formation of a P+ ohmic contact region by aluminum ion implantation in Embodiment 6 of the present invention;

[0034] Figure 7 This is a schematic diagram of nitrogen ion implantation to form an N+ source region and activation annealing in Embodiment 6 of the present invention;

[0035] Figure 8 This is a schematic diagram of etching the gate trench and generating the gate oxide layer by dry oxygen oxidation in Embodiment 6 of the present invention;

[0036] Figure 9 This is a schematic diagram of the deposition and patterning of polysilicon in Embodiment 6 of the present invention;

[0037] Figure 10 This is a schematic diagram of the deposited emitter and gate metal in Embodiment 6 of the present invention;

[0038] Figure 11 This is a schematic diagram of etching metal to form the emitter electrode and the gate electrode in Embodiment 6 of the present invention;

[0039] Figure 12 This is a schematic diagram of the electrode formed by depositing current collector metal in Embodiment 6 of the present invention;

[0040] Figure 13 This is a schematic diagram of the P+ shielding layer self-clamping trench type silicon carbide IGBT device structure in Embodiment 2 of the present invention.

[0041] Figure 14 This is a schematic diagram of the structure of the P+ shielding layer self-clamping trench type silicon carbide IGBT device in Embodiment 3 of the present invention.

[0042] Figure 15 This is a schematic diagram of the P+ shielding layer self-clamping trench type silicon carbide IGBT device structure in Embodiment 4 of the present invention.

[0043] Figure 16 This is a schematic diagram of the P+ shielding layer self-clamping trench type silicon carbide IGBT device structure in Embodiment 5 of the present invention.

[0044] Figure 17 This is the equivalent circuit diagram of the P+ shielding layer self-clamping trench silicon carbide IGBT device of Embodiment 1 of the present invention;

[0045] 1 is the first emitter metal, 2 is the P+ ohmic contact region, 3 is the P-type base region, 4 is the N- drift region, 5 is the N-type buffer layer, 6 is the P+ substrate, 7 is the collector metal, 8 is the N+ source region, 9 is the polysilicon gate, 91 is the virtual polysilicon gate, 10 is the gate dielectric, 11 is the third emitter metal, 12 is the second emitter metal, 14 is the gate metal, 15 is the second gate dielectric, 16 is the N+ field cutoff layer, 12 is the second emitter metal, 22 is the P+ shielding layer, 31 is the N-type base region, and 21 is the second P+ ohmic contact region. Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Example 1

[0048] like Figure 2 As shown, a P+ shielded self-clamping trench silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. A groove is provided on the upper left side of the interior of the N-drift region 4, containing a polysilicon gate 9, a virtual polysilicon gate 91 to the right of the polysilicon gate 9, and a gate dielectric 10 filling the groove. A P-type base region 3 is located to the left of the groove, and a P+ shielding layer 22 is located to the lower right of the groove. An N-type base region 3 is located above the P+ shielding layer 22. Region 31; the upper left of the P-type base region 3 is the P+ ohmic contact region 2, and the upper right of the P-type base region 3 is the N+ source region 8; above the N-type base region 31 is the second P+ ohmic contact region 21; above the P+ ohmic contact region 2 and the N+ source region 8 is the first emitter metal 1; above the virtual polysilicon gate 91 is the second emitter metal 12; above the second P+ ohmic contact region 21 is the third emitter metal 11; above the polysilicon gate 9 is the gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 is the device channel.

[0049] As a preferred embodiment, the gate dielectric is SiO2.

[0050] As a preferred embodiment, the P+ ohmic contact region 2, N+ source region 8, second P+ ohmic contact region 21, P-type base region 3, N-type base region 31 and P+ shielding layer 22 are all formed by multiple ion implantations.

[0051] As a preferred embodiment, the materials of the P+ substrate 6, N-type buffer layer 5, N-drift region 4, P+ ohmic contact region 2, N+ source region 8, second P+ ohmic contact region 21, P-type base region 3, N-type base region 31 and P+ shielding layer 22 of the device are all silicon carbide.

[0052] This example introduces an enhanced P-channel MOSFET structure to achieve automatic clamping of the P+ shielding potential. This effectively reduces the electric field strength of the gate oxide layer while ensuring good forward conduction capability of the device when it is in a forward blocking state. It also reduces the switching loss and EMI noise during the turn-on process and improves the short-circuit capability of the device.

[0053] Example 2

[0054] This embodiment is obtained by modifying the left and right split gate structure of Embodiment 1 into a symmetrical top and bottom split gate structure.

[0055] like Figure 13As shown, a P+ shielded self-clamping trench silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. A groove is provided on the upper left side of the interior of the N-drift region 4, containing a polysilicon gate 9, a virtual polysilicon gate 91 below the polysilicon gate 9, and a gate dielectric 10 filling the groove. A P-type base region 3 is located to the left of the groove, and a P+ shielding layer 22 is located to the lower right of the groove. Above the shielding layer 22 is the N-type base region 31; above the left of the P-type base region 3 is the P+ ohmic contact region 2, and above the right of the P-type base region 3 is the N+ source region 8; above the N-type base region 31 is the second P+ ohmic contact region 21; above the P+ ohmic contact region 2 and the N+ source region 8 is the first emitter metal 1; above the second P+ ohmic contact region 21 is the third emitter metal 11; above the polysilicon gate 9 is the gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 is the device channel.

[0056] Example 3

[0057] The device comprises a planar enhancement-type P-channel MOSFET consisting of a third emitter metal 11, a second gate dielectric 15, a second P+ ohmic contact region 21, an N-type base region 31, and a P+ shielding layer 22.

[0058] like Figure 14 As shown, a P+ shielded self-clamping trench silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. A groove filled with a polysilicon gate 9 and a gate dielectric 10 is provided on the upper left side of the interior of the N-drift region 4. A P-type base region 3 is located to the left of the groove, and a P+ shielding layer 22 is located to the lower right of the groove. An N-type base region 31 is located on the upper left side of the interior of the P+ shielding layer 22. A P+ shielding layer 31 is located to the upper left of the interior of the P+ shielding layer 22. The P-type base region 3 has an N+ source region 8 located to the upper right of the P-type base region 31; the upper left side of the inside of the N-type base region 31 has a second P+ ohmic contact region 21; the P+ ohmic contact region 2 and the N+ source region 8 have a first emitter metal 1 above them; the N-type base region 31 and the P+ shielding layer 22 have a second gate dielectric 15 above them; the second P+ ohmic contact region 21 and the second gate dielectric 15 have a third emitter metal 11 above them; the polysilicon gate 9 has a gate metal 14 above it; and the portion of the P-type base region 3 near the gate dielectric 10 forms the device channel.

[0059] Example 4

[0060] The device forms a punch-through bipolar transistor by the second P+ ohmic contact region 21, the N-type base region 31, and the P+ shielding layer 22 to achieve automatic clamping of the P+ shielding layer potential.

[0061] likeFigure 15 As shown, a P+ shielded self-clamping trench silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. A groove filled with a polysilicon gate 9 and a first gate dielectric 10 is provided on the upper left side of the interior of the N-drift region 4. A P-type base region 3 is located to the left of the groove, and a P+ shielding layer 22 is located to the lower right of the groove. An N-type base region 3 is located above the P+ shielding layer 22. Region 31; the upper left of the P-type base region 3 is the P+ ohmic contact region 2, and the upper right of the P-type base region 3 is the N+ source region 8; above the N-type base region 31 is the second P+ ohmic contact region 21; above the P+ ohmic contact region 2 and the N+ source region 8 is the first emitter metal 1; above the second P+ ohmic contact region 21 is the third emitter metal 11; above the polysilicon gate 9 is the gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 is the channel of the device.

[0062] Example 5

[0063] The device forms a silicon carbide diode by means of the second P+ ohmic contact area 21 and the P+ shielding layer 22, thereby achieving automatic clamping of the P+ shielding layer potential.

[0064] like Figure 16 As shown, a P+ shielded self-clamping trench silicon carbide IGBT device includes a collector metal 7, a P+ substrate 6 above the collector metal 7, an N-type buffer layer 5 above the P+ substrate 6, and an N-drift region 4 above the N-type buffer layer 5. The upper left side of the N-drift region 4 has a groove filled with a polysilicon gate 9 and a gate dielectric 10. To the left of the groove is a P-type base region 3, and to the lower right of the groove is a P+ shielding layer 22. Above the left of the P-type base region 3 is a P+ ohmic contact region 2, and to the upper right of the P-type base region 3 is an N+ source region 8. Above the P+ shielding layer 22 is an N+ field cutoff layer 16. Above the P+ ohmic contact region 2 and the N+ source region 8 is a first emitter metal 1. Above the N+ field cutoff layer 16 is a third emitter metal 11. Above the polysilicon gate 9 is a gate metal 14, and the portion of the P-type base region 3 near the gate dielectric 10 forms the device channel.

[0065] Example 6

[0066] like Figures 3-12 As shown, this example provides a method for fabricating a P+ shielding layer self-clamping trench silicon carbide IGBT device, including the following steps:

[0067] Step 1: Clean the epitaxial wafer; implant aluminum ions onto the N- epitaxial layer using polysilicon as an implantation barrier to form a P+ shielding layer; (e.g., ...) Figure 3 As shown;

[0068] Step 2: Epitaxial formation of the P-type base region; such as... Figure 4As shown;

[0069] Step 3: Nitrogen ion implantation to form the N-type base region; such as... Figure 5 As shown;

[0070] Step 4: Aluminum ion implantation forms a P+ ohmic contact region; such as Figure 6 As shown;

[0071] Step 5: Inject nitrogen ions to form an N+ source region and activate annealing; such as Figure 7 As shown;

[0072] Step 6: Etch the gate trench and perform seventh oxidation to form the gate oxide layer, followed by annealing in a nitrogen atmosphere; as shown Figure 8 As shown;

[0073] Step 7: Deposit polycrystalline silicon, perform ion implantation and annealing, and pattern the polycrystalline silicon; such as... Figure 9 As shown;

[0074] Step 8: Deposit emitter and gate metal; such as Figure 10 As shown;

[0075] Step 9: Etching the metal to form the emitter electrode and gate electrode; such as Figure 11 As shown;

[0076] Step 10: Deposit the current collector metal to form the electrode. For example... Figure 12 As shown;

[0077] The device has a gate dielectric layer end as the gate electrode, a P+ substrate end as the collector electrode, and a P+ ohmic contact region and an N+ source region as the emitter electrode.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A P+ shielding layer self-clamping trench type silicon carbide IGBT device, characterized in that: Includes a collector metal (7), a P+ substrate (6) above the collector metal (7), an N-type buffer layer (5) above the P+ substrate (6), and an N-drift region (4) above the N-type buffer layer (5); the upper left side of the interior of the N-drift region (4) is provided with a groove filled with a polysilicon gate (9) and a gate dielectric (10), the left side of the groove is a P-type base region (3), and the lower right side of the groove is a P+ shielding layer (22); the upper left side of the interior of the P+ shielding layer (22) is an N-type base region (31); the upper left side of the P-type base region (3) is a P+ ohmic contact region (2), and the P-type base region (3) is a P+ ohmic contact region (2). The upper right is the N+ source region (8); the upper left of the N-type base region (31) is the second P+ ohmic contact region (21); the P+ ohmic contact region (2) and the N+ source region (8) are above the first emitter metal (1); the N-type base region (31) and the P+ shielding layer (22) are above the second gate dielectric (15); the second P+ ohmic contact region (21) and the second gate dielectric (15) are above the third emitter metal (11); the polysilicon gate (9) is above the gate metal (14), and the part of the P-type base region (3) near the gate dielectric (10) is the channel of the device.

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