Fractional clock divider

Abstract

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from the following applications, the contents of which are incorporated herein by reference in their entirety:

[0003] U.S. patent application Ser. No. 17 / 710,963, entitled “FRACTIONAL CLOCK DIVIDER,” filed on March 31, 2022;

[0004] U.S. provisional patent application entitled “FRACTIONAL CLOCK DIVIDER” and patent application number 63 / 281,738, filed on November 22, 2021. Technical Field

[0005] The subject matter described herein relates to clock generation, and more particularly, to clock generation with fractional frequency division. Background Art

[0006] In some transmitters and receivers, mixers are used to convert and downconvert data, respectively, between, for example, RF and baseband frequencies. In some embodiments, the RF frequency may be generated using a feedback-controlled frequency generation circuit, which may be sensitive to noise coupled into it at the fundamental RF frequency or its harmonics. Therefore, it may be beneficial to operate other circuitry at frequencies other than the fundamental RF frequency and its harmonics. Consequently, some circuits use clock divider circuits that divide the fundamental RF frequency by a non-integer factor. Summary of the Invention

[0007] One inventive aspect is a communication circuit. The communication circuit includes: a clock input; and a clock divider circuit configured to generate an output clock signal having a fundamental frequency substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein N is an integer, and wherein the clock divider circuit is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 Na specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

[0008] In some embodiments, 2 N +1 pre-aligned phase-shifted clock signals each have a fundamental frequency equal to 2 / (2 N +1) times.

[0009] In some embodiments, 2 N The pulse width of each of the +1 pre-aligned phase-shifted clock signals is substantially equal to the period of the input clock signal.

[0010] In some embodiments, based on the fact that each of the input clock signals has a fundamental frequency equal to 1 / (2 N +1) times the fundamental frequency 2(2 N +1) intermediate phase-shifted clock signals to generate 2 N +1 pre-aligned phase-shifted clock signal.

[0011] In some embodiments, 2 N The fundamental frequency of each of the specific shift clock signals is equal to 2 / (2 N +1) times.

[0012] In some embodiments, 2 N The pulse width of each of the specific shift clock signals has a pulse width substantially equal to twice the period of the input clock signal.

[0013] In some embodiments, 2 N Each of the specific shift clock signals corresponds to 2 N +1 A phase-shifted version of one of the pre-aligned phase-shifted clock signals.

[0014] In some embodiments, the pulse width of the output clock signal is substantially equal to twice the period of the input clock signal.

[0015] Another inventive aspect is a clock divider circuit configured to generate an output clock signal having a fundamental frequency substantially equal to a fundamental frequency of an input clock signal divided by a factor (2 N +1) / 2 N , where N is an integer. The clock divider circuit includes: 2 N +1 frequency division circuit, the 2 N The +1 divide-by-one circuit is configured to generate 2(2 N +1) intermediate phase-shifted clock signals; a 2-frequency multiplication circuit configured to receive 2 (2 N +1) intermediate phase-shifted clock signals and based at least in part on the received 2(2 N+1) intermediate phase-shifted clock signals to generate 2 N +1 pre-aligned phase-shifted clock signal; a phase adjustment circuit configured to receive 2 N +1 pre-aligned phase-shifted clock signal and based at least in part on the received 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degrees of separation; and 2 N / 2 frequency multiplication circuit, the 2 N The / 2 frequency multiplication circuit is configured to receive 2 N a specific phase-shifted clock signal and based at least in part on the received 2 N A specific phase-shifted clock signal is used to generate the output clock signal.

[0016] In some embodiments, 2 N The divide-by-1 circuit includes a first barrel shifter circuit and a second barrel shifter circuit configured to shift in response to an input clock signal.

[0017] In some embodiments, the frequency multiplication circuits include circuits each configured to multiply multiples of 2 (2 N +1) Multiple logic circuits that perform a logical OR function on the intermediate phase-shifted clock signal.

[0018] In some embodiments, the phase adjustment circuit includes a circuit configured to generate 2 N +1 multiple delay circuits that pre-align delayed versions of the phase-shifted clock signal.

[0019] In some embodiments, the delay of the delay circuit is controlled so that 2 N +1 pre-aligned phase-shifted clock signal delayed versions of the first delayed version and 2 N The second delayed version of the delayed versions of the +1 pre-aligned phase-shifted clock signals overlaps.

[0020] In some embodiments, 2 N The / 2 frequency multiplication circuits include circuits each configured to N A plurality of first logic circuits are configured to execute a logic OR function on a plurality of logic signals generated by a specific phase-shifted clock signal.

[0021] In some embodiments, 2 N / 2 frequency multiplication circuits include each configured to multiple 2 N The second logic circuits perform a logic AND function on the specific phase-shifted clock signals to generate a plurality of second logic signals.

[0022] In some embodiments, the output clock signal is differential, and wherein 2 N The / 2 frequency multiplication circuit includes a non-overlap circuit configured to cause the differential output clock signals to non-overlap.

[0023] Another inventive aspect is a method of operating a communication circuit. The method comprises: generating, using a clock divider circuit, an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal divided by a factor (2 N +1) / 2 N , wherein N is an integer, and wherein generating the output clock signal comprises generating 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on the 2 N generating an output clock signal by using a specific phase-shifted clock signal; and receiving the output clock signal by using a mixer.

[0024] In some embodiments, 2 N +1 pre-aligned phase-shifted clock signals each have a fundamental frequency equal to 2 / (2 N +1) times.

[0025] In some embodiments, based on the fact that each of the input clock signals has a fundamental frequency equal to 1 / (2 N +1) times the fundamental frequency 2(2 N +1) intermediate phase-shifted clock signals to generate 2 N +1 pre-aligned phase-shifted clock signal.

[0026] In some embodiments, 2 N The fundamental frequency of each of the specific shift clock signals is equal to 2 / (2 N +1) times. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed embodiments.

[0028] Figure 1 is a schematic diagram of a transmitter circuit according to an embodiment.

[0029] Figure 2 A schematic diagram illustrating a portion of a transmitter or receiver circuit according to some embodiments is shown.

[0030] Figure 3 A schematic diagram of a clock divider circuit according to some embodiments is shown.

[0031] Figure 4 A schematic diagram of a clock divider circuit according to some embodiments is shown.

[0032] Figure 5 shows a diagram illustrating a method according to some embodiments Figure 4 A waveform diagram of the operation of the clock divider circuit.

[0033] Figure 6 A schematic diagram illustrating a clock multiplier and an adjustable delay circuit according to some embodiments is shown.

[0034] Figure 7 and Figure 8 shows a diagram illustrating a method according to some embodiments Figure 6 Waveform diagram of the operation of the clock multiplier and adjustable delay circuit.

[0035] Figure 9 A schematic diagram of a clock multiplier circuit according to some embodiments is shown.

[0036] Figure 10 shows a diagram illustrating a method according to some embodiments Figure 9 A waveform diagram of the operation of the clock multiplier circuit.

[0037] Indeed, similar reference numerals indicate similar structures, features, or elements. DETAILED DESCRIPTION

[0038] As discussed in further detail below, the embodiments discussed herein illustrate circuits and methods for generating clocks having frequencies that are non-integer fractions of a reference clock.

[0039] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form a part of this specification. The subsequent description provides only (multiple) embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the following description of (multiple) embodiments will provide those skilled in the art with an implementation description for implementing one or more embodiments. It should be understood that various changes can be made in the functions and arrangements of the elements without departing from the spirit and scope of the present disclosure. In the following description, for the purpose of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it is apparent that the various embodiments can be implemented without these specific details. The drawings and descriptions are not intended to be restrictive. The words "example" or "exemplary" are used herein to mean "used as an example, instance or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be interpreted as being preferred or advantageous over other embodiments or designs.

[0040] Figure 1 FIG1 is a schematic diagram of an embodiment of a transmitter circuit 100 according to an embodiment. The transmitter circuit 100 includes an antenna or antenna array 110, a switch 120, an RF link 130, and a controller 140. The transmitter circuit 100 illustrates a specific example. Other embodiments of the transmitter circuit may also be used.

[0041] Antenna or antenna array 110 can be any antenna or antenna array. For example, in some embodiments, antenna or antenna array 110 includes one, two, three, four, or more antennas. In some embodiments, antenna or antenna array 110 includes a linear antenna array. In some embodiments, antenna or antenna array 110 includes a two-dimensional antenna array, such as a linear antenna array having multiple rows.

[0042] In embodiments where antenna or antenna array 110 includes one antenna, the one antenna can be directly connected to RF link 130, and switch 120 can be omitted. In embodiments where antenna or antenna array 110 includes multiple antennas, each antenna can be directly connected to a separate RF link. Each RF link can have the characteristics of RF link 130.

[0043] Antenna or antenna array 110 can be configured to transmit an RF signal to a receiver circuit. The RF signal comprises a high-frequency signal at a carrier frequency modulated by a low-frequency information signal. As controlled by controller 140, for example, based on a programmable electrical connection formed by switch 120, the high-frequency signal is transmitted by one of the antennas in antenna array 110.

[0044] The controller 140 is configured to provide a digital signal to the RF link 130 , wherein the digital signal encodes an information signal to be transmitted by the antenna or antenna array 110 .

[0045] RF chain 130 includes a digital-to-analog converter circuit (DAC) 132, a mixer 136, a frequency synthesizer 134, and a power amplifier (PA) 138. RF chain 130 is merely an example, and other RF chain embodiments may alternatively be used. For example, as will be appreciated by those skilled in the art, in some embodiments, one or more amplifiers and / or filters may be included.

[0046] The digital signal is processed by digital-to-analog converter 132 using techniques known in the art to generate an analog baseband signal (BB signal) representing the digital signal. Various digital-to-analog converter structures known in the art can be used.

[0047] Mixer 136 receives the analog baseband signal output from digital-to-analog converter 132 and the oscillator signal at the carrier frequency generated by frequency synthesizer 134. In response to the analog baseband signal and the oscillator signal, mixer 136 up-converts the analog baseband signal from analog-to-digital converter 132 into a high-frequency signal using techniques known in the art. Various mixer structures known in the art can be used. The resulting high-frequency signal is modulated at the carrier frequency so as to include information from the low-frequency information signal.

[0048] The power amplifier 138 is configured to receive a high frequency signal and drive the high frequency signal to one of the antennas in the antenna array 110, for example, according to a programmable electrical connection formed by the switch 120, as controlled by the controller 140. The power amplifier 138 drives the high frequency signal to one of the antennas using techniques known in the art. Various power amplifier structures known in the art can be used.

[0049] As will be appreciated by those skilled in the art, using a communication connection ( Figure 1 ), control signals from controller 140 may control certain variable functions of, for example, switch 120, power amplifier 138, frequency synthesizer 134, mixer 136, and digital-to-analog converter 132, as will be appreciated by those skilled in the art.

[0050] The control signal from the controller 140 may, for example, control the switch 120 to control which of the multiple antennas the RF chain 130 utilizes to drive the high frequency signal.

[0051] In embodiments with multiple antennas, each connected to one of the multiple RF chains, the controller 140 may generate a control signal for each of the RF chains.

[0052] Figure 2 1 shows a schematic diagram of a portion 200 of a frequency synthesizer circuit of a transmitter or receiver circuit according to some embodiments. The frequency synthesizer circuit may have Figure 1 The circuit portion 200 includes a clock divider 210, which may be included in the frequency synthesizer 134. Figure 1 The frequency synthesizer 134 of the circuit part also includes a mixer 220. The mixer 220 can have Figure 1 The mixer 136 may have similar or identical features to the mixer 136. The mixer may be any mixer circuit known to those skilled in the art.

[0053] The clock divider 210 receives an input differential clock signal INP-INN, for example, generated at least in part by a local oscillator circuit. The received input differential clock signal has a fundamental frequency, such as an RF frequency. Based on the received input differential clock signal, the clock divider 210 generates a clock signal having a fundamental frequency equal to the fundamental frequency divided by (2 N +1) / 2 N The output differential clock signal has a frequency of , where N is an integer.

[0054] Mixer 220 is configured to receive the output differential clock signal from clock divider 210 and upconvert or downconvert the information-bearing signal, for example, between an RF frequency and a baseband frequency.

[0055] Figure 3 FIG2 shows a schematic diagram of a clock divider circuit 300 according to some embodiments. The clock divider circuit 300 can be used as Figure 2 In some embodiments, the clock divider 210 of the clock divider 210 is a clock divider or a part thereof. Figure 2 The clock divider 210 uses a different Figure 3 The circuit is specifically shown in FIG.

[0056] Figure 3 The clock divider circuit 300 divides the input differential clock by 9 / 8. The circuit embodiment shown can be modified by those skilled in the art to divide the input differential clock by other factors, such as (2 N +1) / 2 N is any factor of the characteristic, where N is an integer. In the example embodiment shown, N is equal to 3. In other embodiments, N can also be a different number.

[0057] Figure 3The clock divider circuit 300 receives an input differential clock signal, for example, generated at least in part by a local oscillator circuit. The received input differential clock signal has a fundamental frequency, such as an RF frequency. Based on the received input differential clock signal, the clock divider circuit 300 generates a clock signal having a fundamental frequency equal to the fundamental frequency divided by (2 3 +1) / 2 3 =9 / 8 of the output differential clock signal OUTP–OUTN.

[0058] Figure 3 The clock divider circuit 300 includes 2 N +1 frequency division circuit 310, 2 frequency multiplication circuit 320, phase adjustment circuit 330 and 2 N / 2 frequency multiplication circuit 340.

[0059] 2 N +1 divide-by-one circuit 310 receives an input differential clock signal. In the embodiment shown, 2 N The +1 divide-by-1 circuit 310 divides the input differential clock signal by 9 and generates 18 phase-shifted clock signals each having a frequency equal to the fundamental frequency divided by 9.

[0060] The following discusses the use of N +1 frequency dividing circuit 310 2 N +1 frequency divider circuit embodiment. Other 2 N +1 frequency division circuit.

[0061] 2 times the frequency circuit 320 from 2 N The +1 divide-by-one circuit 310 receives 18 phase-shifted clock signals and generates 9 phase-shifted clock signals, wherein each of the 9 phase-shifted clock signals has a frequency equal to 2 times the base frequency divided by 9.

[0062] Discussed below are embodiments of frequency doubling circuits that may be used as or as part of frequency doubling circuit 320. Other frequency doubling circuits may also be used.

[0063] In this embodiment, the phase adjustment circuit 330 receives the nine phase-shifted clock signals from the frequency doubling circuit 320 and generates eight phase-shifted clock signals, wherein the eight phase-shifted clock signals are separated in phase by substantially the same phase. Therefore, the eight phase-shifted clock signals are separated in phase by an angle equal to or substantially equal to 360 / 8 = 45 degrees.

[0064] Discussed below are embodiments of phase adjustment circuits that may be used as or as part of phase adjustment circuit 330. Other phase adjustment circuits may also be used.

[0065] 2 NThe / 2 frequency multiplication circuit 340 receives eight phase-shifted clock signals from the phase adjustment circuit 330 and generates an output differential clock signal OUTP-OUTN, wherein the frequency of the output differential clock signal OUTP-OUTN is equal to the base frequency multiplied by 1 / (2 N +1)x2x2 N / 2 / or divided by (2 N +1) / 2 N .

[0066] The following discussion can be used as or part of 2 N 2 / 2 frequency multiplication circuit 340 N / 2 frequency multiplication circuit embodiment. Other 2 can also be used N / 2 frequency multiplication circuit.

[0067] Figure 4 shows a method configured to divide an input clock by 2 according to some embodiments. N +1 of 2 N Schematic diagram of +1 frequency division circuit 400, where N=3.2 N +1 divider circuit 400 can be used as Figure 3 2 N +1 frequency dividing circuit 310. In some embodiments, the other 2 N The +1 divider circuit is used as Figure 3 2 N +1 frequency dividing circuit 310.

[0068] Figure 4 2 shown in N The +1 divider circuit 400 receives the input differential clock signal INP-INN. In the embodiment shown, 2 N +1 frequency dividing circuit 400 divides the input differential clock signal by 9(2 N +1) and generates 18 2 / (2 N In addition, the pulse width of each of the phase-shifted clock signals is substantially equal to the period of the input clock signal.

[0069] In the embodiment shown, 2 N The divide-by-1 circuit 400 includes first and second resettable barrel shifter circuits 410 and 420 .

[0070] The first resettable barrel shifter circuit 410 includes nine resettable flip-flops, each of which is configured to generate an output of a next flip-flop based on an input from a previous flip-flop in response to a clock input at an input INN, as shown. The first resettable barrel shifter circuit 410 is reset so that output A3 is high, while its other outputs A1, A2, and A4-A9 are low.

[0071] The second resettable barrel shifter circuit 420 includes nine resettable flip-flops, each of which is configured to generate an output of a next flip-flop based on an input from a previous flip-flop in response to a clock input INP, as shown. The second resettable barrel shifter circuit 410 is reset so that the output B3 is high and its other outputs B1, B2, and B4-B9 are low.

[0072] Figure 5 shows a diagram illustrating a method according to some embodiments Figure 4 1 is a waveform diagram of the operation of the clock divider circuit 400.

[0073] As shown, when reset signals CDN1 and CDN2 are low, outputs B3 and A3 are high, while the other outputs B1, B2, B4-B9, A1, A2, and A4-A9 are low. Reset signal CDN2 goes high at both falling edges of input clock INP after reset signal Resetn goes high. Furthermore, reset signal CDN1 goes high at one falling edge of input clock INN after reset signal CDN2 goes high. Thereafter, when reset signal CDN1 is high, one of the Ax outputs of first barrel shifter circuit 410 goes high, with which of the Ax outputs is high rotating through the Ax outputs, starting with output A4, and changing in response to each subsequent falling edge of input clock INN. Furthermore, when the reset signal CDN2 is high, one of the Bx outputs of the second barrel shifter circuit 420 is high, where which of the Bx outputs is high rotates through the Bx outputs starting from output B4 and changes in response to each subsequent falling edge of the input clock INP.

[0074] Figure 6 FIG. 6 is a schematic diagram showing a clock multiplier circuit 610 and an adjustable delay circuit 620 according to some embodiments. The clock multiplier circuit 610 may be used as Figure 3 In some embodiments, other clock multiplier circuits are used as Figure 3 The adjustable delay circuit 620 can be used as a double frequency circuit 320 or a part thereof. Figure 3 In some embodiments, other adjustable delay circuits are used as a part of or as a part of the phase adjustment circuit 330. Figure 3 The phase adjustment circuit 330 is or serves as a part thereof.

[0075] The clock multiplier circuit 610 and the adjustable delay circuit 620 form nine signal paths, each of which includes nine (2 N+1) one of the two frequency multiplication parts and one of the nine phase adjustment parts of the adjustable delay circuit 620.

[0076] Each of the 2x frequency multiplication sections of the clock multiplier circuit 610 receives an output Ax from the first barrel shifter circuit 410 as a first input and an output Bx from the second barrel shifter circuit 420 as a second input. In this embodiment, each of the 2x frequency multiplication sections includes a NOR gate that performs a NOR logic function on the first and second inputs. Accordingly, each of the 2x frequency multiplication sections of the clock multiplier circuit 610 receives two of the 18 phase-shifted clock signals from the clock divider circuit 400. Furthermore, each of the 2x frequency multiplication sections of the clock multiplier circuit 610 generates a multiplied clock signal / (Bx+Ax) or / (Ax+Bx) having a frequency equal to 2 times the base frequency divided by 9.

[0077] The clock multiplier circuit 620 has nine (2 N Each of the phase adjustment sections (+1) receives one of the multiplied clock signals / (Bx+Ax) or / (Ax+Bx) and generates a phase-shifted clock signal D / (Bx+Ax) or D / (Ax+Bx). Each phase adjustment section includes multiple buffer or inverter stages, where the delay of each stage is affected or controlled by a control signal DELAY.

[0078] A control signal DELAY is used to control the delay of the buffer or inverter stage so that the first of the phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx) overlaps with the last of the phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx). Accordingly, in the illustrated embodiment, nine phase adjustment sections receive the nine phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx) generated by the nine multiplication sections and generate nine phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx), wherein two of the phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx) overlap. Accordingly, the nine phase adjustment parts generate eight specific phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx), wherein the eight specific phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx) are separated in phase by equal to or substantially equal to 360 / 8=45 degrees.

[0079] Figure 7 shows a diagram illustrating a method according to some embodiments Figure 6 FIG. 6 is a waveform diagram of the doubled-frequency clock signal output / (Bx+Ax) or / (Ax+Bx) of the doubled-frequency portion of the clock multiplier circuit 610. As shown, the frequency of each of the doubled-frequency clock signals / (Bx+Ax) or / (Ax+Bx) is equal to 2 times the fundamental frequency divided by 9 (2N +1). In addition, the pulse width of each of the frequency-multiplied clock signals / (Bx+Ax) or / (Ax+Bx) is substantially equal to the period of the input clock signal.

[0080] Figure 8 shows a diagram illustrating a method according to some embodiments Figure 6 6 is a waveform diagram of the phase-shifted clock signals D / (Bx+Ax) or D / (Ax+Bx) of the phase adjustment portion of the clock multiplier circuit 610. As shown, the first phase-shifted clock signal DB5+A9 among the phase-shifted clock signals is aligned with and overlaps with the phase-shifted clock signal DB9+A4 among the phase-shifted clock signals. Accordingly, the eight specific phase-shifted clock signals DB5+A9, DA5+B1, DB6+A1, DA6+B2, DB7+A2, DA7+B3, DB8+A3, and DA8+B4 are separated in phase by the same phase, which is equal to or substantially equal to 360 / 8 = 45 degrees. In addition, the frequency of each of the eight specific phase-shifted clock signals DB5+A9, DA5+B1, DB6+A1, DA6+B2, DB7+A2, DA7+B3, DB8+A3 and DA8+B4 is equal to 2 times the fundamental frequency divided by 9 (2N+1), and the pulse width of each of the eight specific phase-shifted clock signals DB5+A9, DA5+B1, DB6+A1, DA6+B2, DB7+A2, DA7+B3, DB8+A3 and DA8+B4 is substantially equal to the period of the input clock signal.

[0081] The alignment of the phase-shifted clock signals DB5+A9 and DB9+A4 is achieved by controlling the delay of a buffer or inverter stage of the phase adjustment portion of the adjustable delay circuit 620 using a control signal DELAY. For example, the control signal DELAY can be an analog voltage, and the buffer or inverter stage can have a delay that is affected or controlled by the analog voltage of the control signal DELAY. The analog voltage of the control signal DELAY can be generated using a phase detection circuit that detects the phase difference between the phase-shifted clock signals DB5+A9 and DB9+A4 and increases or decreases the analog voltage of the control signal DELAY based on the detected phase difference, wherein the increase or decrease in the analog voltage of the control signal DELAY reduces the phase difference between the phase-shifted clock signals DB5+A9 and DB9+A4. The phase detection circuit can include, for example, a phase frequency detector (PFD) circuit or the like.

[0082] Figure 9 FIG2 shows a schematic diagram of a clock multiplier circuit 900 according to some embodiments. The clock multiplier circuit 900 can be used as Figure 3 2 N / 2 frequency multiplication circuit 340 or used as part thereof. In some embodiments, other clock multiplier circuits are used as Figure 3 2 N / 2 frequency multiplication circuit 340 or a portion thereof. In this embodiment, the clock multiplier circuit multiplies the frequency of the clock by 2 N / 2=4.

[0083] The AND gate 910 of the clock multiplier circuit 900 is connected by Figure 6 The adjacent phase-shifted clock signals DB5+A9 and DA5+B1, DB6+A1 and DA6+B2, DB7+A2 and DA7+B3, DB8+A3 and DA8+B4, DA5+B1 and DB6+A1, DA6+B2 and DB7+A2, DA7+B3 and DB8+A3, and DA8+B4 and DB5+A9 generated by the phase adjustment portion of the clock multiplier circuit 610 perform an AND logic function to generate eight clock signals CP1, CP2, CP3, CP4, CN1, CN2, CN3, and CN4. In addition, the frequency of each of the eight clock signals CP1, CP2, CP3, CP4, CN1, CN2, CN3, and CN4 is equal to 2 times the base frequency divided by 9 (2 N +1), and the pulse width of each of the eight clock signals CP1, CP2, CP3, CP4, CN1, CN2, CN3 and CN4 is substantially equal to half a period of the input clock signal.

[0084] The OR gate 920 of the clock multiplier circuit 900 performs a first OR logic function on a first group of clock signals including the clock signals CP1, CP2, CP3, and CP4 to generate a first OR logic signal CP, and performs a second OR logic function on a second group of clock signals including the clock signals CN1, CN2, CN3, and CN4 to generate a second OR logic signal CN. In addition, the frequency of each of the clock signals CP and CN is equal to 4 (2 N ) times divided by 9(2 N +1), and the pulse width of each of the clock signals CP and CN is substantially equal to a half period of the input clock signal.

[0085] The cross-coupled NOR gates 930 of the clock multiplier circuit 900 receive the first and second ORed clock signals CP and CN and generate signals for the inverter 940. Based on these signals, the inverter 940 generates the output clock signals OUTP and OUTN. The cross-coupled NOR gates 930 form a non-overlapping circuit and ensure that adjacent pulses of the output clock signals OUTP and OUTN ideally do not overlap. In addition, the frequency of each of the output clock signals OUTP and OUTN is equal to 4 (2N ) times divided by 9(2 N +1), and the pulse width of each of the output clock signals OUTP and OUTN is substantially equal to a half period of the input clock signal.

[0086] Figure 10 shows a diagram illustrating a method according to some embodiments Figure 9 1 is a waveform diagram of the operation of the clock multiplier circuit 900.

[0087] As shown in the figure, due to the AND operation of AND gates 910, the positive pulse ratio of the CP1 to CP4 and CN1 to CN4 clock signals is Figure 8 The phase-shifted clock signals DB5+A9, DA5+B1, DB6+A1, DA6+B2, DB7+A2, DA7+B3, DB8+A3, and DA8+B4 are narrower. In addition, due to the OR operation of the OR gates, the frequencies of the output clock signals OUTP and OUTN are Figure 8 Four times the frequency of the phase-shifted clock signals DB5+A9, DA5+B1, DB6+A1, DA6+B2, DB7+A2, DA7+B3, DB8+A3 and DA8+B4.

[0088] Accordingly, in this embodiment, by utilizing 2 N +1 frequency dividing circuit 400 divides the input differential clock INP-INN by (2 N +1) frequency division, using the 2-frequency multiplication part of the clock multiplier circuit 610 to perform 2-frequency multiplication, and using the phase adjustment part of the adjustable delay circuit 620 to perform phase adjustment to generate 2 N A specific phase shift clock, and a frequency multiplier circuit 900 with 2 N / 2 multiplication to generate the output clock signals OUTP and OUTN.

[0089] As a result, the frequency of the output differential clock signal is equal to the fundamental frequency of the input differential clock signal multiplied by 2x2 N / 2 / (2 N +1) or divided by (2 N +1) / 2 N As a result, the fundamental frequency and at least the low-order harmonics of the output differential clock signal are different from the fundamental frequency and at least the low-order harmonics of the input differential clock signal.

[0090] One or more aspects or features of the subject matter described herein can be implemented in digital electronic circuit systems, integrated circuit systems, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) computer hardware, firmware, software, and / or combinations thereof. These different aspects or features can be included in embodiments of one or more computer programs executable and / or interpretable on a programmable system, the programmable system including at least one programmable processor, which can be dedicated or general-purpose, coupled to receive data and instructions from a storage system, at least one input device, and at least one output device, and to transmit data and instructions thereto. A programmable system or computing system can include a client and a server. The client and the server are typically remote from each other and typically interact via a communication network. The relationship between the client and the server is generated by a computer program running on respective computers and having a client-server relationship with each other.

[0091] These computer programs (which may also be referred to as programs, software, software applications, applications, components or codes) include machine instructions for programmable processors and can be implemented in high-level procedural languages, object-oriented programming languages, functional programming languages, logic programming languages ​​and / or in assembly / machine languages. As used herein, the term "machine-readable medium" refers to any computer program product, device and / or apparatus (such as a disk, optical disk, memory and programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor. A machine-readable medium can store such machine instructions in a non-transient manner, such as a non-transient solid-state memory or a magnetic hard drive or any equivalent storage medium. A machine-readable medium can alternatively or additionally store such machine instructions in a transient manner, such as a processor cache or other random access memory associated with one or more physical processor cores.

[0092] In the above description and claims, phrases such as "at least one of ... " or "one or more of ... " may appear after a joint list of elements (components) or features. The term "and / or" may also appear in a list of two or more elements or features. Unless the context of its use contradicts implicitly or explicitly, such a phrase is intended to represent any one of the listed elements or features individually, or to represent any one of the listed elements or features in combination with any one of the other listed elements or features. For example, the phrases "at least one of A and B", "one or more of A and B", and "A and / or B" are each intended to represent "only A, only B, or A and B together". A similar interpretation is also intended to be used for a list including three or more items. For example, the phrases "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, and / or C" are each intended to represent "only A, only B, only C, A and B together, A and C together, B and C together, or A and B and C together". Use of the term "based on" above and in the claims is intended to mean "based, at least in part, on" such that unrecited features or elements are also permissible.

[0093] Depending on the desired configuration, the subject matter described herein may be embodied in systems, devices, methods and / or articles. The embodiments set forth in the foregoing description do not represent all embodiments consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. Although some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations may be provided in addition to those set forth herein. For example, the above-described embodiments may be directed to various combinations and subcombinations of the disclosed features, and / or combinations and subcombinations of several additional features disclosed above. In addition, the logical flows depicted in the accompanying drawings and / or described herein do not necessarily require the specific order shown or the sequential order to achieve the desired results. Other embodiments may also fall within the scope of the claims.

Claims

1. A communication circuit, comprising: Clock input; A clock divider circuit configured to generate an output clock signal having a fundamental frequency substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein N is an integer, and wherein the clock divider circuit is configured as: Generates 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal, Based at least in part on the N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, wherein the 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree and separate, and Based at least in part on the N a specific phase-shifted clock signal to generate the output clock signal; as well as A mixer is configured to receive the output clock signal.

2. The communication circuit according to claim 1, wherein said N +1 pre-aligned phase-shifted clock signals, each with a frequency equal to 2 / (2 N +1) times.

3. The communication circuit according to claim 1, wherein said 2 N The pulse width of each of the +1 pre-aligned phase-shifted clock signals has a period substantially equal to that of the input clock signal.

4. The communication circuit according to claim 1 , wherein the base frequency of the input clock signal is 1 / (2 N +1) times the fundamental frequency 2(2 N +1) intermediate phase-shifted clock signals to generate the 2 N +1 pre-aligned phase-shifted clock signal.

5. The communication circuit according to claim 1, wherein said 2 N The fundamental frequency of each of the specific phase-shifted clock signals is equal to 2 / (2 N +1) times.

6. The communication circuit according to claim 1, wherein said 2 N The pulse width of each of the specific phase-shifted clock signals is substantially equal to twice the period of the input clock signal.

7. The communication circuit according to claim 1, wherein the 2 N Each of the specific phase-shifted clock signals corresponds to the 2 N +1 A phase-shifted version of one of the pre-aligned phase-shifted clock signals.

8. The communication circuit of claim 1, wherein a pulse width of the output clock signal is substantially equal to twice a period of the input clock signal.

9. A clock divider circuit configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal divided by a factor (2 N +1) / 2 N , wherein N is an integer, and wherein the clock divider circuit comprises: 2 N +1 frequency dividing circuit, the 2 N The +1 divide-by-one circuit is configured to generate 2(2 N +1) intermediate phase-shifted clock signal; 2 frequency multiplication circuit, the 2 frequency multiplication circuit is configured to receive the 2 (2 N +1) intermediate phase-shifted clock signals and based at least in part on the received 2(2 N +1) intermediate phase-shifted clock signals to generate 2 N +1 pre-aligned phase-shifted clock signal; A phase adjustment circuit configured to receive the 2 N +1 pre-aligned phase-shifted clock signal and based at least in part on the received 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, wherein the 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree and separation; as well as 2 N / 2 frequency multiplication circuit, the 2 N / 2 frequency multiplication circuit is configured to receive the 2 N a specific phase-shifted clock signal and based at least in part on the received 2 N A specific phase-shifted clock signal is used to generate the output clock signal.

10. The clock divider circuit according to claim 9, wherein the 2 N The divide-by-1 circuit includes a first barrel shifter circuit and a second barrel shifter circuit configured to shift in response to the input clock signal.

11. The clock frequency divider circuit according to claim 9, wherein the frequency multiplication circuit comprises a plurality of circuits configured to divide the plurality of 2 (2 N +1) intermediate phase-shifted clock signals to perform a plurality of logic circuits with a logic "OR" function.

12. The clock divider circuit according to claim 9, wherein the phase adjustment circuit comprises a circuit configured to generate the 2 N +1 multiple delay circuits that pre-align delayed versions of the phase-shifted clock signal.

13. The clock divider circuit according to claim 12 , wherein the delay of the delay circuit is controlled so that the 2 N +1 pre-aligned delayed versions of the phase-shifted clock signal with the first delayed version of the 2 N The second delayed version of the delayed versions of the +1 pre-aligned phase-shifted clock signals overlaps.

14. The clock divider circuit according to claim 9, wherein the 2 N / 2 frequency multiplication circuits include each configured to N A plurality of first logic circuits are provided to execute a logic OR function on a plurality of logic signals generated by a specific phase-shifted clock signal.

15. The clock divider circuit according to claim 14, wherein the 2 N / 2 frequency multiplication circuits include each configured to N The specific phase-shifted clock signal performs a logic “AND” function to generate a plurality of second logic circuits of the logic signal.

16. The clock divider circuit of claim 9, wherein the output clock signal is differential, and wherein the 2 N The / 2 frequency multiplication circuit includes a non-overlap circuit configured to cause the differential output clock signals to not overlap.

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