Inverse lithography and machine learning methods for mask synthesis

Abstract

Disclosed are techniques related to synthesizing masks for use in manufacturing semiconductor devices. A plurality of training masks (106) for a machine learning (ML) model are generated by synthesizing one or more polygons related to a design pattern for the semiconductor device using an inverse lithography technique (ILT). The ML model (108) is trained using both the plurality of training masks generated using the ILT and the design pattern for the semiconductor device as input. The trained ML model is configured to synthesize one or more masks (110) for use in manufacturing the semiconductor device based on the design pattern.

Description

Technical Field

[0001] Embodiments presented in this disclosure generally relate to semiconductor manufacturing and machine learning. More specifically, one or more embodiments disclosed herein relate to using inverse lithography techniques to generate training data and train machine learning models for mask synthesis. Background Art

[0002] Photolithographic processing represents an important technology used in the manufacture of integrated circuits (ICs) and microelectromechanical systems (MEMS). Photolithographic techniques are used to define patterns, geometries, features, shapes, etc. ("patterns") on an integrated circuit die or semiconductor wafer or chip, where the pattern can be defined by a set of outlines, lines, boundaries, edges, curves, etc., that surround, enclose, or define the boundaries of the various regions comprising the pattern.

[0003] The demand for increasing the density of features on dies and wafers has led to circuit designs with minimal dimensionality reduction. However, due to the wave nature of light, when the dimensions approach sizes comparable to the wavelength of light used in the lithography process, the resulting wafer pattern deviates from the corresponding mask (e.g., photomask) pattern, accompanied by undesirable distortions and artifacts. Inverse lithography techniques (ILT) can very effectively address these issues and synthesize high-quality masks for manufacturing advanced silicon-based computing nodes. However, the increased quality is often accompanied by a significant computational burden and long tool run times. This can hinder the use of ILT for mask synthesis.

[0004] Machine learning (ML) techniques can be used to accelerate mask synthesis. However, supervised ML models require appropriate training data to successfully solve a given problem. Generating such training data and designing a suitable ML model structure to assist in mask synthesis is a challenging problem. Summary of the Invention

[0005] An embodiment includes a method. The method includes generating multiple training masks for a machine learning (ML) model by synthesizing one or more polygons related to a design pattern for a semiconductor device using an inverse lithography technique (ILT). The method also includes training the ML model using the multiple training masks generated by using the ILT and the design pattern for the semiconductor device as input. The trained machine learning model is configured to synthesize one or more masks for use in manufacturing the semiconductor device based on the design pattern.

[0006] Embodiments also include another method. The method includes providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The method also includes using the ML model to perform a plurality of dilated convolutions associated with the design pattern. The method also includes using the ML model to infer, based on the plurality of dilated convolutions, one or more masks for use in fabricating the semiconductor device.

[0007] An embodiment further includes a system comprising a processor and a memory storing instructions that, when executed by the processor, cause the processor to perform operations. The operations include receiving a trained ML model. The ML model is trained using a plurality of training masks generated by synthesizing one or more polygons associated with a design pattern for a semiconductor device using ILT. The operations also include generating one or more masks for use in manufacturing the semiconductor device by providing the design pattern for the semiconductor device to the trained ML model. The operations also include converting the generated one or more masks from at least one of a rasterized representation or a level set representation to a polygonal representation for use in manufacturing the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the examples described herein. The accompanying drawings are used to provide knowledge and understanding of the examples described herein and do not limit the scope of the present disclosure to these specific examples. In addition, the drawings are not necessarily drawn to scale.

[0009] Figure 1A is a flowchart for training an ML model for mask synthesis using ILT, according to an embodiment.

[0010] Figure 1B Illustrated is a level set representation of mask polygons according to an embodiment.

[0011] Figure 2 is a block diagram illustrating a mask synthesis server for mask synthesis using an ML model according to an embodiment.

[0012] Figure 3 is yet another flow chart for training an ML model for mask synthesis using ILT, according to an embodiment.

[0013] Figure 4 is a flow chart for determining an ML model structure for mask synthesis using an ML model, according to one embodiment.

[0014] Figure 5A Illustrating translation invariance in an ML model for mask synthesis, according to one embodiment.

[0015] Figure 5BIllustrated is a translation-invariant ML model structure for mask synthesis according to one embodiment.

[0016] Figure 6A Illustrating model mesh shift invariance in an ML model for mask synthesis, according to one embodiment.

[0017] Figure 6B Illustrated is a model grid shift-invariant ML model structure for mask synthesis according to one embodiment.

[0018] Figure 7A Illustrated is symmetry in an ML model for mask synthesis, according to one embodiment.

[0019] Figure 7B Illustrated is a symmetric ML model structure for mask synthesis according to one embodiment.

[0020] Figure 8 is a flowchart for inferring mask synthesis using an ML model, according to an embodiment.

[0021] Figures 9A-9F Illustrated is the conversion of a mask generated by inference of an ML model for use by a lithography tool, according to an embodiment.

[0022] Figure 10 is a flow chart of various operations in the design and fabrication of integrated circuits according to an embodiment.

[0023] Figure 11 An example of a computer system according to an embodiment is illustrated within which a set of instructions may be executed for causing the computer system to perform any one or more of the methods discussed herein.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0025] ILT can be used to improve the training of ML models used for mask synthesis. For example, ILT can be used to generate synthesized masks that can be used as training data to train a supervised ML model. The trained ML model can then be used to infer the synthesized mask using the designed pattern. This can significantly improve the accuracy of the ML model by facilitating the creation of a large number of accurate training data samples for use in training the ML model.

[0026] In addition, the ML model structure can be designed to compensate for potential problems in using the design pattern to infer the synthetic mask. For example, the ML model can be designed for translation invariance, model mesh shift invariance, and symmetry. This will be discussed further below. The ML model can then be used to generate the synthetic mask. In an embodiment, the ML model outputs the synthetic mask in a format that is not suitable for local use by the lithography tool (e.g., rasterization or level set representation). A variety of post-processing techniques can be used to convert the mask output by the ML model into a polygonal representation or another representation suitable for local use by the lithography tool.

[0027] Figure 1A 1 is a flowchart 100 for training an ML model for mask synthesis using ILT, according to an embodiment. In an embodiment, a trained ML model 110 synthesizes a mask (e.g., a photomask used in photolithography for manufacturing silicon ICs) using a design pattern 102. For example, the design pattern 102 may be generated by a designer of the IC (e.g., a chip designer, a semiconductor manufacturer, etc.). The design pattern 102 may relate to any suitable IC, MEMS, etc. In an embodiment, the design pattern 102 may relate to the design of a specific device, a representative portion of multiple devices, a design kit of multiple devices, etc. In an embodiment, the design pattern 102 is stored in a training database.

[0028] At block 104, ILT is used to generate a training data mask from the design pattern 102. In an embodiment, standard ILT techniques can be used (e.g., without using the ML model 110). As an example, a level set can be used to represent the mask. For example, a level set function ψ(x,y) can be used to represent an example photomask pattern by defining a contour that encloses a region in the photomask pattern. In this example, ψ(x,y) is a function with the following properties. First, everywhere along the boundary of the region in the photomask pattern, ψ(x,y)=0. Second, "inside" the region in the photomask pattern (e.g., in the region corresponding to the chrome portion of the mask), ψ(x,y)>0. Third, "outside" the region in the photomask pattern (e.g., the region corresponding to the clear quartz portion of the mask), ψ(x,y)<0 or is negative. The contour is defined by a "level set", that is, those values ​​in the (x,y) plane such that ψ(x,y)=0. The following Figure 1B The intersection of the level set function and a plane parallel to the (x, y) plane is illustrated. In embodiments, the cost function and cost function gradient can be used to drive mask optimization in the level set representation. Alternatively or in addition to using ILT to generate training data masks, an ML model (e.g., a previously trained ML model) can also be used.

[0029] Figure 1B1. Level set representations of mask polygons according to an embodiment are illustrated. Level set representations are discussed above. Mask polygon 152 can be represented as level set representation 162. Mask polygon 154 can be represented as level set representation 164. Mask polygon 156 can be represented as level set representation 166. In an embodiment, mask polygons 152, 154, and 156 represent the mask polygon changing shape from a starting shape (e.g., mask polygon 152) to an ending shape (e.g., mask polygon 156). Level set representations 162, 164, and 166 are level set representations of the corresponding mask polygons.

[0030] return Figure 1A In an embodiment, ILT is used on a portion of the design pattern 102. For example, ILT can be used to generate training data masks for a subset of a particular IC (e.g., a portion of the IC). These training data masks can be used to train the ML model 110, which can then be used to generate a mask for the complete IC. Because, as discussed above, ILT is often computationally intensive, this allows ILT to be used on a smaller portion of the IC (e.g., a design pattern 102 representing a subset of the IC rather than the complete IC), thereby saving computational time and resources. The ML model 110 can then generate a mask for the entire IC. Alternatively or additionally, at block 104, standard ILT generates a mask for the complete IC, and the ML model 110 can also be used to generate a mask for the complete IC. This can be advantageous because the ML model can be more accurate than standard ILT.

[0031] In an embodiment, the design pattern 102 selected for ILT at block 104 can impact the effectiveness of the ILT technique and the accuracy of the resulting ML model 110. For example, a set P of potential design patterns for mask synthesis may include billions of unique patterns. To select patterns for use in ILT, the set P can be grouped into subgroups or clusters containing items that are sufficiently similar to one another that a representative of each cluster can be used to represent the cluster. This grouping or clustering can be accomplished in a variety of ways.

[0032] In one example, a parallelized system can use parallelization across multiple CPU nodes to perform fuzzy pattern grouping and cluster patterns. This can be done using the following techniques. First, take (multiple) design layouts and use distributed processing to find unique patterns (e.g., within a user-specified window size at the center of a user-specified window). The distributed system can partition the design into "templates" and then process each template in parallel to find a unique window. For each template, a set of search windows W is selected, and the layout geometry is clipped to the window and its hash key is obtained (e.g., using existing techniques for computing integer hash keys from geometric layout clips). The hash keys can be used to build a global database of patterns. The geometric clips can be stored in a global database D in the format: D[hashkey]=geometry_polygons.

[0033] Secondly, a machine learning autoencoder model is trained using distributed training. In an embodiment, the model can compress the data to a smaller size by storing intermediate encoded portions of the model evaluation. A distributed ML training method can be used to train an autoencoder model that has a smaller data size at the midpoint representing the encoded data. The polygonal data is first converted to a rasterized pixel grid so that a convolutional neural network can be used in subsequent steps. The autoencoder model can be used to fit the data to itself, with a low-dimensional encoded representation at the midpoint of the model. This can be done using a training method similar to Stochastic Weight Averaging, which: 1. splits the data into blocks, 2. partially fits the model in parallel on each block, 3. averages the weights from each partial fit to create a combined model, and 4. returns to step 2 and continues training the model based on the latest weight values ​​found in step 3. In an embodiment, this allows the model to be fit to a larger dataset than can be contained in memory on a single machine. Once the autoencoder is trained, the encoded version of each data point can result in an image of a specified size (e.g., 1024x1024) being scaled down to a smaller (e.g., 8x8) encoded representation. This is done through distributed ML model inference. This is just one example, and the same approach used to create the encoded dataset can be used, such as performing a lithography simulation on polygons and extracting geometry / pixel information from them.

[0034] Third, a distributed hierarchical clustering method is used to cluster the compressed data patterns into clusters. For example, distributed hierarchical clustering can be used because typical clustering algorithms have a computational complexity of O(kNd), where k is the number of clusters, N is the number of patterns to be clustered, and d is the dimensionality of the pattern. Hierarchical clustering reduces k and N (and therefore reduces the turnaround time of each level) by continuously splitting the data into subclusters, which can be subdivided in parallel. By distributing work between the two subclusters of the tree branch, the complexity is reduced to O(Ndlogk), which is a significant saving when k is very large. This can also reduce the memory used. However, this is just an example, and other clustering techniques (e.g., k-means, spectral, agglomeration) (e.g., running on a single machine or distributed machines) can also be used. The selected clustering technique can depend on the data volume and other data characteristics, that is, which clustering method is most suitable for the problem at hand. In an embodiment, k-means clustering can be used at each hierarchical branch of the clustering tree. This is just an example, and other clustering techniques can be used. In an embodiment, once the cluster tree is completed, the leaves are used as the final clusters.

[0035] Block 104 generates training data masks 106. In an embodiment, these training data masks 106 are provided as input to block 108 along with the design pattern 102 and are used to train the ML model 110. In an embodiment, the training data masks 106 are stored in a training database along with the design pattern 102 and provided together to train the ML model at block 108. Alternatively, the design pattern 102 and the training data masks 106 are provided via separate data paths to train the ML model block 108 at block 108. As another alternative, only the training data masks 106 are used to train the ML model 110 (e.g., the design pattern 102 is not used to train the ML model 110).

[0036] ILT mask data (e.g., training data mask 106) can be represented in many different ways, as will be discussed further below. For example, the mask data can be rasterized and represented as a series of pixels in an image. Alternatively or additionally, the mask data can be encoded as a set of offsets from the design edge (e.g., a pattern can be represented as offsets from the design edge). These are merely examples, and other representations can be used, including level set representation on a grid, skeletonization of the mask polygons, possibly followed by rasterization of the mask polygons, or other transformations.

[0037] Figure 22 is a block diagram illustrating a mask synthesis server 200 for mask synthesis using an ML model according to an embodiment. The mask synthesis server 200 includes a processor 202, a memory 210, and a network component 220. The processor 202 generally retrieves and executes programmed instructions stored in the memory 210. The processor 202 is included to represent a single central processing unit (CPU), multiple CPUs, a single CPU with multiple processing cores, a graphics processing unit (GPU) with multiple execution paths, and the like.

[0038] The network component 220 includes the components necessary for the mask synthesis server 200 to interface with components via a network. For example, the mask synthesis server 200 can use the network component to interface with remote storage and computing nodes. The mask synthesis server 200 can interface with these components via a local area network (LAN), such as an enterprise network, a wide area network (WAN), the Internet, or any other suitable network. The network component 220 may include wired, WiFi, or cellular network interface components and associated software to facilitate communication between the mask synthesis server 200 and the communication network.

[0039] Although memory 210 is shown as a single entity, memory 210 may include one or more memory devices having memory blocks associated with physical addresses, such as random access memory (RAM), read-only memory (ROM), flash memory, or other types of volatile and / or non-volatile memory. Memory 210 typically includes program code for performing various functions associated with the use of mask synthesis server 200. The program code is often described as various functional "applications" or "services" within memory 210, but alternative implementations may have different functions and / or combinations of functions.

[0040] Within the memory 210, the ILT service 212 facilitates the use of ILT to synthesize masks from design patterns. For example, as discussed above at block 104 illustrated in FIG. 1 , the ILT service 212 may use ILT to synthesize masks for use in training an ML model. The memory 210 also includes an ML training service 214. In an embodiment, the ML training service 214 may be used to train an ML model, as discussed above with respect to block 108 in FIG. 1 (e.g., using the training data mask 106 and the design pattern 102). The memory 210 also includes an ML inference service 216. In an embodiment, the ML inference service 216 may be used to synthesize masks (e.g., from a design pattern) using a trained ML model (e.g., the ML model 110 illustrated in FIG. 1 ). This will be discussed below with respect to Figure 8 and other figures for further discussion.

[0041] Figure 3is another flow chart 300 for training an ML model for mask synthesis using ILT according to an embodiment. At block 302, a structure for the ML model is designed. This will be discussed below with respect to Figure 4 Further Discussion. In an embodiment, the ML model structure can be a combination of typical ML layers, including convolutional layers, densely connected layers, nonlinear activation functions, etc. The model can have multiple hidden layers (e.g., a deep model). In addition, the model can use a gradient-based optimization scheme, such as stochastic gradient descent (SGD) or a variant of SGD, to converge to a model that fits the data well enough to be used for inference after training and produces acceptable results that are as close as possible to the training masks from ILT.

[0042] In an embodiment, a model developed for a signal processing application (such as image recognition) can be used as a baseline for designing a suitable ML model structure. In this embodiment, the input data polygons (e.g., included in the design pattern 102 illustrated in FIG1 ) and the training mask polygons (e.g., the training data mask 106 illustrated in FIG1 ) can be transformed into image-like objects by rasterizing them before submitting them to the ML model training step.

[0043] Furthermore, in embodiments, models developed for image recognition can be improved by identifying and compensating for several characteristics of lithographic masks. For example, models can be designed for translation invariance, model grid shift invariance, and symmetry. This will be discussed below with respect to Figure 4 - Figure 7 is discussed further.

[0044] At block 304, the ML training service (e.g., Figure 2 1 ) generates training data. For example, as discussed above with respect to block 104 illustrated in FIG1 , ILT techniques may be used to generate training data. In embodiments, training data may be pre-cleaned (e.g., before being used to train an ML model) to correct for grid alignment issues, lack of symmetry, and other potential problems. For example, training data generated using ILT may be less sensitive to grid alignment issues (e.g., shift invariance, as discussed below with respect to Figure 4 ) and the lack of symmetry in the output mask (e.g., as discussed below with respect to block 404 illustrated in Figure 4 ) is sensitive to symmetry. When the training data itself exhibits poor symmetry, using the ML architecture to enforce symmetry in the output can lead to poor calibration. Similarly, if multiple instances of the same design in the training dataset have very different outputs (e.g., due to grid alignment issues), the ML model may have problems.

[0045] Symmetry issues (e.g., symmetric behavior in the input not being carried over to the output) can be improved in a number of ways. For example, the ML training service can identify repeated and symmetric inputs and algorithmically enforce them to have the same solution until a transformation is found. In an embodiment, this can be accomplished by identifying identical repeating chip design regions within a window, synthesizing masks for these designs and storing them in a library, and then using the library as a lookup table for the mask when the full chip mask synthesis is complete. This is just one example, and other suitable techniques can be used. In this example, the library can be created for the specific design being processed, or it can exist as a database of solutions from multiple designs. This can improve symmetry by ensuring that the same placement of design geometry will produce the same mask, and any design symmetry detected locally will be enforced on the mask.

[0046] In an embodiment, this may be one using the following sequence of steps: First, the complete chip design or a representative test pattern set is read. Second, the user places a user-defined search window at the centers of selectively defined search boxes. The technique for selecting these centers may be guided by either within the template design hierarchy or by heuristic-based sparse sampling of the selected designs, and thus the number of searches is not excessive. Third, for each search box, an appropriate software service (e.g., Figure 2 ) clips the design to the box and then computes a hash key or other signature of the geometry. Fourth, the service uses the hash key to index the design pattern into a dictionary that stores the clipped geometry. Fifth, after finding the clips, it can then determine which clips are repeated modulo translation and symmetry operations, so that a subset of clips representing unique clips can be selected. The service performs mask synthesis on the unique patterns (including symmetry detection and enforcement of the clips, as discussed above) and stores the solutions in a suitable database (e.g., a global solution database). Sixth, when solving mask synthesis on the same design or a new chip design, the service uses the same search / hashing technique to find locations with mask solutions that have been stored in the global database. The service places the masks in those appropriate locations and performs blending to produce a lithography-optimized mask. The result of the aforementioned steps is a mask that is globally consistent and symmetric at all locations. After the training data is symmetrized and consistent, the ML training service can use rasterization to transform the polygons into a pixelated domain (e.g., as discussed further below). Alternatively or additionally, a pixelated representation of the polygon may be generated by first converting the polygon to a skeletal representation and then converting the skeletal representation to pixelated data (e.g., focusing on the axes of the mask polygon). This is described below with respect to Figure 9F Further explanation.

[0047] At block 306, the ML training service trains the ML model. In an embodiment, the ML training service takes as input both the training data mask generated using ILT and the underlying design pattern. Furthermore, in an embodiment, these training data mask and design pattern are pre-processed (e.g., converted to the pixel domain or another suitable domain and processed as described above with respect to block 304). Standard ML training techniques can then be used to train the ML model using the input data.

[0048] Figure 4 is a flow chart for determining an ML model structure for mask synthesis using an ML model according to an embodiment. In an embodiment, Figure 4 Corresponding to Figure 3 1 and 3. As discussed above, in embodiments, polygons in a mask (e.g., in the design pattern 102 and training data mask 106 illustrated in FIG. 1 ) are converted to the pixel domain for use in training an ML model (e.g., by rasterization). However, this pixelation may introduce errors (e.g., due to aliasing). For example, a polygon that appears in multiple locations in the design pattern should be represented the same way in each location in the composite mask. However, due to errors, the same polygon may be represented differently in different portions of the pixelated representation of the design pattern. The ML model may be designed to compensate for these errors.

[0049] At block 402, the ML model is designed for translation invariance (e.g., ensuring that polygons remain consistent when translated across the mesh). Most mask synthesis results are expected to exhibit translation consistency. That is, as long as the lithography system has some translation invariance at a certain scale, the mask synthesis results will also be expected to exhibit this invariance. Typical translation invariance can be expected as long as the design pattern polygons are translated farther than the range of the lithography system. For example, for a 193nm system, this is expected to be in the range of ~1 micron. In an embodiment, the ML model is designed for translation invariance. This will be discussed below with respect to Figure 5A-5B Further discussion.

[0050] Although about Figure 5A-5B The translational invariance discussed is a factor in many systems, but some systems (e.g., extreme ultraviolet (EUV) lithography) would be expected to exhibit different or possibly no translational consistency. In these systems, other, longer-range effects (e.g., flare or illumination angle) can affect the solution at scales much larger than micrometers. For example, flare or slit angle can be a significant factor in EUV lithography.

[0051] At block 404, the ML model is designed to model mesh shift invariance. In an embodiment, this includes ensuring that the input data and training data (e.g., design polygons or their representations) used for the ML model are mesh shift invariant. For example, the input data, the training data, or both can be represented using a non-pixelated representation (e.g., using offset distances from polygon edges). This will be discussed below with respect to Figure 6A and Figure 9C Further discussion.

[0052] Alternatively or additionally, designing the ML model for model shift grid invariance includes ensuring that the design polygons do not shift when the grid used in the ML uses larger cells than the design polygon input. In an embodiment, the ML model is further designed to reduce or eliminate grid or pixel shift variance (SV). This type of SV can be found when the basis input to the model has finer cells than the pixelated grid used for convolution. For mask synthesis applications, the design polygons are often stored in database cells of less than 1 nm, while the pixelated grid has a spatial pixel size of multiple nanometers for practical purposes. In an embodiment, the ML model is designed for model grid shift invariance. This will be discussed below with respect to Figure 6A-Figure 6B Further discussion.

[0053] At block 406, the ML model is designed for symmetry (e.g., ensuring that symmetries in the design polygon input are carried over to the output, as discussed above). In an embodiment, the lithography system typically has some symmetric behavior based on the shape of the illumination source. The user will expect that the resulting mask synthesis solution will also exhibit these symmetries. In an embodiment, the ML model is designed to enforce the symmetries specified by the user. This will be discussed below with respect to Figure 7A-7B Further discussion.

[0054] Figure 5A Illustrated is translation invariance in an ML model for mask synthesis according to one embodiment. In an embodiment, Figure 5A-5B Corresponding to Figure 4402 is illustrated in FIG. One possible source of error in the ML model is that repeated convolutions may cause a single pixel (e.g., in a pixelated design pattern) to have a large influence on the output composite mask (e.g., because the pixel's range of influence can change with repeated convolutions). In an embodiment, this can be addressed in the ML model structure by limiting the model range (e.g., the influence of one portion of the input on the entire convolution) to be less than a certain predefined value. This can be done by ensuring that the farthest-reaching influence the model can have given a change in any input value is geometrically limited. This helps ensure that one portion of the design in one location does not affect another portion of the design that is optically isolated from the other portion of the design during the etching process. For deep convolutional neural networks (CNNs), this is done by limiting the dilation, width, and depth of the convolution kernels, as well as limiting other operations that effectively increase their model range, such as downsampling to a coarser pixel representation.

[0055] For example, Figure 5A : The diagram shows a sequence of 3x3 convolutions applied from left to right. The input signal at the pixels labeled X in grids 502, 504, and 506 can have an impact on the output signal labeled y in grid 506. For example, grid 502 illustrates the initial position of pixel X. Grid 504 illustrates the interval impact of pixel X after the initial convolution (or series of convolutions). Grid 506 illustrates the interval impact of pixel X after another convolution (or series of convolutions). Due to repeated convolutions, the value at pixel X in grid 502 may incorrectly affect the value at pixel Y in grid 506, thereby generating errors. Furthermore, if the kernel width and depth in the ML model are increased (e.g., increasing the variation in potential impact through convolutions), then pixel X may potentially affect all pixels in the domain, which may violate translation invariance (e.g., due to failing to ensure that polygons remain consistent when translated across the grid) and generate further errors.

[0056] Figure 5B An example translation-invariant ML model structure 550 for mask synthesis according to an embodiment is illustrated. The illustrated ML model structure 550 includes several layers 552, 554, 556, 558, 560, 562, and 564. The ML model structure also includes dilated convolutions, labeled "Dilated conv."

[0057] The dimensions of each layer are listed in the relevant box as N x N x K, where the pixel dimension N is the first two indices and the number of pixelated fields or channels is the third index K. For example, layer 552 includes pixel dimensions of 1024x1024 and 1 pixelated field. Layer 554 includes pixel dimensions of 1024×1024 and 32 pixelated fields. Convolutions on inputs with multiple channels can be three-dimensional, convolving over the N x N pixelated domain and across all channels simultaneously. The convolution kernel sizes are denoted by ci and co, which are the number of input and output channels, respectively, between any two boxes in the figure. To obtain an output with multiple channels, we can create a convolution kernel of shape cix N x N for each output channel. We concatenate them over the output channel dimension so that the shape of the convolution kernel is co x cix N x N. Therefore, Figure 5B The number of convolutions between each layer in the network (whose outputs have activation functions applied to them) is determined by the number of pixelation layers in the input and destination layers. Each convolution may be followed by batch normalization and an activation function such as tanh, sigmoid, etc. The illustrated choices of model depth, kernel dimension, image dimension, and model layer connectivity are shown for example purposes only, and any suitable parameters may be used.

[0058] In an embodiment, dilated convolutions are used to allow for a larger convolution range than conventional convolution functions. The depth of the network (e.g., the number of convolution steps from left to right) is limited, so the total range of the model is limited in terms of the maximum influence of any pixel in the input on another pixel in the inferred result and is limited to a value comparable to the physical range of the lithography system. A typical way to increase the range of the model is by using larger convolution kernels or having a network with a larger depth (allowing cumulative addition of kernel ranges).

[0059] However, both options result in greater turnaround time and more complex networks. In embodiments, dilated kernels are very beneficial. Dilated kernels allow for increased model range (larger convolution range) without incurring a turnaround time penalty. The range of the model can be calculated using the model depth, the kernel dilation factor: {Di}, and the undilated kernel width w. Given a target model maximum range A, various combinations of depth, kernel width, and kernel dilation factor can be calculated so that the total model range is less than the target range A. In embodiments, each dilated convolution includes a kernel dilation factor greater than 1.

[0060] Figure 6A 1 illustrates model mesh shift invariance in an ML model for mask synthesis according to an embodiment. In an embodiment, Figure 6A-Figure 6B Corresponding to Figure 4 4. Block 404 is shown in FIG. Figure 6AThe polygonal rectangle is shown with an offset of 610 from a point fixed at the pixel corner in a sub-grid size database cell. Many ML models are overly sensitive and amplify SV noise, limiting the effectiveness of the tool. This can be a significant problem. One solution is to use more training data and provide multiple versions of the layout at different grid locations to allow the ML model to "learn" different configurations. This is done in Figure 6A , where multiple versions of the layout at different grid positions are presented in diagrams 602, 604, and 606. However, this approach has disadvantages, including longer turnaround time and generating significantly more training data.

[0061] Alternatively or additionally, using a finite grid alignment in the input (and without dilating the training dataset), model grid shift invariance can be addressed by predicting the output regardless of its grid alignment. This can be done by ensuring that the input data and training data (e.g., design polygons or their representations) are themselves grid shift invariant. One way to achieve this is to avoid using pixelated representations of design polygons altogether. For example, design polygons can be represented by offsets from edges rather than pixelated representations. A neural network can be configured to receive as input features describing the circuit design within a neighborhood of an input location and output offset distances from the edges of the circuit design polygon. The neural network can be used to determine offset distances for locations associated with the circuit design polygon. For example, the system can select locations along the edge of a circuit design polygon and generate offset distances from the edge of the polygon (e.g., as shown below Figure 9C ). The system generates mask design polygons based on the offset distance. The mask design polygons can represent features corresponding to the circuit design polygons, such as primary features or auxiliary features. The system uses the mask design polygons to generate a mask design for the circuit design. However, given the widespread use, research, and success of CNNs on pixelated inputs, it is also desirable to handle pixelation / rasterization of the input polygons.

[0062] To prepare polygons for use in CNNs, they can be transformed into a pixelated domain. For example, "sub-resolution pixel" or "sub-pixel" sampling (SPS) can be used, where the input image is first rendered as a high-density pixel grid and then converted to the desired lower resolution grid by sampling through a finite impulse response (FIR) filter. As another example, a "flash" based technique can be used. For example, a flash-based technique is used to calculate the two-dimensional convolution values ​​of multiple query points on the edge of a pattern layout. The flash-based technique pre-calculates (by numerical integration) the convolution of a set of basis functions with one or more model kernels representing the behavior of the optical lithography system. For example, the set of basis functions can be a set of half-plane basis functions corresponding to a set of predetermined face angles (e.g., 45° face angles, 90° face angles, 135° face angles, etc.). Each half-plane basis function divides the two-dimensional space into two regions. The convolution values ​​evaluated at the predetermined array of pixel positions are then stored in a set of two-dimensional lookup tables called model flash lookup tables.

[0063] In an embodiment, the system decomposes the polygonal pattern into glint representations, where each glint in the glint representation is an instance of one of a set of basis functions (e.g., half-plane basis functions as discussed above). The system then creates a sampled pattern layout by establishing a sampling grid on the polygonal pattern layout. Next, at each grid position in the sampling grid, the system calculates the convolution value (i.e., filtered value) between an anti-aliasing filter (AAF) kernel (e.g., a filter) and the input pattern layout (e.g., using a lookup table). The system stores the convolution value at the grid position in the sampling grid. The system repeats the last two steps for the entire sampling grid to obtain a pixelated sampled image that can be used by the CNN. The following is combined with Figure 6B Discuss other technologies.

[0064] Figure 6B The model grid shift invariant ML model structure 650 mask synthesis according to an embodiment is illustrated. In an embodiment, the ML model structure 650 includes several layers 652, 654, 656, 658, 660, 662 and 664, similar to Figure 5B The ML model structure 550 is shown in FIG. Figure 5B The ML model structure in 550 is the same as Figure 6BThe ML model structure 650 illustrated in FIG5 also includes dilated convolutions, labeled “Dilated conv.”, and the dimensions of each layer are listed in the associated box as N x N x K, where the pixel dimension N is the first two indices and the number of pixelated fields is the third index K. Each convolution can potentially be followed by batch normalization and an activation function such as tanh, sigmoid, etc. The illustrated choices of model depth, kernel dimension, image dimension, and model layer connectivity are shown for example purposes only, and any suitable parameters may be used.

[0065] In an embodiment, the inputs to the ML model layer 652 can be used for model mesh shift invariance. For example, in one embodiment, the ML model layer 652 receives only the rasterized design polygons 674 as input. In another embodiment, the model mesh shift invariance can be improved by providing the rasterized design polygons 674 as one input to the layer 652 and a second input using a lithographic simulation of the design polygons (e.g., with dimensions of 1024 x 1024 x 1) as a mask.

[0066] In another embodiment, rasterized design polygons 674 are provided as one input to layer 652, along with a different second input: a rasterized version of the corrected design polygons. Figure 6B 6. The design polygon 672 is rasterized, and the rasterized design polygon 674 is provided as input to layer 652. Additionally, the design polygon is corrected using known techniques (e.g., optical proximity correction (OPC)) to generate a corrected design polygon 676. The corrected design polygon 676 is rasterized, and the rasterized corrected design polygon 678 is also provided as input to layer 652.

[0067] In another embodiment, the rasterized corrected design polygon 678 is replaced by a lithographic simulation of the corrected design polygon using the corrected design polygon as a mask (e.g., having dimensions of 1024 x 1024 x 1). The design polygon 672 is rasterized, and the rasterized design polygon 674 is provided as an input to layer 652. Additionally, the design polygon is corrected using known techniques (e.g., optical proximity correction (OPC)) to generate a corrected design polygon 676. The corrected design polygon is treated as a mask and used for the lithographic simulation. Based on the corrected polygon, a simulated mask is provided as a second input to layer 652 (e.g., replacing the mask). Figure 6B The rasterized corrected design polygon 678 is shown in FIG.

[0068] In another embodiment, a level set function of a design polygon (e.g., of dimensions 1024 x 1024 x 1) is provided as a second input to layer 652 along with the rasterized design 674. In another embodiment, an ML architecture with different resolutions for the input and output fields can be used. For example, the input can be a coarse bandlimited target or aerial image field, while the output can be a finer rasterized field (e.g., of dimensions 2048 x 2048 x 1), with an upsampling convolution performed between layer 664 and the finer output.

[0069] In an embodiment, the model grid shift invariance can be further improved by eliminating or modifying model terms or functions that may have high pixel placement sensitivity. Terms that select a single pixel value from a group of pixels tend to amplify the SV, such as the maximum selection within a pixel range or downsampling by selecting a single pixel value from a group of pixels (e.g., max pooling functions and subsampling (downsampling) functions). These can be avoided. This also extends to methods such as strided convolutions. In an embodiment, using dilated convolutions to extend the model convolution range, as opposed to using strided convolutions, results in significantly improved performance. In summary, the ML model structure is designed to carefully reduce highly nonlinear and aliasing-induced terms so that the model has a smooth response (thereby improving grid sensitivity) while still allowing the model to encapsulate the complex nonlinear functional representation required to predict the ILT mask for a given design.

[0070] Figure 7A Illustrated is the symmetry in the ML model for mask synthesis according to an embodiment. In an embodiment, Figure 7A-7B Corresponding to Figure 4 406. In embodiments, certain symmetry groups have been defined in the art (e.g., groups of transformations under which an object is invariant). These include complete symmetry groups, correct symmetry groups, rotation groups, discrete symmetry groups (e.g., finite point groups, infinite lattice groups, and infinite space groups), and continuous symmetry groups. For any of these groups, we have a finite set of operations, R = {Ri}, that, starting from a starting orientation, yield all other members of the group. This set of operations defines the operations under which we expect our ML model to be invariant.

[0071] In an embodiment, the ML model can be designed to be invariant under these transformations by ensuring that the operations in the model architecture are invariant. For example, this can be done by applying the operations in R to each operation in the model architecture. For convolution, this means passing R i (K j ) for all R in R iCopy the convolution kernel K j .

[0072] Figure 7A The diagram illustrates an example of how a convolution kernel labeled F is applied and what a 90 degree rotated version of it looks like. In an embodiment, diagram 706 shows a 90 degree rotated version of the convolution kernel F in diagram 702. In diagram 704, the convolution result at pixel x is the sum of the contributions from the four rotated kernels added together.

[0073] Figure 7B An ML model structure 750 is illustrated that compensates for symmetry for mask synthesis according to one embodiment. In an embodiment, the ML model structure 750 includes several layers 752, 754, 756, 758, 760, 762, and 764, similar to Figure 5B The ML model structure 550 is shown in FIG. Figure 5B The ML model structure in 550 is the same as Figure 7B The ML model structure 750 illustrated in FIG also includes dilated convolutions, labeled “Dilated conv.”, and the dimensions of each layer are listed in the associated box as N x N x K, where the pixel dimension N is the first two indices and the number of pixelated fields is the third index K. Each convolution can potentially be followed by batch normalization and an activation function such as tanh, sigmoid, etc. The illustrated choices of model depth, kernel dimension, image dimension, and model layer connectivity are shown for example purposes only, and any suitable parameters may be used.

[0074] In an embodiment, the ML model structure 750 also includes R mirrored or rotated versions of the convolution (e.g., as Figure 7A This is included as "R" in model layers 754, 756, 758, 760, and 762. Alternatively or additionally, the "R" versions of the kernels can be combined before applying the activation function to reduce the applied kernel count by a factor of R.

[0075] Figure 8 FIG. 8 is a flowchart 800 for inferring mask synthesis using an ML model according to an embodiment. A design pattern 802 (eg, one or more polygons) and an ML model 804 (eg, at blocks 108 and 109 in FIG. 1 ) are combined. Figure 3 The ML model trained at block 306 in ( ) is provided to block 810. At block 810, the ML inference service (e.g., Figure 2 ) uses the ML model 804 to infer a synthesis mask from the design pattern 802. In an embodiment, the design pattern 802 may be transformed in any suitable manner as discussed above (e.g., pixelated, transformed into a level set field, etc.).

[0076] At block 820, the ML inference service (or any other suitable service) performs further post-processing on the mask generated at block 810. In embodiments, the service may post-process the mask to enhance the lithographic performance of the mask and repair any artifacts or other regions where the inferred solution was not accurate. This post-processing may be any combination of rule-based corrections, model-based edge perturbations, application of additional ML models, and the like. The service generates an output mask 830.

[0077] In an embodiment, the output mask 830 is a data type that is not suitable for use with a typical lithography tool. For example, the output mask 830 may be pixelated, in the level set domain, etc. The output mask 830 may be converted to a data type suitable for native use by the lithography tool (e.g., polygons). This will be Figures 9A-9F Further discussion.

[0078] Figures 9A-9F Illustrated is the conversion of a mask generated by inference of an ML model for use by a lithography tool, according to an embodiment. Figure 9A The conversion of a pixelated mask to a polygonal format according to an embodiment is illustrated. The pixelated mask 902 output by the ML model inference step is contoured at the appropriate heights, between the maximum and minimum values ​​generated by the inference of the field. This produces all-angle polygons, as illustrated by polygonal mask 904. All-angle polygons are a data type that can be consumed by lithography tools.

[0079] Figure 9B Illustrated is the conversion of a pixelated mask to a level set format according to an embodiment. As discussed above, the pixelated mask 912 output by the ML model is converted to a level set field 914. In an embodiment, the level set field representation of the mask can be used by a lithography tool.

[0080] Figure 9C 924. Assist feature polygons 926 and 928 are also offset from design polygon 924.

[0081] In an embodiment, the offset from the design edge may be constructed by first contouring the field and then calculating the offset from the design edge of the contour (e.g. Figure 9C According to an embodiment, this is Figure 9D The output mask 932 is used to generate a transformed mask 940 , which includes the design polygons 934 , the contoured inferred fields 936 (illustrated in dashed lines), and the offset final mask 938 .

[0082] Alternatively or additionally, a geometric transformation of the level set representation of the ML model output mask can be used to construct an offset from the design edge (e.g. Figure 9C According to an embodiment, this is Figure 9E The output mask 952 from the ML model is represented as a level set function. Direct sampling from the level set function can be used to generate a transformed mask 958, which includes the design polygon 954 and the offset final mask 956.

[0083] Figure 9F The use of skeletons to generate polygons from the output mask according to an embodiment is illustrated. A skeleton representation 960 of the output mask includes design polygons 962, 964, and 966, as well as a skeleton 968 and a resized skeleton 970. In an embodiment, the skeleton representation can be processed directly by the mask synthesis algorithm before being resized to become polygons. The extraction of these skeletons can be accomplished by searching for local extrema of the inferred field or other methods that attempt to find the most important one-dimensional skeleton regions in the field where the mask features should be placed.

[0084] Figure 10 is a flow chart of various operations in the design and fabrication of integrated circuits according to an embodiment. Figure 10 The diagram illustrates a set of example processes 1000 used to transform and verify design data and instructions representing an integrated circuit during the design, verification, and fabrication of an integrated circuit on a semiconductor die. Each of these processes can be structured and implemented as multiple modules or operations. The term "EDA" stands for electronic design automation. These processes begin at block 1010, utilizing information supplied by a designer to create a product idea. This information is then transformed to create the integrated circuit using a set of EDA processes at block 1012. When the design is complete, the design is taped off at block 1034, which is when the artwork (e.g., geometric pattern) for the integrated circuit is sent to a fabrication facility to produce a mask set, which is then used to manufacture the integrated circuit. After taping off, the integrated circuit is fabricated on the semiconductor die at block 1036, and at block 1038, packaging and assembly processes are performed to produce the finished integrated circuit (also commonly referred to as a "chip" or "integrated circuit chip") at block 1040.

[0085] Specifications for circuits or electronic structures can range from low-level transistor material layouts to high-level description languages. Circuits and systems can be designed using a high level of abstraction using a hardware description language (HDL) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level RTL description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction, which is a less abstract description, adds more useful detail to the design description (e.g., more detail of the modules that comprise the description). The lower levels of abstraction, which are less abstract descriptions, can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction that is used to specify a more detailed description is SPICE, which is used to describe circuits in detail using many similar components. The description at each level of abstraction is implemented for use by the corresponding tools at that level (e.g., formal verification tools). The design process can use Figure 10 The described process can be implemented by EDA products (or tools).

[0086] During system design, the functionality of the integrated circuit to be manufactured is specified at block 1014. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, etc. At this stage, the design may be divided into different types of modules or components.

[0087] During logic design and functional verification, at block 1016, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, the components of a circuit can be verified to generate outputs that match the specifications of the designed circuit or system. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some examples, specialized component systems called emulators or prototyping systems are used to accelerate functional verification.

[0088] During synthesis and testing of the design, at block 1018, the HDL code is converted into a netlist. In some examples, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are layered artifacts that EDA products can use to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0089] During netlist verification, the netlist is checked for adherence to timing constraints and correspondence with the HDL code at block 1020. During design planning, at block 1022, an overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0090] During layout or physical implementation, at block 1024, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components through multiple conductors) occur, and selection of cells from the library to implement a specific logic function can be performed. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (e.g., a flip-flop or latch). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be used as physical structures and enabled in simulations. Parameters such as size are specified for the selected cells (based on standard cells) and made accessible in a database for use by EDA products.

[0091] During analysis and extraction, at block 1026, circuit functionality is verified at the layout level, which allows for refinement of the layout design. During physical verification, at block 1028, the layout design is checked to ensure that manufacturing constraints such as design rule checking (DRC) constraints, electrical constraints, and lithography constraints are correct and that the circuit functionality matches the HDL design specifications. During resolution enhancement, at block 1030, the geometry of the layout is transformed to improve the fabrication of the circuit design.

[0092] During tape-out, data for producing photolithographic masks is created (after applying lithographic enhancements, if appropriate). During mask data preparation, at block 1032, the tape-out data is used to produce photolithographic masks for producing finished integrated circuits. In embodiments, the photolithographic masks may be produced using one or more of the techniques described above in conjunction with FIG. 1-9 .

[0093] The computer system's storage subsystem may be used to store programs and data structures used by some or all of the EDA products described herein and by products used to develop libraries and units of physical and logical design that use the libraries.

[0094] Figure 11The diagram illustrates an example of a computer system 1100 in which a set of instructions can be executed to cause the computer system to perform any one or more of the methods discussed herein. In some implementations, the computer system can be connected (e.g., networked) to other machines or computer systems in a local area network (LAN), an intranet, an extranet, and / or the Internet. The computer system can operate as a server or client computer system in a client-server network environment, as a peer computer system in a peer-to-peer (or distributed) network environment, or as a server or client computer system in a cloud computing infrastructure or environment.

[0095] The computer system may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the computer system. Furthermore, although a single computer system is described, the term computer system should also be understood to include any collection of computer systems that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0096] The example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1118, which communicate with each other via a bus 1130. The main memory 1104 includes or is a non-transitory computer-readable medium. The main memory 1104 (e.g., a non-transitory computer-readable medium) may store one or more sets of instructions 1126 that, when executed by the processing device 1102, cause the processing device 1102 to perform some or all of the operations, steps, methods, and processes described herein.

[0097] The processing device 1102 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 1102 may be or include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor(s) implementing a combination of instruction sets. The processing device 1102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1102 may be configured to execute instructions 1126 to perform some or all of the operations, steps, methods, and processes described herein.

[0098] The computer system 1100 may also include a network interface device 1108 for communicating over a network 1120. The computer system 1100 may also include a video display unit 1110 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), a graphics processing unit 1122, a signal generating device 1116 (e.g., a speaker), the graphics processing unit 1122, a video processing unit 1128, and an audio processing unit 1132.

[0099] The data storage device 1118 may include a machine-readable storage medium 1124 (e.g., a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1126 or software embodying any one or more of the methodologies or functions described herein. The instructions 1126 may also reside, completely or at least partially, within the main memory 1104 and / or within the processing device 1102 during execution thereof by the computer system 1100, the main memory 1104 and the processing device 1102 also including machine-readable storage media.

[0100] In some implementations, the instructions 1126 include instructions for implementing the functionality described above. Although the machine-readable storage medium 1124 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a computer system and cause the computer system and processing device 1102 to perform any one or more of the methods described above. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0101] Various features are described herein with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale, or may not be so, and elements of similar structure or function are represented by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the claimed subject matter or to limit the scope of the claimed subject matter. In addition, the illustrated examples do not need to have all aspects or advantages shown. The aspects or advantages described in conjunction with a specific example are not necessarily limited to that example and can be practiced in any other example, even if not illustrated in this way or if not clearly described in this way. In addition, the methods described herein can be described in a specific order of operations, but other methods according to other examples can be implemented in various other orders with more or fewer operations (for example, including different serial or parallel executions of various operations).

[0102] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulations of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0103] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clearly indicated from this disclosure, it should be understood that throughout the description certain terms refer to the actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform them into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0104] The present disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0105] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used in conjunction with the program according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. Furthermore, the present disclosure is not described with reference to any particular programming language. It should be understood that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0106] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0107] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to the specific example implementations of the present disclosure. It is apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular tense, more than one element may be depicted in the accompanying drawings and similar elements may be marked with similar numbers. Therefore, the present disclosure and the accompanying drawings should be regarded as illustrative rather than restrictive.

[0108] In view of the foregoing, the scope of the present disclosure is determined by the following claims.

Claims

1. A method comprising: Generating a plurality of training masks for a machine learning (ML) model by synthesizing one or more polygons using an inverse lithography technique (ILT), the one or more polygons being related to a design pattern for a semiconductor device; as well as The ML model is trained using both the plurality of training masks generated by using ILT and the design pattern for the semiconductor device as input, wherein the trained ML model is configured to synthesize one or more masks for use in manufacturing the semiconductor device based on the design pattern, wherein before training the ML model, one or more of the plurality of training masks are preprocessed to improve symmetry of the one or more training masks.

2. The method of claim 1, wherein the ML model is trained using a rasterized transformation of the plurality of training masks.

3. The method of claim 1, wherein the ML model comprises a plurality of dilated convolutions. The method of claim 3 , wherein the ML model receives as input a rasterization transformation associated with the design pattern. 5 . The method of claim 4 , wherein the ML model further receives as input a rasterization transformation associated with the correction of the design pattern. 6 . The method of claim 4 , wherein the ML model further receives as input a simulated image, the simulated image being related to using the design pattern as a mask for manufacturing the semiconductor device.

7. The method of claim 3, wherein the ML model further comprises at least one mirror or rotated convolution.

8. A system comprising: processor; as well as a memory storing instructions that, when executed by the processor, cause the processor to perform operations comprising: Receiving a trained machine learning (ML) model, wherein the ML model is trained using a plurality of training masks, the plurality of training masks being generated by synthesizing one or more polygons using an inverse lithography technique (ILT), the one or more polygons being related to a design pattern for a semiconductor device, and pre-processing one or more of the plurality of training masks to improve symmetry of the one or more training masks before training the ML model; generating one or more masks for use in manufacturing the semiconductor device by providing the design pattern for the semiconductor device to the trained ML model; as well as The generated one or more masks are converted from at least one of a rasterized representation or a level set representation to a polygonal representation for use in fabricating the semiconductor device.

9. The system of claim 8, wherein the ML model is further trained using the design pattern for the semiconductor device.

10. The system of claim 8, wherein the ML model is trained using a rasterized transformation of the plurality of training masks.

11. The system of claim 8, wherein the operation comprises converting the generated one or more masks from the rasterized representation to the polygonal representation.

12. The system of claim 11, wherein converting the generated one or more masks from the rasterized representation to the polygonal representation comprises: The rasterized representation is contoured to generate a plurality of corner polygons.

13. The system of claim 8, wherein the operation comprises converting the generated one or more masks from the level set representation to the polygonal representation.

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