A testing device and a power supply noise testing method

Abstract

This disclosure relates to the field of integrated circuit technology, and discloses a testing device and a power supply noise testing method. The testing device is used to measure the power supply noise of a memory chip. The testing device includes: a noise generation module, the load current of which varies according to a preset current curve; and a signal transmission module connected between the noise generation module and the motherboard, the signal transmission module having electrical parameters matching the memory packaging structure. The testing device provided by this disclosure is independent of memory production; it allows for advance measurement of the power supply noise of the memory chip based on its design parameters during the memory chip design stage. This testing device can simulate the power supply noise generated by the memory chip during actual operation to determine whether the memory chip poses a risk. The measurement results can be used to guide the manufacturing of the memory chip, thereby improving the yield rate of the memory chip.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically, to a test device and a power supply noise test method. Background Technology

[0002] SODIMM (Small Outline Dual In-line Memory Module) is a small dual in-line memory module used in personal laptops and other applications where size is a critical factor.

[0003] During operation, SDRAM chips experience dynamic current changes, which generate power supply noise on the chip. Since SDRAM chips are packaged in a package, this power supply noise is difficult to measure, and it's impossible to test the power supply noise of memory chips before the memory product leaves the production line.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a testing device and a power supply noise testing method.

[0006] According to exemplary embodiments of this disclosure, a testing device is provided for acquiring power supply noise of a memory chip. The testing device includes: a noise generation module whose load current varies with a preset current curve; a signal transmission module connected between the noise generation module and a motherboard, the signal transmission module having electrical parameters matching the memory package structure; and a voltage acquisition module connected at the connection point between the signal transmission module and the noise generation module, the voltage acquisition module being used to acquire a voltage signal at the connection point when the load current of the noise generation module changes, the voltage signal being used to determine the power supply noise of the memory chip. In some embodiments, the preset current curve is determined based on the current-time curve of a CPM model in the memory chip.

[0007] In some embodiments, the equivalent resistance, equivalent inductance, and equivalent capacitance of the signal transmission module are the same as those of the equivalent resistance, equivalent inductance, and equivalent capacitance of the memory package structure.

[0008] In some embodiments, the noise generation module includes: a power supply; and a plurality of load branches connected to both ends of the power supply, wherein each load branch is arranged in parallel.

[0009] In some embodiments, at least some of the load branches have the same load current and / or at least some of the load branches have different load currents.

[0010] In some embodiments, the load branch includes: a load resistor, with its first end connected to one end of the power supply; and a switching unit, with its first end connected to the second end of the load resistor and its second end connected to the other end of the power supply.

[0011] In some embodiments, the switching unit is a transistor; the control terminal of the transistor receives a switching control signal, the first terminal of the transistor is connected to the second terminal of the load resistor in the same load branch, and the second terminal of the transistor is connected to the other terminal of the power supply.

[0012] In some embodiments, the test device further includes a control module configured to output the switch control signal based on a preset timing sequence.

[0013] In some embodiments, the transistors in each of the load branches are of the same type.

[0014] In some embodiments, the memory package structure has multiple package pins, and the memory is connected to the motherboard through the package pins; the signal transmission module includes multiple first pins, and the signal transmission module is connected to the motherboard through the multiple first pins, and the number of first pins is the same as the number of package pins.

[0015] In some embodiments, the pin structure of the first pin is the same as the pin structure of the packaged pin.

[0016] In some embodiments, the signal transmission module includes: multiple power networks, each power network including an equivalent resistance, an equivalent inductance, and an equivalent capacitance; a first end of the equivalent resistance is connected to the signal input terminal of the power network; a second end of the equivalent resistance is connected to the first end of the equivalent inductance; the second end of the equivalent inductance is connected to the first terminal of the equivalent capacitor and then connected to the signal output terminal of the power network; the second terminal of the equivalent capacitor is grounded; the voltage acquisition module has multiple voltage interfaces, each voltage interface being connected to the signal output terminal of the multiple power networks in a corresponding manner.

[0017] In some embodiments, the signal transmission module further includes: a plurality of decoupling units, each corresponding to a power network, wherein the first pole of the decoupling unit is connected to the signal output terminal of the corresponding power network, and the second pole of the decoupling unit is grounded.

[0018] In some embodiments, the noise generation module and the signal transmission module are disposed on the same circuit board.

[0019] In some embodiments, the dynamic range of the load current of the noise generation module is greater than or equal to the current fluctuation range of the preset current curve.

[0020] According to exemplary embodiments of the present disclosure, a power supply noise testing method is also provided, applied to the testing equipment described in any embodiment of the present disclosure. The testing method includes: controlling the motherboard to supply power to the signal transmission module; activating the noise generation module so that the load current of the noise generation module changes according to a preset current curve; activating the voltage acquisition module to acquire the voltage signal at the connection between the signal transmission module and the noise generation module; and analyzing the power supply noise of the memory chip based on the voltage signal.

[0021] According to an exemplary embodiment of this disclosure, a power supply noise testing method is also provided, applied to the testing equipment described in the embodiments of this disclosure. The testing method includes: controlling the motherboard to supply power to the signal transmission module, so that the signal input terminals of each power network of the signal transmission module acquire corresponding voltage signals; activating the noise generation module, so that the load current of the noise generation module changes according to a preset current curve; activating the voltage acquisition module, so as to acquire the voltage signals of each signal output terminal of the signal transmission module through each voltage interface of the voltage acquisition module; and analyzing the power supply noise of the corresponding power network based on the voltage signals acquired by the voltage interfaces.

[0022] The testing equipment disclosed herein includes a signal transmission module with electrical parameters matching the memory package structure, enabling it to accurately characterize the impact of the memory package structure on the power supply noise of the memory chip during actual operation. The load current of the noise generation module varies according to a preset current curve, simulating the changes in the load current of the memory chip during actual operation. The voltage acquisition module acquires the voltage signal at the connection point between the noise generation module and the signal transmission module, reflecting the power supply noise of the memory chip during actual operation. This testing equipment is independent of memory manufacturing; it allows for advance measurement of the power supply noise of the memory chip based on its design parameters during the design phase. By simulating the power supply noise generated by the memory chip during actual operation, the equipment can assess potential risks. These measurement results can guide memory chip manufacturing, thereby improving the yield rate.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 This is a structural block diagram of a test device according to one embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure;

[0027] Figure 3 A current-time curve of a memory chip according to one embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of the structure of a noise generation module according to one embodiment of the present disclosure;

[0029] Figure 5 An equivalent circuit diagram of a power network in a signal transmission module according to one embodiment of the present disclosure;

[0030] Figure 6 This is a flowchart of a power supply noise testing method according to one embodiment of the present disclosure;

[0031] Figure 7 This is a flowchart of a power supply noise testing method according to one embodiment of the present disclosure. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0033] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0034] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0035] During operation, SDRAM chips experience dynamic current changes, which generate power supply noise on the chip. Since SDRAM chips are packaged in a package, the power supply noise on the SDRAM chip is difficult to measure.

[0036] The power supply noise measured on the motherboard often differs significantly from that measured on the chip itself. To improve measurement accuracy, the following two methods are primarily used to measure the power supply noise on the chip:

[0037] 1. Open the memory chip and use a precision probe to measure the power supply noise on the chip. Although this measurement method can guarantee measurement accuracy, it requires a high investment cost and is difficult to use on a large scale.

[0038] 2. Design a special package structure to route the power pad on the chip to an unused (NC) pin, which can also measure the on-chip power supply noise. However, this method does not conform to the actual definition in the chip's datasheet. If the user connects the NC pin to other signals such as GND, a short circuit between power and ground will occur, burning out the chip.

[0039] Furthermore, neither of the above two measurement methods can perform physical measurements in advance based on simulation results. Power noise can only be measured after the chip is designed and manufactured. If the power noise of the chip exceeds the standard, it will result in a huge waste.

[0040] To address the aforementioned issues, this disclosure provides a testing device that, when connected to a motherboard, can measure the power supply noise of memory chips. Figure 1 The diagram shows the structure of a test device according to an embodiment of the present disclosure. Vin1, Vin2, and Vin3 represent the signal input terminals of each power network of the signal transmission module 20, and Vout1, Vout2, and Vout3 represent the signal output terminals of each power network of the signal transmission module 20. The power noise signal of the noise generation module 10 to each power network can be measured at the signal output terminals of each power network of the signal transmission module 20. The power noise signal characterizes the power noise generated when the current of the memory chip changes. Figure 2 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure. Figure 2 The VDD and VPP shown are for illustrative purposes only and should not be construed as a limitation on the number of power networks in the signal transmission module of this disclosure. Figure 1 , Figure 2 As shown, the testing equipment may include a noise generation module 10, a signal transmission module 20, and a voltage acquisition module 30. The load current of the noise generation module 10 varies according to a preset current curve. The signal transmission module 20 is connected between the noise generation module 10 and the motherboard 1, and has electrical parameters that match the memory packaging structure. The voltage acquisition module 30 is connected at the connection point between the signal transmission module 20 and the noise generation module 10. The voltage acquisition module 30 is used to acquire the voltage signal at the connection point when the load current of the noise generation module 10 changes. This voltage signal is used to determine the power supply noise of the memory chip.

[0041] The testing equipment provided in this disclosure includes a signal transmission module 20 with electrical parameters matching the memory package structure. This allows the signal transmission module 20 to accurately characterize the impact of the memory package structure on the power supply noise of the memory chip during actual operation. The load current of the noise generation module 10 varies according to a preset current curve, simulating the changes in the load current of the memory chip during actual operation. The voltage acquisition module 30 acquires the voltage signal at the connection point between the noise generation module 10 and the signal transmission module 20, reflecting the power supply noise of the memory chip during actual operation. The testing equipment provided in this disclosure is independent of memory production. It allows for advance measurement of the power supply noise of the memory chip based on its design parameters during the design phase. This testing equipment can simulate the power supply noise generated by the memory chip during actual operation to determine if there are any risks associated with the memory chip. The measurement results can guide the manufacturing of the memory chip, thereby improving its yield rate.

[0042] In an exemplary embodiment, the noise generation module 10 simulates the noise generated by the memory chip during current switching in actual operation. A preset current curve can be determined based on the design parameters of the memory chip. For example, the preset current curve can be determined based on the current-time curve of the CPM (Chip Power Model) model in the memory chip, causing the load current of the noise generation module 10 to change with the current curve of the memory chip, thereby simulating the power supply noise signal generated by the memory chip due to changes in load current during actual operation. The preset current curve can be sampled at certain sampling intervals to obtain multiple discrete points, each corresponding to a current value. By acquiring the current values ​​at all sampling times, the change in the load current of the memory chip is determined. It should be understood that the higher the sampling rate of the preset current curve, the more accurate the simulation results for the load current of the memory chip.

[0043] For example, Figure 3 This is a current-time curve of a memory chip according to one embodiment of the present disclosure. In the figure, the horizontal axis represents time and the vertical axis represents current. Figure 3 As shown, by controlling the load current of the noise generation module 10 at each sampling time, it has Figure 3 The current value shown makes the noise generation module 10 have a load current that varies with the current curve. That is, the dynamic current of the noise generation module 10 is the same as the dynamic current of the memory chip in actual operation, so that the noise generated by the noise generation module 10 can accurately reflect the power supply noise signal generated by the memory chip in actual operation.

[0044] It is understandable that controlling the load current of the noise generation module 10 to vary according to a preset current curve can mean that the noise generation module 10 has the load current value at each sampling moment of the preset current curve. For example, in Figure 3 In the sampling time 1-4, the current is 0, so the noise generation module 10 can be controlled to disconnect all loads, so that the load current of the noise generation module 10 is 0. When the current becomes 10mA at sampling time 5, the load of the noise generation module 10 can be adjusted so that the load current of the noise generation module 10 is 10mA. And so on. By adjusting the load of the noise generation module 10, the load current of the noise generation module 10 is controlled to change with the current curve, simulating the current fluctuation of the memory chip in actual operation.

[0045] It should be understood that the electrical parameters of the signal transmission module 20 described in this disclosure are matched with the electrical parameters of the memory package structure. This can be understood as the electrical parameters of the signal transmission module 20 being the same as or nearly the same as the electrical parameters of the memory package structure. For example, the electrical parameters of the signal transmission module 20 being nearly the same as the electrical parameters of the memory package structure could mean that the ratio of the electrical parameters of the signal transmission module 20 to the electrical parameters of the memory package structure is within a set tolerance range, or the difference between the electrical parameters of the signal transmission module 20 and the electrical parameters of the memory package structure is within a set tolerance range, etc.

[0046] Typically, memory chips are packaged within a package structure. The electrical parameters of the package structure can be characterized by its equivalent resistance, equivalent capacitance, and equivalent inductance. Therefore, the equivalent resistance (ESR), equivalent capacitance (ESC), and equivalent inductance (ESL) of the signal transmission module 20 in the test equipment provided in this disclosure correspond to the same equivalent resistance, equivalent capacitance, and equivalent inductance of the memory package structure, respectively. Of course, in other embodiments, the electrical parameters of the package structure can also be characterized by other electrical characteristics. When characterized by other electrical characteristics, the electrical parameters of the signal transmission module 20 must still match the electrical parameters of the package structure.

[0047] The preset current curve can be a design parameter of the memory chip. This preset current curve reflects the current change of the memory chip in actual operation. Therefore, the load current of the noise generation module 10 changes with the preset current curve, which is equivalent to the load current of the noise generation module 10 reflecting the current change of the memory chip in actual operation. Therefore, the voltage interference signal caused by the load current change of the noise generation module 10 to the power network of the signal transmission module 20 reflects the power noise generated by the memory chip under the dynamic current change in actual operation.

[0048] It is understood that the noise generation module 10 and the signal transmission module 20 in the test equipment provided in this disclosure can be mounted on the same circuit board.

[0049] The signal transmission module 20 is connected between the noise generation module 10 and the motherboard 1. This can be understood as the signal transmission module 20 being connected to the motherboard 1, and the noise generation module 10 being connected to the signal transmission module 20. For example, the signal transmission module 20 has multiple voltage input terminals and multiple voltage output terminals. The voltage input terminals are connected to the corresponding power supply signal terminals of the motherboard 1 to obtain the power supply signal provided by the motherboard 1. The voltage output terminals are connected to the noise signal generation module, thereby superimposing the interference voltage signal generated by the noise generation module 10 onto the voltage output terminal of the signal transmission module 20. The voltage acquisition module 30 is connected at the connection point between the signal transmission module 20 and the noise generation module 10, which is equivalent to the voltage acquisition module 30 being connected to the voltage output terminal of the signal transmission module 20. Obviously, the voltage signal acquired by the voltage acquisition module 30 is superimposed with the interference voltage signal generated by the noise generation module 10. Therefore, by detecting the voltage signal of the voltage acquisition module 30, the power supply noise signal of the memory chip during actual operation can be analyzed. This disclosure determines the power supply noise of the memory chip by qualitatively analyzing the power supply noise signal of the memory chip, or by quantitatively determining the magnitude of the power supply signal of the memory chip.

[0050] The structure of the noise generation module 10 and the signal transmission module 20 in the test equipment will be further described below with reference to the accompanying drawings.

[0051] Figure 4 This is a schematic diagram of the structure of a noise generation module according to one embodiment of the present disclosure, as shown below. Figure 4 As shown, in an exemplary embodiment, the noise generation module 10 may include multiple load branches 101, which may be connected in parallel. The load branches 101 can be controllably turned on or off, thereby adjusting the load current of the noise generation module 10 by changing the number of on load branches. For example, each load branch 101 may include a load resistor R and a switching unit 102. A first end of the load resistor R is connected to one end of a power supply, a second end of the load resistor R is connected to the first end of the switching unit 102, and a second end of the switching unit 102 is connected to the other end of the power supply. Thus, by controlling the on / off state of the switching unit 102 in each load branch 101, the connection between the load branch 101 and the power supply can be controlled.

[0052] In some embodiments, the load current of each load branch 101 when connected to a power source may be different. For example, the noise generation module 10 may include 10 load branches 101, each with a current consumption of 10mA, 20mA, 30mA, 40mA...100mA when turned on. Thus, a current range of 0-550mA can be achieved through these 10 load branches 101, with a minimum resolution of 10mA. In other embodiments, the load current of the load branches 101 in the noise generation module 10 may also be partially the same. For example, the noise generation module 10 may include 10 load branches 101, two of which consume 10mA of current when turned on, and the other load branches 101 consume 30mA, 40mA...100mA of current when turned on. When the load current of the noise generation module 10 needs to be 20mA at a certain moment, the load current of the noise generation module 10 at that moment can be made 20mA by simultaneously turning on two load branches 101 that have a load current of 10mA when turned on.

[0053] It should be understood that the load current of a certain load branch 101 described in this disclosure can be understood as the current flowing through the load branch 101 when the load branch 101 is connected to a power source. The load current value of the load branch 101 can be set by adjusting the resistance value of the load resistor R in the load branch 101.

[0054] In addition, it should be understood that the switch control signal needs to be output according to a certain timing sequence to conduct the corresponding load branch 101 according to the preset current curve, so that the load current of the noise generation module 10 at the corresponding time matches the preset current curve.

[0055] like Figure 4 As shown, in an exemplary embodiment, the test device may further include a control module 40, which is connected to the switching units in each load branch of the noise generation module 10. The control module 40 can be used to output switching control signals according to a preset timing sequence to control the switching units 102 in each load branch 101 of the noise generation module 10 to switch on and off, and adjust the load branch 101 connected to the power supply in real time so that the load current of the noise generation module 10 fluctuates with a preset current curve.

[0056] The control module 40 can be a microcontroller, a general-purpose processor such as an ARM processor, or another device with data processing and computation capabilities such as an FPGA. The control module 40 can be mounted on the same circuit board as the noise generation module 10 and the signal transmission module 20. For example, the control module 40 can be an embedded ARM processor mounted on the circuit board, with high and low level signals output from the ARM processor's I / O ports serving as switch control signals to control the switching unit 102 to turn on or off. Alternatively, in other embodiments, a control signal interface can be reserved on the circuit board, allowing an external processor to generate the switch control signals; all of these fall within the scope of this disclosure.

[0057] In an exemplary embodiment, the switching unit 102 can be implemented using a transistor. For example, the switching unit 102 can be a P-type transistor or an N-type transistor. The control terminal of the transistor is used to receive a switching control signal, the first terminal of the transistor is connected to the second terminal of the load resistor R in the same load branch 101, and the second terminal of the transistor is connected to the other terminal of the power supply. Because the load branches 101 are connected in parallel, according to the current division formula of the parallel circuit, the current of each load branch 101 can be calculated by the following formula:

[0058] I = V0 / (Ron + Resistot) (1)

[0059] In the formula: I is the current flowing through the load branch 101, V0 is the power supply voltage of the noise generation module 10 that supplies power to the load branch 101, Ron is the on-state resistance of the transistor, and Resistant is the load resistance R in the load branch 101.

[0060] It is known that the on-state resistance of the transistor is a fixed value. Therefore, the resistance value of the load branch 101 can be set according to the determined current value that each load branch 101 needs to flow through, so that when the transistor in the load branch 101 is turned on, the branch current of the load branch 101 is a predetermined set value.

[0061] In an exemplary embodiment, the transistors in each load branch 101 can be of the same type, meaning that the transistors in each load branch 101 are of the same kind. For example, the transistors in each load branch 101 can all be N-type MOSFETs. When the switching control signal output by the control module 40 to a certain transistor is high, the transistor is turned on, and the load branch 101 containing that transistor is turned on and has a corresponding load current. Of course, in other embodiments, the transistors in each load branch 101 can also be of different types, or partially the same, etc., all of which fall within the protection scope of this disclosure.

[0062] In an exemplary embodiment, the switching unit 102 in the load branch 101 can be implemented using integrated devices. For example, the switching unit 102 of each load branch 101 can be constructed using one or more high-speed CMOS integrated switches. The high-speed CMOS switch has multiple signal selection terminals, one of which is used to receive a switch control signal. One switch control signal controls one load branch 101, so that one integrated CMOS switch can control multiple load branches 101, thereby simplifying the structure of the noise generation module 10 and improving the operational reliability of the noise generation module 10.

[0063] In an exemplary embodiment, the dynamic range of the load current in the noise generation module 10 is greater than or equal to the current fluctuation range in a preset current curve. For example, if the maximum current value in the preset current curve is 170mA and the minimum current value is 0, meaning the current fluctuation range in the preset current curve is 0 to 170mA, then the maximum load current that the noise generation module 10 provided in this disclosure can provide must be greater than or equal to 170mA, so that the dynamic range of the load current of the noise generation module 10 can cover the current fluctuation range of the preset current curve.

[0064] As described above, memory includes a chip and a package structure. The chip is housed within the package structure. Due to the presence of the package structure, the power supply noise of the memory chip cannot be directly measured. This disclosure addresses this by setting a signal transmission module 20 and configuring its electrical parameters to match the electrical parameters of the memory package structure. This avoids introducing other interference signals, allowing the noise detection results obtained using the testing equipment of this disclosure to accurately characterize the power supply noise of the memory chip during actual operation.

[0065] Typically, memory chips require multiple power supply signals, each with a different voltage value to meet the voltage requirements of different operations. For example, these multiple power supply signals may include VDD, VPP, and VTT voltages. VDD can be 1.2V, used to provide voltage for memory I / O operations and the memory chip itself; VPP can be 2.5V, used to provide the activation voltage for the memory; and VTT can be 0.6V, used to provide voltage for memory addressing operations, command operations, and the control bus. Each power supply signal constitutes its corresponding power network, and the test equipment provided in this disclosure can perform power noise tests on the power networks formed by each power supply signal separately.

[0066] For example, Figure 5 This is an equivalent circuit diagram of a power network in a signal transmission module according to one embodiment of the present disclosure. Figure 5 This explanation uses only a VDD power network as an example. Figure 5As shown, for each power network, its electrical parameters can be represented by an equivalent circuit consisting of an equivalent resistance (ESR), an equivalent inductance (ESL), and an equivalent capacitance (ESC). The first terminal of the ESR is connected to the signal input terminal of the power network. The second terminal of the ESR is connected to the first terminal of the ESL. The second terminal of the ESL is connected to the first terminal of the ESC, which in turn is connected to the signal output terminal of the power network. The second terminal of the ESC is grounded. The signal output terminal of the power network is connected to the noise generation module 10 via pins. This signal output terminal serves as the test pin for the power network's power noise; by connecting the probes of the testing equipment to this signal output terminal, the power noise of the memory chip in this power network can be detected.

[0067] It should be understood that the number of power networks in the signal transmission module 20 provided in this disclosure corresponds one-to-one with the number of power networks actually present in the memory, and the electrical parameters of each power network in the signal transmission module 20 are matched with the electrical parameters of the power network in the memory. That is, the electrical parameters of each power network in the signal transmission module 20 of this disclosure are specifically determined based on the electrical parameters of each power network in the memory.

[0068] In addition, such as Figure 5 As shown, the signal transmission module 20 of this disclosure may further include multiple decoupling units 203. The decoupling units 203 can be used to simulate the decoupling capacitors within the memory chip to reduce noise coupled from the noise generation module 10 to the power network. Each decoupling unit 203 corresponds one-to-one with a power network. In each power network, the first terminal of the decoupling unit 203 is connected to the signal output terminal of the corresponding power network, and the second terminal of the decoupling unit 203 is grounded. The decoupling unit 203 can be, for example, an equivalent decoupling capacitor C. The capacitance value of the equivalent decoupling capacitor C needs to match the capacitance value of the on-chip decoupling capacitor in the memory chip. For example, for the VDD power network, the equivalent capacitance value of the decoupling unit 203 connected to it is the same as the capacitance value of the decoupling capacitor corresponding to the VDD power network in the memory chip. By setting multiple decoupling units 203 that correspond to and match the on-chip decoupling capacitors in the memory chip, this disclosure enables the signal transmission module 20 to have the decoupling effect of the actual memory chip and memory package structure, allowing the power noise detected by the test equipment of this disclosure to truly characterize the actual power noise generated by the memory chip during current switching.

[0069] The signal transmission module 20 can be mounted on a circuit board, such as a PCB. In some embodiments, the electrical parameters of each power network in the signal transmission module 20 can be adjusted by changing the trace width of the power network on the circuit board, the stack-up structure of the circuit board, etc., so that the equivalent resistance (ESR), equivalent capacitance (ESC), and equivalent inductance (ESL) of the power network in the signal transmission module 20 correspond to the equivalent resistance, equivalent capacitance, and equivalent inductance of the same power network in the memory package structure, respectively. For example, increasing the trace width can reduce the resistance value of the equivalent resistance (ESR), decreasing the spacing thickness between the power and ground planes can increase the capacitance value (C) of the equivalent capacitance (ESC), and shortening the trace length can reduce the inductance value of the equivalent inductance (ESL). In other embodiments, corresponding equivalent resistances (ESR), equivalent capacitances (ESC), and equivalent inductances (ESL) can be set on the circuit board. The specific values ​​of these equivalent resistances (ESR), equivalent capacitances (ESC), and equivalent inductances (ESL) can be adjusted so that the equivalent resistances (ESR), equivalent inductances (ESL), and equivalent capacitances (ESC) of the signal transmission module 20 correspond identically to those of the memory package structure. For example, if adjusting the trace width or the stack-up structure of the circuit board cannot completely match the electrical parameters of the signal transmission module 20 with the electrical parameters of the memory package structure, corresponding equivalent resistances (ESR) and / or equivalent capacitances (ESC) and / or equivalent inductances (ESL) can be set on the circuit board of the signal transmission module 20 to ensure that the electrical parameters of the signal transmission module 20 correspond and match the electrical parameters of the package structure.

[0070] It is understood that the memory package structure has multiple package pins, through which the memory is connected to the motherboard 1. In an exemplary embodiment, as shown... Figure 5 As shown, the signal transmission module 20 may include a plurality of first pins 301, which may be arrayed along the row and column directions. The signal transmission module 20 is connected to the motherboard 1 through these first pins 301, and the number of first pins 301 is the same as the number of pins of the memory package, thereby ensuring that the electrical connection characteristics between the signal transmission module 20 and the motherboard 1 are the same as or nearly the same as the electrical connection characteristics between the memory package structure and the motherboard 1, thus improving the reliability of the test results of the test equipment of this disclosure.

[0071] In an exemplary embodiment, the pin type of the first pin 301 of the signal transmission module 20 connecting to the motherboard 1 can be the same as the pin type of the memory package pin. For example, if the memory package pin is a BGA pin structure, then the first pin 301 of the signal transmission module 20 connecting to the motherboard 1 in this disclosure is also a BGA pin structure. Of course, in other embodiments, the memory package pin can also be other structures, and accordingly, the signal transmission module 20 has a pin structure that matches the memory package pin, so that the signal transmission module 20 can be connected to the motherboard 1.

[0072] In addition, the signal transmission module 20 may also include multiple second pins 302, through which the signal transmission module 20 is connected to the noise generation module 10. Furthermore, the pin type of the second pins 302 may be the same as or different from the pin type of the first pins 301 of the signal transmission module 20, as long as electrical connection between the signal transmission module 20 and the noise generation module 10 can be ensured.

[0073] like Figure 1 , Figure 2 As shown, in an exemplary embodiment, the voltage acquisition module 30 can be, for example, a voltage measurement device such as an oscilloscope. The voltage acquisition module 30 may include multiple voltage interfaces, which are connected to the signal output terminals of the power networks of the signal transmission module 20. That is, one voltage interface is connected to the signal output terminal of each power network, so that the voltage acquisition module 30 can acquire the voltage signals of each power network through multiple voltage interfaces. Obviously, when the load current of the noise generation module 10 changes with a preset current curve, the voltage signals acquired by each voltage interface of the voltage acquisition module 30 are superimposed with the noise signal generated by the noise generation module 10. Therefore, the magnitude of the power supply noise signal during the actual operation of the memory chip can be analyzed based on the voltage signals acquired by the voltage acquisition module 30. For example, power supply noise signals can be analyzed based on voltage signal fluctuations. For instance, if the voltage signal fluctuation is small, i.e., the voltage signal is relatively stable, it indicates that the interference signal generated by the noise generation module 10 during load current changes is small, reflecting a small power supply noise signal generated by the memory chip during actual operation. Conversely, if the voltage signal fluctuation is large, it indicates that the interference signal generated by the noise generation module 10 during load current changes is large, reflecting a large power supply noise signal generated by the memory chip during actual operation, suggesting a higher risk for the chip. It should be understood that a large fluctuation in the voltage signal obtained from any voltage interface of the voltage acquisition module 30 indicates a higher risk for the memory chip; only when the voltage signals obtained from all voltage interfaces show small fluctuations does it indicate a low power supply noise signal for the memory chip. It should also be understood that in other embodiments, the power supply noise signal of the memory chip can be determined based on the voltage signal obtained from the voltage acquisition module 30 in other ways.

[0074] This disclosure also provides a power supply noise testing method, which can be applied to the power supply noise testing equipment described in any embodiment of this disclosure. Figure 6 This is a flowchart of a power supply noise testing method according to one embodiment of the present disclosure. Figure 7 This is a flowchart of a power supply noise testing method according to one embodiment of the present disclosure. Figure 7 The method shown is a test method specifically for the power network structure of the signal transmission module, such as... Figure 6 , Figure 7 As shown, the testing method may include the following steps:

[0075] S110, Control the mainboard to supply power to the signal transmission module;

[0076] S120. Start the noise generation module so that the load current of the noise generation module changes according to the preset current curve.

[0077] S130. Start the voltage acquisition module to acquire the voltage signal at the connection between the signal transmission module and the noise generation module.

[0078] S140. Analyze the power supply noise of the memory chip based on the voltage signal.

[0079] In step S110, after the test device provided in this disclosure is connected to the motherboard, the motherboard can output a corresponding power supply signal to the signal transmission module in the test device after being powered on.

[0080] In step S120, the noise generation module is activated. The load current of the noise generation module can change according to the preset current curve. The preset current curve is determined according to the design parameters of the memory chip. Thus, the dynamic current change of the memory chip during actual operation can be simulated through the noise generation module.

[0081] As mentioned above, the signal transmission module can have multiple power networks. The motherboard can provide corresponding power supply signals to the signal input terminals of each power network of the signal transmission module. The signal output terminals of the power networks of the signal transmission module are connected to the noise generation module. Therefore, the interference voltage signal generated by the noise generation module will be superimposed on the signal output terminals of each power network of the signal transmission module.

[0082] Then, in step S130, after startup, the signal acquisition module can acquire the voltage signals at the signal output terminals of each power network of the signal transmission module. Obviously, this voltage signal is superimposed with the interference signal from the noise generation module. Then, in step S140, by analyzing the voltage signal acquired by the voltage acquisition module, the interference signal generated by the noise generation module can be analyzed, that is, the power supply noise signal generated by the memory chip during actual operation. For example, the power supply noise signal of the memory chip can be determined by analyzing whether the acquired voltage signal changes smoothly. For instance, if the acquired voltage signal is relatively stable, it indicates that the interference signal generated by the noise generation module during load current changes is small, reflecting that the power supply noise signal generated by the memory chip during actual operation is small; if the acquired voltage signal fluctuates greatly, it indicates that the interference signal generated by the noise generation module during load current changes is large, reflecting that the power supply noise signal generated by the memory chip during actual operation is large, indicating that the chip has a greater risk. It should be understood that in other embodiments, the interference signal superimposed on the voltage signal can also be extracted using methods such as signal extraction to determine whether the interference signal is within the allowable noise range. These all fall within the protection scope of this disclosure.

[0083] It should be noted that the test method disclosed herein is based on pre-calibrated test equipment. That is, before running the test method described herein, the test equipment has already adjusted its relevant parameters, meaning the load current of the noise generation module can change according to a preset current curve, and the electrical parameters of the signal transmission module are matched to the electrical parameters of the memory package structure. The parameter debugging of the test equipment can be performed before running the test method disclosed herein. For details on the parameter debugging process, please refer to the description of the above-described equipment embodiments; it will not be detailed here.

[0084] It should be understood that the above steps are not sequential in time, and each step can be run simultaneously. The above sequence numbers are only for convenience of description and should not be interpreted as a restriction on the timing of the test method.

[0085] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A testing device, characterized in that, The testing equipment for acquiring power supply noise of memory chips includes: A noise generation module, wherein the load current of the noise generation module varies according to a preset current curve; A signal transmission module is connected between the noise generation module and the motherboard. The equivalent resistance, equivalent inductance, and equivalent capacitance of the signal transmission module are the same as those of the equivalent resistance, equivalent inductance, and equivalent capacitance of the memory package structure, respectively. A voltage acquisition module is connected at the connection point between the signal transmission module and the noise generation module. The voltage acquisition module is used to acquire the voltage signal at the connection point when the load current of the noise generation module changes. The voltage signal is used to determine the power supply noise of the memory chip.

2. The testing equipment according to claim 1, characterized in that, The preset current curve is determined based on the current-time curve of the CPM model in the memory chip.

3. The testing equipment according to claim 1, characterized in that, The noise generation module includes: power supply; Multiple load branches are connected to both ends of the power supply, and the load branches are arranged in parallel.

4. The testing equipment according to claim 3, characterized in that, The load currents of at least some of the load branches are the same and / or the load currents of at least some of the load branches are different.

5. The testing equipment according to claim 3, characterized in that, The load branch includes: The load resistor has its first end connected to one end of the power supply. The switching unit has a first terminal connected to the second terminal of the load resistor, and the second terminal connected to the other terminal of the power supply.

6. The testing equipment according to claim 5, characterized in that, The switching unit is a transistor; The control terminal of the transistor receives a switch control signal. The first terminal of the transistor is connected to the second terminal of the load resistor in the same load branch, and the second terminal of the transistor is connected to the other terminal of the power supply.

7. The testing equipment according to claim 6, characterized in that, The testing equipment also includes: A control module is configured to output the switch control signal based on a preset timing sequence.

8. The testing equipment according to claim 1, characterized in that, The memory package structure has multiple package pins, and the memory is connected to the motherboard through the package pins; The signal transmission module includes a plurality of first pins, which are connected to the motherboard. The number of first pins is the same as the number of package pins.

9. The testing equipment according to claim 8, characterized in that, The pin structure of the first pin is the same as that of the packaged pin.

10. The testing equipment according to claim 1, characterized in that, The signal transmission module includes: Multiple power networks, each power network including an equivalent resistance, an equivalent inductance, and an equivalent capacitance, wherein a first end of the equivalent resistance is connected to the signal input terminal of the power network, a second end of the equivalent resistance is connected to the first end of the equivalent inductance, the second end of the equivalent inductance is connected to the first terminal of the equivalent capacitance and then connected to the signal output terminal of the power network, and the second terminal of the equivalent capacitance is grounded. The voltage acquisition module has multiple voltage interfaces, which are connected one-to-one to the signal output terminals of the multiple power networks.

11. The testing equipment according to claim 10, characterized in that, The signal transmission module further includes: Multiple decoupling units are configured one-to-one with the power network. The first pole of each decoupling unit is connected to the signal output terminal of the corresponding power network, and the second pole of each decoupling unit is grounded.

12. The testing equipment according to claim 1, characterized in that, The noise generation module and the signal transmission module are mounted on the same circuit board; The dynamic range of the load current of the noise generation module is greater than or equal to the current fluctuation range of the preset current curve.

13. A power supply noise testing method, characterized in that, The test method, applied to the test apparatus according to any one of claims 1-12, comprises: The control motherboard supplies power to the signal transmission module; The noise generation module is activated so that its load current varies according to a preset current curve. The voltage acquisition module is activated to acquire the voltage signal at the connection point between the signal transmission module and the noise generation module. The power supply noise of the memory chip is analyzed based on the voltage signal.

14. A power supply noise testing method, characterized in that, The test method, applied to the test equipment of claim 10, comprises: The control motherboard supplies power to the signal transmission module so that the signal input terminals of each power network of the signal transmission module obtain the corresponding voltage signal. The noise generation module is activated so that its load current varies according to a preset current curve. The voltage acquisition module is activated to acquire the voltage signals of each signal output terminal of the signal transmission module through each voltage interface of the voltage acquisition module. The power noise of the corresponding power network is analyzed based on the voltage signal obtained from the voltage interface.

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