A high-precision laser echo waveform sequence timing method and system

Abstract

The present invention discloses a method and system for realizing high-stability and high-precision laser echo waveform sequence timing of full-waveform laser radar. The laser main wave and echo signal are collected by high-speed AD, and are input into the timing FPGA after threshold comparison. A high-stability constant temperature crystal oscillator, a high-frequency crystal oscillator ≥1Gsps, and a clock management chip together constitute a time synchronization management system, which generates a timing reference clock and a synchronous sampling clock and inputs them into the timing FPGA. The timing FPGA completes the time interval of each echo sampling point relative to the main wave, and then realizes the measurement of laser flight time by waveform analysis. The high-speed sampling waveform sampling point point-by-point timing is realized, which solves the technical problem of high-stability and high-precision waveform sequence timing for long-distance laser ranging. It lays the foundation for realizing high-precision laser ranging and ground object target feature recognition of full-waveform laser radar.

Description

Technical Field

[0001] The present invention relates to the field of laser radar signal processing, and in particular to a high-precision laser echo waveform sequence timing method and system. Background Art

[0002] Traditional LiDAR mainly obtains distance images by obtaining the time interval between the transmitted pulse and the echo pulse. However, the rich information contained in the echo waveform is not fully utilized. The new generation of LiDAR adopts full waveform acquisition and analysis technology. Through the mechanism of full waveform analysis of complex target characteristics, it can fully analyze the full waveform comprehensive information including pulse time information, amplitude information, pulse width information and multi-echo distribution. The waveform sorting algorithm can be used to separate trees, crops and the ground surface, and further realize the quantitative measurement of biomass such as vegetation height. Therefore, compared with traditional LiDAR, full waveform LiDAR has the advantages of obtaining richer information and higher ranging accuracy.

[0003] Existing full-waveform lidars usually measure the laser flight time by counting the sampling points between the transmitting pulse and the echo pulse, and further analyze and calculate the ranging distance. In order to improve the timing accuracy, a temperature-compensated crystal oscillator or a constant temperature crystal oscillator is generally used as a high-speed sampling clock. The frequency stability of the temperature-compensated crystal oscillator is relatively poor, especially for the hundreds of kilometers of ranging on the satellite platform, which will introduce a large error. The constant temperature crystal oscillator clock frequency is difficult to achieve a very high frequency. Even if it can exceed 1GHz, it cannot be used in engineering projects due to the high cost. Summary of the invention

[0004] In view of the above-mentioned shortcomings, the present invention provides an echo sequence timing technology based on a time synchronization management system, which realizes the delay of the sampling moment of each sampling point in the echo sequence relative to the transmitting pulse. Through waveform analysis, laser ranging and ground target feature recognition can be further realized, solving the technical difficulties of high-precision and high-stability echo waveform acquisition and timing in long-distance laser ranging.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] A laser echo sequence high-precision timing method, characterized in that it specifically comprises the following steps:

[0007] S1: The constant temperature crystal oscillator is the system clock reference source, which is input to the FPGA-TDC and the clock management chip respectively;

[0008] S2: The constant temperature crystal oscillator clock is multiplied inside the FPGA to generate a rough counting reference clock for timing, which is used by the FPGA-TDC function module for timing.

[0009] S3: The RF crystal oscillator is input to the clock management chip, which is phase-locked with the constant temperature crystal oscillator clock to generate a sampling clock output to the high-speed AD. The high-speed AD realizes the analog-to-digital conversion of the laser echo signal and outputs a high-speed echo waveform sequence signal;

[0010] S4: The clock management chip outputs a sampling synchronization clock that is synchronized with the high-speed AD sampling clock, but the clock frequency is reduced to a level that the FPGA can handle.

[0011] S5: The transmitted pulse signal and echo sequence are input into the FPGA, and the echo sequence is continuously cached into the FPGA. Meanwhile, after the FPGA detects that the amplitude of the echo sequence exceeds the threshold, the FPGA-TDC functional module realizes the time interval between the first sampling synchronization clock edge after the threshold is exceeded and the transmitted pulse signal.

[0012] S6: The sampling synchronization clock edge time measured by the FPGA-TDC corresponds to the waveform sampling point in the FPGA buffer area, and an echo waveform sequence marked with the sampling time is output.

[0013] S7: Waveform inversion analysis is performed based on the echo waveform sequence marked with sampling time to achieve laser ranging and ground target feature recognition.

[0014] In the above method and system of the present invention, it is characterized in that: the reference clock source of step S1: a high-stability constant temperature crystal oscillator is used as the FPGA-TDC timing reference clock and also as the reference clock of the clock management chip.

[0015] Preferably, in the above-mentioned method and system of the present invention, the timing clock in step S2 adopts a constant temperature crystal oscillator clock as a clock source, and generates the timing clock by clock multiplication of 1 times or more. The timing clock serves as a coarse counting clock, and the timing time is obtained by a combination of coarse counting, the time interval between the emission pulse and the coarse counting clock edge, and the time interval between the first sampling clock edge after crossing the threshold and the coarse counting clock edge.

[0016] Preferably, in the above method and system of the present invention, the high-speed AD sampling clock in step S3 uses a radio frequency crystal oscillator as a clock source, and after being phase-locked with a constant temperature crystal oscillator reference clock, a high-quality clock is output by a clock management chip.

[0017] Preferably, in the above-mentioned method and system of the present invention, the synchronous clock input into the FPGA for timing in step S4 is generated by a clock management chip or a high-speed AD after frequency reduction, and the frequency-reduced clock can be processed by the FPGA.

[0018] Preferably, in the above method and system of the present invention, in step S5, the time interval between the sampling synchronization clock edge and the transmission pulse is measured, and the selection criteria of the synchronization clock edge are after passing the threshold and being easy to correspond to the sampling point.

[0019] Preferably, in the above method and system of the present invention, in step S6, the FPGA caches the echo sequence, and there is a fixed correspondence between the sampling synchronization clock and the sampling point. The edge of the synchronization clock after crossing the threshold is matched with a certain sampling point in the memory relative to the time interval of the transmitted pulse to form the sampling moment of the sampling point. After the moment of a sampling point is marked, the entire echo sequence is timed.

[0020] Preferably, in the above-mentioned method and system of the present invention, in step S7, a waveform analysis algorithm is applied to the echo waveform sequence marked with the sampling time to locate the peak, centroid, centroid and other moments of the waveform, and calculate the flight time from the echo sequence positioning moment to the laser emission pulse.

[0021] A method and system for realizing high-stability and high-precision laser echo waveform sequence timing of full-waveform laser radar. The laser main wave and echo signal are collected by high-speed AD, and are input into the timing FPGA after threshold comparison. The high-stability constant temperature crystal oscillator, ≥1Gsps high-frequency crystal oscillator and clock management chip together form a time synchronization management system, which generates a timing reference clock and a synchronous sampling clock and inputs them into the timing FPGA. The timing FPGA completes the time interval of each echo sampling point relative to the main wave, and then realizes the measurement of laser flight time through waveform analysis. The high-speed sampling waveform sampling point timing is realized point by point, which solves the technical problem of high-stability and high-precision waveform sequence timing for long-distance laser ranging. It lays the foundation for realizing high-precision laser ranging and ground target feature recognition of full-waveform laser radar.

[0022] To achieve the above object, the present invention provides the following technical solutions:

[0023] A laser echo sequence high-precision timing method, comprising:

[0024] The clock management module inputs the constant temperature crystal oscillator clock and the RF steady crystal oscillator clock, and outputs the high-speed AD sampling clock after phase locking with the constant temperature crystal oscillator clock, as well as the high-speed AD sampling synchronization;

[0025] The constant temperature crystal oscillator module is the system clock reference source and is input to the FPGA-TDC and clock management chip;

[0026] RF crystal oscillator module, which is a high-speed AD sampling clock source with a clock frequency greater than 1GHz;

[0027] FPGA-TDC module, which measures the time interval between the first rising edge of the synchronous clock and the laser emission pulse signal after the laser echo waveform passes the threshold;

[0028] FPGA data cache and processing module, FIFO stores laser echo waveform sampling points, marks the sampling point time according to the FPGA-TDC timing result, and finally outputs the waveform sampling points and the sampling point marking time.

[0029] High-speed AD module realizes the conversion of laser echo analog signal to digital signal, with AD quantization bit greater than 8 bits and sampling rate ≥1Gsps;

[0030] The above scheme uses the technical scheme of combining constant temperature crystal oscillator and radio frequency crystal oscillator. The low-frequency constant temperature crystal oscillator is used as the clock reference source to reduce the difficulty of system design and ensure the timing accuracy and high stability at the same time. On the other hand, the sampling and simultaneous clock is used as the end signal of echo timing, avoiding the circuit of analog echo edge detection and realizing the full digital processing of waveform sequence timing.

[0031] The present invention provides a method for timing an echo waveform sequence in a full-waveform laser radar, which is based on a low-clock frequency constant-temperature crystal oscillator, a high-speed temperature-compensated crystal oscillator, a clock management chip, and an FPGA-TDC system, and has the advantages of high precision, high reliability, and low cost. The high-precision timing technology for sampling points of a laser radar high-speed echo waveform sequence based on a time synchronization management system adopted by the present invention is widely applicable to full-waveform laser radars to realize laser ranging, and is particularly applicable to satellite-borne and airborne laser radars, and can realize high-precision analysis of complex ground target features under long-distance conditions.

[0032] Advantages of the present invention:

[0033] 1. The system is easy to build and low cost: This method does not place excessive demands on the selected devices. The constant temperature crystal oscillator used is a low-frequency clock with strong availability and low cost. No dedicated timing chip is used, and FPGA is used to implement the TDC function, which improves the system's integration. Compared with the previous technical route of using high-frequency constant temperature crystal oscillators and dedicated timing chips, the project is more feasible and has lower costs.

[0034] 2. High stability, suitable for long-distance ranging: This method uses a constant temperature crystal oscillator as the clock reference for FPGA-TDC timing and high-speed AD waveform sampling, and performs synchronization management through a clock management chip. It has the characteristics of high temperature stability and small time drift, and is particularly suitable for satellite-borne laser ranging applications of hundreds of kilometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the system framework of the present invention;

[0037] Figure 2 It is a schematic diagram of the laser ranging principle of the high-precision laser echo waveform sequence timing technology based on the time synchronization management system of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] An example of a system implementation of the method of the present invention is Figure 1 As shown, the constant temperature crystal oscillator outputs a low-frequency clock to the clock management chip and FPGA, and the RF crystal oscillator inputs the clock management chip, which outputs a high-quality clock as the high-speed sampling clock of the high-speed AD after phase locking with the constant temperature crystal oscillator reference clock. The clock management chip synchronously outputs the sampling synchronization clock to the FPGA, and its frequency is obtained after the high-speed AD sampling clock is reduced. The echo analog signal is output to the high-speed AD, and the echo sequence is output to the FPGA after analog-to-digital conversion. The FPGA clock module uses the constant temperature crystal oscillator as a reference to generate a reference clock for the FPGA-TDC module to measure time. The transmitted pulse signal is input to the FPGA, and the FPGA cache receives the echo sequence. The FPGA-TDC module measures the time interval between the first sampling synchronization clock edge and the transmitted pulse after the echo sequence crosses the threshold, thereby realizing the echo waveform sequence timing and marking the sampling time of the echo waveform sequence sampling point.

[0040] Figure 2 for Figure 1 The timing relationship diagram of each signal marked in the system implementation example reflects the principle of high-precision laser echo waveform sequence timing technology based on the time synchronization management system, where:

[0041] a constant temperature crystal oscillator clock;

[0042] bRF crystal oscillator clock;

[0043] c is a high-speed AD sampling clock output after being phase-locked with the constant temperature crystal oscillator clock;

[0044] d High-speed AD sampling synchronous clock (after frequency reduction);

[0045] e echo analog signal;

[0046] f transmits a pulse signal;

[0047] gEcho sequence after high-speed AD analog-to-digital conversion;

[0048] h threshold after sampling the first clock rising edge of the synchronous clock and the time interval between the transmitted pulse;

[0049] i echo sequence sampling point marks the sampling moment;

[0050] The FPGA outputs an echo sequence marked with the sampling time to the waveform analysis unit. After waveform inversion analysis, the peak, centroid or centroid of the positioning waveform and other characteristic moments are obtained. Laser ranging is achieved by calculating the echo pulse flight time. For complex waveform shapes, the characteristics of ground objects can be further recognized.

[0051] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for high-precision timing of full-waveform laser radar laser echo sequence, It is characterized in that The method comprises the following steps: S1: The constant temperature crystal oscillator is the system clock reference source, which is input to the FPGA-TDC and the clock management chip respectively; S2: The constant temperature crystal oscillator clock is multiplied inside the FPGA to generate a rough counting reference clock for timing, which is used by the FPGA-TDC function module for timing; S3: The RF crystal oscillator is input to the clock management chip, which is phase-locked with the constant temperature crystal oscillator clock to generate a sampling clock output to the high-speed AD. The high-speed AD realizes the analog-to-digital conversion of the laser echo signal and outputs a high-speed echo waveform sequence signal; S4: The clock management chip outputs a sampling synchronization clock, which is synchronized with the high-speed AD sampling clock, but the clock frequency is reduced to a level that the FPGA can handle; S5: The transmitting pulse signal and the echo sequence are input to the FPGA, and the echo sequence is continuously cached to the FPGA. At the same time, after the FPGA detects that the amplitude of the echo sequence exceeds the threshold, the FPGA-TDC function module realizes the time interval between the first sampling synchronization clock edge after the threshold is exceeded and the transmitting pulse signal; S6: The sampling synchronization clock edge time measured by FPGA-TDC corresponds to the waveform sampling point in the FPGA buffer area, and an echo waveform sequence marked with the sampling time is output; S7: Waveform inversion analysis is performed based on the echo waveform sequence marked with sampling time to achieve laser ranging and ground target feature recognition.

2. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that The reference clock source of step S1: a high-stability constant temperature crystal oscillator is used as the FPGA-TDC timing reference clock and also as the reference clock of the clock management chip.

3. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that The timing clock in step S2 uses a constant temperature crystal oscillator clock as a clock source, and generates a timing clock by clock multiplication of 1 or more. The timing clock is used as a coarse counting clock, and the timing time is obtained by combining the coarse counting, the time interval between the emission pulse and the coarse counting clock edge, and the time interval between the first sampling clock edge after crossing the threshold and the coarse counting clock edge.

4. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that In step S3, the high-speed AD sampling clock uses a radio frequency crystal oscillator as a clock source, and after being phase-locked with a constant temperature crystal oscillator reference clock, a high-quality clock is output by a clock management chip.

5. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that The synchronous clock input into the FPGA for timing in step S4 is generated by a clock management chip or a high-speed AD after frequency reduction, and the frequency-reduced clock can be processed by the FPGA.

6. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that In step S5, the time interval between the sampling synchronization clock edge and the transmission pulse is measured, and the selection criteria of the synchronization clock edge are after the threshold value is passed and it is easy to correspond to the sampling point.

7. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that In step S6, the FPGA caches the echo sequence, and there is a fixed corresponding relationship between the sampling synchronization clock and the sampling point. The edge of the synchronization clock after crossing the threshold is matched with a certain sampling point in the memory relative to the transmission pulse time interval to form the sampling moment of the sampling point. After a sampling point is marked, the entire echo sequence is timed.

8. The method for high-precision timing of a full-waveform laser radar laser echo sequence according to claim 1, It is characterized in that In step S7, a waveform analysis algorithm is applied to the echo waveform sequence marked with the sampling time to locate the peak, centroid, centroid and other moments of the waveform, and to calculate the flight time from the echo sequence positioning moment to the laser emission pulse.

9. A high-precision timing system for full-waveform laser radar laser echo sequence, It is characterized in that include: The clock management module inputs the constant temperature crystal oscillator clock and the RF temperature compensated crystal oscillator clock, and outputs the high-speed AD sampling clock after phase locking with the constant temperature crystal oscillator clock, as well as the high-speed AD sampling synchronization; The constant temperature crystal oscillator module is the system clock reference source and is input to the FPGA-TDC and clock management chip; RF crystal oscillator module, which is a high-speed AD sampling clock source with a clock frequency greater than 1GHz; FPGA-TDC module, which measures the time interval between the first rising edge of the synchronous clock and the laser emission pulse signal after the laser echo waveform passes the threshold; FPGA data cache and processing module, FIFO stores laser echo waveform sampling points, marks the sampling point time according to the FPGA-TDC timing results, and finally outputs the waveform sampling points and the sampling point marking time; High-speed AD module realizes the conversion of laser echo analog signal to digital signal. The AD quantization bit number is greater than 8 bits and the sampling rate is ≥1Gsps.

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