A method for manufacturing an enhanced field effect transistor and a device

Abstract

The application discloses a preparation method of an enhanced field effect transistor and a device, and the method comprises the following steps: obtaining a preparation substrate; the preparation substrate comprises a substrate layer, a channel layer and a barrier layer which are sequentially grown on the substrate layer; AlGaN base layers and GaN quantum dots are sequentially grown on the preparation substrate under a magnesium source atmosphere, and after the growth of the GaN quantum dots is completed, the gallium source is turned off while the nitrogen source is kept on for a preset time; the magnesium source is turned off, and the AlGaN buried layer is grown on the GaN quantum dots; the AlGaN base layers, the GaN quantum dots and the AlGaN buried layer are grown for multiple cycles, and the P-AlGaN gate dielectric layer is formed by etching; the source electrode and the drain electrode are grown on the barrier layer, and the gate electrode is grown on the P-AlGaN gate dielectric layer. The method can improve the breakdown voltage of the prepared enhanced device and reduce the on-resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of an enhancement-mode field effect transistor and an enhancement-mode field effect transistor device. BACKGROUND

[0002] Gallium nitride (GaN) is the third generation of wide band gap semiconductor material representative, which is widely concerned by researchers all over the world. As the key material of high-voltage and high-frequency devices, GaN and its related nitrides are attributed to their wide band gap, high electron saturation velocity and high breakdown field strength. Compared with Si, the band gap of GaN is more than three times, the breakdown field strength is ten times, and the electron saturation velocity reaches 2.7×10 7 cm / s; therefore, compared with Si-based devices, GaN-based HEMT devices have lower on-resistance, smaller parasitic capacitance, higher breakdown voltage and other excellent performances, which can meet the application requirements of larger power, smaller size and higher frequency of semiconductor devices for the next generation system.

[0003] The traditional HEMT device based on AlGaN / GaN heterojunction is a depletion-mode device due to the existence of spontaneous polarization and piezoelectric polarization effects to form a natural two-dimensional electron gas conduction channel. However, due to the complexity of the design of the driving circuit and the reduction of the reliability of the depletion-mode device, an enhancement-mode HEMT device is needed to meet the application requirements. Among the several commonly used enhancement-mode technologies, P-GaN enhancement-mode devices have been commercialized. The implementation method of P-GaN HEMT device is to epitaxially grow a P-type GaN layer in the gate region, and the P-GaN forms a PiN structure with the AlGaN / GaN heterojunction. The built-in electric field in the diode-like structure can offset the electric field effect of the spontaneous polarization and piezoelectric polarization in the AlGaN / GaN heterojunction, so as to deplete the two-dimensional electron gas under the gate, thereby making the device have a normally-off characteristic.

[0004] However, the P-GaN HEMT device still has problems such as low breakdown voltage, which need to be solved. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to solve the problem of low breakdown voltage of the existing enhancement-mode field effect transistor, and to provide a preparation method of an enhancement-mode field effect transistor with high breakdown voltage and low on-resistance, and an enhancement-mode field effect transistor device prepared by the preparation method.

[0006] To this end, according to a first aspect, the present application provides a preparation method of an enhancement-mode field effect transistor, comprising the following steps:

[0007] obtaining a preparation substrate; the preparation substrate comprises a substrate layer and a channel layer and a barrier layer successively grown on the substrate layer;

[0008] growing the AlGaN base layer and the GaN quantum dots on the prepared substrate under the magnesium source atmosphere in sequence, and turning off the gallium source while keeping the nitrogen source on for a preset time after the growth of the GaN quantum dots is completed;

[0009] turning off the magnesium source, and growing the AlGaN buried layer on the GaN quantum dots;

[0010] repeatedly growing the AlGaN base layer, the GaN quantum dots and the AlGaN buried layer, and etching to form the P-AlGaN gate dielectric layer;

[0011] growing the source electrode and the drain electrode on the barrier layer, and growing the gate electrode on the P-AlGaN gate dielectric layer.

[0012] Further, the channel layer is a first AlGaN structure layer, the barrier layer is a second AlGaN structure layer, and the Al component in the second AlGaN structure layer is higher than the Al components in the first AlGaN structure layer and the P-AlGaN gate dielectric layer.

[0013] Further, the Al component content in the first AlGaN structure layer is between 20% and 70%, the Al component content in the second AlGaN structure layer is between 30% and 80%, and the Al component content in the P-AlGaN gate dielectric layer is between 20% and 70%.

[0014] Further, the preparation method of the enhancement mode field effect transistor further comprises the following steps:

[0015] growing a passivation layer on the barrier layer; the passivation layer covers the source electrode, the gate electrode and the drain electrode.

[0016] Further, the prepared substrate further comprises a buffer layer grown between the substrate layer and the channel layer.

[0017] Further, the growth time of the AlGaN base layer is between 10 seconds and 50 seconds, the growth time of the GaN quantum dots is between 1 second and 20 seconds, and the preset time for keeping the nitrogen source on after turning off the gallium source is between 10 seconds and 50 seconds.

[0018] According to a second aspect, the present application further provides an enhancement mode field effect transistor device, comprising:

[0019] a substrate and a channel layer and a barrier layer grown on the substrate in sequence;

[0020] A P-AlGaN gate dielectric layer is grown on the barrier layer in a position region under the gate; the P-AlGaN gate dielectric layer comprises a plurality of AlGaN base layers, GaN quantum dots and AlGaN buried layers which are alternately stacked, and Mg is doped in the AlGaN base layers and the GaN quantum dots, and the AlGaN buried layers are non-intentionally doped layers;

[0021] A source electrode, a drain electrode and a gate electrode are grown on the barrier layer, and the gate electrode is grown on the P-AlGaN gate dielectric layer.

[0022] Further, the channel layer is a first AlGaN structure layer, the barrier layer is a second AlGaN structure layer, and the Al component in the second AlGaN structure layer is higher than that in the first AlGaN structure layer and the P-AlGaN gate dielectric layer.

[0023] Further, the enhanced field effect transistor device further comprises:

[0024] A passivation layer is grown on the barrier layer and covers the source electrode, the gate electrode and the drain electrode.

[0025] The technical scheme provided by the present application has the following advantages:

[0026] 1. The preparation method of the enhanced field effect transistor provided by the present application can make the heterojunction between the P-AlGaN gate dielectric layer and the barrier layer / channel layer form a PiN structure, that is, the device prepared by the method has a normally-off characteristic (is an enhanced device); by using the alternating layers of Mg-doped (AlGaN base layer and GaN quantum dot) / non-Mg-doped (AlGaN buried layer) when growing the P-AlGaN gate dielectric layer, the holes generated in the Mg-doped layer can diffuse into the adjacent non-Mg-doped layer, and due to the weak ionization impurity scattering of the non-Mg-doped layer, the hole mobility can be significantly improved; and by embedding GaN quantum dots in the Mg-doped layer, the band edge displacement caused by the embedded local quantum structure reduces the activation energy of the acceptor (Mg), thereby achieving a high hole concentration, so that the prepared enhanced field effect transistor device has the performance of high breakdown voltage and low on-resistance.

[0027] Further, by keeping the N source and Mg source open for a preset time after the growth of the AlGaN base layer and GaN quantum dots is completed, and then closing the Ga source, the Mg atoms adsorbed on the surface of the GaN quantum dots are replaced by Ga atoms to become acceptor centers, the self-compensation effect of Mg is reduced, the hole concentration of the P-AlGaN gate dielectric layer can be further improved; at the same time, by cutting off the Ga source during the doping process, that is, the growth of GaN is intermittently interrupted, the dislocation climbing is reduced, the dislocation density is reduced, so that the interface between the AlGaN base layer and the GaN quantum dots is uniform, the hole mobility in the prepared enhancement-mode field effect transistor device is further improved, and the on-resistance is further reduced.

[0028] 2、The preparation method of the enhancement-mode field effect transistor provided by the application can fully exert the characteristics of the AlGaN material, and further improve the breakdown voltage of the prepared enhancement-mode field effect transistor device and the stability of the device at high temperature. x Ga 1-x N / Al y Ga 1-y heterojunction), the characteristics of the AlGaN material can be fully exerted, and the breakdown voltage of the prepared enhancement-mode field effect transistor device and the stability of the device at high temperature can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] Figure 1 The flow chart of the preparation method of the enhancement-mode field effect transistor provided by the embodiment of the application is shown in the figure.

[0031] Figure 2 The structure schematic diagram of the enhancement-mode field effect transistor device provided by the embodiment of the application is shown in the figure.

[0032] Figure 3 The structure schematic diagram of the enhancement-mode field effect transistor device provided by the embodiment of the application is shown in the figure.

[0033] Figure 4 The structure schematic diagram of the enhancement-mode field effect transistor device provided by the embodiment of the application is shown in the figure.

[0034] Explanation of reference signs:

[0035] 11-Substrate; 12-Channel layer; 13-Barrier layer; 14-Buffer layer; 2-P-AlGaN gate dielectric layer; 3-Source; 4-Drain; 5-Gate; 6-Passivation layer. Detailed Implementation

[0036] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] Example 1

[0039] This embodiment provides a method for fabricating an enhancement-mode field-effect transistor, such as... Figure 1 As shown, the method includes the following steps:

[0040] S10: Obtain the substrate for preparation.

[0041] In this embodiment, as Figure 2 As shown, the substrate includes a substrate 11 layer and a channel layer 12 and a barrier layer 13 sequentially grown on the substrate 11 layer.

[0042] In this embodiment, the substrate can be prepared together with the entire method, or it can be a preform obtained directly. Specifically, taking the preparation of the substrate as an example where it is prepared together with the entire method, the substrate can be prepared through the following steps:

[0043] (1) Obtaining the substrate 11. In this embodiment, the material of the substrate 11 can be any of the existing substrate materials such as Si, SiC, or sapphire. Of course, the substrate 11 can also be prepared together in the entire process of the method, and the preparation process is an existing technology, which will not be described in detail here.

[0044] (2) A channel layer 12 is grown on the substrate 11 using chemical vapor deposition (MOCVD) or other methods. Specifically, the thickness of the channel layer 12 can be between 50 nm and 500 nm.

[0045] (3) A barrier layer 13 is grown on the channel layer 12 by chemical vapor deposition (MOCVD) or other methods. As shown, a channel (heterojunction) of two-dimensional electron gas is formed between the channel layer 12 and the barrier layer 13. Specifically, the thickness of the barrier layer 13 can be between 5 nm and 100 nm. Figure 2

[0046] In this embodiment, in order to fully exert the characteristics of the AlGaN material, further improve the breakdown voltage of the enhancement-mode field effect transistor device prepared by this method and its stability at high temperature, while reducing the lattice mismatch between the channel layer 12 and the barrier layer 13 and improving the stability of the prepared enhancement-mode field effect transistor device, the channel layer 12 can be set as a first AlGaN structure layer, the barrier layer 13 is set as a second AlGaN structure layer (a heterojunction formed between the two is an AlGaN / AlGaN heterojunction), and the Al content in the second AlGaN structure layer is higher than the Al content in the first AlGaN structure layer. Specifically, the Al content in the first AlGaN structure layer can be between 20% and 70%, and the Al content in the second AlGaN structure layer can be between 30% and 80%. x Ga 1-x N / Al y Ga 1-y N heterojunction).

[0047] In this embodiment, in order to improve the quality of the channel layer 12 and the barrier layer 13, especially the quality of both when the channel layer 12 and the barrier layer 13 are both AlGaN material layers, a buffer layer 14 can be grown on the substrate 11 before growing the channel layer 12 by chemical vapor deposition (MOCVD) or other methods. Specifically, the material of the buffer layer 14 can be one or more of GaN, AlGaN, and AlN. Specifically, the thickness of the buffer layer 14 can be between 100 nm and 10 um.

[0048] S20: Growing an AlGaN base layer and GaN quantum dots on the prepared substrate under a magnesium source atmosphere, and after completing the growth of the GaN quantum dots, turning off the gallium source while keeping the nitrogen source on for a preset time.

[0049] Specifically, the AlGaN base layer can be grown by chemical vapor deposition (MOCVD) method, at this time, the growth atmosphere of the chemical vapor deposition reaction chamber can include TMAl, NH3, TMGa and Cp2Mg, and the growth time can be between 10 seconds and 50 seconds.

[0050] ​Specifically, the GaN quantum dots can also be grown by the chemical vapor deposition (MOCVD) method, in which case the growth atmosphere of the chemical vapor deposition reaction chamber can include NH3, TMGa and Cp2Mg (i.e. TMAl is turned off after the growth of the AlGaN base layer is completed), and the growth time can be between 1 second and 20 seconds.

[0051] Specifically, the entire growth process based on step S20 is performed in a magnesium source atmosphere, and therefore, after the growth of the GaN quantum dots is completed, the growth atmosphere including NH3 and Cp2Mg is continuously maintained for a preset time. Specifically, the preset time can be between 10 seconds and 50 seconds.

[0052] S30: Turn off the magnesium source and grow an AlGaN buried layer on the GaN quantum dots.

[0053] Specifically, the AlGaN buried layer can be grown by the chemical vapor deposition (MOCVD) method, in which case the growth atmosphere of the chemical vapor deposition reaction chamber can include TMAl, NH3 and TMGa (i.e. this AlGaN buried layer is an unintentionally doped AlGaN layer). Specifically, the thickness of the AlGaN buried layer can be between 1 nm and 20 nm.

[0054] S40: repeatedly grow the AlGaN base layer, the GaN quantum dots and the AlGaN buried layer, and etch to form a P-AlGaN gate dielectric layer 2.

[0055] Specifically, the number of cycles of the repeated growth of the AlGaN base layer, the GaN quantum dots and the AlGaN buried layer can be between 20 and 100 periods, so as to form a P-AlGaN layer with a thickness of 20 nm to 200 nm.

[0056] Specifically, before the P-AlGaN layer is etched to form the P-AlGaN gate dielectric layer 2, the P-AlGaN layer also needs to be subjected to an annealing treatment, and specifically, the annealing treatment temperature can be between 700°C and 900°C, and the annealing treatment time can be between 10 min and 20 min. In addition, the grown P-AlGaN layer can also be subjected to an 800°C to 1000°C non-in-situ annealing for 10 min to 20 min in an N2 atmosphere, so as to further remove H atoms combined with Mg atoms and improve the activation efficiency of the Mg atoms. Specifically, the doping concentration of Mg ions in the P-AlGaN layer can be between 1 x E18cm -3 ~ 5 x E19cm -3

[0057] Specifically, the P-AlGaN gate dielectric layer 2 is obtained by performing ICP etching on the P-AlGaN layer and only retaining the part of the region below the gate 5, and the specific etching process is the prior art and will not be described here. ​

[0058] Specifically, the Al content in the P-AlGaN gate dielectric layer 2 is lower than the Al content in the second AlGaN structural layer (barrier layer 13), and the Al content in the P-AlGaN gate dielectric layer 2 can be between 20% and 70%.

[0059] S50: Source 3 and drain 4 are grown on barrier layer 13, and gate 5 is grown on P-AlGaN gate dielectric layer 2.

[0060] Specifically, such as Figure 2 As shown, source 3 and drain 4 are located on both sides of gate 5, respectively. Source 3 and drain 4 can be formed by sequentially depositing germanium / titanium / aluminum / titanium / titanium nitride using electron beam evaporation technology (the metal structure of source 3 and drain 4 is set to be compatible with Al). x Ga 1-x N / Al y Ga 1-y The N heterojunction is formed by N-type heavy doping to reduce the ohmic contact resistance (of course, both can be other existing metal structures), and then annealed to form the ohmic contact. The thickness of the germanium metal layer can be between 1 nm and 20 nm.

[0061] Specifically, Ni / Au can be deposited sequentially using electron beam evaporation to form the gate 5, which can be a Schottky contact or a metal-dielectric-semiconductor structure.

[0062] In this embodiment, after step S50 is completed, step S60 can be performed: a passivation layer 6 is grown on the barrier layer 13. Specifically, as shown... Figure 3 As shown, the passivation layer 6 can be disposed only on the portion of the barrier layer 13 excluding the areas covered by the source 3, drain 4, and P-AlGaN gate dielectric layer 2 (that is, the exposed portion of the passivation layer 6 on the barrier layer 13, the portion not covered by the source 3, drain 4, and P-AlGaN gate dielectric layer 2); or, as... Figure 4 As shown, a passivation layer 6 can also be provided to cover the source 3, gate 5, and drain 4, that is, the passivation layer 6 covers the entire area above the barrier layer 13, in order to isolate the barrier layer 13 from direct contact with the gate 5, reduce gate leakage current, and improve the device breakdown voltage. Specifically, the passivation layer 6 can be deposited using the PECVD method, and the material of the passivation layer 6 is nitride, aluminum oxide, or AlN, etc.

[0063] The preparation method of the enhancement-mode field effect transistor in the embodiment can form a PiN structure for the heterojunction between the P-AlGaN gate dielectric layer 2 and the barrier layer 13 / channel layer 12, that is, the device prepared by the method has a normally-off characteristic (is an enhancement-mode device); the alternating layer of the Mg-doped (AlGaN matrix layer and GaN quantum dot) / non-Mg-doped (AlGaN buried layer) is used when the P-AlGaN gate dielectric layer 2 is grown, so that the holes generated in the Mg-doped layer can diffuse into the adjacent non-Mg-doped layer, and the weakly ionized impurity scattering of the non-Mg-doped layer can significantly improve the hole mobility; and the GaN quantum dot embedded in the Mg-doped layer can reduce the acceptor (Mg) activation energy caused by the band edge displacement of the embedded local quantum structure, thereby achieving a high hole concentration, and the enhancement-mode field effect transistor device prepared by the method has the performance of high breakdown voltage and low on-resistance.

[0064] In addition, after the growth of the AlGaN matrix layer and the GaN quantum dot is completed, the Ga source is turned off and the N source and the Mg source are kept on for a preset time, so that the Mg atoms adsorbed on the surface of the GaN quantum dot replace the Ga atoms to become acceptor centers, the self-compensation effect of Mg is reduced, the hole concentration of the P-AlGaN gate dielectric layer 2 can be further improved; at the same time, the Ga source is cut off during the doping process, that is, the growth of GaN is intermittently interrupted, so that the dislocation climbing is reduced, the dislocation density is reduced, the interface between the AlGaN matrix layer and the GaN quantum dot is kept uniform, the hole mobility in the prepared enhancement-mode field effect transistor is further improved, and the on-resistance is further reduced.

[0065] Embodiment 2

[0066] The embodiment provides an enhancement-mode field effect transistor device, which is prepared by the preparation method of the enhancement-mode field effect transistor in the above-mentioned embodiment 1, and thus the content stated in embodiment 1 will not be repeated here.

[0067] As shown in Figures 2-4 , the device comprises a substrate 11, a channel layer 12, a barrier layer 13, a P-AlGaN gate dielectric layer 2, a source 3, a drain 4 and a gate 5.

[0068] The channel layer 12 and the barrier layer 13 are sequentially grown on the substrate 11. Specifically, the channel layer 12 can be a first AlGaN structure layer, the barrier layer 13 can be a second AlGaN structure layer, and the Al component in the second AlGaN structure layer is higher than that in the first AlGaN structure layer and the P-AlGaN gate dielectric layer 2 described below.

[0069] The P-AlGaN gate dielectric layer 2 is grown on the gate-down position area of the barrier layer 13. Specifically, the P-AlGaN gate dielectric layer 2 comprises a plurality of AlGaN base layers, GaN quantum dots and AlGaN buried layers which are alternately stacked, and the AlGaN base layers and GaN quantum dots are doped with Mg, while the AlGaN buried layers are non-intentionally doped layers (not doped with Mg).

[0070] The source electrode 3 and the drain electrode 4 are grown on the barrier layer 13, and the gate electrode 5 is grown on the P-AlGaN gate dielectric layer 2, and the source electrode 3 and the drain electrode 4 are respectively located on the two sides of the gate electrode 5.

[0071] In the embodiment, as shown in Figures 2-4 , the buffer layer 14 can also be included between the substrate 11 and the channel layer 12.

[0072] In the embodiment, as shown in Figure 3 and Figure 4 , the passivation layer 6 can also be grown on the barrier layer 13. Specifically, as shown in Figure 3 , the passivation layer 6 can be provided only on the part of the barrier layer 13 other than the covered area of the source electrode 3, the drain electrode 4 and the P-AlGaN gate dielectric layer 2 (i.e. the exposed part of the barrier layer 13, which is not covered by the source electrode 3, the drain electrode 4 and the P-AlGaN gate dielectric layer 2); or, as shown in Figure 4 , the passivation layer 6 can also be provided to cover the source electrode 3, the gate electrode 5 and the drain electrode 4, i.e. the passivation layer 6 covers all the areas above the barrier layer 13, so as to isolate the barrier layer 13 from the direct contact with the gate electrode 5, reduce the gate-drain current and improve the breakdown voltage of the device.

[0073] The enhancement-mode field effect transistor device in the embodiment forms a PiN structure between the P-AlGaN gate dielectric layer 2 and the barrier layer 13 / channel layer 12 by forming the P-AlGaN gate dielectric layer 2 on the barrier layer 13, so that the device has the normally-off characteristic (is an enhancement-mode device); the P-AlGaN gate dielectric layer 2 is provided as the alternating layer of the Mg-doped AlGaN base layer and the non-Mg-doped AlGaN buried layer, so that the holes generated in the Mg-doped layer can diffuse into the adjacent non-Mg-doped layer, and the weakly ionized impurity scattering in the non-Mg-doped layer can significantly improve the hole mobility; and the GaN quantum dots are embedded in the Mg-doped layer, so that the local quantum structure embedded in the Mg-doped layer reduces the activation energy of the acceptor (Mg) and achieves a high hole concentration, and the enhancement-mode field effect transistor device has the performance of high breakdown voltage and low on-resistance.

[0074] Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments need not and can not be enumerated. The obvious changes or variations derived from the above description are still within the protection scope of the present application.

Claims

1. A method of fabricating an enhanced field effect transistor, characterized by, The method comprises the following steps: obtaining a preparation substrate; the preparation substrate comprises a substrate layer, a channel layer and a barrier layer grown on the substrate layer in sequence; growing an AlGaN base layer and GaN quantum dots on the preparation substrate under a magnesium source atmosphere, and after the growth of the GaN quantum dots is completed, turning off the gallium source while keeping the nitrogen source on for a preset time; turning off the magnesium source, and growing an AlGaN buried layer on the GaN quantum dots; growing the AlGaN base layer, the GaN quantum dots and the AlGaN buried layer for multiple cycles, and etching to form a P-AlGaN gate dielectric layer; growing a source electrode and a drain electrode on the barrier layer, and growing a gate electrode on the P-AlGaN gate dielectric layer.

2. The method of claim 1, wherein the method further comprises: The channel layer is a first AlGaN structure layer, the barrier layer is a second AlGaN structure layer, and the Al component in the second AlGaN structure layer is higher than that in the first AlGaN structure layer and the P-AlGaN gate dielectric layer.

3. The method for fabricating an enhancement-mode field-effect transistor according to claim 2, characterized in that, The Al component content in the first AlGaN structure layer is between 20% and 70%, the Al component content in the second AlGaN structure layer is between 30% and 80%, and the Al component content in the P-AlGaN gate dielectric layer is between 20% and 70%.

4. The method of claim 1-3, wherein, The method further comprises the following steps: growing a passivation layer on the barrier layer; the passivation layer covers the source electrode, the gate electrode and the drain electrode.

5. The method of claim 1-4, wherein the method further comprises: The preparation substrate further comprises a buffer layer grown between the substrate layer and the channel layer.

6. The method for fabricating an enhancement-mode field-effect transistor according to claim 5, characterized in that, The growth time of the AlGaN base layer is between 10 seconds and 50 seconds, the growth time of the GaN quantum dots is between 1 second and 20 seconds, and the preset time for keeping the nitrogen source on after turning off the gallium source is between 10 seconds and 50 seconds.

7. An enhanced field effect transistor device, characterized by The method comprises the following steps: a substrate and a channel layer and a barrier layer grown on the substrate in sequence; a P-AlGaN gate dielectric layer grown on a gate-under region of the barrier layer; the P-AlGaN gate dielectric layer comprises a plurality of AlGaN base layers, GaN quantum dots and AlGaN buried layers stacked in an alternating manner, and the AlGaN base layers and the GaN quantum dots are doped with Mg, and the AlGaN buried layers are unintentionally doped layers; a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are grown on the barrier layer, and the gate electrode is grown on the P-AlGaN gate dielectric layer.

8. The enhanced field effect transistor device of claim 7, wherein, The channel layer is a first AlGaN structure layer, the barrier layer is a second AlGaN structure layer, and the Al component in the second AlGaN structure layer is higher than that in the first AlGaN structure layer and the P-AlGaN gate dielectric layer.

9. The enhanced field effect transistor device according to claim 7 or 8, c h a r a c t e r i z e d b y The method further comprises the following steps: a passivation layer grown on the barrier layer and covering the source electrode, the gate electrode and the drain electrode.

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