Method for removing hard mask layer on pseudo gate polysilicon surface

Abstract

The present invention provides a method for removing a hard mask layer on the surface of a pseudo-gate polysilicon. The method comprises providing a substrate on which are formed first and second regions each including semiconductor structures of different densities, wherein the maximum height of the semiconductor structures is a first thickness; forming a photoresist layer covering the first and second regions on the substrate, wherein the thickness of the photoresist layer on the second region is less than that of the first region, and the height difference between the two regions is a second thickness; etching the photoresist layer so that the thickness difference between the photoresist layers on the first and second regions is a third thickness less than the first thickness; and continuing to spin-coat photoresist on the photoresist layer so that the thickness difference between the photoresist layers on the first and second regions is reduced to a fourth thickness less than the second thickness. The method reduces the height difference between various graphic structures through a half-etching technique of the photoresist and increases the thickness of the photoresist in the active area through a photoresist re-coating technique, thereby avoiding defects generated in subsequent process steps.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a method for removing a hard mask layer on the surface of a pseudo-gate polysilicon. Background Art

[0002] Before filling the metal gate, the dummy gate polysilicon on the high-K material needs to be removed. The first task is to remove the hard mask layer on the surface of the polysilicon. The removal process is as follows:

[0003] Step 1: Provide a substrate with a dummy gate structure, and then apply photoresist coating

[0004] In this step, due to the inherent characteristics of the photoresist coating process (the height h1 from the active area to the dummy gate polysilicon will block the flow of photoresist, and the higher the height and the higher the density, the slower the photoresist flows, resulting in thicker thickness), the thickness of the photoresist on the dummy gate polysilicon will increase with the increase of the dummy gate density, forming a photoresist height difference h2.

[0005] Step 2: Photoresist etch back (remove the photoresist on the pseudo gate polysilicon surface)

[0006] In this step, due to the uneven height h2 caused by the photoresist coating, the dry etching step cannot take care of the high-density and low-density areas at the same time. Excessive dry etching causes the photoresist thickness in the active area of ​​the low-density area to be insufficient, resulting in photoresist residue on the pseudo-gate polysilicon in the high-density area.

[0007] Step 3: Etch back the oxide on the pseudo gate polysilicon (remove the oxide on the surface of the pseudo gate polysilicon)

[0008] In this step, due to the problem caused by step 2, oxide residues will be left in the high-density area during oxide etching, and nickel metal compounds will be damaged in the low-density area.

[0009] In order to solve the above problems, a new method for removing the hard mask layer on the surface of dummy gate polysilicon is needed. Summary of the Invention

[0010] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for removing the hard mask layer on the surface of the pseudo-gate polysilicon, which is used to solve the problem in the prior art that when etching the pseudo-gate structure, due to the difference in the thickness of the photoresist, there will be oxide residues in the high-density areas during oxide etching, and the nickel metal compounds will be damaged in the low-density areas.

[0011] To achieve the above-mentioned and other related objectives, the present invention provides a method for removing a hard mask layer on a dummy gate polysilicon surface, comprising:

[0012] Step 1: providing a substrate, on which are formed first and second regions each including a semiconductor structure of different densities, wherein the maximum height of the semiconductor structure is a first thickness;

[0013] Step 2: forming a photoresist layer covering the first and second regions on the substrate, wherein the thickness of the photoresist layer on the second region is smaller than that on the first region, and the height difference between the two regions is a second thickness;

[0014] Step 3: etching the photoresist layer so that the difference in thickness between the photoresist layer in the first and second regions is a third thickness that is smaller than the first thickness;

[0015] Step 4: Continue to spin-coat the photoresist on the photoresist layer, so that the thickness difference between the photoresist layers on the first and second regions is reduced to a fourth thickness that is smaller than the second thickness;

[0016] Step 5: Etching back the photoresist layer and the semiconductor structures on the first and second regions thereunder, so that the semiconductor structures on the first and second regions are etched to a desired height.

[0017] Preferably, the substrate in step 1 is a silicon substrate.

[0018] Preferably, in step 1, the density of the semiconductor structure in the first region is greater than that in the second region.

[0019] Preferably, the semiconductor structure in step 1 is a dummy gate.

[0020] Preferably, the dummy gate in step 1 includes a dummy gate polysilicon layer, a nitride layer and an oxide layer from bottom to top, a sidewall spacer formed on the sidewall of the dummy gate, and an etch stop layer covering the surface of the dummy gate.

[0021] Preferably, before forming the photoresist layer in step 2, the step further includes forming an anti-reflective coating covering the first and second regions on the substrate.

[0022] Preferably, the etching method in step three is dry etching.

[0023] Preferably, the back etching method in step five is dry etching.

[0024] Preferably, in step five, the oxide layer is removed by etching back.

[0025] Preferably, the method is used in a process of 22 or 28 nanometer technology node.

[0026] As described above, the method of removing the hard mask layer on the surface of the dummy gate polysilicon of the present invention has the following beneficial effects:

[0027] The present invention reduces the height difference between various graphic structures by using the half-etching technology of the photoresist and increases the thickness of the photoresist in the active area by using the photoresist re-coating technology without changing the density of the pseudo-gate structure, thereby avoiding defects caused in subsequent process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0029] Figure 2 Shown is a schematic diagram of a substrate of the present invention;

[0030] Figure 3 Shown is a schematic diagram of the first spin coating of photoresist according to the present invention;

[0031] Figure 4 Shown is a schematic diagram of the etched portion of the photoresist of the present invention;

[0032] Figure 5 Shown is a schematic diagram of the second spin coating of photoresist according to the present invention;

[0033] Figure 6 It shows a schematic diagram of etching the hard mask layer on the surface of dummy gate polysilicon according to the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figure 1 The present invention provides a method for removing a hard mask layer on a surface of a pseudo-gate polysilicon, comprising:

[0036] Step 1, see Figure 2 , providing a substrate 01, on which are formed first and second regions each including a semiconductor structure 02 of different densities, wherein the maximum height of the semiconductor structure 02 is a first thickness;

[0037] In an embodiment of the present invention, the substrate 01 in step 1 is a silicon substrate 01 .

[0038] In the embodiment of the present invention, in step 1, the density of the semiconductor structure 02 in the first area A1 is greater than that in the second area A2. Due to the density difference, subsequent spin coating of the photoresist may cause height differences between areas with different densities.

[0039] In an embodiment of the present invention, the semiconductor structure 02 in step 1 is a dummy gate.

[0040] In an embodiment of the present invention, in step one, the dummy gate includes a dummy gate polysilicon layer, a nitride layer and an oxide layer from bottom to top, a side wall formed on the side wall of the dummy gate, and an etch stop layer covering the surface of the dummy gate. When removing the hard mask layer, i.e., the oxide layer, on the dummy gate polysilicon layer, the dry etching is too excessive and the photoresist thickness in the active area with low density is not enough, resulting in photoresist residue on the dummy gate polysilicon in the high density area.

[0041] Step 2, please refer to Figure 3 , forming a photoresist layer 03 covering the first and second regions on the substrate 01, wherein the thickness of the photoresist layer 03 on the second region is smaller than that of the first region A1, and the height difference between the two is a second thickness;

[0042] In an embodiment of the present invention, before forming the photoresist layer 03 in step 2, an anti-reflective coating covering the first and second regions is formed on the substrate 01 .

[0043] Step 3, please refer to Figure 4 , etching the photoresist layer 03, that is, first thinning the photoresist layer 03 by a half-etching technique, so that the thickness difference between the photoresist layer 03 on the first and second regions is a third thickness that is smaller than the first thickness;

[0044] In an embodiment of the present invention, the etching method in step three is dry etching.

[0045] Step 4, please refer to Figure 5 , continue to spin-coat photoresist on the photoresist layer 03. Because the third thickness is less than the first thickness and the fluidity of the photoresist is greater than the fluidity of the photoresist cross in step 2, the thickness difference between the photoresist layer 03 on the first and second regions is reduced to a fourth thickness that is less than the second thickness;

[0046] Step 5, please refer to Figure 6 , the photoresist layer 03 and the semiconductor structure 02 on the first and second regions thereunder are etched back, so that the semiconductor structure 02 on the first and second regions is etched to the required height. The remaining thickness R2 of the photoresist layer 03 after oxide etching is much larger than the thickness of the existing process. While ensuring that the hard mask layer on the surface of the pseudo-gate polysilicon layer is completely removed, the nickel metal compound in the active area can be effectively prevented from being damaged.

[0047] In an embodiment of the present invention, the etching back method in step five is dry etching.

[0048] In an embodiment of the present invention, in step five, the oxide layer is removed by etching back.

[0049] In an embodiment of the present invention, the above method is used in a process of 22 or 28 nanometer technology nodes.

[0050] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0051] In summary, the present invention reduces the height differences between various pattern structures through photoresist half-etching and increases the thickness of the active area photoresist through photoresist re-coating, without changing the density of the dummy gate structure. This avoids defects that may arise during subsequent processing. Therefore, the present invention effectively overcomes the shortcomings of the prior art and has high industrial application value.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for removing a hard mask layer on a dummy gate polysilicon surface, characterized in that: At least: Step 1: providing a substrate, on which a first region and a second region are formed, each including a semiconductor structure of different densities, wherein the semiconductor structure is a dummy gate, and the density in the first region is greater than the density in the second region, and the maximum height of the semiconductor structure is a first thickness; Step 2: forming a photoresist layer covering the first and second regions on the substrate, wherein the thickness of the photoresist layer on the second region is smaller than that on the first region, and the height difference between the two regions is a second thickness; Step 3: etching the photoresist layer so that the difference in thickness between the photoresist layer in the first and second regions is a third thickness that is smaller than the first thickness; Step 4: Continue to spin-coat the photoresist on the photoresist layer, so that the thickness difference between the photoresist layers on the first and second regions is reduced to a fourth thickness that is smaller than the second thickness; Step 5: etching back the photoresist layer and the semiconductor structures on the first and second regions thereunder, so that the semiconductor structures on the first and second regions are etched to a desired height, and removing the oxide layer on the dummy gate by etching back.

2. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 1, wherein: The substrate in step 1 is a silicon substrate.

3. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 1, wherein: The dummy gate in step 1 includes a dummy gate polysilicon layer, a nitride layer and an oxide layer from bottom to top, a sidewall formed on the sidewall of the dummy gate, and an etch stop layer covering the surface of the dummy gate.

4. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 1, wherein: Before forming the photoresist layer in step 2, the method further includes forming an anti-reflective coating covering the first and second regions on the substrate.

5. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 3, wherein: The etching method in step three is dry etching.

6. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 1, wherein: The etching back method in step five is dry etching.

7. The method for removing the hard mask layer on the surface of dummy gate polysilicon according to claim 1, wherein: The method is used for a process at a 22- or 28-nanometer technology node.

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