CIS device shallow trench isolation structure defect detection structure and method

Abstract

The application provides a shallow trench isolation structure defect detection structure and method of a CIS device, and the structure comprises: an N-type well region in a cutting channel; a shallow trench isolation structure and an N-type drain region in the N-type well region, the N-type drain region being a certain distance from the shallow trench isolation structure, and the width of the shallow trench isolation structure meeting the minimum size of design; a gate oxide layer on the surface of the shallow trench isolation structure; and a gate electrode on the surface of the gate oxide layer. The method comprises: applying a first voltage to the floating gate, the value of the first voltage changing from low to high; applying a second voltage to the N-type drain region, the value of the first voltage being greater than or equal to the value of the second voltage; testing the capacitance value of the shallow trench isolation structure, and if the value changes abruptly, then the shallow trench isolation structure is considered to have a defect. Through this method, whether the shallow trench isolation structure has a defect can be detected without being affected by the detection method, the detection machine and the range, and the detection cost is low, the time consumption is short, and the sensitivity is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a shallow trench isolation structure defect detection structure and method of CIS device. BACKGROUND

[0002] A chip goes through many process steps from the production line to the shipment, and each step has the possibility of producing defects.

[0003] CIS products use high-density plasma chemical vapor deposition (HDP) for the shallow trench isolation structure. The plasma provides the activation energy required for the reaction, which can be performed at a lower temperature, reducing the thermal load. However, the disadvantage of this CIS formation method is that the shallow trench isolation structure is prone to particles, and the filling capacity is relatively low compared to HARP, which can cause the shallow trench isolation structure to have voids. In addition, the etching of the shallow trench isolation structure and the expansion of the active area shallow trench can also affect the HDP filling of the shallow trench isolation structure, causing the shallow trench isolation structure to form voids inside or on the surface. The voids of the shallow trench isolation structure are an important source of yield loss in the front-end of CIS products. The voids found in the current CIS product SIN RM are generally located in the shallow trench isolation structure between two shorter active areas. This defect can cause SRAM failure, with a failure rate close to 100%. Failure analysis results show that the CVD closes too early when filling the shallow trench isolation structure oxide, which is related to the aspect ratio of the shallow trench isolation structure trench and the filling capacity of the CVD.

[0004] The existing shallow trench isolation structure failure analysis adopts a scanning method, which is limited by the detection method, detection machine, and limited wafer scanning, has high detection cost, long time consumption, and low sensitivity. There is a monitoring blind area in the non-specified area. SUMMARY

[0005] The purpose of the present application is to provide a shallow trench isolation structure defect detection method for CIS devices, which can not be affected by the limitations of the detection method, detection machine, and range, has low detection cost, short time consumption, and high sensitivity.

[0006] In order to achieve the above purpose, the present application provides a shallow trench isolation structure defect detection structure for CIS devices, comprising:

[0007] An N-type well region located in a scribe lane;

[0008] A shallow trench isolation structure and an N-type drain region located in the N-type well region, the N-type drain region has a certain distance from the shallow trench isolation structure, and the width of the shallow trench isolation structure meets the minimum size of the design;

[0009] a gate oxide layer on a surface of the shallow trench isolation structure; and

[0010] a gate on a surface of the gate oxide layer.

[0011] Optionally, in the shallow trench isolation structure defect detection structure, the cut-off groove is located around the CIS device.

[0012] Optionally, in the shallow trench isolation structure defect detection structure, the surface of the N-type drain region further has a silicide.

[0013] Optionally, in the shallow trench isolation structure defect detection structure, the shallow trench isolation structure defect detection structure is formed together with the CIS device.

[0014] The present application provides a shallow trench isolation structure defect detection method of a CIS device, comprising:

[0015] applying a first voltage to the floating gate, the value of the first voltage changing from low to high;

[0016] applying a second voltage to the N-type drain region, the value of the first voltage being greater than or equal to the value of the second voltage; and

[0017] testing the capacitance value of the shallow trench isolation structure, and if the capacitance value changes abruptly, considering that the shallow trench isolation structure has a defect.

[0018] Optionally, in the shallow trench isolation structure defect detection method, the value of the first voltage ranges from 0V to 6V.

[0019] Optionally, in the shallow trench isolation structure defect detection method, the initial value of the first voltage is 0V, and the value of the first voltage gradually increases from 0.

[0020] Optionally, in the shallow trench isolation structure defect detection method, the value of the second voltage is 0.

[0021] Optionally, in the shallow trench isolation structure defect detection method, the method of judging that the capacitance value changes abruptly comprises:

[0022] obtaining the capacitance value under different voltages to form a curve of the capacitance value and voltage;

[0023] if the slope of the curve changes abruptly, considering that the capacitance value changes abruptly.

[0024] Optionally, in the shallow trench isolation structure defect detection method, the defect includes a cavity and a particle.

[0025] The present invention provides a defect detection structure and method for shallow trench isolation structures in CIS devices. The structure includes: an N-type well region located within a diced channel; a shallow trench isolation structure and an N-type drain region located within the N-type well region, wherein the N-type drain region and the shallow trench isolation structure are at a certain distance, and the width of the shallow trench isolation structure meets the minimum design dimensions; a gate oxide layer located on the surface of the shallow trench isolation structure; and a gate electrode located on the surface of the gate oxide layer. The method includes: applying a first voltage to the floating gate, the value of which varies from low to high; applying a second voltage to the N-type drain region, the value of which is greater than or equal to the value of the second voltage; and testing the capacitance value of the shallow trench isolation structure. If the capacitance value changes abruptly, the shallow trench isolation structure is considered defective. This method for detecting defects in shallow trench isolation structures is not limited by detection techniques, equipment, or range, resulting in low detection cost, short processing time, and high sensitivity. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the shallow trench isolation structure defect detection structure of the CIS device according to an embodiment of the present invention;

[0027] Figure 2 This is a flowchart of a method for detecting defects in the shallow trench isolation structure of a CIS device according to an embodiment of the present invention;

[0028] In the diagram: 110 - N-type well region, 120 - shallow trench isolation structure, 130 - N-type drain region, 140 - gate oxide, 150 - gate. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0030] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0031] CMOS Image Sensor (CIS) devices are widely used, and defects can affect their performance. For example, shallow trench isolation structures may develop voids internally and on the surface, as well as particles on the surface. Both voids and particles are defects that affect the isolation performance of the shallow trench isolation structure, thus impacting the overall yield of the CIS. Existing shallow trench isolation structure failure analysis uses scanning methods, which are limited by inspection techniques, equipment, and the number of wafers that can be scanned. This results in high inspection costs, long processing times, and low sensitivity. Furthermore, blind spots exist in non-designated areas. Therefore, this invention forms a shallow trench isolation structure defect detection structure for CIS devices within the dicing channel, creating the detection structure simultaneously with the CIS chip formation. Each CIS device is surrounded by a dicing channel, thus each CIS device has a dedicated shallow trench isolation structure defect detection structure. This eliminates the need for additional scanning equipment, making detection convenient and eliminating blind spots.

[0032] For details, please refer to Figure 1 This invention provides a shallow trench isolation structure defect detection structure for CIS devices, comprising:

[0033] N-type trap zone 110 located within the cutting channel;

[0034] The shallow trench isolation structure 120 and the N-type drain region 130 are located within the N-type well region 110. The N-type drain region 130 and the shallow trench isolation structure 120 are at a certain distance. The width of the shallow trench isolation structure 120 meets the minimum design dimensions.

[0035] The gate oxide layer 130 located on the surface of the shallow trench isolation structure 120; and

[0036] Gate 140 located on the surface of gate oxide layer 130.

[0037] Preferably, the dicing channel is located around the CIS device. The shallow trench isolation structure defect detection structure is formed together with the CIS device. The shallow trench isolation structure defect detection structure of the CIS device provided by the present invention is located within the dicing channel, specifically including an N-type well region 110, a shallow trench isolation structure 120 located within the N-type well region 110, an N-type drain region 130 located within the N-type well region 110, and silicide on the surface of the N-type drain region 130. The N-type drain region 130 is at a certain distance from the shallow trench isolation structure 120. It also includes a gate oxide 140 located on the surface of the N-type well region 110 and the shallow trench isolation structure 120, and a gate 150 located on the gate oxide 140. The surface of the shallow trench isolation structure 120 is flush with the surface of the remaining N-type well region 110. The gate oxide 140 can be silicon dioxide, and the gate 150 can be polysilicon. The width of the contact between the shallow trench isolation structure 120 and the gate oxide 140 meets the minimum design dimension. Here, width refers to the width of the surface of the shallow trench isolation structure (the contact between the shallow trench isolation structure 120 and the gate oxide 140) when the test structure is sliced ​​radially perpendicular to the scribe line. Because the width of the shallow trench isolation structure in the CIS device is greater than or equal to the minimum design dimension, if the shallow trench isolation structure of this test structure is defect-free, then the shallow trench isolation structure within the CIS device is also defect-free.

[0038] A detection method is needed for the shallow trench isolation structure defect detection of CIS devices. Therefore, please refer to... Figure 2 This invention provides a method for detecting defects in the shallow trench isolation structure of a CIS device, comprising:

[0039] S11: Apply a first voltage to the floating gate, the value of which changes from low to high;

[0040] S12: Apply a second voltage to the N-type drain region, wherein the value of the first voltage is greater than or equal to the value of the second voltage; and

[0041] S13: Test the capacitance value of the shallow trench isolation structure. If the capacitance value changes abruptly, the shallow trench isolation structure is considered to be defective.

[0042] Preferably, the first voltage ranges from 0V to 6V, with an initial value of 0V. The first voltage gradually increases from 0V and can be applied to the gate via probe contact. The second voltage is 0V and remains constant. This second voltage can be applied to the surface of the N-type drain region, i.e., the silicide, via probe contact. Simultaneously, the capacitance between the gate and the N-type drain region is measured using two probes. The capacitance between the gate and the N-type drain region primarily includes the capacitance of the shallow trench isolation structure, and the change in capacitance between them is mainly due to the change caused by the shallow trench isolation structure. Therefore, the capacitance between the gate and the N-type drain region can be used to measure the capacitance of the shallow trench isolation structure. Since the first voltage gradually increases, a capacitance value can be obtained at regular intervals. Thus, as the first voltage increases, a capacitance-voltage curve, i.e., a CV curve, can be obtained, and the slope of this curve can be determined. For example, a capacitance value is taken at 0.5V, and the slope between 0V and 0.5V is obtained. Then, the slope between 0.5V and 1V is obtained. If the slope between 0.5V and 1V suddenly increases or decreases significantly compared to the slope between 0V and 0.5V, it indicates a sudden change in the capacitance value of the shallow trench isolation structure. If the shallow trench isolation structure has voids or particles, it proves that the shallow trench isolation structure of the corresponding CIS has voids or particles. This method can be used to pre-test the CV curve of a good shallow trench isolation structure to verify whether there are problems with the detection structures of other identical chips on the wafer. It can also be used to determine whether a batch of chips is defective. Therefore, the entire method is not limited by the detection method, detection equipment, or range, and has low detection cost, short processing time, and high sensitivity.

[0043] In this embodiment of the invention, the method for determining a sudden change in capacitance value includes: obtaining capacitance values ​​under different voltages to form a curve of capacitance value versus voltage; if the slope of the curve changes abruptly, then the capacitance value is considered to have changed abruptly.

[0044] In this embodiment of the invention, defects include voids and particles. As the amount of stored electrons increases, the curve appears with a certain slope. Voids may exist inside and on the surface of the shallow trench isolation structure. Particles are generally present on the surface of the shallow trench isolation structure. The slope of the CV curve when voids are present is different from the slope when particles are present, but any sudden change in capacitance value can be considered as caused by a defect in the shallow trench isolation structure.

[0045] In summary, the shallow trench isolation structure defect detection structure and method for CIS devices provided in this invention includes: an N-type well region located within a diced channel; a shallow trench isolation structure and an N-type drain region located within the N-type well region, wherein the N-type drain region and the shallow trench isolation structure are at a certain distance, and the width of the shallow trench isolation structure meets the minimum design dimensions; a gate oxide layer located on the surface of the shallow trench isolation structure; and a gate electrode located on the surface of the gate oxide layer. The method includes: applying a first voltage to the floating gate; applying the first voltage to the floating gate, wherein the value of the first voltage varies from low to high; applying a second voltage to the N-type drain region, wherein the value of the first voltage is greater than or equal to the value of the second voltage; and testing the capacitance value of the shallow trench isolation structure. If the capacitance value changes abruptly, the shallow trench isolation structure is considered to have a defect. This method for detecting defects in shallow trench isolation structures is not limited by detection techniques, equipment, or range, and has low detection cost, short processing time, and high sensitivity.

[0046] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A shallow trench isolation structure defect detection structure for CIS devices, characterized in that, include: The N-type well region is located within the cutting channel; The shallow trench isolation structure and the N-type drain region are located within the N-type well region. The N-type drain region and the shallow trench isolation structure are at a certain distance in the horizontal direction. The width of the shallow trench isolation structure meets the minimum design dimensions. The gate oxide layer located on the surface of the shallow trench isolation structure; as well as The gate located on the surface of the gate oxide layer.

2. The shallow trench isolation structure defect detection structure as described in claim 1, characterized in that, The cut channel is located around the CIS device.

3. The shallow trench isolation structure defect detection structure as described in claim 1, characterized in that, The surface of the N-type drain region also has silicide.

4. The shallow trench isolation structure defect detection structure as described in claim 1, characterized in that, The shallow trench isolation structure defect detection structure is formed together with the CIS device.

5. A method for detecting defects in the shallow trench isolation structure of a CIS device formed using the shallow trench isolation structure defect detection structure of the CIS device according to any one of claims 1 to 4, characterized in that, include: A first voltage is applied to the floating gate, the value of which changes from low to high; A second voltage is applied to the N-type drain region, wherein the value of the first voltage is greater than or equal to the value of the second voltage; as well as The capacitance value of the shallow trench isolation structure is tested. If the capacitance value changes abruptly, the shallow trench isolation structure is considered to have an internal defect.

6. The method for detecting defects in shallow trench isolation structures as described in claim 5, characterized in that, The first voltage ranges from 0 V to 6 V.

7. The method for detecting defects in shallow trench isolation structures as described in claim 6, characterized in that, The initial value of the first voltage is 0V, and the value of the first voltage gradually increases from 0.

8. The method for detecting defects in shallow trench isolation structures as described in claim 5, characterized in that, The value of the second voltage is 0.

9. The method for detecting defects in shallow trench isolation structures as described in claim 5, characterized in that, The methods for determining if the capacitance value has changed abruptly include: Obtain the capacitance values ​​at different voltages to form a curve of the capacitance value versus voltage; If the slope of the curve changes abruptly, the capacitance value is considered to have changed abruptly.

10. The method for detecting defects in shallow trench isolation structures as described in claim 5, characterized in that, The defects include voids and particles.

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