A method for manufacturing a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure, comprising the following steps: providing a substrate with a storage area and a non-storage area; forming a tunneling oxide layer, a nitride layer and a sacrificial oxide layer on the substrate in sequence; and forming a photoresist layer on the sacrificial oxide layer of the storage area; etching and removing the sacrificial oxide layer and the nitride layer on the non-storage area by taking the photoresist layer as a mask; removing the photoresist layer; and removing at least part of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area. The photoresist layer is formed on the sacrificial oxide layer, which avoids the damage to the nitride layer in the coating and removing process of the photoresist layer, and further avoids the influence on the storage capacity of the nitride layer to the electric charge.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory is a charge-trap type memory that utilizes a nitride layer to store charge. It offers advantages such as small cell size, low operating voltage, and compatibility with CMOS processes. Since its advent, SONOS memory has continuously driven the development of memory towards miniaturization, high capacity, and low cost. However, the current fabrication process of SONOS memory can damage the nitride layer, affecting its ability to store charge and consequently impacting the reliability of the SONOS memory. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure to solve the problem of nitride layer damage during the fabrication of existing SONOS memory.

[0004] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] A substrate is provided, the substrate having a storage region and a non-storage region, a tunnel oxide layer, a nitride layer and a sacrificial oxide layer are sequentially formed on the substrate, and a photoresist layer is formed on the sacrificial oxide layer in the storage region;

[0006] The sacrificial oxide layer and the nitride layer on the non-storage area are removed by etching using the photoresist layer as a mask;

[0007] Remove the photoresist layer;

[0008] Remove at least a portion of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area.

[0009] Optionally, when etching away the sacrificial oxide layer and the nitride layer on the non-memory region using the photoresist layer as a mask, at least a portion of the thickness of the tunnel oxide layer in the non-memory region is also removed simultaneously.

[0010] Optionally, after simultaneously removing at least a portion of the thickness of the tunneling oxide layer in the non-storage area, the remaining thickness of the tunneling oxide layer in the non-storage area is less than the thickness of the sacrificial oxide layer.

[0011] Optionally, after removing a portion of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area, the remaining sacrificial oxide layer in the storage area constitutes a first dielectric layer.

[0012] Optionally, after forming the first dielectric layer, the method further includes:

[0013] A second dielectric layer is formed on the substrate, the second dielectric layer covering the first dielectric layer and the substrate of the non-memory region, the first dielectric layer and the second dielectric layer constituting a gate dielectric layer.

[0014] Optionally, after removing the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area, the method further includes:

[0015] A gate dielectric layer is formed on the substrate, the gate dielectric layer covering the nitride layer and the substrate of the non-memory region.

[0016] Optionally, the thickness of the gate dielectric layer is

[0017] Optionally, a wet etching process can be used to remove at least a portion of the thickness of the sacrificial oxide layer on the storage region and the tunneling oxide layer on the non-storage region.

[0018] Optionally, the wet etching process uses a mixed solution of hydrofluoric acid, ammonium fluoride, and phosphoric acid as the etching agent.

[0019] Optionally, a dry etching process can be used to remove the sacrificial oxide layer and the nitride layer in the non-storage area.

[0020] Optionally, when forming the sacrificial oxide layer, the thickness of the sacrificial oxide layer is less than the thickness of the tunneling oxide layer.

[0021] Optionally, a nitrogen oxide layer may be formed between the nitrided layer and the sacrificial oxide layer.

[0022] This invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a storage region and a non-storage region; sequentially forming a tunneling oxide layer, a nitride layer, and a sacrificial oxide layer on the substrate; forming a photoresist layer on the sacrificial oxide layer in the storage region; etching away the sacrificial oxide layer and the nitride layer in the non-storage region using the photoresist layer as a mask; removing the photoresist layer; and removing at least a portion of the thickness of the sacrificial oxide layer in the storage region and the tunneling oxide layer in the non-storage region. Forming the photoresist layer on the sacrificial oxide layer avoids damage to the nitride layer during the photoresist coating and stripping process, thus preventing any impact on the charge storage capacity of the nitride layer.

[0023] Furthermore, the semiconductor structure fabrication process employs only a single wet etching process, generating less waste liquid, saving costs while reducing pollution. Attached Figure Description

[0024] Figures 1-2 This is a schematic diagram of the structure corresponding to the steps in a method for fabricating a SONOS memory.

[0025] Figure 3 A flowchart of a method for preparing a semiconductor structure provided in Embodiment 1 of the present invention;

[0026] Figures 4-8 A schematic diagram of some steps in the method for preparing a semiconductor structure provided in Embodiment 1 of the present invention;

[0027] Figures 9-10 This is a schematic diagram of some steps in the method for preparing the semiconductor structure provided in Embodiment 2 of the present invention.

[0028] The attached figures are labeled as follows:

[0029] A - a-Storage area; b - Non-Storage area; B - Selection area; C - Peripheral logical area;

[0030] 20, 100 - Substrate; 21, 101 - Shallow trench isolation structure; 22, 102 - Tunnel oxide layer; 23, 103 - Nitride layer; 24, 104 - Sacrificial oxide layer; 25, 105 - Photoresist layer; 106 - Gate dielectric layer; 107 - First dielectric layer; 108 - Second dielectric layer. Detailed Implementation

[0031] Figures 1-2 This is a schematic diagram of the structure corresponding to the steps in a method for fabricating a SONOS memory, as shown below. Figure 1 and Figure 2 As shown, the SONOS memory has a storage area a and a non-storage area b. During the fabrication of the SONOS memory, a tunnel oxide layer 22, a nitride layer 23, and a sacrificial oxide layer 24 are typically stacked sequentially on the substrate 20. To improve fabrication efficiency, the tunnel oxide layer 22, the nitride layer 23, and the sacrificial oxide layer 24 are usually formed in a single process on the same equipment. However, due to limitations in the equipment's process, the sacrificial oxide layer 24 is relatively thin and has poor density, making it difficult to meet the requirements of the SONOS memory. Therefore, it is necessary to remove the sacrificial oxide layer 24 before forming subsequent film layers. In existing processes, the sacrificial oxide layer 24 is typically removed using a wet etching process. However, the etchant used in the wet etching process can damage the nitride layer 23.

[0032] Continue reading Figure 2After removing the sacrificial oxide layer 24, a photoresist layer 25 is formed on the nitride layer 23. Using the photoresist layer 25 as a mask, the nitride layer 23 and the tunnel oxide layer 22 on the non-memory region b are removed. Finally, the photoresist layer 25 is removed. Specifically, a dry ashing process is used to remove the photoresist layer 25, followed by further cleaning of the substrate 20 with a chemical solution such as sulfuric acid to remove residual photoresist layer 25 and polymers generated during the dry ashing process from the surface of the nitride layer 23. Removing the photoresist layer 25 further damages the nitride layer 23, degrading its film quality and affecting its ability to store charge, thus impacting the reliability of the SONOS memory.

[0033] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0034] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.

[0035] Example 1

[0036] Figure 3 A flowchart of the semiconductor structure fabrication method provided in this embodiment is shown below. Figure 3 As shown, the method for fabricating the semiconductor structure includes:

[0037] Step S1: Provide a substrate having a storage region and a non-storage region, and sequentially form a tunnel oxide layer, a nitride layer and a sacrificial oxide layer on the substrate, and form a photoresist layer on the sacrificial oxide layer in the storage region;

[0038] Step S2: Using the photoresist layer as a mask, etch away the sacrificial oxide layer and the nitride layer on the non-storage area;

[0039] Step S3: Remove the photoresist layer;

[0040] Step S4: Remove at least a portion of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area.

[0041] Figures 4-8 This is a schematic diagram of the corresponding steps in the semiconductor structure fabrication method provided in this embodiment. Next, we will combine... Figures 4 to 8 The method for preparing the semiconductor structure is described in detail.

[0042] like Figure 4 As shown, a substrate 100 is provided, which has a storage region A and a non-storage region. The non-storage region includes a selection region B and a peripheral logic region C. A shallow trench isolation structure 101 is provided in the substrate 100 between the storage region A and the peripheral logic region C. Stacked tunnel oxide layer 102, nitride layer 103, and sacrificial oxide layer 104 are sequentially formed on the substrate 100. The tunnel oxide layer 102 covers the substrate 100, the nitride layer 103 covers the tunnel oxide layer 102, and the sacrificial oxide layer 104 covers the nitride layer 103. The tunnel oxide layer 102, the nitride layer 103, and the sacrificial oxide layer 104 are generated in one step in the same machine, thereby improving the fabrication efficiency.

[0043] The thickness of the sacrificial oxide layer 104 is less than the thickness of the tunnel oxide layer 102; the height of the upper surface of the substrate 100 in the storage region A is lower than the height of the upper surface of the substrate 100 in the non-storage region, so as to reduce the height difference between the nitride layer 103 in the storage region A and the substrate 100 in the non-storage region.

[0044] like Figures 5-6 As shown, a photoresist layer 105 is formed on the sacrificial oxide layer 104, and the photoresist layer 105 is patterned. The patterned photoresist layer 105 covers the sacrificial oxide layer 104 of the storage region A. Then, using the photoresist layer 105 as a mask, a dry etching process is used to remove the sacrificial oxide layer 104 and the nitride layer 103 on the non-storage region. Since the dry etching process is anisotropic, it can avoid lateral erosion of the nitride layer 103 on the storage region A.

[0045] In this embodiment, the photoresist layer 105 also covers part of the shallow trench isolation structure 101, further preventing the nitride layer 103 on the storage area A from being affected during the dry etching process.

[0046] like Figures 6-7As shown, the photoresist layer 105 is removed. Specifically, the photoresist layer 105 is first subjected to a dry ashing process, and then the substrate 100 is further cleaned to remove residual photoresist layer 105 and polymer generated during the dry ashing process. Since the sacrificial oxide layer 104 is located below the photoresist layer 105, the removal of the photoresist layer 105 will not damage the nitride layer 103, thus better protecting the nitride layer 103.

[0047] Furthermore, the tunneling oxide layer 102 on the non-storage area and the sacrificial oxide layer 104 on the storage area A are removed simultaneously. Since the dry etching process also affects a portion of the tunneling oxide layer 102 on the non-storage area, resulting in uneven thickness of the tunneling oxide layer 102, continuing to etch the tunneling oxide layer 102 at this point could damage the substrate 100. Therefore, in this embodiment, a wet etching process is used to etch the tunneling oxide layer 102. The wet etching process uses a mixed solution of hydrofluoric acid, ammonium fluoride, and phosphoric acid as the etchant. The etchant has good selectivity for the tunnel oxide layer 102 (and the sacrificial oxide layer 104), the nitride layer 103 (and the substrate 100), and silicon nitride. It can remove the sacrificial oxide layer 104 on the storage area A and the tunnel oxide layer 102 on the non-storage area while preventing damage to the nitride layer 103 and the substrate 100.

[0048] In order to completely remove the tunnel oxide layer 102 on the non-storage area, the etching time of the wet etching process needs to be set according to the etching time of the tunnel oxide layer 102. Since the thickness of the sacrificial oxide layer 104 before etching is less than the thickness of the tunnel oxide layer 102, when the sacrificial oxide layer 104 is completely removed, the tunnel oxide layer 102 in the non-storage area is not completely removed, and the etchant will continue to etch the film layer below the sacrificial oxide layer 104.

[0049] It should be noted that in this embodiment, the tunneling oxide layer 102, the nitride layer 103, and the sacrificial oxide layer 104 are formed in the same machine using the same process. Due to process limitations, the sacrificial oxide layer 104 is not directly generated after the formation of the nitride layer 103. Instead, a nitride oxide layer is first formed on the nitride layer 103, and then the sacrificial oxide layer 104 is formed on the nitride oxide layer. Therefore, the etchant does not directly contact the nitride layer 103, but first etches the nitride oxide layer. Since the etchant has a slow etching rate on the nitride oxide layer, the nitride oxide layer can effectively prevent the nitride layer 103 from being damaged, ensuring the film properties of the nitride layer 103, and thus ensuring the reliability of the SONOS memory.

[0050] In addition, using a one-step wet etching process to remove both the tunnel oxide layer 102 and the sacrificial oxide layer 104 can effectively reduce waste liquid discharge, saving costs while reducing pollution.

[0051] like Figure 8 As shown, a gate dielectric layer 106 is formed on the substrate 100, the gate dielectric layer 106 covering the nitride layer 103 and the substrate 100, and the thickness of the gate dielectric layer 106 is [missing information]. The gate dielectric layer 106, the nitride layer 103, and the tunnel oxide layer 102 on the storage region A constitute an ONO layer.

[0052] Example 2

[0053] Figures 9-10 This is a schematic diagram of some steps in the semiconductor structure fabrication method described in this embodiment, as shown below. Figure 9 As shown, the difference between this embodiment and Embodiment 1 is that, while etching away the sacrificial oxide layer 104 and the nitride layer 103 on the non-memory region using the photoresist layer 105 as a mask, the tunneling oxide layer 102 is further etched to simultaneously remove at least a portion of the thickness of the tunneling oxide layer 102 on the non-memory region. In this embodiment, the thickness of the tunneling oxide layer 102 on the non-memory region after etching is less than the thickness of the sacrificial oxide layer 104 on the memory region A.

[0054] See Figures 9-10The photoresist layer 105 is removed, and then the sacrificial oxide layer 104 on the storage region A and the tunneling oxide layer 102 on the non-storage region are simultaneously etched. Since the thickness of the tunneling oxide layer 102 on the non-storage region is less than the thickness of the sacrificial oxide layer 104 on the storage region A, when the tunneling oxide layer 102 is completely removed, the sacrificial oxide layer 104 is not completely removed. The remaining sacrificial oxide layer 104 on the storage region A constitutes the first dielectric layer 107. The sacrificial oxide layer 104 can effectively protect the nitride layer 103 from damage during the etching process. Further, a second dielectric layer 108 is formed on the substrate 100, covering the substrate 100 and the first dielectric layer 107. The second dielectric layer 108 and the first dielectric layer 107 constitute the gate dielectric layer 106.

[0055] In other alternative embodiments, the tunneling oxide layer 102 can be removed while removing the sacrificial oxide layer 104 and the nitride layer 103 on the non-storage area, and then at least a portion of the thickness of the sacrificial oxide layer 104 can be removed by an etching process.

[0056] In summary, the present invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate 100 having a storage region A and a non-storage region; sequentially forming a tunneling oxide layer 102, a nitride layer 103, and a sacrificial oxide layer 104 on the substrate 100; forming a photoresist layer 105 on the sacrificial oxide layer 104 in the storage region A; using the photoresist layer 105 as a mask to etch and remove the sacrificial oxide layer 104 and the nitride layer 103 on the non-storage region; removing the photoresist layer 105; and removing at least a portion of the thickness of the sacrificial oxide layer 104 on the storage region A and the tunneling oxide layer 102 on the non-storage region. Forming the photoresist layer 105 on the sacrificial oxide layer 104 avoids damage to the nitride layer 103 during the coating and removal of the photoresist layer 105, thus avoiding affecting the charge storage capacity of the nitride layer 103 and ensuring the reliability of the device.

[0057] Furthermore, the semiconductor structure fabrication process employs only a single wet etching process, generating less waste liquid, saving costs while reducing pollution.

[0058] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, the substrate having a storage region and a non-storage region. A tunneling oxide layer, a nitride layer, and a sacrificial oxide layer are sequentially formed on the substrate, and a photoresist layer is formed on the sacrificial oxide layer in the storage region. The sacrificial oxide layer and the nitride layer on the non-storage region are etched away using the photoresist layer as a mask. When the sacrificial oxide layer and the nitride layer on the non-storage region are etched away using the photoresist layer as a mask, at least a portion of the thickness of the tunneling oxide layer in the non-storage region is also simultaneously removed. After simultaneously removing at least a portion of the thickness of the tunneling oxide layer in the non-storage region, the remaining thickness of the tunneling oxide layer in the non-storage region is less than the thickness of the sacrificial oxide layer. Remove the photoresist layer; Remove at least a portion of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area; After removing a portion of the thickness of the sacrificial oxide layer on the storage area and the tunneling oxide layer on the non-storage area, the remaining sacrificial oxide layer in the storage area constitutes the first dielectric layer. After forming the first dielectric layer, the method further includes: forming a second dielectric layer on the substrate, the second dielectric layer covering the first dielectric layer and the substrate of the non-memory region, the first dielectric layer and the second dielectric layer constituting a gate dielectric layer.

2. The method of producing a semiconductor structure according to claim 1, wherein After removing the sacrificial oxide layer on the storage region and the tunneling oxide layer on the non-storage region, the system further includes: A gate dielectric layer is formed on the substrate, the gate dielectric layer covering the nitride layer and the substrate of the non-memory region.

3. The method of producing a semiconductor structure according to claim 1 or 2, wherein The thickness of the gate dielectric layer is 30 Å to 50 Å.

4. The method of producing a semiconductor structure according to claim 1, wherein At least a portion of the thickness of the sacrificial oxide layer on the storage region and the tunneling oxide layer on the non-storage region are removed using a wet etching process.

5. The method of producing a semiconductor structure according to claim 4, wherein The wet etching process uses a mixed solution of hydrofluoric acid, ammonium fluoride, and phosphoric acid as the etching agent.

6. The method of producing a semiconductor structure according to claim 1, wherein The sacrificial oxide layer and the nitride layer in the non-storage area are removed using a dry etching process.

7. The method of producing a semiconductor structure according to claim 1, wherein When the sacrificial oxide layer is formed, the thickness of the sacrificial oxide layer is less than the thickness of the tunneling oxide layer.

8. The method for preparing a semiconductor structure as described in claim 1, characterized in that, A nitrogen oxide layer is also formed between the nitrided layer and the sacrificial oxide layer.

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