A trench SiC MOSFET device

Abstract

The present invention relates to a trench-type SiC MOSFET device, belonging to the field of power semiconductor technology. The present invention removes the gate oxide at the bottom of the trench, so that a diode structure is formed between the shielding layer, the drift region and the substrate, thereby increasing the reverse freewheeling capability of the device and improving the surge resistance of the device body diode; secondly, by introducing polysilicon of different doping types into the trench, the Miller capacitance of the device is reduced and the switching speed of the device is improved; in addition, the different doping types of polysilicon are connected to different potentials, which can respectively play the role of controlling the channel when conducting in the forward and reverse directions, and the polysilicon diode can also play the freewheeling role when working in the third quadrant, thereby obtaining a compromise between the forward conduction characteristics and the body diode conduction characteristics. Therefore, the present invention effectively improves the switching speed of the device on the basis of ensuring the original electrical performance of the SiC MOSFET, and greatly improves the forward and reverse conduction performance of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a trench-type SiC MOSFET device. Background Art

[0002] Silicon carbide, due to its excellent material and electrical properties, boasts a far superior quality factor for power devices than silicon, making it a research hotspot in the field of high-power power electronics. The theoretical maximum operating voltage of SiC-based power devices exceeds 10kV, exceeding the operating voltage of silicon-based insulated-gate bipolar transistors (IGBTs). Furthermore, as unipolar devices, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) also offer faster switching speeds. Therefore, SiC MOSFETs are considered an excellent alternative to Si IGBTs.

[0003] For controllable switch devices such as IGBT and MOSFET, reverse freewheeling is often required in practical applications. In order to suppress the opening of the internal parasitic BJT, the MOSFET device electrically short-circuits the source and p-well (taking NMOS as an example), so that the device itself has a reverse-parallel PN junction diode. However, due to the large bandgap of SiC material, the turn-on voltage drop of the PN junction diode of SiCMOSFET is high, reaching about 2.8V. If the body diode is directly used for reverse freewheeling, additional power consumption will be added. Therefore, when using SiC MOSFET, it is generally necessary to connect a SiC Schottky diode in reverse parallel to the outside, which will introduce additional parasitic parameters and increase the manufacturing cost of the system. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention aims to provide a trench SiC MOSFET device that reduces the device's Miller capacitance by introducing polysilicon of different doping types into the gate trench, while improving the device's third-quadrant conduction capability, thereby achieving the goal of reducing system power consumption and manufacturing costs.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A trench SiC MOSFET device comprises a metallized drain 1; a heavily doped first conductivity type semiconductor substrate 2 located above the metallized drain 1; a lightly doped first conductivity type semiconductor drift region 3 located above the heavily doped first conductivity type semiconductor substrate 2; and a trench region 13 located above the lightly doped first conductivity type semiconductor drift region 3.

[0007] A second conductive type semiconductor body region 6 is provided above the lightly doped first conductive type semiconductor drift region 3; a heavily doped first conductive type semiconductor source region 5 and a heavily doped second conductive type semiconductor contact region 4 are located adjacent to the top of the second conductive type semiconductor body region 6; the heavily doped first conductive type semiconductor source region 5 and the heavily doped second conductive type semiconductor contact region 4 are both in direct contact with the metallized source electrode 14 in the form of ohmic contact; the side surfaces of the heavily doped first conductive type semiconductor source region 5 and the second conductive type semiconductor body region 6 are both in direct contact with the sidewalls of the trench region 13, and the bottom of the trench region 13 exceeds the lower surface of the second conductive type semiconductor body region 6;

[0008] The sidewalls of the trench region 13 have a gate dielectric layer 7; the trench region 13 is filled with a lightly doped second conductivity type polysilicon region 10; the upper sides of the lightly doped second conductivity type polysilicon region 10 have heavily doped first conductivity type polysilicon gate electrode regions 9, and the lower surface of the heavily doped first conductivity type polysilicon gate electrode region 9 exceeds the lower surface of the second conductivity type semiconductor body region 6; the lower surface of the lightly doped second conductivity type polysilicon region 10 has an adjacent heavily doped second conductivity type polysilicon source electrode region 11; the bottom of the trench region 13 is heavily doped with the second conductivity type polysilicon source electrode region 11; The second conductive type semiconductor shielding layer 12 is wrapped, and the upper surface of the second conductive type semiconductor shielding layer 12 is in direct contact with the lower surface of the heavily doped second conductive type polycrystalline silicon source electrode region 11; the heavily doped first conductive type polycrystalline silicon gate electrode region 9 is connected to the gate potential; the heavily doped second conductive type polycrystalline silicon source electrode region 11 is connected to the metallized source electrode 14 by means of a through hole through layout design; an insulating dielectric layer 8 is provided under the metallized source electrode 14 to achieve electrical isolation between the metallized source electrode 14 and the heavily doped first conductive type polycrystalline silicon gate electrode region 9;

[0009] In some cross-sections perpendicular to the device surface, the side surfaces of the second conductive type semiconductor body region 6 are completely covered by the heavily doped first conductive type polycrystalline silicon gate electrode region 9; in other cross-sections perpendicular to the device surface, the side surfaces of the second conductive type semiconductor body region 6 are completely covered by the lightly doped second conductive type polycrystalline silicon region 10.

[0010] As a preferred embodiment, a first conductive type semiconductor current extension region 15 is further included, the upper surface of which is adjacent to the lower surface of the second conductive type semiconductor body region 6 , and the side surface of which is in direct contact with the side wall of the trench region 13 .

[0011] As a preferred embodiment, the doping concentration of the first conductive type semiconductor current extension region 15 is 1.1 to 1000 times that of the lightly doped first conductive type semiconductor drift region 3. When the device is forward-conducting, the first conductive type semiconductor current extension region 15 alleviates the current concentration and reduces the on-resistance of the device.

[0012] As a preferred embodiment, a lightly doped first conductive type semiconductor channel region 16 is also included, the upper surface of which is adjacent to the heavily doped first conductive type semiconductor source region 5, the lower surface of which is adjacent to the first conductive type semiconductor current extension region 15, and the side surfaces are in direct contact with the side walls of the second conductive type semiconductor body region 6 and the trench region 13 respectively.

[0013] As a preferred embodiment, the doping concentration of the lightly doped first conductive type semiconductor channel region 16 is 10 16 cm -3 It is about the order of magnitude and is used to reduce the channel resistance when the device is turned on.

[0014] As a preferred embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

[0015] As a preferred embodiment, the first conductivity type is p-type, and the second conductivity type is n-type.

[0016] As a preferred embodiment, the semiconductor is SiC.

[0017] As a preferred method, the doping concentration of the heavily doped -3 , the doping concentration of lightly doped is less than 1E16cm -3 .

[0018] The beneficial effects of the present invention are as follows: the trench-type SiC MOSFET device proposed by the present invention removes the gate oxide at the bottom of the trench, thereby forming a diode structure between the shielding layer, the drift region, and the substrate, thereby increasing the reverse freewheeling capability of the device and improving the surge resistance of the device body diode; secondly, by introducing polysilicon of different doping types into the trench, the Miller capacitance of the device is reduced and the switching speed of the device is increased; in addition, the different doping types of polysilicon are connected to different potentials, which can respectively play the role of controlling the channel when conducting in the forward and reverse directions, and the polysilicon diode can also play a freewheeling role when operating in the third quadrant, thereby obtaining a compromise between the forward conduction characteristics and the body diode conduction characteristics. Therefore, the present invention effectively improves the switching speed of the device while ensuring the original electrical performance of the SiC MOSFET, and greatly improves the forward and reverse conduction performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the three-dimensional structure of Example 1 of the present invention. To more clearly illustrate the top-view structure of the device, only the metallized source 14 above the cell is drawn. In actual practice, the metallized source 14 will cover the entire top of the cell.

[0020] Figure 2This is a schematic diagram of the three-dimensional structure after removing the metallized source 14 and the insulating dielectric layer 8 according to Example 1 of the present invention. The heavily doped first conductivity type polysilicon gate electrode regions 9 are spaced apart in the trench.

[0021] Figure 3 Based on Figure 1 and Figure 2 The cell cross-section of the AA` tangent line;

[0022] Figure 4 Based on Figure 1 and Figure 2 Cell section diagram of BB` tangent line;

[0023] Figure 5 This is a schematic diagram of the three-dimensional structure of Example 2 of the present invention, in which only the metallized source portion above the cell is drawn.

[0024] Figure 6 This is a schematic diagram of the three-dimensional structure of Example 3 of the present invention, in which only the metallized source portion above the cell is drawn.

[0025] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0026] Among them, 1 is a metallized drain, 2 is a heavily doped first conductivity type semiconductor substrate, 3 is a lightly doped first conductivity type semiconductor drift region, 4 is a heavily doped second conductivity type semiconductor contact region, 5 is a heavily doped first conductivity type semiconductor source region, 6 is a second conductivity type semiconductor body region, 7 is a gate dielectric layer, 8 is an insulating dielectric layer, 9 is a heavily doped first conductivity type polysilicon gate electrode region, 10 is a lightly doped second conductivity type polysilicon region, 11 is a heavily doped second conductivity type polysilicon source electrode region, 12 is a heavily doped second conductivity type semiconductor shielding layer, 13 is a trench region, 14 is a metallized source, 15 is a first conductivity type semiconductor current extension region, and 16 is a lightly doped first conductivity type semiconductor channel region. DETAILED DESCRIPTION

[0027] In order to make the content and principles of the present invention more clear, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Example 1

[0029] like Figure 1As shown in FIG. 1 , a schematic diagram of the three-dimensional structure of a trench SiC MOSFET device of the present invention is shown. Two tangent lines are drawn: AA` and BB` to obtain two cross sections, respectively. Figure 3 、 4 As shown, it includes a metallized drain 1; a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1; a lightly doped first conductivity type semiconductor drift region 3 located on the heavily doped first conductivity type semiconductor substrate 2; and a trench region 13 is further provided on the lightly doped first conductivity type semiconductor drift region 3.

[0030] A second conductive type semiconductor body region 6 is provided above the lightly doped first conductive type semiconductor drift region 3; a heavily doped first conductive type semiconductor source region 5 and a heavily doped second conductive type semiconductor contact region 4 are located adjacent to the top of the second conductive type semiconductor body region 6; the heavily doped first conductive type semiconductor source region 5 and the heavily doped second conductive type semiconductor contact region 4 are both in direct contact with the metallized source electrode 14 in the form of ohmic contact; the side surfaces of the heavily doped first conductive type semiconductor source region 5 and the second conductive type semiconductor body region 6 are both in direct contact with the sidewalls of the trench region 13, and the bottom of the trench region 13 exceeds the lower surface of the second conductive type semiconductor body region 6;

[0031] The sidewalls of the trench region 13 have a gate dielectric layer 7; the trench region 13 is filled with a lightly doped second conductivity type polysilicon region 10; the upper sides of the lightly doped second conductivity type polysilicon region 10 have heavily doped first conductivity type polysilicon gate electrode regions 9, and the lower surface of the heavily doped first conductivity type polysilicon gate electrode region 9 exceeds the lower surface of the second conductivity type semiconductor body region 6; the lower surface of the lightly doped second conductivity type polysilicon region 10 has an adjacent heavily doped second conductivity type polysilicon source electrode region 11; the bottom of the trench region 13 is heavily doped with the second conductivity type polysilicon source electrode region 11; The second conductive type semiconductor shielding layer 12 is wrapped, and the upper surface of the second conductive type semiconductor shielding layer 12 is in direct contact with the lower surface of the heavily doped second conductive type polycrystalline silicon source electrode region 11; the heavily doped first conductive type polycrystalline silicon gate electrode region 9 is connected to the gate potential; the heavily doped second conductive type polycrystalline silicon source electrode region 11 is connected to the metallized source electrode 14 by means of a through hole through layout design; an insulating dielectric layer 8 is provided under the metallized source electrode 14 to achieve electrical isolation between the metallized source electrode 14 and the heavily doped first conductive type polycrystalline silicon gate electrode region 9;

[0032] It is necessary to make special remarks on the polysilicon structure: in some cross sections perpendicular to the device surface, such as Figure 3As shown, the side of the second conductive type semiconductor body region 6 is completely covered by the heavily doped first conductive type polysilicon gate electrode region 9. When the device is forward-conducting, that is, when the gate voltage is positive, the corresponding channel can be turned on and the forward conduction of the semiconductor device is achieved. In other cross-sections perpendicular to the device surface, such as Figure 4 As shown, the side of the second conductive type semiconductor body region 6 is completely covered by the lightly doped second conductive type polysilicon region 10. When the device operates in the third quadrant, that is, when the gate voltage is zero and the source potential is positive, the corresponding channel can be turned on and the reverse freewheeling of the semiconductor device can be achieved. Figure 2 As shown, the heavily doped first conductivity type polysilicon gate electrode region 9 is spaced apart within the trench. Furthermore, under forward operating conditions, the lightly doped second conductivity type polysilicon region 10 located between the heavily doped first conductivity type polysilicon gate electrode region 9 and the heavily doped second conductivity type polysilicon source electrode region 11 does not experience punch-through breakdown.

[0033] A trench SiC MOSFET device is not limited to the strip-shaped cell shown in the accompanying drawings, and can also be used in square, hexagonal and other cell structures.

[0034] Optionally, the first conductivity type is n-type, and the second conductivity type is p-type.

[0035] Optionally, the first conductivity type is p-type, and the second conductivity type is n-type.

[0036] Taking NMOS as an example, that is, the first conductivity type is n-type and the second conductivity type is p-type, the working principle of the present invention is further explained:

[0037] When the device is forward-conducting, the gate potential is positive, that is, the heavily doped first conductivity type polysilicon gate electrode region 9 is at a positive voltage, attracting electrons, causing the channel in the second conductivity type semiconductor body region 6 covered by the heavily doped first conductivity type polysilicon gate electrode region 9 to open, allowing electrons to flow from the source to the drain. At this time, the heavily doped second conductivity type polysilicon source electrode region 11 has the same potential as the source, that is, zero potential, so no conductive channel can be formed in the second conductivity type semiconductor body region 6 covered by the lightly doped second conductivity type polysilicon region 10.

[0038] When the device withstands reverse voltage, the gate and source are at zero potential, and the drain is connected to a high potential. The device withstands voltage through the mutual depletion of the heavily doped second conductivity type semiconductor shield layer 12, the second conductivity type semiconductor body region 6, and the lightly doped first conductivity type semiconductor drift region 3. The trench gate of a conventional trench SiC MOSFET device is entirely wrapped by a gate oxide layer. To ensure the reliability of the oxide layer, the oxide layer at the bottom of the trench is relatively thicker. In addition, a method of introducing a heavily doped shield layer at the bottom of the trench is used to improve the reliability of the oxide layer and prevent the device from breaking down prematurely in the oxide layer. The present invention removes the oxide layer at the bottom of the trench region 13, allowing the lower surface of the heavily doped second conductivity type polysilicon source electrode region 11 to directly contact the heavily doped second conductivity type semiconductor shield layer 12, ensuring the high withstand voltage of the device while also avoiding the reliability issues of the gate oxide layer.

[0039] During the device switching process, due to the gate-source potential difference, the middle lightly doped second conductivity type polysilicon region 10 is depleted, and the polysilicon gate electrode region and the polysilicon source electrode region form a PN junction self-isolation, while reducing the overlapping area between the gate and the drain, thereby greatly reducing the Miller capacitance of the device and effectively improving the switching speed of the device during operation.

[0040] When the body diode of the device is in reverse freewheeling mode, the gate and drain are at zero potential, and the source is connected to a positive voltage, such as Figure 4 As shown in the BB' cross-section, the second conductive type semiconductor body region 6 covered by the lightly doped second conductive type polysilicon region 10 accumulates electrons near the side of the trench, so that the channel is opened, and electrons flow from the drain through the channel to the source; in addition, since the drain and the gate are both connected to zero potential, the heavily doped first conductive type polysilicon gate electrode region 9, the lightly doped second conductive type polysilicon region 10, and the heavily doped second conductive type polysilicon source electrode region 11 can be cleverly used to form a polysilicon diode for freewheeling. Since polysilicon is essentially a silicon material, the forward voltage drop of its diode is only 0.6~0.7V, which can effectively reduce the reverse freewheeling loss; furthermore, since the heavily doped second conductive type semiconductor shield layer 12 is in direct contact with the polysilicon source electrode region 11, the potential of the second conductive type semiconductor shield layer 12 is the same as the source potential, and the second conductive type semiconductor shield layer 12 and the lightly doped first conductive type semiconductor drift region 3 also form a PN junction diode, which can also be used as a reverse freewheeling path under large current conditions. Therefore, in the reverse freewheeling process of the diode in this structure, three diodes and one MOS channel actually take on the reverse freewheeling function, and the forward conduction voltage drop of the polysilicon diode is about 0.7V, which is much lower than the forward conduction voltage drop of the conventional SiC MOSFET body diode. Therefore, it effectively alleviates the problem of excessive local junction temperature caused by current concentration and improves the surge resistance of the device body diode.

[0041] Example 2

[0042] like Figure 5 As shown, the device structure of this embodiment, based on embodiment 1, further includes a first conductive type semiconductor current extension region 15, whose upper surface is adjacent to the lower surface of the second conductive type semiconductor body region 6, and whose side surface is in direct contact with the side wall of the trench region 13.

[0043] Furthermore, the doping concentration of the first conductive type semiconductor current extension region 15 is 1.1 to 1000 times that of the lightly doped first conductive type semiconductor drift region 3. When the device is forward-conducting, the first conductive type semiconductor current extension region 15 can effectively alleviate the current concentration and reduce the on-resistance of the device.

[0044] Example 3

[0045] like Figure 6 As shown, the device structure of this embodiment, based on embodiment 2, further includes a lightly doped first conductive type semiconductor channel region 16, whose upper surface is adjacent to the heavily doped first conductive type semiconductor source region 5, and the lower surface is adjacent to the first conductive type semiconductor current extension region 15, and the side surfaces are in direct contact with the side walls of the second conductive type semiconductor body region 6 and the trench region 13 respectively.

[0046] Furthermore, the doping concentration of the lightly doped first conductive type semiconductor channel region 16 is 10 16 cm -3 The channel resistance of the device when it is turned on can be reduced by about an order of magnitude.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A trench SiC MOSFET device, comprising a metallized drain (1); a heavily doped first conductivity type semiconductor substrate (2) located above the metallized drain (1); a lightly doped first conductivity type semiconductor drift region (3) located on the heavily doped first conductivity type semiconductor substrate (2); and a trench region (13) located above the lightly doped first conductivity type semiconductor drift region (3). A second conductive type semiconductor body region (6) is provided above the lightly doped first conductive type semiconductor drift region (3); a heavily doped first conductive type semiconductor source region (5) and a heavily doped second conductive type semiconductor contact region (4) are located adjacent to the top of the second conductive type semiconductor body region (6); the heavily doped first conductive type semiconductor source region (5) and the heavily doped second conductive type semiconductor contact region (4) are both in direct contact with a metallized source electrode (14) in the form of ohmic contact; the metallized source electrode (14) is located above the heavily doped first conductive type semiconductor source region (5) and the heavily doped second conductive type semiconductor contact region (4); the side surfaces of the heavily doped first conductive type semiconductor source region (5) and the second conductive type semiconductor body region (6) are both in direct contact with the side walls of the trench region (13), and the bottom of the trench region (13) exceeds the lower surface of the second conductive type semiconductor body region (6); The sidewalls of the trench region (13) have a gate dielectric layer (7); the trench region (13) is filled with a lightly doped second conductive type polysilicon region (10); both sides of the upper portion of the lightly doped second conductive type polysilicon region (10) have heavily doped first conductive type polysilicon gate electrode regions (9), and the lower surface of the heavily doped first conductive type polysilicon gate electrode region (9) exceeds the lower surface of the second conductive type semiconductor body region (6); the lower surface of the lightly doped second conductive type polysilicon region (10) has an adjacent heavily doped second conductive type polysilicon source electrode region (11); the bottom of the trench region (13) is heavily doped The second conductive type semiconductor shielding layer (12) is wrapped, and the upper surface of the second conductive type semiconductor shielding layer (12) is in direct contact with the lower surface of the heavily doped second conductive type polysilicon source electrode region (11); the heavily doped first conductive type polysilicon gate electrode region (9) is connected to the gate potential; the heavily doped second conductive type polysilicon source electrode region (11) is connected to the metallized source electrode (14) by means of a through hole through layout design; an insulating dielectric layer (8) is provided below the metallized source electrode (14) to achieve electrical isolation between the metallized source electrode (14) and the heavily doped first conductive type polysilicon gate electrode region (9); Its characteristics are: On some cross sections perpendicular to the device surface, the side surfaces of the second conductive type semiconductor body region (6) are completely covered by the heavily doped first conductive type polysilicon gate electrode region (9); and on other cross sections perpendicular to the device surface, the side surfaces of the second conductive type semiconductor body region (6) are completely covered by the lightly doped second conductive type polysilicon region (10).

2. A trench SiC MOSFET device according to claim 1, characterized in that: It also includes a first conductive type semiconductor current extension region (15), the upper surface of which is adjacent to the lower surface of the second conductive type semiconductor body region (6), and the side surface of which is in direct contact with the side wall of the trench region (13).

3. The trench SiC MOSFET device according to claim 2, wherein: The doping concentration of the first conductive type semiconductor current extension region (15) is 1.1 to 1000 times that of the lightly doped first conductive type semiconductor drift region (3). When the device is forward-conducting, the first conductive type semiconductor current extension region (15) alleviates current concentration and reduces the on-resistance of the device.

4. The trench SiC MOSFET device according to claim 2, wherein: The invention also includes a lightly doped first conductive type semiconductor channel region (16), the upper surface of which is adjacent to the heavily doped first conductive type semiconductor source region (5), the lower surface of which is adjacent to the first conductive type semiconductor current extension region (15), and the side surfaces of which are in direct contact with the side walls of the second conductive type semiconductor body region (6) and the trench region (13).

5. The trench SiC MOSFET device according to claim 4, wherein: The doping concentration of the lightly doped first conductive type semiconductor channel region (16) is 10 16 cm -3 It is about the order of magnitude and is used to reduce the channel resistance when the device is turned on.

6. A trench SiC MOSFET device according to any one of claims 1 to 5, characterized in that: The first conductivity type is n-type, and the second conductivity type is p-type.

7. A trench SiC MOSFET device according to any one of claims 1 to 5, characterized in that: The first conductivity type is p-type, and the second conductivity type is n-type.

8. A trench SiC MOSFET device according to any one of claims 1 to 5, characterized in that: The semiconductor is SiC.

9. A trench SiC MOSFET device according to any one of claims 1 to 5, characterized in that: The doping concentration of heavily doped samples is greater than 1E19 cm -3 , the doping concentration of lightly doped is less than 1E16cm -3 .

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