Methods for preserving repair information of memory, chips, and memory components.

Abstract

This application provides a memory, a chip, and a method for storing repair information in the memory. The memory includes: a repair circuit configured to receive a first signal from a processor, and to determine, based on the state of the first signal, to supply power via a first power supply or a second power supply to store the repair information, wherein the repair information is information about failed memory cells in the memory; the first power supply is zero or in a high-impedance state when the system is powered off, and the second power supply is not zero when the system is powered off; and a processing circuit configured to enable communication between the memory and the processor based on the repair information. Thus, the repair information in the memory can be continuously stored.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a memory, a chip, and a method for storing memory repair information. Background Technology

[0002] Random access memory (RAM), such as static random access memory (SRAM) and dynamic random access memory (DRAM), is an internal memory that directly exchanges data with processors such as graphics processing units (GPUs), central processing units (CPUs), and digital signal processing units (DSPs). It is usually used as a temporary data storage medium for operating systems or other running programs.

[0003] Figure 1 A schematic diagram of the structure of a random access memory 2 is shown. For example... Figure 1 As shown, a conventional random access memory (RAM) 2 may include a controller 20 and a processing module 40. Due to various reasons such as improper manufacturing processes or operation, a row and / or a column in the RAM 2 may fail, resulting in defects or problems in the memory's bit cells. In conventional technology, through professional testing, the repair information of the RAM 2, i.e., the address information and / or column address information of the failed memory cells, is usually stored in an eFuse or other non-volatile memory (for ease of explanation). Figure 1 (An example is illustrated using eFuse). Before the random access memory 2 is used, the repair information of the random access memory 2 in the eFuse needs to be shifted into the controller 20 step by step via clock control. When the random access memory 2 is used, the controller 20 can obtain the repair information of the random access memory 2 from the eFuse, preventing the processing module 40 from performing data read and write operations with the processor through the failed memory unit, so that the random access memory 2 functions normally, and the processing module 40 can communicate smoothly with the processor. Figure 1 (A double-headed arrow is used for illustration).

[0004] In summary, providing efficient and reliable repair information is crucial for the random access memory (RAM) 2 containing failed memory cells. A chip with a processor can supply power to the RAM 2. During this power supply period, the controller 20 can acquire and maintain the repair information of the RAM 2 from external sources (i.e., eFuse or other non-volatile memory). To achieve low power consumption, the chip frequently needs to switch between operating mode and standby mode. In operating mode, the power supply is normal, and the repair information can be acquired by the RAM 2; however, in standby mode, to reduce power consumption, the power supply is cut off, and the repair information is lost due to lack of power. After power is restored, the controller 20 needs to reload the repair information of the RAM 2. Therefore, repeated mode switching leads to repeated information loading, a cumbersome and inefficient process. For example, in existing GPU applications, especially in scenarios with inter-frame power drops, the time spent reloading repair information not only occupies the inter-frame interval time but also fails to meet certain inter-frame protocols or achieve effective power drops.

[0005] Therefore, how to preserve the repair information of the memory is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a memory, a chip, and a method for storing memory repair information. This method enables the memory to continuously store the memory repair information, which facilitates timely access to the memory repair information, facilitates smooth communication between the memory and the processor, and also helps the chip to effectively power down.

[0007] In a first aspect, this application provides a memory, comprising: a repair circuit configured to receive a first signal from a processor, and to determine, based on the state of the first signal, to supply power via a first power supply or a second power supply to store repair information, wherein the repair information is information of a failed memory cell in the memory, the first power supply is zero or in a high-impedance state when the system is powered off, and the second power supply is not zero when the system is powered off; and a processing circuit configured to realize communication between the memory and the processor based on the repair information.

[0008] The repair circuit, powered by the memory provided in the first aspect, can be connected to a first power supply and a second power supply. The first power supply is zero or in a high-impedance state when the system loses power, while the second power supply is not zero when the system loses power. The repair circuit can receive a first signal from the processor and, based on the state of the first signal, supply power through either the first or second power supply to store the repair information, thus avoiding the situation where the first power supply cannot provide power. The processing circuit realizes communication between the memory and the processor based on the repair information in the memory. The repair information is the address information of the failed memory cell. In this application, since the repair circuit is supplied by both the first and second power supplies, and the first power supply loses power when the system loses power, while the second power supply is not affected by the system power failure and can provide continuous power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply to continuously provide power for acquiring and maintaining the repair information of the memory. This ensures that the repair information of the memory can be saved indefinitely, avoiding the problem of not being able to save the repair information due to power failure in traditional technology. This allows the processing circuit to obtain the repair information of the memory from the repair circuit in a timely and accurate manner, identify the failed memory cell in the memory, and realize communication between the memory and the processor in the chip. This improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process caused by the need to reload the repair information in traditional technology. It reduces the time spent on reloading the repair information by the repair circuit, so that even if the chip experiences a system power failure, the time spent on data read and write operations will not be occupied due to reloading the repair information. This is conducive to the chip achieving effective power failure, so as to smoothly complete the communication between processors.

[0009] In one possible design, the repair circuit is configured to save repair information via a first power supply when the first signal is in a first state; and to save the repair information via a second power supply when the first signal is in a second state, wherein the second state is different from the first state. This allows for the continuous supply of power to the memory for acquiring and maintaining the repair information via either the first or second power supply.

[0010] In one possible design, the first state is a low-level state and the second state is a high-level state; or, the first state is a high-level state and the second state is a low-level state.

[0011] In one possible design, the repair circuit includes: a first circuit and a second circuit electrically connected, the second circuit also being electrically connected to the processing circuit; the first circuit is configured to receive first information from the processor and, based on the state of the first signal, control the second circuit to be powered by either a first power supply or a second power supply to maintain the repair information. In this way, the first circuit can control the second circuit to continuously maintain the stored repair information via either the first or second power supply.

[0012] In one possible design, the first circuit is configured to control the second circuit to save the repair information via the first power supply when the state of the first signal is a first state; the first circuit is also configured to control the second circuit to save the repair information via the second power supply when the state of the first signal is a second state; wherein the second state is different from the first state.

[0013] In one possible design, the first circuit includes: M inverters, a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor; where M is a positive integer, the M inverters are connected in series, one end of the M inverters connected in series is configured to receive a first signal, and the other end of the M inverters connected in series is electrically connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. The power supply terminal of each inverter and the source of the first PMOS transistor are configured to receive a second power supply. The source and substrate of the first PMOS transistor are electrically connected, and the drain of the first PMOS transistor, the drain of the first NMOS transistor, and the second NMOS transistor are also connected. The gate and drain of the S-channel MOSFET, the gate of the second PMOS transistor, and the gate of the third PMOS transistor are electrically connected. The source and substrate of the first NMOS transistor are electrically connected. The source of the second PMOS transistor is configured to receive a first power supply. The source and substrate of the second PMOS transistor are electrically connected. The drain of the second PMOS transistor and the source of the third PMOS transistor are electrically connected. The source and substrate of the third PMOS transistor are electrically connected. The drain of the third PMOS transistor and the source of the second NMOS transistor are both electrically connected to the second circuit. The ground terminal of each inverter, the source of the first NMOS transistor, and the substrate of the second NMOS transistor are all grounded. The voltage value of the first power supply is less than the voltage value of the second power supply.

[0014] In this application, regardless of how the level of the first signal changes, the first circuit can provide the second circuit with electrical energy to acquire and maintain the repair information of the memory, and the power supply can be maintained at a high voltage level so that the repair information is not lost.

[0015] Furthermore, the first circuit, employing the aforementioned structure, can achieve safe power switching using a minimal number of components. On one hand, the presence of the body diode in the second NMOS transistor in the first circuit prevents the path from the first power supply VDDP to the second power supply VDDC from being closed, thus preventing reverse voltage flow. On the other hand, the presence of the first PMOS transistor ensures that the drain of the second NMOS transistor is not directly electrically connected to the second power supply VDDC, avoiding the electrostatic discharge (ESD) risk associated with direct connection between the two.

[0016] In one possible design, the first circuit is configured to control the second circuit to save the repair information via the first power supply when the state of the first signal is a first state; the first circuit is also configured to control the second circuit to save the repair information via the second power supply when the state of the first signal is a second state; wherein the second state is different from the first state.

[0017] In one possible design, M is an odd number when the first state is low and the second state is high; and M is an even number when the first state is high and the second state is low.

[0018] In one possible design, the size of the m-th inverter is smaller than the size of the (m+1)-th inverter, where m is a positive integer and is greater than or equal to 1 and less than M. This improves the driving performance of the M inverters and reduces their latency, achieving a balance between their delay and driving performance.

[0019] In one possible design, the second circuit is configured to pre-store the repair information. This eliminates the need for the repair circuit to retrieve the repair information from other memory modules, saving the power required to do so.

[0020] In one possible design, the second circuit includes N D flip-flops or N JK flip-flops, where N is a positive integer.

[0021] In one possible design, the processing circuit is powered by a first power supply and a second power supply. This eliminates the need for a new power supply; both the repair and processing circuits can operate normally powered by the first and second power supplies.

[0022] Secondly, this application provides a chip, comprising: a power supply, a processor, and a memory in the first aspect and any possible design of the first aspect; wherein the power supply supplies power to the memory through a first power supply and a second power supply, the processor sends a first signal to the memory, and the memory realizes communication between the memory and the processor according to the memory's repair information.

[0023] The beneficial effects of the chip provided in the second aspect and the various possible designs of the second aspect can be found in the first aspect and the various possible implementations of the first aspect, and will not be repeated here.

[0024] Thirdly, this application provides a method for storing repair information of a memory, applied to a memory including: a repair circuit and a processing circuit; the processing circuit is configured to realize communication between the memory and a processor based on the repair information.

[0025] The method includes: a repair circuit receiving a first signal from a processor; the repair circuit determining, based on the state of the first signal, to supply power via a first power supply or a second power supply to store repair information, wherein the repair information is information about a failed memory cell in the memory, the first power supply is zero or in a high-impedance state when the system is powered off, and the second power supply is not zero when the system is powered off.

[0026] The repair circuit, using the memory repair information storage method provided in the third aspect, can be connected to a first power supply and a second power supply. The first power supply is zero or in a high-impedance state when the system loses power, while the second power supply is not zero when the system loses power. The repair circuit can receive a first signal from the processor and, based on the state of the first signal, supply power through either the first or second power supply to store the repair information, thus avoiding the situation where the first power supply cannot provide power. The processing circuit realizes communication between the memory and the processor based on the memory repair information. The repair information refers to the information of failed memory cells. In this application, because the repair circuit is supplied by both the first and second power supplies, and the first power supply loses power when the system loses power, while the second power supply is not affected by the system power failure and can continuously supply power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply to continuously provide power for acquiring and maintaining the repair information of the memory. This ensures that the repair information of the memory can be saved indefinitely, avoiding the problem of not being able to save the repair information due to power failure in traditional technology. This allows the processing circuit to obtain the repair information of the memory from the repair circuit in a timely and accurate manner, identify the failed memory cell in the memory, and realize communication between the memory and the processor in the chip. This improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process caused by the need to reload the repair information in traditional technology. It reduces the time spent on reloading the repair information by the repair circuit, so that even if the chip experiences a system power failure, the time spent on data read and write operations will not be occupied due to reloading the repair information. This is conducive to the chip achieving effective power failure, so as to smoothly complete the communication between processors.

[0027] In one possible design, the repair circuit determines whether to power the circuit with a first power supply or a second power supply to save the repair information based on the state of the first signal. This includes: when the state of the first signal is a first state, the repair circuit saves the repair information with the first power supply; or, when the state of the first signal is a second state, the repair circuit saves the repair information with the second power supply; wherein the second state is different from the first state.

[0028] In one possible design, the first state is a low-level state and the second state is a high-level state; or, the first state is a high-level state and the second state is a low-level state.

[0029] In one possible design, the repair information is pre-stored in the repair circuit. This saves the repair circuit the energy required to retrieve the repair information, thus conserving energy. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a random access memory (RAM).

[0031] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0033] Figure 4 A circuit diagram of the first circuit in a repair circuit provided in an embodiment of this application;

[0034] Figure 5 A circuit diagram of the second circuit in a repair circuit provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of the structure of a chip provided in one embodiment of this application;

[0036] Figure 7 A flowchart illustrating a method for saving repair information of a memory according to an embodiment of this application.

[0037] Figure captions:

[0038] 2—Random Access Memory; 20—Controller; 40—Processing Module;

[0039] 1—Memory; 10—Repair circuit; 11—First circuit; 12—Second circuit;

[0040] 30—Processing circuit; 100—Chip; 3—Power supply; 5—Processor. Detailed Implementation

[0041] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] This application provides a memory, a chip, and a method for storing memory repair information. The method can obtain and maintain the electrical energy for storing the memory's repair information from a first power source or a second power source by controlling the state of a first signal. This not only avoids the problem of not being able to save repair information due to power failure in traditional technologies, but also allows the repair circuit in the memory to continuously store the memory's repair signal. This enables the processing circuit in the memory to promptly obtain the memory's repair information from the repair circuit, achieving communication between the memory and the processor. This improves the efficiency and accuracy of data read / write operations between the memory and the processor in the chip. Furthermore, it avoids the cumbersome and inefficient process of reloading repair information in traditional technologies, reducing the time spent on reloading repair information. Even if the system experiences a power failure, the chip will not occupy data read / write operation time due to reloading repair information, facilitating effective system power failure and ensuring smooth communication between processors.

[0043] Below, in conjunction with Figure 2 The specific structure of the memory in this application will be described in detail.

[0044] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. Figure 2 As shown, the memory 1 of this application may include: a repair circuit 10 and a processing circuit 30 that are electrically connected.

[0045] The memory 1 involved in this application may include, but is not limited to, random access memory (RAM) such as SRAM or DRAM.

[0046] In this application, the repair circuit 10 can be connected to the first power supply ( Figure 2(VDDP is used for illustration). The first power supply can be provided by the power supply within the chip (…). Figure 2 The power supply (not shown) can be supplied directly to the repair circuit 10, or it can be supplied by the power supply in the chip through components such as a voltage divider. This application does not limit the specific implementation of this power supply. Furthermore, the specific implementation of this power supply can be found in the following description, and will not be repeated here.

[0047] Furthermore, the first power supply can be zero or in a high-impedance state when the system is powered off. Here, "system power failure" in this application can be understood as a power outage in the chip's power supply. For example, in standby mode, to reduce power consumption, the chip's power supply will be powered off, i.e., the system will power off.

[0048] In other words, the primary power source will lose power when the system loses power.

[0049] That is, the first power supply will drop to 0V or close to 0V when the system loses power, causing the repair circuit 10 to be unable to obtain the power to store the repair information of the memory 1 through the first power supply.

[0050] Alternatively, the first power supply may become high-impedance when the system loses power. In this case, the first power supply cannot be connected to the repair circuit 10, causing the repair circuit 10 to be unable to obtain the electrical energy to store the repair information of the memory 1 through the first power supply. The high-impedance state here can be understood as the impedance between the power supply in the chip and the repair circuit 10 being very large, making it impossible for the power supply in the chip to supply the first power to the repair circuit 10.

[0051] The repair information of memory 1 is the information of the failed memory cell in the memory, such as the address information and / or column address information of the failed memory cell. This application does not limit the specific representation of the repair information.

[0052] Furthermore, the repair information of memory 1 can be pre-stored in repair circuit 10, or it can be obtained by repair circuit 10 from other modules of memory 1; this application does not limit this. When the repair information of memory 1 is not pre-stored in repair circuit 10, repair circuit 10 can obtain the repair information of memory 1 from other modules of memory 1. When the repair information of memory 1 is pre-stored in repair circuit 10, the first power supply or the second power supply can provide electrical energy to repair circuit 10 to maintain the repair information of memory 1, saving the electrical energy required to obtain the repair information and conserving power supply and consumption.

[0053] In this application, the repair circuit 10 can be connected to a second power supply ( Figure 2(VDDC is used for illustration). The second power supply can be provided directly to the repair circuit 10 by the power module in the chip, or it can be provided to the repair circuit 10 by the power module in the chip through components such as voltage dividers. This application does not limit this.

[0054] Furthermore, the second power supply can be non-zero when the system loses power. That is, the second power supply will not lose power along with the system, allowing the repair circuit 10 to obtain the electrical energy needed to store the repair information in the memory 1, and enabling the repair circuit 10 to continuously store the repair information in the memory 1. Typically, the second power supply can be maintained at a relatively high voltage level.

[0055] The first power supply and the second power supply can be powered by the same power supply or by different power supplies; this application does not limit this. The specific implementation of the power supply will be described later and will not be repeated here.

[0056] In summary, a system power failure (i.e., a power outage in the chip's power supply) can affect or prevent the first power supply from continuing to supply power to the repair circuit 10, while a system power failure will not affect the second power supply from continuing to supply power to the repair circuit 10. Furthermore, the voltage values ​​of the first power supply and the second power supply can be equal or unequal; this application does not impose any limitation on this.

[0057] Those skilled in the art will understand that the repair circuit 10 requires electrical energy to acquire and maintain the repair information of the memory 1 in order to save the repair information of the memory 1. Based on the foregoing, during the entire process of the repair circuit 10 providing electrical energy to acquire and maintain the repair information of the memory 1, since the first power supply may fail to maintain power supply due to system power failure, while the second power supply can continuously maintain power supply, there is no need to consider the impact of system power failure on the second power supply, and the processor in the chip can usually detect system power failure. Therefore, in this application, the processor in the chip ( Figure 2 (Not illustrated in the text) The power supply status of the first power source can be indicated by the state of the first signal, such as whether the first power source can supply power, whether the first power source has lost power, or whether it does not need to supply power.

[0058] The first signal can be a digital signal or an analog signal. It can be sent directly from the processor in the chip to the repair circuit 10, or indirectly from the processor in the chip to the repair circuit 10 through registers or other components; this application does not limit the specifics. Furthermore, the specific implementation of the processor can be found in the following description and will not be repeated here.

[0059] In this application, the repair circuit 10 can receive a first signal from the processor ( Figure 2(Simplified using SD), so that the repair circuit 10 can avoid the phenomenon that the first power supply is zero or in a high impedance state due to system power failure based on the first information, thereby ensuring that the repair circuit 10 can be continuously supplied with electrical energy to acquire and maintain the repair information of the memory 1 through the first power supply or the second power supply.

[0060] When the state of the first information indicates that power can be supplied by the first power source, the repair circuit 10 can be powered by either the first power source or the second power source to save the repair information of the memory 1. To save power consumption, the repair circuit 10 can be powered by the first power source. When the state of the first signal indicates that power has failed or is not needed (e.g., the first power source has been repurposed), the repair circuit 10 can be powered by the second power source to save the repair information of the memory 1.

[0061] This application does not limit the specific state of the first information. Optionally, when the state of the first signal is the first state, the repair circuit 10 can determine based on the first state that it can currently be powered by the first power supply, such as when the first power supply has not experienced a power outage, and thus power is supplied by either the first power supply or the second power supply to save the repair information. To save power consumption, the repair circuit 10 can be powered by the first power supply. When the level state of the first signal is the second state, the repair circuit 10 can determine based on the second state that it cannot currently be powered by the first power supply, such as when the first power supply has experienced a power outage or when power is not currently needed by the first power supply, and thus power is supplied by the second power supply to save the repair information.

[0062] The second state differs from the first state. This application does not limit the specific implementation of the first and second states. Optionally, the first state is a low-level state and the second state is a high-level state; or, the first state is a high-level state and the second state is a low-level state.

[0063] In this application, the memory 1 also includes a processing circuit 30. The processing circuit 30 constitutes the core circuit of the memory 1, and this application does not limit the specific implementation of the processing circuit 30. For example, the processing circuit 30 can consist of four parts: an input / output module, a mode selection module, a read / write control module, and a storage array module. The input / output module is mainly used for data exchange between the memory 1 and the processor in the chip, as well as data transmission between the processing circuit 30 and the repair circuit 10. The mode selection module is mainly used for verification, debugging, and control operations of the processing circuit 30. The read / write control module is mainly used for reading or writing between the memory 1 and the processor in the chip. The storage array module mainly consists of multiple storage cells controlled by word line addresses and bit line addresses, used for storing data arrays.

[0064] In this application, in order to determine whether the repair information stored in the repair circuit 10 has failed, the processing circuit 30 can obtain the address information of the failed storage cell in the memory 1 and the address information of the storage cell in the memory 1 that can be read and written through software programs and other modules. The processing circuit 30 can also obtain the repair information stored in the repair circuit 10 from the repair circuit 10.

[0065] Furthermore, the processing circuit 30 can perform a bit-by-bit matching to determine whether the address information of the failed memory cell in memory 1 matches the repair information stored in the repair circuit 10. When it is determined that the address information of the failed memory cell in memory 1 matches the repair information, the processing circuit 30 can replace the repair information stored in the repair circuit 10 using the address information of the readable and writable memory cells in memory 1. When it is determined that the address information of the failed memory cell in memory 1 does not match the repair information, the processing circuit 30 does not need to replace the repair information stored in the repair circuit 10.

[0066] Therefore, based on the electrical connection between the processing circuit 30 and the processor in the chip, the processing circuit 30 performs communication between the memory 1 and the processor in the chip through data read and write operations according to the address information of the memory cell in the memory 1 that can be read and written.

[0067] Figure 1 In traditional systems, the random access memory 2 (RAM 2) cannot continue to retain its repair information when the power supply provided by the chip fails. However, in this application, the repair circuit 10, through the indication of the state of a first signal, can continuously provide power to acquire and maintain the repair information of the memory 1 via a first power supply or a second power supply. This avoids the situation where the first power supply may fail, allowing the repair circuit 10 to continuously retain the repair information of the memory 1. This facilitates the processing circuit 30 in timely obtaining the repair information of the memory 1 from the repair circuit 10, enabling the processing circuit 30 to accurately identify the failed memory cells in the memory 1. This improves the efficiency and accuracy of data read / write operations between the memory 1 and the processor in the chip.

[0068] Meanwhile, traditional random access memory 2 requires reloading repair information before memory 1 is used, resulting in a cumbersome and inefficient process. In this application, the repair circuit 10, due to the continuous power supply of the first or second power supply, does not need to reload the memory's repair information, reducing the time spent on reloading the repair information. This avoids the chip consuming data read / write operations time due to reloading repair information even if the system experiences a power failure, which is beneficial for the chip to achieve effective power-off and smoothly complete data read / write operations between memory 1 and the processor.

[0069] The memory provided in this application can be connected to a first power supply and a second power supply through a repair circuit. The first power supply is zero or in a high-impedance state when the system loses power, while the second power supply is not zero when the system loses power. The repair circuit can receive a first signal from the processor and, based on the state of the first signal, supply power through either the first or second power supply to save the repair information, thus avoiding the situation where the first power supply cannot provide power. The processing circuit realizes communication between the memory and the processor based on the repair information in the memory. The repair information refers to the information of the failed memory cells. In this application, because the repair circuit is supplied by both the first and second power supplies, and the first power supply loses power when the system loses power, while the second power supply is not affected by the system power failure and can continuously supply power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply to continuously provide power for acquiring and maintaining the repair information of the memory. This ensures that the repair information of the memory can be saved indefinitely, avoiding the problem of not being able to save the repair information due to power failure in traditional technology. This allows the processing circuit to obtain the repair information of the memory from the repair circuit in a timely and accurate manner, identify the failed memory cell in the memory, and realize communication between the memory and the processor in the chip. This improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process caused by the need to reload the repair information in traditional technology. It reduces the time spent on reloading the repair information by the repair circuit, so that even if the chip experiences a system power failure, the time spent on data read and write operations will not be occupied due to reloading the repair information. This is conducive to the chip achieving effective power failure, so as to smoothly complete the communication between processors.

[0070] The specific implementation structure of the memory 1 of this application will be illustrated below with reference to specific embodiments.

[0071] In this application, the repair circuit 10 may include various implementations. Based on the function of the repair circuit 10, optionally, in... Figure 2 Based on the illustrated embodiments, as Figure 3 As shown, the repair circuit 10 of this application may include: a first circuit 11 and a second circuit 12 electrically connected, and the second circuit 12 is also electrically connected to the processing circuit 30.

[0072] The first circuit 11 is used to connect to a first power supply and a second power supply, and to receive a first signal from the processor. The second circuit 12 is used to store or store repair information. This application does not limit the specific implementation of the first circuit 11 and the second circuit 12.

[0073] It should be noted that the second circuit 12 can pre-store the repair information, or it can store the repair information through the transmission of the first circuit 11; this application does not limit this. Specifically, when the second circuit 12 does not pre-store the repair information of the memory 1, the first circuit 11 can obtain the repair information of the memory 1 from other modules of the memory 1. When the second circuit 12 pre-stores the repair information of the memory 1, the first circuit 11 does not need to obtain the repair information of the memory 1 from other modules of the memory 1; it only needs to provide the second circuit 12 with the power to store the repair information of the memory 1, thus saving the power required to obtain the repair information of the memory 1.

[0074] In summary, based on the electrical connection between the first circuit 11 and the second circuit 12, in order to acquire and maintain the repair information of the memory 1, the first circuit 11 can control the second circuit 12 to be powered by either the first power supply or the second power supply based on the state of the first signal, so as to save the repair information of the memory 1. Therefore, based on the electrical connection between the second circuit 12 and the processing circuit 30, the processing circuit 30 can acquire the repair information of the memory 1 from the second circuit 12, realizing communication between the memory 1 and the processor.

[0075] Optionally, when the first signal is in a first state, the first circuit 11 can control the second circuit 12 to be powered by either a first power supply or a second power supply to save the repair information. To save power, the first circuit 11 can be powered by the first power supply. When the first signal is in a second state, the first circuit 11 can control the second circuit 12 to be powered by the second power supply to save the repair information.

[0076] In this application, the first circuit 11 may include various implementations. Below, in the above... Figure 3 Based on the illustrated embodiments, combined with Figure 4 The specific structure of the first circuit 11 of this application is illustrated by example.

[0077] In one feasible implementation, such as Figure 4 As shown, the first circuit 11 of this application may include: M inverters, a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor. The field-effect transistors (MOS) include: P-type metal-oxide-semiconductor (PMOS) transistors and N-type metal-oxide-semiconductor (NMOS) transistors.

[0078] For ease of explanation, Figure 4In the diagram, the first PMOS transistor is represented by MP1, the first NMOS transistor by MN1, the second PMOS transistor by MP2, the third PMOS transistor by MP3, and the second NMOS transistor by MN2.

[0079] In this application, M inverters are connected in series. One end of each of the M inverters is configured to receive a first signal, and the other end of each inverter is electrically connected to the gate of a first PMOS transistor and the gate of a first NMOS transistor. The power supply terminal of each inverter and the source of the first PMOS transistor are configured to receive a second power supply. The source and substrate of the first PMOS transistor are electrically connected. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate and drain of the second NMOS transistor, the gate of the second PMOS transistor, and the third PMOS transistor are also connected. The gate of the OS transistor is electrically connected, the source and substrate of the first NMOS transistor are electrically connected, the source of the second PMOS transistor is configured to receive the first power supply, the source and substrate of the second PMOS transistor are electrically connected, the drain of the second PMOS transistor and the source of the third PMOS transistor are electrically connected, the source and substrate of the third PMOS transistor are electrically connected, the drain of the third PMOS transistor and the source of the second NMOS transistor are both electrically connected to the second circuit 12, and the ground terminal of each inverter, the source of the first NMOS transistor and the substrate of the second NMOS transistor are all grounded.

[0080] Where M is a positive integer, and this application does not limit the specific size of M. Based on the above connection method, when the first state is a low level state and the second state is a high level state, M is an odd number, such as M = 3. When the first state is a high level state and the second state is a low level state, M is an even number, such as M = 4.

[0081] In this application, the sizes of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, the third PMOS transistor, and the second NMOS transistor are set to be relatively large, so that the voltage loss consumed by the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, the third PMOS transistor, and the second NMOS transistor is reduced, thereby ensuring that sufficient power supply can be provided to the second circuit 12.

[0082] In addition to using a second PMOS transistor connected in series with a third PMOS transistor, the first circuit 11 in this application may also use three or more PMOS transistors connected in series. Generally, considering the complexity of circuit layout implementation, the first circuit 11 usually uses a second PMOS transistor connected in series with a third PMOS transistor, which is simple to lay out, easy to design, and saves layout space.

[0083] For ease of explanation, Figure 4In this example, taking the first state as low level, the second state as high level, M as 3, and the three inverters as INV1, INV2, and INV3, the specific structure of the first circuit 11 is illustrated. Furthermore, the operation of the first circuit 11 and the second circuit 12 is as follows:

[0084] When the first signal is in the first state (i.e., low level state), the second power supply VDDC supplies power to the three inverters (INV1, INV2, and INV3) and the first PMOS transistor MP1. The voltage at node sd_n (i.e., the output voltage of inverter INV3, or the gate voltage of the first PMOS transistor MP1 and the first NMOS transistor MN1) is equal to the second power supply VDDC. The first PMOS transistor MP1 is off, the first NMOS transistor MN1 is on, and the voltage at node sd_pp (i.e., the drain voltage of the first PMOS transistor MP1 and the first NMOS transistor MN1, or the gate voltage of the second PMOS transistor MP2 and the third PMOS transistor MP3) is equal to the ground voltage VSS.

[0085] The first power supply VDDP supplies power to the second PMOS transistor, and both the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on. Therefore, the first power supply VDDP inputs voltage VDD_COM to the second circuit 12 through the second PMOS transistor MP2 and the third PMOS transistor MP3.

[0086] Since the second PMOS transistor MP2 and the third PMOS transistor MP3 are relatively large, and the current consumption of the second circuit 12 is relatively small, the voltage VDD_COM is close to the voltage value of the first power supply VDDP, that is, the second circuit 12 is powered by the first power supply VDDP.

[0087] When the state of the first signal is the second state (i.e., high level state), the second power supply VDDC supplies power to the three inverters (INV1, INV2, and INV3) and the first PMOS transistor MP1. The voltage at node sd_n (i.e., the output voltage of inverter INV3, or the gate voltage of the first PMOS transistor MP1 and the first NMOS transistor MN1) is equal to the ground voltage VSS. The first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, and the voltage at node sd_pp (i.e., the drain voltage of the first PMOS transistor MP1 and the first NMOS transistor MN1, or the gate voltage of the second PMOS transistor MP2 and the third PMOS transistor MP3) is equal to the second power supply VDDC.

[0088] The first power supply VDDP supplies power to the second PMOS transistor. Since the voltage of the first power supply VDDP is less than the voltage of the second power supply VDDC (i.e., VDDP < VDDC), both the second PMOS transistor MP2 and the third PMOS transistor MP3 are disconnected. Based on the connection relationship between the second PMOS transistor MP2 and the third PMOS transistor MP3, the body diodes in the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected in series, preventing the path from the voltage VDD_COM in the second circuit 12 to the first power supply VDDP from being closed, thus preventing voltage reverse flow.

[0089] Since the voltage at node sd_n is equal to the ground voltage VSS, the second NMOS transistor MN2 is turned on. Furthermore, because the gate (G) and drain (D) of the second NMOS transistor MN2 are connected together, and its substrate (B) (body) is directly connected to the ground voltage VSS, the substrate bias effect of the second NMOS transistor MN2 is very weak, resulting in a low threshold voltage Vth. th MMN2 remains essentially unchanged. Therefore, when the voltage VDD_COM decreases to below the threshold voltage V of the second power supply VDDC and the second NMOS transistor MN2 due to the internal power consumption of the second circuit 12, th The voltage difference between MMN2 and VDD_COM <VDDC-V th When MMN2 is turned on, the second NMOS transistor MN2 is turned on, making the voltage VDD_COM close to the threshold voltage V of the second power supply VDDC and the second NMOS transistor MN2. th The voltage difference between MMN2 and MMN2 (i.e., VDDC-V) th The second circuit 12 is powered by the second power supply VDDC. Since the second power supply VDDC can continuously supply power, the repair information of memory 1 can be stored in the second circuit 12 indefinitely. Thus, the second power supply VDDC inputs voltage VDD_COM to the second circuit 12 through the first PMOS transistor MP1 and the second NMOS transistor MN2.

[0090] In summary, regardless of how the state of the first signal changes, the first circuit 11 can provide the second circuit 12 with electrical energy to acquire and maintain the repair information of the memory 1, and the power supply can be maintained at a high voltage level so that the repair information will not be lost.

[0091] Furthermore, the first circuit 11, employing the aforementioned structure, can achieve safe power switching using a minimal number of components. On one hand, the presence of the body diode in the second NMOS transistor in the first circuit 11 prevents the path from the first power supply VDDP to the second power supply VDDC from being closed, thus preventing voltage backflow. On the other hand, the presence of the first PMOS transistor MP1 prevents the drain of the second NMOS transistor MN2 from being directly electrically connected to the second power supply VDDC, avoiding the electrostatic discharge (ESD) risk associated with direct connection between the two.

[0092] Considering the delay and driving performance of inverters, optionally, the size of the m-th inverter is smaller than the size of the (m+1)-th inverter, where m is a positive integer and is greater than or equal to 1 and less than M. In other words, the size of the M inverters can be increased progressively, meaning the size of each subsequent inverter is larger than the size of the preceding inverter. This improves the driving performance of the M inverters, reduces their delay, and achieves a balance between delay and driving performance.

[0093] In this application, the second circuit 12 may include multi-level registers with various implementations. Optionally, the second circuit 12 may include N D flip-flops or N JK flip-flops, where N is a positive integer, and N is determined by the number of wordline address bits and bitline address bits of memory 1. Below, in the above... Figure 3 or Figure 4 Based on the illustrated embodiments, combined with Figure 5 The specific structure of the second circuit 12 in this application is illustrated with an example. For ease of explanation, Figure 5 In the example, the second circuit 12 is illustrated using N D flip-flops.

[0094] like Figure 5 As shown, the Q terminal of the nth D flip-flop in the second circuit 12 is electrically connected to the D terminal of the (n+1)th D flip-flop, where n is a positive integer and is greater than or equal to 1 and less than N. Furthermore, the D terminal of the first D flip-flop in the second circuit 12 is electrically connected to the first circuit 11 to receive repair information from the memory 1.

[0095] The RST reset terminals of each D flip-flop are electrically connected together to form the RPRST reset terminal of the second circuit 12. The processor in the chip is also electrically connected to the RPRST reset terminal of the second circuit 12. Figure 5 (Not illustrated in the diagram), used to transmit a reset signal, causing each D flip-flop to reset to its initial state based on the reset signal. The CLK clock inputs of each D flip-flop are electrically connected together to form the RPCLK clock input of the second circuit 12. Furthermore, the processor in the chip is electrically connected to the RPCLK clock input of the second circuit 12. Figure 5 (Not illustrated in the image), used to transmit clock cycle signals.

[0096] Before the repair information is written into memory 1, the N D flip-flops are reset to their initial state via the RPRST reset pin of the second circuit 12. Controlled by the RPCLK clock pin of the second circuit 12, each D flip-flop writes one address bit of the repair information within its corresponding clock cycle. Thus, the second circuit 12 completes the process of saving the repair information.

[0097] In this application, when the state of the first signal is the first state, the N D flip-flops are powered by the first power supply VDDP. When the state of the first signal is the second state, the N D flip-flops are switched from the first power supply VDDP to the second power supply VDDC.

[0098] Furthermore, since the processing circuit 30 can perform data read and write operations between the memory 1 and the processor, the power supply requirement of the memory 1 mainly comes from the processing circuit 30, with a small portion coming from the repair circuit 10. The power supply requirement of the processing circuit 30 mainly comes from the storage data array, with a small portion coming from data read and write operations. Therefore, to save power, the processing circuit 30 is typically powered by two power supplies to maintain its operation.

[0099] Based on the above, in this application, the processing circuit 30 can be powered by a first power supply to control data read and write operations, and by a second power supply to store the data array. Furthermore, considering that the first power supply will fail when the system loses power, while the second power supply will remain unaffected by power outages and continue to provide power, the data array in the processing circuit 30 can still be stored. This eliminates the need for a new power supply to be introduced into the memory 1, thus making efficient use of power to achieve the functions of the memory 1 and avoiding resource waste.

[0100] By way of example, this application also provides a chip. Figure 6 This is a schematic diagram of the structure of a chip provided in one embodiment of this application. Figure 6 As shown, the chip 100 of this application may include: a power supply 3, a processor 5, and a memory 1.

[0101] This application does not limit the specific implementation of chip 100, and chip 100 can be integrated into various electronic devices such as televisions, mobile phones, laptops, or wearable devices, or it can be set up independently; this application does not limit this. In addition, chip 100 can also communicate with external devices, such as receiving user commands or transmitting data.

[0102] In this application, the power supply 3 supplies a first power supply and a second power supply to the memory 1, enabling the repair circuit 10 in the memory 1 to provide continuous power for acquiring and maintaining the repair information in the random access memory 1, thus allowing the memory 1 to continuously store the repair information. Additionally, the power supply 3 also enables the processing circuit 30 in the memory 1 to operate normally.

[0103] This application does not limit the specific implementation of the power supply 3. For example, the power supply 3 can be a single power supply or multiple power supplies. The power supply 3 can be built into the chip 100 or externally inserted into the chip 100. This application does not limit the specific implementation of the power supply 3.

[0104] In this application, the processor 5 can send a first signal to the repair circuit 10 in the memory 1, so that the repair circuit 10 in the memory 1 can be powered by a first power supply or a second power supply according to the state of the first signal, in order to save the repair information of the memory 1. And based on the electrical connection between the memory 1 and the processor 5 ( Figure 5 (Double arrows are used for illustration) The processing circuit 30 in memory 1 can realize communication between memory 1 and processor 5 based on the repair information.

[0105] The processor 5 may include components such as a GPU, CPU, or DSP capable of performing data read and write operations in the memory 1. The memory 1 can be used to execute... Figures 2-5 The technical solutions of the embodiments shown are similar in principle and in effect, and will not be described again here.

[0106] In addition, power supply 3 can also supply power to processor 5. Figure 6 (Not illustrated in the diagram) to maintain the normal operation of processor 5, and also to supply power to other modules in chip 100 ( Figure 6 (Not illustrated in the text), this application does not limit this.

[0107] The chip provided in this application can be used to perform... Figures 2-5 The technical solution for the memory in the embodiments has a similar implementation principle and technical effect, and will not be described again here.

[0108] For example, this application also provides a method for saving repair information of a memory. Figure 7 A flowchart illustrating a method for saving memory repair information according to an embodiment of this application. The method for saving memory repair information according to this application can be applied to, for example... Figures 2-6 The memory shown is used to implement the operations corresponding to the repair circuit in any of the above embodiments. The memory includes a repair circuit and a processing circuit. The processing circuit can realize communication between the memory and the processor based on the repair information.

[0109] like Figure 7 As shown, the method for saving repair information of the memory provided in this application may include:

[0110] S101, The repair circuit receives the first signal from the processor.

[0111] S102. The repair circuit determines whether to supply power through the first power supply or the second power supply to save the repair information based on the state of the first signal. The repair information is the information of the failed memory cell in the memory.

[0112] In this application, the repair circuit has power inputs from a first power supply and a second power supply. The first power supply is zero or in a high-impedance state when the system loses power, meaning it can lose power along with the system. The second power supply is not zero when the system loses power, meaning it is unaffected by power loss and can continue to supply power. Therefore, the repair circuit can save the memory's repair information by being powered by either the first or second power supply based on the indication of the state of the first signal.

[0113] This approach allows the repair circuit to switch between the first and second power supplies based on the status of the first signal. This ensures the continuous preservation of the memory's repair information, enabling the processing circuit to retrieve this information promptly and accurately, identify failed memory cells, and improve the efficiency and accuracy of data read / write operations between the memory and processor. Simultaneously, it reduces the time required for the repair circuit to reload and repair, ensuring that even during system power outages, the chip's read / write time is not interrupted by reloading and repair, facilitating effective power-off and ensuring smooth data read / write operations between the memory and processor.

[0114] In some embodiments, the repair circuit in S102 determines, based on the state of the first signal, whether to supply power via a first power source or a second power source to save the repair information, and may include:

[0115] When the first signal is in the first state, the repair circuit saves the repair information through the first power supply; or, when the first signal is in the second state, the repair circuit saves the repair information through the second power supply; wherein the second state is different from the first state.

[0116] In some embodiments, the method may further include: when the state of the first signal is a first state, the repair circuit can determine that the first power supply is in a power-on state, that is, the first power supply is not currently experiencing a power outage. When the state of the first signal is a second state, the repair circuit can determine that the first power supply is in a power-off state, that is, the first power supply may currently experience a power outage; or, the repair circuit can determine to stop saving repair information through the first power supply, that is, it is not currently necessary to use the first power supply to power the repair circuit.

[0117] In some embodiments, the first state is a low-level state and the second state is a high-level state; or, the first state is a high-level state and the second state is a low-level state.

[0118] In some embodiments, the repair information is information pre-stored in the repair circuit.

[0119] The method for saving memory repair information provided in this application can be applied to execution. Figures 2-6 The technical solution for the memory in the embodiments has a similar implementation principle and technical effect, and will not be described again here.

Claims

1. A memory, characterized in that, include: The repair circuit is configured to receive a first signal from the processor and determine, based on the state of the first signal, to supply power via a first power supply or a second power supply to store repair information, wherein the repair information is information about a failed memory cell in the memory, the first power supply is zero or in a high-impedance state when the system is powered off, and the second power supply is not zero when the system is powered off. The processing circuitry is configured to enable communication between the memory and the processor based on the repair information; The repair circuit includes: a first circuit and a second circuit electrically connected, wherein the second circuit is also electrically connected to the processing circuit; The first circuit is configured to receive first information from the processor, and to control the second circuit to be powered by the first power supply or the second power supply according to the state of the first signal to maintain the repair information; The first circuit is configured to control the second circuit to save the repair information through the first power supply when the state of the first signal is a first state; The first circuit is also configured to control the second circuit to save the repair information through the second power supply when the state of the first signal is the second state; The second state is different from the first state.

2. The memory according to claim 1, characterized in that, The repair circuit is configured to save the repair information via the first power supply when the state of the first signal is a first state; and to save the repair information via the second power supply when the state of the first signal is a second state; wherein the second state is different from the first state.

3. The memory according to claim 2, characterized in that, The first state is a low-level state, and the second state is a high-level state; or, The first state is a high-level state, and the second state is a low-level state.

4. The memory according to claim 1, characterized in that, The first circuit includes: M inverters, a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor; Where M is a positive integer, the M inverters are connected in series, one end of the M inverters connected in series is configured to receive the first signal, and the other end of the M inverters connected in series is electrically connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. The power supply terminal of each inverter and the source of the first PMOS transistor are configured to receive the second power supply. The source and substrate of the first PMOS transistor are electrically connected, and the drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate and drain of the second NMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor are electrically connected. The source and substrate of the first NMOS transistor are electrically connected. The source of the second PMOS transistor is configured to receive the first power supply. The source and substrate of the second PMOS transistor are electrically connected. The drain of the second PMOS transistor and the source of the third PMOS transistor are electrically connected. The source and substrate of the third PMOS transistor are electrically connected. The drain of the third PMOS transistor and the source of the second NMOS transistor are both electrically connected to the second circuit. The ground terminal of each inverter, the source of the first NMOS transistor, and the substrate of the second NMOS transistor are all grounded. The voltage value of the first power supply is less than the voltage value of the second power supply.

5. The memory according to claim 4, characterized in that, When the first state is a low level state and the second state is a high level state, M is an odd number; When the first state is a high level state and the second state is a low level state, M is an even number.

6. The memory according to claim 5, characterized in that, The size of the m-th inverter is less than the size of the (m+1)-th inverter, where m is a positive integer and is greater than or equal to 1 and less than M.

7. The memory according to any one of claims 1, characterized in that, The second circuit is configured to pre-save the repair information.

8. The memory according to any one of claims 1, characterized in that, The second circuit includes N D flip-flops or N JK flip-flops, where N is a positive integer.

9. The memory according to any one of claims 1, characterized in that, The processing circuit is powered by the first power supply and the second power supply.

10. A chip, characterized in that, include: A power supply, a processor, and a memory as described in any one of claims 1-9; The power supply supplies power to the memory through a first power supply and a second power supply. The processor sends a first signal to the memory, and the memory communicates with the processor based on the memory's repair information.

11. A method for storing repair information in a memory, characterized in that, The method is applied to the memory, which includes a repair circuit and a processing circuit; the processing circuit is configured to enable communication between the memory and a processor based on the repair information. The method includes: The repair circuit receives a first signal from the processor; The repair circuit determines whether to supply power through a first power supply or a second power supply to save the repair information based on the state of the first signal. The repair information is the information of the failed memory cell in the memory. The first power supply is zero or in a high-impedance state when the system is powered off, and the second power supply is not zero when the system is powered off. When the first signal is in the first state, the repair circuit saves the repair information through the first power supply; or, when the first signal is in the second state, the repair circuit saves the repair information through the second power supply; wherein the second state is different from the first state.

12. The method according to claim 11, characterized in that, The repair circuit determines whether to supply power via a first power source or a second power source to save the repair information based on the state of the first signal, including: When the state of the first signal is in the first state, the repair circuit saves the repair information through the first power supply; or... When the state of the first signal is the second state, the repair circuit saves the repair information through the second power supply; The second state is different from the first state.

13. The method according to claim 12, characterized in that, The first state is a low-level state, and the second state is a high-level state; or, the first state is a high-level state, and the second state is a low-level state.

14. The method according to any one of claims 11-13, characterized in that, The repair information is information that has been pre-stored in the repair circuit.

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