Ultrasonic transducer self-test circuit

Abstract

The application relates to an ultrasonic transducer self-checking circuit. The ultrasonic transducer self-checking circuit comprises an ultrasonic wave generating module, a self-checking control module and a waveform shaping module. The self-checking control module is used for generating a first enabling control signal, a second enabling control signal and a third enabling control signal based on a self-checking enabling signal and a self-checking clock signal. The ultrasonic wave generating module comprises an ultrasonic transducer, is connected with the self-checking control module and is used for generating ultrasonic waves based on the first enabling control signal and the second enabling control signal. The waveform shaping module is connected with the self-checking control module and the ultrasonic wave generating module and is used for obtaining a square wave signal. The self-checking control module is further used for comparing an aftershock count result with a diagnosis count result when the third enabling signal is at a high level, and generating an alarm signal when the comparison result is abnormal. The ultrasonic transducer self-checking circuit can realize self-checking of the ultrasonic transducer and can timely discover and alarm when the ultrasonic transducer is abnormal.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a self-test circuit for an ultrasonic transducer. Background Technology

[0002] As cities develop, urban space and parking spaces become increasingly limited. Both automated and manual parking systems require highly precise distance measurements. Currently, the most mature and effective distance measurement system uses ultrasonic probes. These probes rely on ultrasonic transducers to convert electrical power into mechanical power (ultrasound waves) for transmission. The proper functioning of the ultrasonic transducer directly impacts the functional safety and reliability of the ultrasonic ranging system. However, there is currently no circuitry for self-checking ultrasonic transducers, making it impossible to detect transducer malfunctions promptly. Summary of the Invention

[0003] Therefore, it is necessary to provide a self-testing circuit for ultrasonic transducers to enable self-testing of ultrasonic transducers and to promptly detect and alarm when abnormalities occur in the ultrasonic transducers.

[0004] This application provides a self-test circuit for an ultrasonic transducer, including: an ultrasonic generation module, a self-test control module, and a waveform shaping module;

[0005] The self-test control module is used to generate a first enable control signal, a second enable control signal, and a third enable control signal based on the self-test enable signal and the self-test clock signal;

[0006] The ultrasonic generation module includes an ultrasonic transducer and is connected to the self-test control module for generating ultrasonic waves based on the first enable control signal and the second enable control signal.

[0007] The waveform shaping module is connected to the self-test control module and the ultrasonic wave generation module, and is used to shape the ultrasonic wave signal to obtain a square wave signal when the third enable control signal is high.

[0008] The self-test control module is also used to perform aftershock counting and diagnostic counting on the square wave signal. When the third enable signal is high, the aftershock counting result is compared with the diagnostic counting result, and an alarm signal is generated when the comparison result is abnormal.

[0009] The aforementioned ultrasonic transducer self-test circuit, by setting a self-test control module, can realize the self-test of the ultrasonic transducer. When there is an abnormality in the ultrasonic transducer, it can detect it in time and trigger an alarm, thereby improving the safety and reliability of the ultrasonic transducer self-test circuit.

[0010] Optionally, the self-test control module includes:

[0011] The first input terminal is used to receive the self-test enable signal;

[0012] The second input terminal is used to receive the self-test clock signal;

[0013] The third input terminal is used to receive the square wave signal;

[0014] The first output terminal is connected to the ultrasonic generation module and is used to output the first enable signal to the ultrasonic generation module.

[0015] The second output terminal is connected to the ultrasonic generation module and is used to output the second enable signal to the ultrasonic generation module.

[0016] The third output terminal is connected to the waveform shaping module and is used to output the third enable signal to the waveform shaping module;

[0017] The fourth output terminal is used to output the alarm signal.

[0018] Optionally, the self-test control module is further configured to generate a fourth enable signal; the ultrasonic transducer self-test circuit further includes a constant current module, which is connected to the self-test control module and the ultrasonic generation module, and is configured to provide a constant current to the ultrasonic generation module under the control of the fourth enable signal.

[0019] Optionally, the self-test control module further includes a fifth output terminal, which is connected to the constant current module and is used to output the fourth enable signal to the constant current module.

[0020] Optionally, the constant current source module includes:

[0021] A DC power supply, wherein the negative terminal of the DC power supply is grounded;

[0022] The constant current source includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the constant current source is connected to the positive terminal of the DC power supply, the second input terminal of the constant current source is connected to the self-test control module, and the output terminal of the constant current source is connected to the ultrasonic wave generating module.

[0023] Optionally, the ultrasonic wave generating module includes:

[0024] The first switch includes a first terminal, a second terminal, and a third terminal. The first terminal of the first switch is connected to the first output terminal of the self-test control module, and the third terminal of the first switch is grounded.

[0025] The second switch includes a first terminal, a second terminal, and a third terminal. The first terminal of the second switch is connected to the second output terminal of the self-test control module, and the third terminal of the second switch is grounded.

[0026] The transformer includes a main winding and a secondary winding, wherein the main winding is connected to the constant current source module, the second terminal of the first switch and the second terminal of the second switch;

[0027] An ultrasonic transducer is connected to the secondary winding and the waveform shaping module.

[0028] Optionally, the waveform shaping module includes:

[0029] A DC blocking capacitor includes a first end and a second end, wherein the first end of the blocking capacitor is connected to the ultrasonic wave generating module;

[0030] A Schmitt trigger includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the Schmitt trigger is connected to the second terminal of the isolation capacitor, the second input terminal of the Schmitt trigger is connected to the third output terminal of the self-test control module, the third input terminal of the Schmitt trigger is connected to a reference voltage, and the output terminal of the Schmitt trigger is connected to the third input terminal of the self-test control module.

[0031] Optionally, the ultrasonic wave includes an ultrasonic initiation signal and an ultrasonic aftershock signal; the waveform shaping module is used to shape the ultrasonic aftershock signal to obtain the square wave signal when the third enable control signal is high.

[0032] Optionally, the self-test control module includes:

[0033] An aftershock acquisition module is connected to the waveform shaping module and the self-test clock signal, and is used to acquire the square wave signal based on the self-test clock signal;

[0034] An aftershock counting module is connected to the aftershock acquisition module and the self-test clock signal, and is used to count aftershocks on the square wave signal based on the self-test clock signal;

[0035] A diagnostic counting module, connected to the self-test clock signal, is used to perform diagnostic counting after the aftershock counting module has counted for a preset time.

[0036] The main control module is connected to the self-test enable signal, the self-test clock signal, the aftershock counting module, and the diagnostic counting module. It is used to generate the first enable control signal, the second enable control signal, and the third enable control signal based on the self-test enable signal and the self-test clock signal. When the third enable signal is high, it compares the aftershock counting result with the diagnostic counting result and generates an alarm signal when the comparison result is abnormal.

[0037] Optionally, the main control module includes:

[0038] The frequency divider includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the first input terminal of the frequency divider is connected to the self-test enable signal, and the second input terminal of the frequency divider is connected to the self-test clock signal; the frequency divider is used to generate a frequency-divided signal based on the self-test enable signal and the self-test clock signal.

[0039] A control counter, the input of which is connected to the second output of the frequency divider, is used to control and count the frequency division signal;

[0040] The first comparator is connected to the output of the control counter and is used to compare the result of the control count with a first preset value, and output a comparison signal when the result of the control count reaches the first preset value.

[0041] The first AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the first AND gate is connected to the output terminal of the first comparator, and the second input terminal of the first AND gate is connected to the self-test enable signal; the first AND gate is used to perform AND logic processing on the self-test enable signal and the comparison signal to obtain the third enable signal.

[0042] A first inverter, the input of which is connected to the output of the first comparator, is used to invert the comparison signal to obtain an inverted comparison signal;

[0043] The second AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the second AND gate is connected to the self-test enable signal, and the second input terminal of the second AND gate is connected to the output terminal of the first inverter. The second AND gate is used to perform AND logic processing on the self-test enable signal and the inverse comparison signal to obtain a fourth enable signal.

[0044] The third AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the third AND gate is connected to the output terminal of the second AND gate, and the second input terminal of the third AND gate is connected to the second output terminal of the frequency divider. The third AND gate is used to perform AND logic processing on the fourth enable signal and the frequency divider signal to obtain the first enable signal.

[0045] The second inverter, whose input is connected to the first output of the frequency divider, is used to reverse the frequency division signal to obtain an inverted frequency division signal.

[0046] The fourth AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the fourth AND gate is connected to the output terminal of the second AND gate, and the second input terminal of the fourth AND gate is connected to the output terminal of the second inverter. The fourth AND gate is used to perform AND logic processing on the fourth enable signal and the inverted frequency divider signal to obtain the second enable signal.

[0047] The second comparator includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the second comparator is connected to the diagnostic counting module, the second input terminal of the second comparator is connected to the aftershock counting module, and the third input terminal of the second comparator is connected to the output terminal of the first AND gate; the second comparator is used to compare the aftershock counting result with the diagnostic counting result when the third enable signal is high, and generate an alarm signal when the comparison result is abnormal. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A circuit diagram of the self-test circuit for the ultrasonic transducer provided in this application;

[0050] Figure 2 The circuit diagram of the self-test control module in the provided ultrasonic transducer self-test circuit;

[0051] Figure 3 The circuit of the main control module in the self-test control module provided in this application;

[0052] Figure 4 The timing diagram of the self-test circuit of the ultrasonic transducer provided in this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10. Ultrasonic generation module; 20. Waveform shaping module; 30. Self-test control module; 40. Constant current source module; 101. DC power supply; 102. Constant current source; 103. First switch; 104. Second switch; 105. Transformer; 106. Ultrasonic transducer; 107. DC blocking capacitor; 108. Schmitt trigger; 201. Aftershock acquisition module; 202. Aftershock calculation module; 203. Diagnostic counting module; 204. Main control module; 301. Frequency divider; 302. Control counter; 303. First comparator; 304. First AND gate; 305. First inverter; 306. Second AND gate; 307. Third AND gate; 308. Second inverter; 309. Fourth AND gate; 310. Second comparator. Detailed Implementation

[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0057] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0058] It is understood that the terms "first," "second," "third," "fourth," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first control device may be referred to as a second control device, and similarly, a second control device may be referred to as a first control device. Both the first control device and the second control device are control devices, but they are not the same control device.

[0059] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0061] Please see Figure 1 This application provides an ultrasonic transducer self-test circuit, which includes: an ultrasonic generation module 10, a self-test control module 30, and a waveform shaping module 20. The self-test control module 30 is used to generate a first enable control signal sw1_en, a second enable control signal sw2_en, and a third enable control signal smit_en based on a self-test enable signal diag_en and a self-test clock signal diag_clk. The ultrasonic generation module 10 includes an ultrasonic transducer 106, and is connected to the self-test control module 30, used to generate a first enable control signal sw1_en, a second enable control signal sw2_en, and a third enable control signal smit_en based on a self-test enable signal diag_en and a self-test clock signal diag_clk. The control signal sw1_en and the second enable control signal sw2_en generate ultrasonic wave TP1; the waveform shaping module 20 is connected to the self-test control module 30 and the ultrasonic wave generation module 10, and is used to shape the ultrasonic wave signal TP1 to obtain a square wave signal TP2 when the third enable control signal smit_en is high; the self-test control module 30 is also used to perform aftershock counting and diagnostic counting on the square wave signal TP2, and compares the aftershock counting result with the diagnostic counting result when the third enable signal smit_en is high, and generates an alarm signal alarm when the comparison result is abnormal.

[0062] The aforementioned ultrasonic transducer self-test circuit, by setting a self-test control module 30, can realize the self-test of the ultrasonic transducer 106. When there is an abnormality in the ultrasonic transducer 106, it can detect and alarm in time, thereby improving the safety and reliability of the ultrasonic transducer self-test circuit.

[0063] In an optional example, the self-test control module 30 may include: a first input terminal (not shown), used to receive a self-test enable signal diag_en; a second input terminal (not shown), used to receive a self-test clock signal diag_clk; and a third input terminal (not shown), used to receive a square wave signal (TP2, i.e. Figure 1 The self-test control module 30 has the following output terminals: a first output terminal (not shown), a second output terminal (not shown), a third output terminal (not shown), a fourth output terminal (not shown), and an alarm signal (alarm). The first output terminal is connected to the ultrasonic generation module 10 and is used to output the first enable signal sw1_en to the ultrasonic generation module 10. The second output terminal (not shown) is connected to the ultrasonic generation module 10 and is used to output the second enable signal sw2_en to the ultrasonic generation module 10. The third output terminal (not shown) is connected to the waveform shaping module 20 and is used to output the third enable signal smit_en to the waveform shaping module 20. The fourth output terminal (not shown) is used to output the alarm signal (alarm).

[0064] In an optional example, please continue reading Figure 1 The self-test control module 30 can also be used to generate a fourth enable signal cur_en; the ultrasonic transducer self-test circuit also includes a constant current module 40, which is connected to the self-test control module 30 and the ultrasonic generation module 10. The constant current source module 40 is used to provide constant current to the ultrasonic generation module 10 under the control of the fourth enable signal cur_en.

[0065] Specifically, the self-test control module also includes a fifth output terminal (not shown). The fifth output terminal of the self-test control module 30 is connected to the constant current module 40. The fifth output terminal of the self-test control module 30 is used to output a fourth enable signal cur_en to the constant current module 40.

[0066] In an optional example, please continue reading Figure 1 The constant current source module 40 may include: a DC power supply 101, the negative terminal of which is grounded; a constant current source 102, which includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the constant current source 102 is connected to the positive terminal of the DC power supply 101, the second input terminal of the constant current source 102 is connected to the self-test control module 30, and the output terminal of the constant current source 102 is connected to the ultrasonic generation module 10.

[0067] Specifically, the second input terminal of the constant current source 102 is connected to the fifth output terminal of the detection and control module 30.

[0068] In an optional example, the ultrasonic generation module 10 may include: a first switch 103, which may include a first terminal, a second terminal, and a third terminal, the first terminal of the first switch 103 being connected to the first output terminal of the self-test control module 30, and the third terminal of the first switch 103 being grounded; a second switch 104, which may include a first terminal, a second terminal, and a third terminal, the first terminal of the second switch 104 being connected to the second output terminal of the self-test control module 30, and the third terminal of the second switch 104 being grounded; a transformer 105, which includes a main winding (not shown) and a secondary winding (not shown), the main winding being connected to the constant current source module 40, the second terminal of the first switch 103, and the second terminal of the second switch 104; and an ultrasonic transducer 106, which is connected to the secondary winding and the waveform shaping module 20.

[0069] Specifically, the main winding is connected to the output terminal of the constant current source 102, the second terminal of the first switch 103, and the second terminal of the second switch 104.

[0070] More specifically, the first enable signal sw1_en and the second enable signal sw2_en alternately enable and switch, with a switching frequency that can be, but is not limited to, 50 kHz (kilohertz). The first enable signal sw1_en and the second enable signal sw2_en respectively control the first switch 103 and the second switch 104, thereby generating a sine wave in the secondary winding of the transformer 105, which in turn drives the ultrasonic transducer 106 to generate ultrasonic waves. The frequency of the ultrasonic waves is the same as the frequency of the sine wave generated by the secondary winding of the transformer 105.

[0071] In an optional example, please continue reading Figure 1 The waveform shaping module 20 may include: a DC blocking capacitor 107, which includes a first terminal and a second terminal, the first terminal of which is connected to the ultrasonic wave generating module 10; a Schmitt trigger 108, which includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the Schmitt trigger 108 is connected to the second terminal of the isolation capacitor 107, the second input terminal of the Schmitt trigger 108 is connected to the third output terminal of the self-test control module 30, the third input terminal of the Schmitt trigger 108 is connected to the reference voltage Vcomp, and the output terminal of the Schmitt trigger 108 is connected to the third input terminal of the self-test control module 30. The output terminal of the Schmitt trigger 108 outputs a square wave signal TP2.

[0072] Specifically, when the fourth enable signal cur_en is low (i.e., the fourth enable signal cur_en is 0), the first enable signal sw1_en and the second enable signal sw2_en also simultaneously become low (i.e., 0). At this time, the secondary winding of transformer 105 stops generating sine waves, and the ultrasonic transducer 106 continues to generate aftershocks due to inertia, with the amplitude gradually attenuating to 0; the waveform of the ultrasonic wave during this process is as follows: Figure 4 As shown in ring (TP1), the ultrasonic wave can include an ultrasonic initiation signal and an ultrasonic aftershock signal. The waveform shaping module 20 is used to shape the ultrasonic aftershock signal to obtain a square wave signal TP2 when the third enable control signal smit_en is high (i.e., the third enable control signal smit_en is 1).

[0073] In an optional example, please refer to Figure 2 The self-test control module 30 may include: an aftershock acquisition module 201, which is connected to the waveform shaping module 20 and the self-test clock signal diag_en. The aftershock acquisition module 201 is used to acquire the square wave signal ring_in (i.e., based on the self-test clock signal diag_en). Figure 1 The system acquires data via TP2; aftershock counting module 202 and aftershock calculation module 202 are connected to aftershock acquisition module 201 and self-test clock signal diag_clk. Aftershock calculation module 202 is used to count aftershocks based on self-test clock signal diag_clk; diagnostic counting module 203 is connected to self-test clock signal diag_clk. Diagnostic counting module 203 is used to perform diagnostic counting after aftershock counting module 202 has counted for a preset time; main control module 204 is connected to self-test enable signal d The iag_en, self-test clock signal diag_clk, aftershock counting module 202, and diagnostic counting module 203 are all connected. The main control module 204 is used to generate a first enable control signal sw1_en, a second enable control signal sw2_en, and a third enable control signal smit_en based on the self-test enable signal diag_en and the self-test clock signal diag_clk. When the third enable signal smit_en is high, the aftershock counting result ring_cnt is compared with the diagnostic counting result diag_cnt, and an alarm signal is generated when the comparison result is abnormal.

[0074] In an optional example, such as Figure 3As shown, the main control module 204 may include: a frequency divider 301, which includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the first input terminal of the frequency divider 301 is connected to a self-test enable signal diag_en, and the second input terminal of the frequency divider 301 is connected to a self-test clock signal diag_clk; the frequency divider 301 is used to generate a frequency division signal freq_50k based on the self-test enable signal diag_en and the self-test clock signal diag_clk; a control counter 302, whose input terminal is connected to the second output terminal of the frequency divider 301; the control counter 302 is used to control the counting of the frequency division signal freq_50k; and a first comparator 303. Connected to the output of the control counter 302, the first comparator 303 compares the result of the control count, freq_50k_cnt, with a first preset value, and outputs a comparison signal cnt_eq_5 when the result of the control count, freq_50k_cnt, reaches the first preset value; the first AND gate 304 includes a first input, a second input, and an output; the first input of the first AND gate 304 is connected to the output of the first comparator 303, and the second input of the first AND gate 304 is connected to the self-test enable signal, diag_en; the first AND gate 304 performs AND logic processing on the self-test enable signal, diag_en, and the comparison signal, cnt_eq_5, to obtain a third enable signal, s. mit_en; First inverter 305, the input of the first inverter 305 is connected to the output of the first comparator 303, the first inverter 305 is used to invert the comparison signal cnt_eq_5 to obtain an inverted comparison signal; Second AND gate 306, the second AND gate 306 includes a first input, a second input, and an output; the first input of the second AND gate 306 is connected to the self-test enable signal diag_en, the second input of the second AND gate 306 is connected to the output of the first inverter 305, the second AND gate 306 is used to perform AND logic processing on the self-test enable signal diag_en and the inverted comparison signal to obtain a fourth enable signal cur_en; Third AND gate 307, the third AND gate 307 includes a first input The system includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the third AND gate 307 is connected to the output terminal of the second AND gate 306, and the second input terminal of the third AND gate 307 is connected to the second output terminal of the frequency divider 301. The third AND gate 307 is used to perform AND logic processing on the fourth enable signal cur_en and the frequency divider signal freq_50k to obtain the first enable signal sw1_en; the second inverter 308 has its input terminal connected to the first output terminal of the frequency divider 301. The second inverter 308 is used to invert the frequency divider signal freq_50k to obtain the inverted frequency divider signal freq_50k_neg; the fourth AND gate 309 includes a first input terminal, a second input terminal, and an output terminal;The first input of the fourth AND gate 309 is connected to the output of the second AND gate 306, and the second input of the fourth AND gate 309 is connected to the output of the second inverter 308. The fourth AND gate 309 is used to perform AND logic processing on the fourth enable signal cur_en and the inverse frequency divider signal freq_50k_neg to obtain the second enable signal sw2_en. The second comparator 310 includes a first input, a second input, a third input, and an output. The first input of the second comparator 310 is connected to the diagnostic counting module 203, the second input of the second comparator 310 is connected to the aftershock counting module 202, and the third input of the second comparator 310 is connected to the output of the first AND gate 304. The second comparator 310 is used to compare the aftershock counting result ring_cnt with the diagnostic counting result diag_cnt when the third enable signal smit_en is high, and to generate an alarm signal alarm when the comparison result is abnormal.

[0075] Specifically, the first preset value can be set according to actual needs. In this embodiment, the first preset value can be, but is not limited to, 5. In other examples, the first preset value can also be any value other than 5.

[0076] Specifically, the frequency divider 301 starts working when the self-test enable signal diag_en is high (i.e., diag_en is 1). The self-test clock signal diag_en is divided by 32 to generate a 50kHz frequency divider signal freq_50k. The frequency divider signal freq_50k is counted by the control counter 302 to obtain the control count result freq_50k_cnt. The control count result freq_50k_cnt is sent to the first comparator 303 for comparison. If the control count result freq_50k_cnt is equal to the first preset value (e.g., 5), a comparison signal cnt_eq_5 is generated, and the control counter 302 stops counting. The AND logic of the self-test enable signal diag_en and the comparison signal cnt_eq_5 generates the third enable signal smit_en. The AND logic of the self-test enable signal diag_en and the inverse comparison signal generates the fourth enable signal cur_en. The AND logic of the fourth enable signal cur_en and the frequency divider signal freq_50k generates the first enable signal sw1_en. The AND logic of the fourth enable signal cur_en and the inverse frequency divider signal freq_50k_neg generates the second enable signal sw2_en.

[0077] The working principle of the ultrasonic transducer self-test circuit of the present invention is as follows:

[0078] When the self-test enable signal diag_en is high (i.e., diag_en = 1), the main control module 204 in the self-test control module 30 generates a first enable signal sw1_en, a second enable signal sw2_en, and a fourth enable signal cur_en. The fourth enable signal cur_en enables the constant current source 102, providing constant current to the ultrasonic generation module 10. Simultaneously, the first enable signal sw1_en and the second enable signal sw2_en alternately enable and switch, with a switching frequency that can be, but is not limited to, 50 kHz. The first enable signal sw1_en and the second enable signal sw2_en control the first switch 103 and the second switch 104, respectively, thus generating a sine wave in the secondary winding of the transformer 105, which in turn drives the ultrasonic transducer 106 to generate ultrasonic waves. The frequency of the ultrasonic waves is the same as the frequency of the sine wave generated by the secondary winding of the transformer 105. When the fourth enable signal cur_en is low (i.e., the fourth enable signal cur_en is 0), the first enable signal sw1_en and the second enable signal sw2_en also simultaneously become low (i.e., 0). At this time, the secondary winding of transformer 105 stops generating sine waves, and the ultrasonic transducer 106 continues to generate aftershocks due to inertia, with the amplitude gradually decaying to 0; the waveform of the ultrasonic wave during this process is as follows: Figure 4 As shown in ring (TP1), it is divided into two stages: ultrasonic initiation and ultrasonic aftershock.

[0079] After the ultrasonic initiation phase is completed, the aftershocks are processed and measured during the ultrasonic aftershock phase. Specifically, the main control module 204 in the self-test control module 30 generates a third enable signal smit_en. The ultrasonic signal TP1, after passing through the DC blocking capacitor 107, is sent to the Schmitt trigger 108 for shaping, generating a signal such as... Figure 4The ring_in(TP2) square wave signal shown has the same frequency as the ultrasonic signal TP1. The aftershock acquisition module 201 in the main control module 204 acquires the square wave signal and counts it through the aftershock counting module 202. The aftershock counting result is recorded as ring_cnt[3:0]. When ring_cnt[3:0] = 2 (of course, in other examples it can be other values ​​besides 2, such as 4, 6, or 8, etc.), the diagnostic counting module 203 is activated to count, and the diagnostic counting result is recorded as diag_cnt[7:0]. The counting clock of diag_cnt[7:0] is the self-test clock signal diag_clk, whose clock frequency is the first... The switching frequency of the enable signal sw1_en and the second enable signal sw2_en is 32 times, i.e., 1.6MHz; when ring_cnt[3:0] = n (2 < n ≤ 15), ring_cnt[3:0] and diag_cnt[8:0] stop counting simultaneously. At this time, the value of diag_cnt[8:0] is m. Finally, the main control module 204 compares the values ​​of ring_cnt[3:0] and diag_cnt[8:0] on the falling edge of the third enable signal smit_en and generates a self-test alarm signal alarm, specifically:

[0080] When diag_cnt[8:5]>(n-2), alarm = 1;

[0081] When diag_cnt[8:5] = (n-2) and diag_cnt[4:0] > 25, alarm = 1;

[0082] When diag_cnt[8:5] = (n-3) and diag_cnt[4:0] < 6, alarm = 1;

[0083] When diag_cnt[8:5]<(n-3), alarm=1.

[0084] It should be noted that in the above example, ring_cnt[3:0] represents a 4-bit wide variable; diag_cnt[4:0] represents a 5-bit wide variable; diag_cnt[8:0] represents a 9-bit wide variable (0 to 8, a total of 9 bits); diag_cnt[8:5] represents truncating the high 4 bits (5 to 8, a total of 4 bits); and alarm=1 indicates that an alarm signal is generated to trigger an alarm.

[0085] In the description of this specification, the technical features of the above-described embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A self-test circuit for an ultrasonic transducer, characterized in that, include: Ultrasonic generation module, self-test control module, and waveform shaping module; The self-test control module is used to generate a first enable signal, a second enable signal, and a third enable signal based on the self-test enable signal and the self-test clock signal; The ultrasonic generation module includes an ultrasonic transducer and is connected to the self-test control module for generating ultrasonic waves based on the first enable signal and the second enable signal. The waveform shaping module is connected to the self-test control module and the ultrasonic wave generation module, and is used for... When the third enable signal is high, the ultrasonic signal is shaped to obtain a square wave signal; The self-test control module is also used to perform aftershock counting and diagnostic counting on the square wave signal. When the third enable signal is high, the aftershock counting result is compared with the diagnostic counting result, and an alarm signal is generated when the comparison result is abnormal. The self-test control module is further configured as follows: After the ultrasonic wave generation module stops generating ultrasonic waves, the waveform shaping module is restarted after a preset time delay. The diagnostic counting is initiated only after the aftershock count reaches a preset threshold. The alarm signal is generated based on whether the difference between the aftershock count result and the diagnostic count result exceeds the dynamic threshold range. The self-test control module includes: The first input terminal is used to receive the self-test enable signal; The second input terminal is used to receive the self-test clock signal; The third input terminal is used to receive the square wave signal; The first output terminal is connected to the ultrasonic generation module and is used to output the first enable signal to the ultrasonic generation module. The second output terminal is connected to the ultrasonic generation module and is used to output the second enable signal to the ultrasonic generation module. The third output terminal is connected to the waveform shaping module and is used to output the third enable signal to the waveform shaping module; The fourth output terminal is used to output the alarm signal; The self-test control module is also used to generate a fourth enable signal; the ultrasonic transducer self-test circuit also includes a constant current module, which is connected to the self-test control module and the ultrasonic generation module, and is used to provide constant current to the ultrasonic generation module under the control of the fourth enable signal.

2. The ultrasonic transducer self-test circuit as described in claim 1, characterized in that, The self-test control module also includes a fifth output terminal, which is connected to the constant current module and is used to output the fourth enable signal to the constant current module.

3. The ultrasonic transducer self-test circuit as described in claim 1, characterized in that, The constant current module includes: A DC power supply, wherein the negative terminal of the DC power supply is grounded; The constant current source includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the constant current source is connected to the positive terminal of the DC power supply, the second input terminal of the constant current source is connected to the self-test control module, and the output terminal of the constant current source is connected to the ultrasonic wave generating module.

4. The ultrasonic transducer self-test circuit as described in claim 1, characterized in that, The ultrasonic wave generation module includes: The first switch includes a first terminal, a second terminal, and a third terminal. The first terminal of the first switch is connected to the first output terminal of the self-test control module, and the third terminal of the first switch is grounded. The second switch includes a first terminal, a second terminal, and a third terminal. The first terminal of the second switch is connected to the second output terminal of the self-test control module, and the third terminal of the second switch is grounded. The transformer includes a main winding and a secondary winding, wherein the main winding is connected to the constant current module, the second terminal of the first switch and the second terminal of the second switch; An ultrasonic transducer is connected to the secondary winding and the waveform shaping module.

5. The ultrasonic transducer self-test circuit as described in claim 1, characterized in that, The waveform shaping module includes: An isolation capacitor includes a first terminal and a second terminal, wherein the first terminal of the isolation capacitor is connected to the ultrasonic wave generating module; A Schmitt trigger includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the Schmitt trigger is connected to the second terminal of the isolation capacitor, the second input terminal of the Schmitt trigger is connected to the third output terminal of the self-test control module, the third input terminal of the Schmitt trigger is connected to a reference voltage, and the output terminal of the Schmitt trigger is connected to the third input terminal of the self-test control module.

6. The ultrasonic transducer self-test circuit as described in any one of claims 1 to 5, characterized in that, The ultrasonic wave includes an ultrasonic initiation signal and an ultrasonic aftershock signal; the waveform shaping module is used to shape the ultrasonic aftershock signal to obtain the square wave signal when the third enable signal is high.

7. The ultrasonic transducer self-test circuit as described in claim 6, characterized in that, The self-test control module includes: An aftershock acquisition module is connected to the waveform shaping module and the self-test clock signal, and is used to acquire the square wave signal based on the self-test clock signal; An aftershock counting module is connected to the aftershock acquisition module and the self-test clock signal, and is used to count aftershocks on the square wave signal based on the self-test clock signal; A diagnostic counting module, connected to the self-test clock signal, is used to perform diagnostic counting after the aftershock counting module has counted for a preset time. The main control module is connected to the self-test enable signal, the self-test clock signal, the aftershock counting module, and the diagnostic counting module. It is used to generate the first enable signal, the second enable signal, and the third enable signal based on the self-test enable signal and the self-test clock signal. When the third enable signal is high, it compares the aftershock counting result with the diagnostic counting result and generates an alarm signal when the comparison result is abnormal.

8. The ultrasonic transducer self-test circuit as described in claim 7, characterized in that, The main control module includes: The frequency divider includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the first input terminal of the frequency divider is connected to the self-test enable signal, and the second input terminal of the frequency divider is connected to the self-test clock signal; the frequency divider is used to generate a frequency-divided signal based on the self-test enable signal and the self-test clock signal. A control counter, the input of which is connected to the second output of the frequency divider, is used to control and count the frequency division signal; The first comparator is connected to the output of the control counter and is used to compare the result of the control count with a first preset value, and output a comparison signal when the result of the control count reaches the first preset value. The first AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the first AND gate is connected to the output terminal of the first comparator, and the second input terminal of the first AND gate is connected to the self-test enable signal; the first AND gate is used to perform AND logic processing on the self-test enable signal and the comparison signal to obtain the third enable signal. A first inverter, the input of which is connected to the output of the first comparator, is used to invert the comparison signal to obtain an inverted comparison signal; The second AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the second AND gate is connected to the self-test enable signal, and the second input terminal of the second AND gate is connected to the output terminal of the first inverter. The second AND gate is used to perform AND logic processing on the self-test enable signal and the inverse comparison signal to obtain a fourth enable signal. The third AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the third AND gate is connected to the output terminal of the second AND gate, and the second input terminal of the third AND gate is connected to the second output terminal of the frequency divider. The third AND gate is used to perform AND logic processing on the fourth enable signal and the frequency divider signal to obtain the first enable signal. The second inverter, whose input is connected to the first output of the frequency divider, is used to reverse the frequency division signal to obtain an inverted frequency division signal. The fourth AND gate includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the fourth AND gate is connected to the output terminal of the second AND gate, and the second input terminal of the fourth AND gate is connected to the output terminal of the second inverter. The fourth AND gate is used to perform AND logic processing on the fourth enable signal and the inverted frequency divider signal to obtain the second enable signal. The second comparator includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; the first input terminal of the second comparator is connected to the diagnostic counting module, the second input terminal of the second comparator is connected to the aftershock counting module, and the third input terminal of the second comparator is connected to the output terminal of the first AND gate; the second comparator is used to compare the aftershock counting result with the diagnostic counting result when the third enable signal is high, and generate an alarm signal when the comparison result is abnormal.

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