Redundant array management technology

Abstract

This application relates to redundant array management technology. A memory system may include volatile memory devices, non-volatile memory devices, and one or more independent node redundant arrays. The memory system may include a first redundant array controller and a second redundant array controller for the independent node redundant arrays. The memory system can receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system can use one or both of the first and second redundant array controllers to generate parity data corresponding to the data. In some instances, the first redundant array controller may be configured to generate parity data associated with a first type of fault, and the second redundant array controller may be configured to generate parity data associated with a second type of fault.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 648,395, entitled "Redundant Array Management Technologies," filed January 19, 2022, by Yeung et al.; and priority to U.S. Provisional Patent Application No. 63 / 162,141, entitled "Redundant Array Management Technologies," filed March 17, 2021, by Yeung et al., each of which is assigned to the assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves redundant array management technology. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power supply, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even without an external power supply. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a volatile memory device; a non-volatile memory device; a first redundant array controller for an independent node redundant array associated with the non-volatile memory device; a second redundant array controller for the independent node redundant array; and a controller coupled to the volatile memory device, the non-volatile memory device, the first redundant array controller, and the second redundant array controller, the controller being configured such that the apparatus: receives a first write command associated with writing first data to a memory cell of a first type; generates first parity data corresponding to the first data using the first redundant array controller; receives a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and generates second parity data corresponding to the second data using the second redundant array controller, which is different from the first redundant array controller.

[0007] Another device is described. The device may include: a non-volatile memory device; a volatile memory device coupled to and configured to store information associated with operating the non-volatile memory device; a first redundant array controller coupled to the volatile memory device and configured to generate first parity data to correct errors associated with a first type of fault, the first type of fault being associated with accessing data in the non-volatile memory device; and a second redundant array controller coupled to the volatile memory device and configured to generate second parity data to correct errors associated with a second type of fault, the second type of fault being associated with accessing data in the non-volatile memory device.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first write command associated with writing first data to a memory cell of a first type; generate first parity data corresponding to the first data using a first redundant array controller of an independent node redundant array associated with a non-volatile memory device; receive a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and generate second parity data corresponding to the second data using a second redundant array controller of the independent node redundant array, different from the first redundant array controller. Attached Figure Description

[0009] Figure 1 and 2An example of a system supporting redundant array management technology is shown, based on examples disclosed herein.

[0010] Figure 3 An example of a process flow supporting redundant array management technology is shown, based on examples disclosed herein.

[0011] Figure 4 A block diagram of a memory system supporting redundant array management technology is shown, based on examples disclosed herein.

[0012] Figure 5 A flowchart illustrating one or more methods for supporting redundant array management techniques based on examples disclosed herein is shown. Detailed Implementation

[0013] Memory systems can implement various redundancy techniques to prevent various failures. For example, a memory system can implement a Redundant Array of Independent Nodes (RAIN) scheme (e.g., a Redundant Array of Independent Devices (RAID) scheme), in which data is partitioned and / or replicated among multiple memory devices of the memory system. A RAIN scheme may include striping and / or mirroring the data among two or more memory devices. For example, striping may involve separating the data so that different portions of the data are stored on different memory devices, where the different portions of the separated data are collectively referred to as stripes. Mirroring may involve redundantly storing duplicate copies of the data in at least two memory devices. Additionally, the memory system can generate error information, such as parity data, and store it in the same and / or different memory devices storing the data. Therefore, if any memory device fails, or if at least a portion of the data is lost (e.g., due to some failure of the memory system), the memory system can use the parity data, along with the striped and / or mirrored data, to recover the lost data (e.g., using an XOR circuit system).

[0014] The memory system may include a redundant array controller (e.g., a RAIN engine) for implementing the RAIN scheme. In other operations, the redundant array controller may generate parity data corresponding to data stored between two or more non-volatile memory devices in the memory system. However, generating and storing parity data may increase the latency associated with writing data to the non-volatile memory devices. For example, due to the storage capacity limitations of the volatile memory devices in the memory system, parity data may be written to the non-volatile memory devices while it is being generated (e.g., writing data to the non-volatile memory devices simultaneously). Because volatile memory devices may be associated with faster access operations compared to non-volatile memory devices, writing parity data to the non-volatile memory devices may increase the latency of writing data. Furthermore, in some cases, multiple types of parity data may be generated based on the type of memory cell to which the data is written. Therefore, in some cases, the redundant array controller may generate a first type of parity data and then generate a second type of parity data, thereby increasing the latency of generating parity data.

[0015] This document describes techniques, systems, and apparatus for improving system performance, increasing memory utilization, and reducing latency associated with implementing a RAIN scheme by including multiple redundant array controllers in a memory system, each dedicated to generating a specific type of parity data. For example, the memory system may include a first redundant array controller configured to generate first parity data that can be used to correct errors associated with a first type of fault in the memory system. Alternatively, the memory system may include a second redundant array controller configured to independently generate second parity data that can be used to correct errors associated with a second type of fault in the memory system. The memory system may be configured to generate the first parity data, the second parity data, or both based on the operation performed, the data type accessed, or the type of memory cell accessed. The first parity data, the second parity data, or both may be generated using the appropriate redundant array controller in response to receiving a write command. By using different controllers, some parity information determination can be parallelized, or in some cases, some parity information may not be generated. For example, a memory system may receive a write command to write data to a specific type of memory cell. Based on the type of memory cell, the memory system may select and then generate first parity data, second parity data, or both. In some instances, a first redundant array controller and a second redundant array controller may generate the first and second parity data in parallel, thereby reducing the latency associated with generating parity data corresponding to the data. Additionally, the memory system may dynamically allocate portions of volatile memory devices to store information associated with the first parity data, the second parity data, or both. Therefore, the memory system may store the first parity data, the second parity data, or both in volatile memory devices while simultaneously writing data to one or more non-volatile memory devices (e.g., until after the data is written), thereby reducing the latency associated with writing data and improving the memory utilization of the volatile memory devices. In addition, by dynamically allocating (or deallocating) portions of the volatile memory device to RAIN operations, the memory system can determine the space range within the volatile memory device to perform specific operations and increase the amount of space used in the volatile memory device.

[0016] Firstly, in reference Figures 1 to 2 The features of this disclosure are described within the context of the system being described. (Referencing...) Figure 3 The features of this disclosure are described in the context of the process flow. These and other features of this disclosure are described by reference. Figures 4 to 5 The context of the device diagrams and flowcharts involving redundant array management technology is further illustrated and described.

[0017] Figure 1 An example of a system 100 supporting redundant array management technology, as disclosed herein, is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0019] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0020] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to examples described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more cache memories (e.g., memory native to host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may (e.g., in response to or otherwise in conjunction with commands from the host system 105) exchange data with the host system 105 and one or more memory devices 130. For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0024] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache memory for the memory system controller 115. For example, if data is read from or written to memory device 130, data may be stored in local memory 120 and may be available within local memory 120 for subsequent retrieval or operation (e.g., update) by the host system 105 according to a caching strategy (e.g., reduced latency relative to memory device 130).

[0027] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to each store two bits of information, it may be referred to as a multi-level cell (MLC), if configured to each store three bits of information, it may be referred to as a three-level cell (TLC), if configured to each store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Compared to SLC memory cells, multi-level memory cells can provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0032] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more limitations, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but can be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they are rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0035] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages 175 of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data retained in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such as due to latency or wear considerations, this copying and remapping may be performed instead of erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0036] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data because the latest or newest version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing both valid and invalid data, selecting pages 175 in block 170 containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0038] In some instances, memory system 110 may implement a RAIN scheme in which data is striped and / or mirrored between two or more memory devices 130. For example, in response to receiving a write command to write data, memory system controller 115 (e.g., or local controller 135) may divide the data into multiple parts and may store different parts of the data on different memory devices 130. Alternatively, memory system controller 115 may store duplicate copies of the data on different memory devices 130. Memory system 110 may include one or more redundant array controllers (e.g., included in or coupled to memory system controller 115) configured to generate parity data corresponding to the data, which can be used to recover data in the event of loss of any part of the data due to a failure of components of memory system 110 (e.g., using an XOR circuit system). Some examples of failures may include multiplane failures and word line failures, as well as other failures. Multiplane failures may correspond to errors in word lines in two or more planes 165 of the memory die 160 of memory device 130. In some instances, multi-plane faults may be caused by a failure of the charge pump associated with a word line, increased latency in one or more planes 165, or other reasons. A word line fault may correspond to an error in one or more word lines of planes 165 in the memory die 160 of the memory device 130.

[0039] To improve performance associated with implementing the RAIN scheme, the memory system 110 may include two redundant array controllers, each configured to generate a specific type of parity data. For example, the memory system 110 may include a first redundant array controller configured to generate first parity data, which can be used to correct errors associated with multiplane faults (e.g., fault type). Additionally, the memory system 110 may include a second redundant array controller configured to independently generate second parity data, which can be used to correct errors associated with word line faults (e.g., fault type). In response to receiving a write command, one or both of the first and second redundant array controllers may generate corresponding parity data. For example, the memory system 110 may receive a write command to write data to a specific type of memory cell. If data is written to a memory cell configured to store two or more data bits (e.g., MLC, TLC, QLC), the first redundant array controller may generate the first parity data and the second redundant array controller may generate the second parity data (e.g., in parallel with the first redundant array controller). Alternatively, if data is written to a memory cell configured to store one data bit (e.g., SLC), the second redundant array controller can generate second parity data. Additionally, the memory system 110 can dynamically allocate a portion of local memory 120 to store either the first parity data or the second parity data, or both. Therefore, the memory system 110 can store either the first parity data or the second parity data, or both, in local memory 120 while simultaneously writing data to one or more memory devices 130 (e.g., until after the data is written), thereby reducing latency associated with writing data and improving memory utilization of the memory system 110.

[0040] System 100 may include any number of non-transitory computer-readable media supporting redundant array management techniques. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0041] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is an MNAND system.

[0042] Figure 2 An example of a system 200 supporting redundant array management technology, as disclosed herein, is shown. System 200 may be as described in the references... Figure 1 An example of system 100 as described in the preceding description. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented as described in the reference. Figure 1 Aspects of the system 100 described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0043] Memory system 210 may include non-volatile memory devices 235 (e.g., non-volatile memory devices 235-a and 235-b) for storing data transferred between memory system 210 and host system 205, as described herein, for example, in response to receiving an access command from host system 205. Non-volatile memory devices 235 may be instances of memory device 130 containing non-volatile memory cells, NAND devices, or some other type of non-volatile memory device. Furthermore, non-volatile memory devices 235 may contain different types of memory cells. For example, non-volatile memory device 235-a may contain a first type of memory cell configured to store two or more data bits (e.g., TLC, MLC, QLC), and non-volatile memory device 235-b may contain a second type of memory cell configured to store one data bit (e.g., SLC).

[0044] The memory system 210 may additionally include an interface 220 for communicating with the host system 205. Interface 220 may be an instance of a physical host interface for transferring data between the host system 205 and the memory system 210. If the host system 205 issues an access command to the memory system 210, the interface 220 may receive the command, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). Therefore, the interface 220 can be considered as a front end of the memory system 210.

[0045] The memory system 210 may additionally include a controller 215 for executing commands received from the host system 205 and controlling the movement of data throughout the memory system 210. The controller 215 may be a reference... Figure 1 Examples of memory system controller 115 or local controller 135 described herein. Upon receiving each access command, interface 220 may, for example, transmit the command to controller 215 contained in memory system 210 via a bus.

[0046] Controller 215 may include a volatile memory device 225 for executing commands received from host system 205. Volatile memory device 225 may be an instance of local memory 120, a memory device 130 containing volatile memory cells, an SRAM device, or any other type of volatile memory device. In some instances, volatile memory device 225 may be associated with faster access and operation speeds compared to non-volatile memory device 235, and non-volatile memory device 235 may be associated with larger storage capacity compared to volatile memory device 225. Therefore, if an operation is performed on data, controller 215 may transfer data (e.g., from non-volatile memory device 235) to volatile memory device 225 and then perform the operation on the data. For example, to update the L2P mapping table, controller 215 can transfer a portion of the L2P mapping table to be updated from non-volatile memory device 235 to volatile memory device 225, update said portion of the L2P mapping table, and transfer said portion of the L2P mapping table back to non-volatile memory device 235. Additionally, in some instances, volatile memory device 225 can be used as a buffer for temporarily storing data transferred throughout memory system 210. For example, volatile memory device 225 can be divided into multiple portions, each associated with storing different types of data. For example, volatile memory device 225 may include at least a write data portion 240 associated with storing write data received from host system 205, a read data portion 245 associated with storing data read from non-volatile memory device 235, and an L2P portion 250 associated with storing the portion of the L2P mapping table. Therefore, the volatile memory device 225 can store the write data received from the host system 205 in the write data section 240, and then write the data to one or more corresponding non-volatile memory devices 235; it can store the read data in the read data section 245, and then transmit the data to the host system 205; and it can store a portion of the L2P mapping table in the L2P section 250 when updating the L2P mapping table.

[0047] The memory system 210 may implement a RAIN scheme using one or more redundant array controllers 230. The RAIN scheme can be implemented to prevent failures of one or more components of the memory system 210 (e.g., multiplane failure, word line failure, or other failures of the memory system 210). For example, in response to receiving a write command to write data to one or more non-volatile memory devices 235, the controller 215 may stripe and / or mirror the data among the multiple non-volatile memory devices 235. Here, portions of the non-volatile memory devices 235 may be configured to store redundant data and may be referred to as redundant nodes, redundant devices, or redundant NAND. Additionally, in some cases, the redundant array controller 230 may generate parity data corresponding to the data, which the controller 215 may use to recover the data if at least a portion of the data is lost or corrupted due to a failure in the memory system 210.

[0048] In some cases, the memory system 210 may implement a RAIN scheme using a single redundant array controller 230. However, using a single redundant array controller 230 may degrade system performance and increase latency. For example, if data is written to a second type of memory cell (e.g., TLC, MLC, QLC), the redundant array controller 230 may generate first parity data to correct errors associated with multiplane faults, and then generate second parity data to correct errors associated with word line faults (e.g., vice versa), thereby increasing the latency associated with generating the first or second parity data. Additionally, in some cases, in addition to the write data section 240, read data section 245, and L2P section 250, the volatile memory device 225 may also include a first parity section 255 for storing the first parity data and a second parity section 260 for storing the second parity data. However, in some cases, the size of each section of the volatile memory device 225 may be static or fixed. Therefore, in some instances, the first parity section 255 and the second parity section 260 may have limited storage capacity insufficient to store the first parity data and the second parity data. Consequently, the controller 215 may write the first parity data and the second parity data to the corresponding non-volatile memory device 235 as the first parity data and the second parity data are generated (e.g., write data simultaneously), which may increase the latency associated with writing the data.

[0049] To improve performance associated with implementing the RAIN scheme, memory system 210 may include two redundant array controllers 230, each configured to generate a specific type of parity data. For example, controller 215 may include or be coupled to a redundant array controller 230-a configured to generate parity data 265 and a redundant array controller 230-b configured to generate parity data 270. In some instances, parity data 265 can be used to correct multiplane errors, and parity data 270 can be used to correct word line errors.

[0050] Redundant array controllers 230-a and 230-b can generate corresponding parity data based on the type of memory cell to which data will be written, and can manage other aspects related to the generation of the corresponding parity data. Redundant array controllers 230-a and 230-b can be instances of a RAIN engine. In some cases, redundant array controllers 230-a and 230-b can be implemented using hardware, firmware, software, or any combination thereof. In some instances, controller 215 can receive write commands from host system 205 associated with writing data to a first type of memory cell (e.g., to a TLC, MLC, or QLC contained in non-volatile memory device 235-a) or to a second type of memory cell (e.g., to an SLC contained in non-volatile memory device 235-b), and the controller can temporarily store the data in the write data portion 240. In some instances, data written to the first type of memory cell may be susceptible to both multiplane errors and word line errors. Therefore, if a write command includes writing data to a first type of memory cell, redundant array controller 230-a can generate parity data 265 and redundant array controller 230-b can generate parity data 270. In some instances, redundant array controller 230-a and redundant array controller 230-b can generate parity data 265 and parity data 270 in parallel, respectively, thereby reducing the latency associated with generating parity data corresponding to said data. Alternatively, in some instances, data written to a second type of memory cell may be susceptible to word line errors but may be less susceptible to multiplane errors. Therefore, if a write command includes writing data to a second type of memory cell, redundant array controller 230-b can generate parity data 270 and redundant array controller 230-a can avoid generating parity data 265.

[0051] Redundant array controller 230-a can store parity data 265 in volatile memory device 225, and redundant array controller 230-b can store parity data 270 in volatile memory device 225. For example, redundant array controller 230-a can send parity data 265 to volatile memory device 225, and volatile memory device 225 can store parity data 265 in a first parity section 255. Additionally, redundant array controller 230-b can send parity data 270 to volatile memory device 225, and volatile memory device 225 can store parity data 270 in a second parity section 260.

[0052] To increase the amount of parity data 265 or parity data 270 (or both) that can be stored in volatile memory device 225 (e.g., to enable the storage of parity data 265, parity data 270, or a combination thereof in volatile memory device 225), controller 215 can dynamically allocate portions of volatile memory device 225 (e.g., write data portion 240, read data portion 245, L2P portion 250, first parity portion 255, second parity portion 260). For example, in response to receiving a write command, controller 215 can allocate at least a portion of read data portion 245 or L2P portion 250, or both, to write data portion 240, first parity portion 255, second parity portion 260, or a combination thereof. Therefore, controller 215 can accommodate additional write data, parity data 265, parity data 270, or a combination thereof in volatile memory device 225. In some instances, controller 215 may allocate portions of volatile memory device 225 based on the type of parity data to be generated. For example, if redundant array controller 230-a does not (e.g., in response to writing data to a second type of memory cell) generate parity data 265, controller 215 may allocate at least a portion of the first parity portion 255 to one or more other portions of volatile memory device 225 (e.g., to write data portion 240, to the second parity portion 260). For example, controller 215 may allocate at least a portion of the first parity portion 255 to cache data to be written to the second type of memory cell, thereby increasing the amount of data that can be written to the corresponding non-volatile memory device 235 and reducing latency associated with write operations. Since space in the volatile memory device 225 (e.g., SRAM) of memory system 210 may be limited, memory system 210 may be configured to dynamically allocate space in volatile memory device 225 based on a list of currently executed operations, including dynamically allocating space for RAIN operations.

[0053] Additionally, controller 215 can allocate portions of volatile memory device 225 based on various parameters. For example, controller 215 can receive a read command from host system 205. In response to receiving a read command, controller 215 can allocate one or more portions of volatile memory device 225 (e.g., write data portion 240, L2P portion 250, first parity portion 255, second parity portion 260, or a combination thereof) to read data portion 245. In this way, controller 215 can increase the amount of read data that can be stored in volatile memory device 225, thereby reducing the latency associated with read operations.

[0054] Alternatively, controller 215 may allocate portions of volatile memory device 225 based on the power state of volatile memory device 225, the number of received write commands, the number of received read commands, the amount of parity data 265 stored or to be stored in volatile memory device 225, the amount of parity data 270 stored or to be stored in volatile memory device 225, or combinations thereof. For example, based on the number of received read commands or write commands, controller 215 may allocate portions of volatile memory device 225 to accommodate the storage of read data, write data, L2P table mapping portions, parity data 265, parity data 270, or combinations thereof associated with read commands, write commands, or combinations thereof.

[0055] Based on the allocation of volatile memory device 225, controller 215 can avoid writing parity data 265 and parity data 270 to the corresponding non-volatile memory device 235 when writing data to the corresponding non-volatile memory device 235. For example, controller 215 may store parity data 265 in volatile memory device 225 until the data corresponding to parity data 265 is written to a page of non-volatile memory device 235-a (e.g., to a page of a first type of memory cell). After the data is written to the page, controller 215 may store parity data 265 in one or more non-volatile memory devices 235-a, which may or may not include non-volatile memory devices 235-a. Alternatively, controller 215 may store parity data 270 in volatile memory device 225 until a threshold number of pages storing the data corresponding to parity data 270 are valid. After storing valid data in a threshold number of pages of the block, the controller 215 may store parity data 270 in one or more non-volatile memory devices 235.

[0056] In some instances, the redundant array controller 230-a and the redundant array controller 230-a may be coupled to one or more non-volatile memory devices 235 and may send corresponding parity data to one or more non-volatile memory devices 235.

[0057] Figure 3 An example of a process flow 300 supporting redundant array management technology according to examples disclosed herein is shown. Process flow 300 may be provided by a memory system (e.g., reference...) Figure 1 and 2 The process flow 300 may be executed by components of the memory system 110 or memory system 210 described herein. For example, the process flow 300 may be executed by a controller of the memory system or memory device (or both) and one or more redundant array controllers. The controller may be as described in the reference... Figure 1 and 2 Examples of the described memory system controller 115, local controller 135, or controller 215. The one or more redundant array controllers may be as described in the references... Figure 2 An example of the described redundant array controller 230. Process flow 300 can depict a process for generating parity data using one or more redundant array controllers in response to receiving a write command at the controller, and the process can be implemented to improve memory utilization, reduce latency and improve redundant operation performance, and other benefits.

[0058] Various aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system controller 115, local controller 135, and / or redundant array controller 230). For example, when executed by a controller (e.g., memory system controller 115, local controller 135, redundant array controller 230), the instructions may cause the controller to perform the operation of process flow 300.

[0059] In the following description of process flow 300, operations may be performed in different orders or at different times. Some operations may be omitted from process flow 300, or other operations may be added to process flow 300. In addition, the controller may receive multiple write commands and may execute different operations of process flow 300 based on the write commands described below.

[0060] At 305, a write command can be received. For example, the controller can receive a write command from a host system coupled to the controller, the write command being associated with writing data to a type of memory cell (e.g., containing data to be written to one or more memory cells of a specific type). For example, the memory system may include one or more non-volatile memory devices having memory cells of a first type configured to store two or more data bits. Alternatively, the memory system may include one or more other non-volatile memory devices having memory cells of a second type configured to store one data bit.

[0061] At 310, the type of memory cell to which the data to be written can be evaluated. For example, the controller can determine whether a write command is associated with writing data to a first type of memory cell or to a second type of memory cell.

[0062] If at 310 the controller determines that a write command is associated with writing data to a memory cell of the first type, then the controller, the first redundant array controller and the second redundant array controller may execute 315 to 345 as follows.

[0063] At 315, first parity data may be generated in response to receiving a write command. For example, data written to a first type of memory cell may be susceptible to a first type of fault (e.g., multiplane error) associated with accessing data in a non-volatile memory device. The first redundant array controller may generate the first parity data to correct errors associated with the first type of fault.

[0064] At 320, second parity data may be generated in response to receiving a write command. For example, data written to a first-type memory cell may be additionally susceptible to a second type of fault (e.g., word line error) associated with accessing data in a non-volatile memory device. The second redundant array controller may generate second parity data to correct errors associated with the second type of fault.

[0065] At point 325, the first parity data and the second parity data can be stored in the volatile memory device of the memory system. For example, a first redundant array controller can send the first parity data to the volatile memory device, and a second redundant array controller can send the second parity data to the volatile memory device. In some instances, to enable the storage of the first parity data and the second parity data, the volatile memory device can allocate one or more portions of the volatile memory device for storing write data, read data, or allocate portions of the L2P mapping table to store the first parity data, the second parity data, or a combination thereof.

[0066] At point 330, data can be written to a page of a memory cell in a memory cell of the first type. For example, the controller can write data to a page of a first non-volatile memory device having memory cells of the first type.

[0067] At position 335, the first parity data can be stored in the second non-volatile memory device. For example, the controller can first write the first parity data to the second non-volatile memory device, and then the controller writes the first parity data to a page. That is, the controller can store the first parity data in the volatile memory device until the controller writes the data to a page. In some instances, the second non-volatile memory device can be the first non-volatile memory device. In some other instances, the second non-volatile memory device is different from the first non-volatile memory device.

[0068] At 340, a threshold number of pages within a block storing data can be determined to store valid data. For example, the controller can determine the number of pages storing valid data within the block and whether the number of pages satisfies (e.g., greater than, greater than, or equal to) a threshold number of pages. In some instances, the threshold number of pages may be the number of pages contained within the block.

[0069] At position 345, the second parity data may be stored in a third non-volatile memory device. For example, if the controller determines that the number of pages storing valid data in the block meets a page threshold, the controller may store the second parity data in the third non-volatile memory device. That is, in some instances, the controller may store the second parity data in the volatile memory device until the number of pages storing valid data in the block meets the page threshold. In some instances, the third non-volatile memory device may contain the block. In some other instances, the third non-volatile memory device may not contain the block.

[0070] If at 310, the controller determines that the write command is associated with writing data to a second type of memory cell, then the controller and the first redundant array controller may execute 350 to 365 as follows.

[0071] At 350, parity data can be generated in response to a received write command. For example, data written to a second type of memory cell may be susceptible to second type faults (e.g., word line errors) but may be less susceptible to first type faults. Therefore, the second redundant array controller can generate parity data to correct errors associated with second type faults. The first redundant array controller can avoid generating parity data.

[0072] At position 355, parity data can be stored in a volatile memory device. For example, a second redundant array controller can send the second parity data to the volatile memory device. In some instances, to enable the storage of the second parity data, the volatile memory device can allocate one or more portions of the volatile memory device for storing write data, read data, or allocate a portion of the L2P mapping table to store the second parity data.

[0073] At 360, a threshold number of pages within a block of stored data can be determined to store valid data. For example, the controller can write data to pages within the block, which is contained in a first non-volatile memory device. The controller can determine the number of pages in the block that store valid data and whether the number of pages satisfies (e.g., greater than, greater than, or equal to) the threshold number of pages.

[0074] At position 365, parity data can be stored in a second non-volatile memory device. For example, if the controller determines that the number of pages storing valid data in the block meets a page threshold, the controller can store the parity data in the second non-volatile memory device. That is, in some instances, the controller can store parity data in volatile memory devices until the number of pages storing valid data in the block meets the page threshold. In some instances, the second non-volatile memory device may be the first non-volatile memory device. In some other instances, the second non-volatile memory device is different from the first non-volatile memory device.

[0075] Figure 4 A block diagram 400 of a memory system 420 supporting redundant array management technology according to an example disclosed herein is shown. The memory system 420 may be as described in the references... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing various aspects of the redundant array management techniques described herein. For example, memory system 420 may include command component 425, first redundancy component 430, second redundancy component 435, parity check component 440, storage component 445, threshold component 450, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0076] Command component 425 may be configured or otherwise supported to support means for receiving a first write command associated with writing first data to a memory cell of a first type. First redundancy component 430 may be configured or otherwise supported to support means for generating first parity data corresponding to the first data using a first redundant array controller of an independent node redundant array associated with a non-volatile memory device. In some instances, command component 425 may be configured or otherwise supported to support means for receiving a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell. Second redundancy component 435 may be configured or otherwise supported to support means for generating second parity data corresponding to the second data using a second redundant array controller of an independent node redundant array, different from the first redundant array controller.

[0077] In some instances, a first redundant array controller is configured to generate first parity data to correct errors associated with a first type of fault, which is related to accessing data in a non-volatile memory device. In some instances, a second redundant array controller is configured to generate second parity data to correct errors associated with a second type of fault, which is also related to accessing data in a non-volatile memory device.

[0078] In some instances, the second redundancy component 435 may be configured or otherwise supported to generate third parity data corresponding to the first data using the second redundancy array controller, the third parity data being used to correct errors associated with a second type of fault.

[0079] In some instances, a Type 1 fault corresponds to a first error in word lines on two or more planes of a memory die in a non-volatile memory device. In some instances, a Type 2 fault corresponds to a second error in one or more word lines on a plane of a memory die.

[0080] In some instances, the parity check component 440 may be configured or otherwise support a component for storing first parity check data in a volatile memory device coupled to a first redundant array controller and a second redundant array controller until the first data is written to a page of a memory cell containing a memory cell of the first type.

[0081] In some instances, the parity component 440 may be configured or otherwise supported for storing the first parity data in a non-volatile memory device after the first data has been written to a page.

[0082] In some instances, the parity check component 440 may be configured or otherwise supported for storing the second parity check data in a volatile memory device coupled to the first and second redundant array controllers.

[0083] In some instances, the threshold component 450 may be configured or otherwise supported to determine that the number of pages storing valid data in a block meets a threshold, at least a portion of the block storing second data. In some instances, the parity component 440 may be configured or otherwise supported to store second parity data in a non-volatile memory device, at least in part based on the determination.

[0084] In some instances, storage component 445 may be configured or otherwise support a component for allocating a portion of the volatile memory device associated with storing first parity data or storing data associated with mapping logical addresses to physical addresses in response to receiving a read command.

[0085] In some instances, storage component 445 may be configured or otherwise support a component for allocating a portion of the volatile memory device to cache the second data in response to receiving a second write command for writing the second data to a memory cell of the second type, said portion of the volatile memory device being associated with storage parity data corresponding to writing the data to the memory cell of the first type.

[0086] In some instances, storage component 445 may be configured or otherwise support a component for allocating a first portion of the volatile memory device to store first parity data, allocating a second portion of the volatile memory device to store second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

[0087] In some instances, the first type of memory cell is configured to store two or more data bits. In some instances, the second type of memory cell is configured to store one data bit.

[0088] In some instances, the first parity data is associated with a multiplane error, and the second parity data is associated with a word line error.

[0089] Figure 5A flowchart illustrating a method 500 supporting redundant array management techniques according to an example disclosed herein is shown. The operation of method 500 can be implemented by a memory system or its components as described herein. For example, the operation of method 500 can be implemented by, as referenced... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0090] At point 505, the method may include receiving a first write command associated with writing first data to a memory cell of a first type. The operation at point 505 can be performed according to examples disclosed herein. In some instances, it can be performed by, as referenced... Figure 4 The command component 425 described performs various aspects of the operation of 505.

[0091] At 510, the method may include generating first parity data corresponding to the first data using a first redundant array controller of an independent node redundant array associated with a non-volatile memory device. The operation of 510 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 510 may be as described in references... Figure 4 The first redundant component 430 described is executed.

[0092] At point 515, the method may include receiving a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell. The operation at 515 can be performed according to examples disclosed herein. In some instances, it can be performed by, as referenced... Figure 4 The command component 425 described performs various aspects of the operation of 515.

[0093] At point 520, the method may include generating second parity data corresponding to the second data using a second redundant array controller, different from the first redundant array controller, employing an independent node redundant array. The operation at 520 can be performed according to examples disclosed herein. In some instances, aspects of the operation at 520 may be derived from references... Figure 4 The described second redundant component 435 is executed.

[0094] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuit logic components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a first write command associated with writing first data to a memory cell of a first type; generating first parity data corresponding to the first data using a first redundant array controller of an independent node redundant array associated with a non-volatile memory device; receiving a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and generating second parity data corresponding to the second data using a second redundant array controller of an independent node redundant array, different from the first redundant array controller.

[0095] In some instances of the method 500 and apparatus described herein, a first redundant array controller may be configured to generate first parity data to correct errors associated with a first type of fault, which may be associated with access to data in a non-volatile memory device, and a second redundant array controller may be configured to generate second parity data to correct errors associated with a second type of fault, which may be associated with access to data in a non-volatile memory device.

[0096] Some examples of the method 500 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for generating third parity data corresponding to the first data using a second redundant array controller, the third parity data being used to correct errors associated with a second type of fault.

[0097] In some instances of the method 500 and apparatus described herein, a first type of fault corresponds to a first error in word lines in two or more planes of a memory die of a non-volatile memory device, and a second type of fault corresponds to a second error in one or more word lines of a plane of a memory die.

[0098] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing first parity data in a volatile memory device coupled to a first redundant array controller and a second redundant array controller until the first data is written to a page of a memory cell containing a memory cell of the first type.

[0099] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for storing first parity data in a non-volatile memory device after first data has been written to a page.

[0100] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for storing second parity data in a volatile memory device coupled to a first redundant array controller and a second redundant array controller.

[0101] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining that the number of pages storing valid data in a block satisfies a threshold, at least a portion of the block stores second data, and for storing the second parity data in a non-volatile memory device, at least in part based on the determination.

[0102] Some instances of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for allocating a portion of the volatile memory device associated with storing first parity data or storing data associated with mapping logical addresses to physical addresses in response to receiving a read command.

[0103] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for allocating a portion of a volatile memory device to cache second data in response to receiving a second write command for writing second data to a memory cell of a second type, said portion of the volatile memory device being associated with stored parity data corresponding to writing data to a memory cell of a first type.

[0104] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for allocating a first portion of the volatile memory device to store first parity data, allocating a second portion of the volatile memory device to store second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

[0105] In some instances of the method 500 and apparatus described herein, a first type of memory cell may be configured to store two or more data bits, and a second type of memory cell may be configured to store one data bit.

[0106] In some instances of the method 500 and apparatus described herein, the first parity data may be associated with a multiplane error, and the second parity data may be associated with a word line error.

[0107] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described can be combined.

[0108] An apparatus is described. The apparatus may include: a volatile memory device; a non-volatile memory device; a first redundant array controller for an independent node redundant array associated with the non-volatile memory device; a second redundant array controller for the independent node redundant array; and a controller coupled to the volatile memory device, the non-volatile memory device, the first redundant array controller, and the second redundant array controller, the controller being configured such that the apparatus: receives a first write command associated with writing first data to a memory cell of a first type; generates first parity data corresponding to the first data using the first redundant array controller; receives a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and generates second parity data corresponding to the second data using the second redundant array controller, which is different from the first redundant array controller.

[0109] In some instances of the device, a first redundant array controller may be configured to generate first parity data to correct errors associated with a first type of fault, which may be associated with accessing data in a non-volatile memory device, and a second redundant array controller may be configured to generate second parity data to correct errors associated with a second type of fault, which may be associated with accessing data in a non-volatile memory device.

[0110] In some instances of the device, the controller may be further configured such that the device uses a second redundant array controller to generate third parity data corresponding to the first data, the third parity data being used to correct errors associated with a second type of fault.

[0111] In some instances of the device, a first type of fault corresponds to a first error in word lines in two or more planes of a memory die in a non-volatile memory device, and a second type of fault corresponds to a second error in one or more word lines of a plane in a memory die.

[0112] In some instances of the device, the controller may be further configured such that the device stores the first parity data in a volatile memory device coupled to a first redundant array controller and a second redundant array controller until the first data can be written to a page of a memory cell containing a memory cell of the first type.

[0113] In some instances of the device, the controller may be further configured such that the device stores the first parity data in a non-volatile memory device after writing the first data to the page.

[0114] In some instances of the device, the controller may be further configured such that the device stores the second parity data in a volatile memory device coupled to the first and second redundant array controllers.

[0115] In some instances of the device, the controller may be further configured such that the device determines that the number of pages storing valid data in a block meets a threshold, at least a portion of the block stores second data, and at least in part stores the second parity data in a non-volatile memory device based on the determination.

[0116] In some instances of the device, the controller may be further configured such that the device, in response to receiving a read command, allocates a portion of the volatile memory device to store read data associated with storing first parity data or to store data associated with mapping logical addresses to physical addresses.

[0117] In some instances of the device, the controller may be further configured such that the device, in response to receiving a second write command for writing second data to a memory cell of the second type, allocates a portion of the volatile memory device to cache the second data, the portion of the volatile memory device being associated with storage parity data corresponding to writing data to a memory cell of the first type.

[0118] In some instances of the device, the controller may be further configured such that the device allocates a first portion of the volatile memory to store the first parity data, allocates a second portion of the volatile memory to store the second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

[0119] In some instances of the device, a first type of memory cell may be configured to store two or more data bits, and a second type of memory cell may be configured to store one data bit.

[0120] In some instances of the device, the first parity data may be associated with a multiplane error, and the second parity data may be associated with a word line error.

[0121] Another device is described. The device may include: a non-volatile memory device; a volatile memory device coupled to and configured to store information associated with operating the non-volatile memory device; a first redundant array controller coupled to the volatile memory device and configured to generate first parity data to correct errors associated with a first type of fault, the first type of fault being associated with accessing data in the non-volatile memory device; and a second redundant array controller coupled to the volatile memory device and configured to generate second parity data to correct errors associated with a second type of fault, the second type of fault being associated with accessing data in the non-volatile memory device.

[0122] In some instances of the device, a first redundant array controller may be further configured to generate first parity data in response to a first write command associated with writing first data to a memory cell of a first type in a non-volatile memory device, the first parity data corresponding to the first data, and a second redundant array controller may be further configured to generate second parity data in response to a second write command associated with writing second data to a memory cell of the first type and to a memory cell of a second type in a non-volatile memory device, different from the first type of memory cell, the second parity data corresponding to the second data.

[0123] In some instances of the device, the first redundant array controller may be further configured to store the first parity data in a volatile memory device until the first data can be written to a page of a memory cell containing a first type of memory cell in a non-volatile memory device.

[0124] In some instances of the device, the second redundant array controller may be further configured to store the second parity data in a volatile memory device until a threshold number of pages in the block storing the second data store valid data.

[0125] In some instances of the device, a first type of memory cell may be configured to store two or more data bits, and a second type of memory cell may be configured to store one data bit.

[0126] In some instances of the device, the volatile memory device may be configured to allocate a portion of the volatile memory device associated with storing first parity data to store read data or data associated with mapping logical addresses to physical addresses during a read operation.

[0127] In some instances of the device, the volatile memory device may be configured to allocate a portion of the volatile memory device to cache the first data during a write operation to write the first data to a memory cell of the second type, the portion of the volatile memory device being associated with storage parity data corresponding to writing the second data to a memory cell of the first type.

[0128] In some instances of the device, the volatile memory device may be configured to allocate a first portion of the volatile memory device to store the first parity data, allocate a second portion of the volatile memory device to store the second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

[0129] In some instances of the device, a first type of fault corresponds to a first error in word lines in two or more planes of a memory die in a non-volatile memory device, and a second type of fault corresponds to a second error in one or more word lines of a plane in a memory die.

[0130] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0131] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enable the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path or an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0132] The term "coupling" refers to a condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. If, for example, a component of a controller couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0133] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. If an open circuit exists between components, the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0134] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0135] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0136] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other conditions or actions.

[0137] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0138] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals can be connected to other electronic components via a conductive material, such as a metal. The source and drain can be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "off" or "deactivated."

[0139] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0140] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral but independent of the second reference numeral.

[0141] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that different parts of the functions are implemented in different physical locations.

[0142] For example, the various illustrative blocks and components described in connection with the disclosure herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0143] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Similarly, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0144] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, these are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0145] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: Volatile memory devices; Non-volatile memory devices; A first redundant array controller for an independent node redundant array associated with the non-volatile memory device; The second redundant array controller of the independent node redundant array; as well as A controller coupled to the volatile memory device, the non-volatile memory device, the first redundant array controller, and the second redundant array controller, the controller being configured such that the memory system: Receive a first write command associated with writing first data to a memory cell of a first type; The first parity check data corresponding to the first data is generated using the first redundant array controller, and the first parity check data is associated with the redundant array of the independent node recovery scheme. Receive a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and A second redundant array controller, different from the first redundant array controller, generates second parity data corresponding to the second data, which is associated with the redundant array of the independent node recovery scheme.

2. The memory system according to claim 1, wherein: The first redundant array controller is configured to generate the first parity data to correct errors associated with a first type of fault, which is associated with accessing data in the non-volatile memory device. and The second redundant array controller is configured to generate the second parity data to correct errors associated with a second type of fault, which is associated with accessing data in the non-volatile memory device.

3. The memory system of claim 2, wherein the controller is further configured such that the memory system: The second redundant array controller is used to generate third parity data corresponding to the first data, the third parity data being used to correct errors associated with the second type of fault.

4. The memory system according to claim 2, wherein: The first type of fault corresponds to a first error in a word line in two or more planes of the memory die of the non-volatile memory device; and The second type of fault corresponds to a second error in one or more word lines of a plane in the memory die.

5. The memory system of claim 1, wherein the controller is further configured such that the memory system: The first parity check data is stored in the volatile memory device coupled to the first redundant array controller and the second redundant array controller until the first data is written to a page of a memory cell that includes the first type of memory cell.

6. The memory system of claim 5, wherein the controller is further configured such that the memory system: After the first data is written to the page, the first parity data is stored in the non-volatile memory device.

7. The memory system of claim 1, wherein the controller is further configured such that the memory system: The second parity check data is stored in the volatile memory device coupled to the first redundant array controller and the second redundant array controller.

8. The memory system of claim 7, wherein the controller is further configured such that the memory system: The number of pages storing valid data in a block meets a threshold, and at least a portion of the block stores the second data; and The second parity check data is stored in the non-volatile memory device, at least in part based on the determination.

9. The memory system of claim 1, wherein the controller is further configured such that the memory system: In response to receiving a read command, the volatile memory device may allocate a portion of the data associated with storing the first parity data to store read data or to store data associated with mapping logical addresses to physical addresses.

10. The memory system of claim 1, wherein the controller is further configured such that the memory system: In response to receiving a second write command for writing the second data to a memory cell of the second type, a portion of the volatile memory device is allocated to cache the second data, the portion of the volatile memory device being associated with storage parity data corresponding to writing the data to the memory cell of the first type.

11. The memory system of claim 1, wherein the controller is further configured such that the memory system: The first portion of the volatile memory device is allocated to store the first parity data, and the second portion of the volatile memory device is allocated to store the second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

12. The memory system according to claim 1, wherein: The memory cells of the first type are configured to store two or more data bits; and The memory cell of the second type is configured to store one data bit.

13. The memory system of claim 1, wherein the first parity data is associated with a multiplane error and the second parity data is associated with a word line error.

14. A memory system comprising: Non-volatile memory devices; A volatile memory device coupled to the non-volatile memory device and configured to store information associated with operating the non-volatile memory device; A first redundant array controller is coupled to the volatile memory device and configured to generate first parity data to correct errors associated with a first type of fault, the first type of fault being associated with access to data in the non-volatile memory device, and the first parity data being associated with a redundant array of an independent node recovery scheme. as well as A second redundant array controller is coupled to the volatile memory device and configured to generate second parity data to correct errors associated with a second type of fault, which is associated with access to data in the non-volatile memory device. The second parity data is associated with the redundant array of the independent node recovery scheme.

15. The memory system according to claim 14, wherein: The first redundant array controller is further configured to generate the first parity data in response to a first write command associated with writing the first data to a memory cell of a first type of the non-volatile memory device, the first parity data corresponding to the first data; and The second redundant array controller is further configured to generate the second parity data in response to a second write command associated with writing the second data to a memory cell of a second type different from the first type of memory cell in the non-volatile memory device and to write the second data to the memory cell of the first type. The second parity data corresponds to the second data.

16. The memory system of claim 15, wherein the first redundant array controller is further configured to store the first parity data in the volatile memory device until the first data is written to a page of a memory cell comprising the first type of memory cell in the non-volatile memory device.

17. The memory system of claim 15, wherein the second redundant array controller is further configured to store the second parity data in the volatile memory device until a threshold number of pages in the block storing the second data store valid data.

18. The memory system according to claim 15, wherein: The memory cells of the first type are configured to store two or more data bits; and The memory cell of the second type is configured to store one data bit.

19. The memory system of claim 14, wherein the volatile memory device is configured to allocate a portion of the volatile memory device to store read data associated with storing the first parity data or to store data associated with mapping logical addresses to physical addresses.

20. The memory system of claim 14, wherein the volatile memory device is configured to allocate a portion of the volatile memory device to cache the first data during a write operation for writing the first data to a memory cell of the second type, the portion of the volatile memory device being associated with storage parity data corresponding to writing the second data to a memory cell of the first type.

21. The memory system of claim 14, wherein the volatile memory device is configured to allocate a first portion of the volatile memory device to store the first parity data, allocate a second portion of the volatile memory device to store the second parity data, or both, based at least in part on the power state of the volatile memory device, the number of write commands received, the number of read commands received, the amount of first parity data stored in the volatile memory device, the amount of second parity data stored in the volatile memory device, or a combination thereof.

22. The memory system of claim 14, wherein: The first type of fault corresponds to a first error in a word line in two or more planes of the memory die of the non-volatile memory device; and The second type of fault corresponds to a second error in one or more word lines of a plane in the memory die.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a first write command associated with writing first data to a memory cell of a first type; A first redundant array controller using an independent node redundant array associated with a non-volatile memory device generates first parity data corresponding to the first data, the first parity data being associated with a redundant array of the independent node recovery scheme. Receive a second write command associated with writing second data to a memory cell of a second type different from the first type of memory cell; and A second redundant array controller, different from the first redundant array controller, using the independent node redundant array generates second parity data corresponding to the second data, and the second parity data is associated with the redundant array of the independent node recovery scheme.

24. The non-transitory computer-readable medium according to claim 23, wherein: The first redundant array controller is configured to generate the first parity data to correct errors associated with a first type of fault, which is associated with accessing data in the non-volatile memory device. and The second redundant array controller is configured to generate the second parity data to correct errors associated with a second type of fault, which is associated with accessing data in the non-volatile memory device.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The second redundant array controller is used to generate third parity data corresponding to the first data, the third parity data being used to correct errors associated with the second type of fault.

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