A method for precise EEPROM writing based on the I2C bus

Abstract

This application relates to the field of Internet technology, specifically to a method, device, and storage medium for precise EEPROM writing based on the I2C bus. The method is applied to scenarios involving writing multiple EEPROMs page by page. It includes a control module for page-by-page EEPROM writing. The method comprises: the I2C host collecting the device address, total storage capacity, and page size of each EEPROM mounted on the I2C bus, and forming a reference table accordingly; before performing page-by-page write operations on the mounted EEPROMs, the I2C host providing the target starting address for writing data, the data length, and the page size of the target EEPROM, and transmitting this information to the control module; calculating the number of pages to be written starting from the target starting address and the amount of data to be written per page, and writing the data to the target address, thus realizing page-by-page write operations with arbitrary starting addresses and arbitrary data amounts for each EEPROM. This control module is independently designed and offers high security and flexibility.

Description

Technical Field

[0001] This invention relates to the field of Internet technology, and to a method for accurately writing EEPROM based on the I2C bus, and more particularly to a method, device and storage medium for accurately writing EEPROM based on the I2C bus. Background Technology

[0002] With the continuous development of internet technology, traditional host computers write to EEPROM via the I2C bus. The I2C bus (Inter-Integrated Circuit) is a simple, bidirectional two-wire synchronous serial bus used to connect microcontrollers and their peripherals, requiring only two wires to transmit information between devices connected to the bus. EEPROM (Electrically Erasable Programmable Read-Only Memory) is a type of memory chip that retains data even after power loss. EEPROM can be erased and reprogrammed on a computer or dedicated device.

[0003] In traditional master-to-master (MTB) EEPROM writing via the I2C bus, as shown in the diagram, the I2C MTB communicates with multiple EEPROMs through the I2C bus. The I2C bus includes a serial data line (SDA) and a serial clock line (SCL). SDA (Serial Data) refers to the data signal line of the I2C bus, and SCL (Serial Clock) refers to the clock signal line. The EEPROM acts as a slave device on the I2C bus, allowing the MTB to actively read and write to it, and control the data transmission direction and start. When the MTB writes to an EEPROM via the I2C bus, it first sends the device address and a one-bit write data control signal on the SDA bus. If the slave EEPROM matches the device address, it returns a response. Then, the MTB sends the data address and the data. In scenarios where large amounts of data are written to the EEPROM via the I2C bus, to improve writing efficiency, a page-based writing mode is needed. However, if the amount of data written exceeds the address of one page, the writing will return to the beginning address of that page, causing duplicate writing of EEPROM pages, and data cannot be written to the correct address.

[0004] Therefore, when a traditional host writes to an EEPROM via the I2C bus, the page-by-page data writing operation based on the I2C bus is problematic because the page sizes of each EEPROM are inconsistent, and if the data exceeds the size of a page, data writing errors will occur. Therefore, it is usually stipulated that the written data cannot exceed the size of a page, and the address must be set to the first address of each page. However, this greatly limits the flexibility of writing to EEPROM page by page. Summary of the Invention

[0005] To address the problems associated with traditional host-to-EEPROM writing via I2C bus, this application provides a method, device, and storage medium for precise EEPROM writing based on I2C bus. This involves scenarios where a host writes data to multiple EEPROMs via I2C bus, and to improve writing efficiency, page-by-page write operations are performed on the EEPROMs.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] This invention is applied to scenarios where multiple EEPROMs are written page by page. For cases where multiple EEPROMs are mounted with inconsistent page sizes, a control module for writing EEPROMs page by page is designed. This module enables page-by-page write operations with arbitrary start addresses and arbitrary data amounts for each EEPROM. The control module is independently designed and has high security and flexibility.

[0008] In a first aspect, one embodiment of this application provides a method for precisely writing EEPROM based on the I2C bus, applicable to scenarios of writing multiple EEPROMs page by page. The method includes a control module for writing EEPROM page by page, and comprises:

[0009] The I2C host collects the device address, total storage capacity, and single page size of each EEPROM mounted on the I2C bus, and forms a reference table accordingly.

[0010] Before performing page-by-page write operations on the mounted EEPROM, the I2C host provides the target starting address of the write data, the length of the data, and the single-page size of the target EEPROM, and transmits them to the control module for page-by-page write EEPROM.

[0011] The control module for writing EEPROM page by page calculates the number of pages to be written starting from the target address and the amount of data to be written per page, and then writes the data to the target address.

[0012] As a further aspect of the present invention, when the I2C host performs a page-by-page write operation on the mounted EEPROM, it inputs the data target starting address I, the data length L, and the single-page size N of the target EEPROM into the page-by-page write control module. By calculating the number of page writes M, the initial address Ax of each data write, and the number of data items written each time, all data is accurately written into the EEPROM.

[0013] As a further aspect of the present invention, the method for accurately writing EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target can be divided by the page size N, and whether the data length L can be divided by the page size N of the target EEPROM.

[0014] If the starting address I of the data target is divisible by the page size N, and the data length L is divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N.

[0015] As a further aspect of the present invention, if the starting address I of the data target is divisible by the page size N, and the data length L is divisible by the page size N of the target EEPROM, the initial address for each data write is:

[0016] The first write operation starts at address A0 = 1, with N data items.

[0017] The second write starts at address A1 = I + N, and the number of data items is N.

[0018] The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data items is N.

[0019] As a further aspect of the present invention, the method for accurately writing EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target can be divided by the page size N, and whether the data length L can be divided by the page size N of the target EEPROM.

[0020] If the starting address I of the data target is divisible by the page size N, and the data length L is not divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N + 1.

[0021] As a further aspect of the present invention, if the starting address I of the data target is divisible by the page size N, and the data length L is not divisible by the page size N of the target EEPROM, the initial address for each data write is:

[0022] The first write operation starts at address A0 = 1, with N data items.

[0023] The second write starts at address A1 = I + N, and the number of data items is N.

[0024] The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data is L%N.

[0025] As a further aspect of the present invention, the method for accurately writing EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target can be divided by the page size N;

[0026] If the starting address I of the data target is not divisible by the page size N, and the data length L is any integer, the number of page writes is: M = (I + L - 1) / N1 / N + 1.

[0027] As a further aspect of the present invention, if the starting address I of the data target is not divisible by the page size N, and the data length L is any integer, the initial address for each data write is:

[0028] The first write operation starts at address A0 = I, and the number of data items is NI%N;

[0029] The second write starts at address A1 = (I / N+1)*N, and the number of data items is N.

[0030] The initial address for the Mth write is AM-1 = (I / N + M-1) * N, and the number of data is (I + L-1) % 8 + 1.

[0031] Secondly, in another embodiment provided in this application, a device for precisely writing EEPROM based on an I2C bus is provided, including a memory and a processor. The memory stores a computer program, and the processor loads and executes the computer program to implement the steps of a method for precisely writing EEPROM based on an I2C bus.

[0032] Thirdly, in another embodiment provided in this application, a storage medium is provided storing a computer program, which, when loaded and executed by a processor, implements the steps of the method for precisely writing to EEPROM based on the I2C bus.

[0033] The technical solution provided in this application has the following beneficial effects:

[0034] The method, device, and storage medium for precise EEPROM writing based on the I2C bus provided in this application are applied to scenarios involving writing multiple EEPROMs page by page. For cases where multiple EEPROMs are mounted with inconsistent page sizes, a control module for page-by-page EEPROM writing is designed. This module can perform page-by-page write operations on each EEPROM mounted on the I2C bus. The page size of each EEPROM can be different. By simply providing the target address of the data to be written, the data length, and the page size of the target EEPROM, data can be written to the EEPROM precisely and efficiently page by page. This achieves page-by-page write operations on each EEPROM with arbitrary start addresses and arbitrary data amounts. The control module is independently designed and offers high security and flexibility.

[0035] These or other aspects of this application will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the application. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0037] In the diagram:

[0038] Figure 1 This diagram illustrates the traditional host architecture for writing to EEPROM via the I2C bus.

[0039] Figure 2 This illustration shows an architecture diagram of a method for precisely writing EEPROM based on the I2C bus according to an embodiment of this application, in which the host writes EEPROM via the I2C bus;

[0040] Figure 3 A flowchart illustrating a method for precisely writing to an EEPROM based on an I2C bus, according to one embodiment of this application, is shown.

[0041] Figure 4 This illustration shows a structural block diagram of a device for precise EEPROM writing based on an I2C bus according to an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0045] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0046] In this context, "a device for precisely writing EEPROM based on the I2C bus," also known as a "computer," refers to an intelligent electronic device that can perform predetermined processing procedures such as numerical calculations and / or logical calculations by running predetermined programs or instructions. It may include a processor and memory. The processor executes pre-stored instructions in memory to perform the predetermined processing procedures, or the predetermined processing procedures are performed by hardware such as ASICs, FPGAs, and DSPs, or a combination of both. Devices for precisely writing EEPROM based on the I2C bus include, but are not limited to, servers, personal computers, laptops, tablets, and smartphones.

[0047] The I2C bus-based precise EEPROM writing device includes user equipment and network devices. The user equipment includes, but is not limited to, computers, smartphones, and PDAs; the network devices include, but are not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The I2C bus-based precise EEPROM writing device can operate independently to implement this application, or it can connect to a network and interact with other I2C bus-based precise EEPROM writing devices in the network to implement this application. The network in which the I2C bus-based precise EEPROM writing device is located includes, but is not limited to, the Internet, wide area networks, metropolitan area networks, local area networks, and VPN networks.

[0048] It should also be understood that the term "and / or" as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0049] When writing data to EEPROM page by page based on the I2C bus, the page size of each EEPROM is inconsistent, and if the data exceeds the size of a page, a data write error will occur. Therefore, it is usually stipulated that the written data cannot exceed the size of a page, and the address must be set to the first address of each page. However, this greatly limits the flexibility of writing EEPROM page by page.

[0050] To address the problem of inconsistent page sizes in multiple mounted EEPROMs when writing to EEPROM via the I2C bus using traditional host architectures, this application provides a method, device, and storage medium for precise EEPROM writing based on the I2C bus. This involves scenarios where the host writes data to multiple EEPROMs via the I2C bus. To improve writing efficiency, a page-by-page write control module is designed to perform page-by-page write operations on each EEPROM, enabling arbitrary start addresses and data volumes for each EEPROM. This control module is independently designed and offers high security and flexibility.

[0051] Specifically, the embodiments of this application will be further described below with reference to the accompanying drawings.

[0052] Please see Figure 2 and Figure 3 As shown, one embodiment of the present invention provides a method for precise EEPROM writing based on the I2C bus, which is applied to the scenario of writing multiple EEPROMs page by page. The method includes a control module for writing EEPROM page by page and includes steps S10 to S30.

[0053] S10: The I2C host collects the device address, total storage capacity, and single page size of each EEPROM mounted on the I2C bus, and forms a reference table accordingly.

[0054] Before performing page-by-page write operations on the mounted EEPROM, the S20 and I2C host provide the target starting address of the write data, the length of the data, and the single-page size of the target EEPROM, and transmit them to the control module for page-by-page write EEPROM.

[0055] S30. The control module for writing EEPROM by page calculates the number of pages to be written starting from the target address and the amount of data to be written per page, and writes the data to the target address.

[0056] When obtaining the application configuration request from the user application, the execution subject in this embodiment is the user application device that executes the method of precisely writing EEPROM based on the I2C bus. This device can be a PC, a portable computer, a mobile terminal, or other device with display and processing functions.

[0057] This invention is applied to scenarios where multiple EEPROMs are written page by page. For cases where multiple EEPROMs are mounted with inconsistent page sizes, a control module for writing EEPROMs page by page is designed. This module enables page-by-page write operations with arbitrary start addresses and arbitrary data amounts for each EEPROM. The control module is independently designed and has high security and flexibility.

[0058] In an embodiment of the present invention, when the I2C host performs a page-by-page write operation on the mounted EEPROM, it inputs the data target starting address I, the data length L, and the single-page size N of the target EEPROM into the page-by-page write control module. By calculating the number of page writes M, the initial address Ax of each data write, and the number of data items written each time, all data is accurately written into the EEPROM.

[0059] In one embodiment of the present invention, the method for precise writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N, and whether the data length L is divisible by the page size N of the target EEPROM.

[0060] If the starting address I of the data target is divisible by the page size N, and the data length L is divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N;

[0061] The initial address for each data write is:

[0062] The first write operation starts at address A0 = 1, with N data items.

[0063] The second write starts at address A1 = I + N, and the number of data items is N.

[0064] ...

[0065] The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data items is N.

[0066] In one embodiment of the present invention, the method for precise writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N, and whether the data length L is divisible by the page size N of the target EEPROM.

[0067] If the starting address I of the data target is divisible by the page size N, and the data length L is not divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N + 1.

[0068] The initial address for each data write is:

[0069] The first write operation starts at address A0 = 1, with N data items.

[0070] The second write starts at address A1 = I + N, and the number of data items is N.

[0071] ...

[0072] The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data is L%N.

[0073] In one embodiment of the present invention, the method for precise writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N.

[0074] If the starting address I of the data target is not divisible by the page size N, and the data length L is any integer, the number of page writes is: M = (I + L - 1) / N1 / N + 1.

[0075] The initial address for each data write is:

[0076] The first write operation starts at address A0 = I, and the number of data items is NI%N;

[0077] The second write starts at address A1 = (I / N+1)*N, and the number of data items is N.

[0078] ...

[0079] The initial address for the Mth write is AM-1 = (I / N + M-1) * N, and the number of data is (I + L-1) % 8 + 1.

[0080] Therefore, when performing page-by-page data writing operations on EEPROM based on the I2C bus, the initial data address is sent first, and then data is sent continuously. However, once the data volume exceeds the end address of the current page, the writing will start from the beginning address of the current page instead of automatically jumping to the next page, causing data overwriting and errors. Generally, it is required that the initial address and data volume of page-by-page data writing be aligned with the page size. However, this greatly limits the flexibility of page-by-page EEPROM writing.

[0081] This invention designs a control module for page-by-page EEPROM writing, enabling page-by-page write operations to multiple EEPROMs mounted on an I2C bus. Each EEPROM can have a different page size. By simply providing the target address of the data to be written, the data length, and the page size of the target EEPROM, data can be written to the EEPROMs accurately and efficiently, thus achieving fast data write operations. The module's structure and specific algorithm are independently designed, exhibiting high reliability and flexibility.

[0082] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0083] In one embodiment of the present invention, see Figure 4 As shown, an embodiment of this application also provides a device for precise EEPROM writing based on an I2C bus, including at least one processor 1001 and a memory 1002 communicatively connected to the at least one processor 1001. The memory 1002 stores instructions executable by the at least one processor 1001. The instructions are executed by the at least one processor 1001 to cause the at least one processor 1001 to perform the method for precise EEPROM writing based on an I2C bus. When the processor 1001 executes the instructions, it implements the steps in the above-described method embodiments:

[0084] The I2C host collects the device address, total storage capacity, and single page size of each EEPROM mounted on the I2C bus, and forms a reference table accordingly.

[0085] Before performing page-by-page write operations on the mounted EEPROM, the I2C host provides the target starting address of the write data, the length of the data, and the single-page size of the target EEPROM, and transmits them to the control module for page-by-page write EEPROM.

[0086] The control module for writing EEPROM page by page calculates the number of pages to be written starting from the target address and the amount of data to be written per page, and then writes the data to the target address.

[0087] In one embodiment of this application, a storage medium is also provided, on which a computer program is stored, which, when executed by the processor 1001, implements the steps in the above-described method embodiments:

[0088] The I2C host collects the device address, total storage capacity, and single page size of each EEPROM mounted on the I2C bus, and forms a reference table accordingly.

[0089] Before performing page-by-page write operations on the mounted EEPROM, the I2C host provides the target starting address of the write data, the length of the data, and the single-page size of the target EEPROM, and transmits them to the control module for page-by-page write EEPROM.

[0090] The control module for writing EEPROM page by page calculates the number of pages to be written starting from the target address and the amount of data to be written per page, and then writes the data to the target address.

[0091] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory 1002, storage, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory.

[0092] In summary, the method, device, and storage medium for precise EEPROM writing based on the I2C bus provided in this application are applied to scenarios involving page-by-page writing of multiple EEPROMs. For cases with multiple mounted EEPROMs of inconsistent page sizes, a control module for page-by-page writing of EEPROMs is designed. This module can perform page-by-page writing operations on each EEPROM mounted on the I2C bus. The page size of each EEPROM can be different. By simply providing the target address of the data to be written, the data length, and the page size of the target EEPROM, data can be written precisely and efficiently page-by-page to the EEPROM. This achieves page-by-page writing operations with arbitrary start addresses and arbitrary data volumes for each EEPROM. The control module is independently designed, offering high security and flexibility, with a clear, flexible, reliable, and scalable structure.

[0093] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0094] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0095] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for precisely writing to an EEPROM based on an I2C bus, characterized in that, For scenarios involving writing multiple EEPROMs page by page, a control module for writing EEPROMs page by page is designed. This method includes: The I2C host collects the device address, total storage capacity, and single page size of each EEPROM mounted on the I2C bus, and forms a reference table accordingly. Before performing page-by-page write operations on the mounted EEPROM, the I2C host provides the target starting address of the write data, the length of the data, and the single-page size of the target EEPROM, and transmits them to the control module for page-by-page write EEPROM. The control module for writing EEPROM page by page calculates the number of pages to be written starting from the target address and the amount of data to be written per page, and then writes the data to the target address. When the I2C host performs a page-by-page write operation on the mounted EEPROM, it inputs the data target starting address I, the data length L, and the single-page size N of the target EEPROM into the page-by-page write control module. By calculating the number of page writes M, the initial address Ax of each data write, and the number of data items written each time, all data is accurately written into the EEPROM.

2. The method for precisely writing to EEPROM based on the I2C bus as described in claim 1, characterized in that, The method for accurately writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N, and whether the data length L is divisible by the page size N of the target EEPROM. If the starting address I of the data target is divisible by the page size N, and the data length L is divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N.

3. The method for precisely writing to EEPROM based on the I2C bus as described in claim 2, characterized in that, If the starting address I of the data target is divisible by the page size N, and the data length L is divisible by the page size N of the target EEPROM, then the initial address for each data write is: The first write operation starts at address A0=I, with N data items. The second write starts at address A1 = I + N, and the number of data items is N. The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data items is N.

4. The method for precisely writing to EEPROM based on the I2C bus as described in claim 1, characterized in that, The method for accurately writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N, and whether the data length L is divisible by the page size N of the target EEPROM. If the starting address I of the data target is divisible by the page size N, and the data length L is not divisible by the page size N of the target EEPROM, then the number of page writes is: M = L / N + 1.

5. The method for precisely writing to EEPROM based on the I2C bus as described in claim 4, characterized in that, If the starting address I of the data target is divisible by the page size N, and the data length L is not divisible by the page size N of the target EEPROM, then the initial address for each data write is: The first write operation starts at address A0=I, with N data items. The second write starts at address A1 = I + N, and the number of data items is N. The initial address for the Mth write is AM-1 = I + (M-1)*N, and the number of data is L%N.

6. The method for precisely writing to EEPROM based on the I2C bus as described in claim 1, characterized in that, The method for accurately writing to EEPROM based on the I2C bus further includes: determining whether the starting address I of the data target is divisible by the page size N; If the starting address I of the data target is not divisible by the page size N, and the data length L is any integer, the number of page writes is: M = (I + L - 1) / N1 / N + 1.

7. The method for precisely writing to EEPROM based on the I2C bus as described in claim 6, characterized in that, If the starting address I of the data target is not divisible by the page size N, and the data length L is any integer, the initial address for each data write is: The first write operation starts at address A0=I, with a data count of NI%N; The second write starts at address A1 = (I / N + 1) * N, and the number of data items is N. The initial address for the Mth write is AM-1 = (I / N + M-1) * N, and the number of data is (I + L-1)%8 + 1.

8. A device for precise EEPROM writing based on the I2C bus, characterized in that, The device for precise EEPROM writing based on the I2C bus includes a processor, a memory, and a program for precise EEPROM writing based on the I2C bus stored in the memory and executable by the processor, wherein when the program for precise EEPROM writing based on the I2C bus is executed by the processor, it implements the steps of the method for precise EEPROM writing based on the I2C bus as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program for precisely writing EEPROM based on the I2C bus, wherein when the program for precisely writing EEPROM based on the I2C bus is executed by a processor, it implements the steps of the method for precisely writing EEPROM based on the I2C bus as described in any one of claims 1 to 7.

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