A data transmission configuration method, device, electronic device and storage medium

Abstract

The present application relates to the field of communication technology, and in particular to a data transmission configuration method, device, electronic device and storage medium for improving the accuracy of data verification. The method includes: sending the target write data and target write verification data to be written; receiving the returned verification result, the verification result is obtained after the receiving end samples and verifies the target write data and the target write verification data based on the sampling signal, and each first bit corresponds to each second bit of the target write verification data; by adjusting the transmission delay of each second bit, respectively, determining the corresponding delay parameters when the corresponding first bit changes from the first target value to the second target value; based on the delay parameters corresponding to each second bit, setting the transmission mode of the write verification data to be transmitted. The present application ensures that the write verification data to be transmitted received by the receiving end can be accurately sampled by adjusting the offset between the write verification data and the sampling signal, thereby improving the verification accuracy.

Description

Background Art

[0002] High Bandwidth Memory (HBM) is a high-performance dynamic random access memory (DRAM) based on 3D stacking technology. HBM DRAM includes a set of command and address bus parity (Parity for command and address, PAR) pins to support the bidirectional data bus parity (DQ Parity) check function. In the write direction, after the receiving end HBM DRAM receives the write (WRITE, referred to as WR) instruction from the sending end HBMHost, it receives the data and PAR signal written from the HBM Host. After receiving the PAR signal, the HBM DRAM verifies the written data.

[0003] Since the write PAR pin of HBM can work at a sampling frequency of up to 3.6GHz, at such a high operating frequency, the transmission and data sampling of the write parity check data (referred to as write check data) are easily affected by environmental changes in the process voltage temperature (PVT) and crosstalk between signals, resulting in an offset between the write parity check data and the sampling signal WDQS, thereby causing sampling errors in the write parity check data. When errors occur in the check data written to the HBM DRAM, it further causes errors in the HBM Host during the verification of the written data, which affects the correct execution of the entire HBM subsystem, and in severe cases even affects the normal operation of the entire chip.

[0004] Therefore, how to adjust the offset between the sampling signal and the writing parity verification data to improve the accuracy of data verification is an urgent problem to be solved. Summary of the invention

[0005] Embodiments of the present application provide a data transmission configuration method, device, electronic device, and storage medium to improve the accuracy of data verification.

[0006] A data transmission configuration method provided in an embodiment of the present application includes:

[0007] Sending to a receiving end target write data to be written and target write verification data for verifying the target write data;

[0008] Receive a verification result returned by the receiving end, wherein the verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on a sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data in a one-to-one manner;

[0009] Determine, by adjusting the transmission delay of each of the second bits, the delay parameter corresponding to each of the second bits when the corresponding first bit in the verification result is changed from the first target value to the second target value; the first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly;

[0010] Based on the delay parameters corresponding to the second bits in the target write verification data, a transmission mode of the write verification data to be transmitted is set.

[0011] An embodiment of the present application provides a data transmission configuration device, including:

[0012] A first transmission unit, used for sending target write data to be written and target write verification data for verifying the target write data to a receiving end;

[0013] A second transmission unit is used to receive a verification result returned by the receiving end, wherein the verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on a sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data in a one-to-one manner;

[0014] an adjusting unit, configured to determine, by adjusting the transmission delays of the second bits, the delay parameters corresponding to the second bits when the corresponding first bit in the verification result is changed from a first target value to a second target value; the first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly;

[0015] A configuration unit is used to set a transmission mode of the write verification data to be transmitted based on the delay parameters corresponding to each second bit position in the target write verification data.

[0016] Optionally, the delay parameter includes a delay parameter to be adjusted up and a delay parameter to be adjusted down;

[0017] The configuration unit is specifically used for:

[0018] Determine the intermediate transmission delay corresponding to the target write verification data according to the delay parameters to be adjusted up and the average values ​​of the delay parameters to be adjusted down corresponding to the second bits respectively;

[0019] If, when the target write verification data is transmitted according to the intermediate transmission delay, the corresponding first bits of the verification result have a second target value, the corresponding transmission delay is adjusted again according to the delay parameter of each target second bit until the target transmission delay corresponding to the target write verification data is obtained, so that when the target write verification data is transmitted according to the target transmission delay, the corresponding first bits of the verification result are all the first target values;

[0020] The write verification data to be transmitted is set to be transmitted according to the target transmission delay.

[0021] Optionally, the intermediate transmission delay corresponding to the target write verification data includes the intermediate transmission delay corresponding to each of the second bits; and the configuration unit is specifically configured to:

[0022] For each second bit, the following operations are performed respectively:

[0023] For a second bit position, determining an average value of the delay parameter to be adjusted upward and the delay parameter to be adjusted downward corresponding to the second bit position;

[0024] The transmission delay corresponding to the one second bit is adjusted upward or downward according to the average value to obtain an intermediate transmission delay corresponding to the one second bit.

[0025] Optionally, the configuration unit is further used for:

[0026] If, when the target write verification data is transmitted according to the intermediate transmission delay, all first bits of the corresponding verification result are first target values, the write verification data to be transmitted is set to be transmitted according to the intermediate transmission delay.

[0027] Optionally, the configuration unit is specifically used to:

[0028] For each target second bit, perform the following operations:

[0029] For a target second bit, the sum of the delay parameter to be adjusted upward and the delay parameter to be adjusted downward corresponding to the target second bit is used as the adjustment step size;

[0030] According to the adjustment step, the transmission delay of the target second bit continues to be adjusted until the corresponding first bit in the verification result is the first target value.

[0031] Optionally, the adjustment unit is further used for:

[0032] When it is determined that the corresponding first bit in the verification result is changed from the first target value to the second target value by adjusting the transmission delay of each second bit respectively, before the delay parameters corresponding to each second bit, if the second target value exists in each first bit of the verification result returned by the receiving end, the transmission frequency of the target write verification data is gradually reduced until all the first bits of the verification result are the first target value.

[0033] Optionally, the target write data and the target write verification data are data with fixed verification errors, the first target value indicates a verification error, and the second target value indicates a verification success; or

[0034] The target write data and the target write verification data are fixedly verified correct data, the first target value indicates a correct verification, and the second target value indicates a verification error.

[0035] Optionally, the adjustment unit is specifically used for:

[0036] Inputting the target write verification data into a delay control circuit, wherein the delay control circuit includes a delay unit group corresponding to each of the second bits;

[0037] For each second bit, perform the following operations:

[0038] For a second bit, the transmission delay of the second bit is adjusted by adjusting the number of delay units that the second bit passes through in the corresponding delay unit group; wherein each delay unit is used to increase the transmission delay of the passing data by a fixed value.

[0039] Optionally, each delay unit in the delay unit group corresponds to a tap interface; and the adjustment unit is specifically used for:

[0040] The selection of the tap interface for outputting the one second bit in the delay unit group is controlled by a step counter to adjust the transmission delay of the one second bit.

[0041] An electronic device provided by an embodiment of the present application includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of any one of the above-mentioned data transmission configuration methods.

[0042] An embodiment of the present application provides a computer-readable storage medium, which includes a computer program. When the computer program is executed on an electronic device, the computer program is used to enable the electronic device to execute the steps of any one of the above-mentioned data transmission configuration methods.

[0043] An embodiment of the present application provides a computer program product, which includes a computer program, and the computer program is stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device performs the steps of any one of the above-mentioned data transmission configuration methods.

[0044] The beneficial effects of this application are as follows:

[0045] The embodiment of the present application provides a data transmission configuration method, device, electronic device and storage medium. Because the present application uses a method of adjusting the transmission delay of the write verification data before the HBM chip starts initial operation, the offset between the write verification data and the sampling signal is adjusted. Specifically, the target write data and the target write verification data are used as sample data for training, and the target write verification data is sent to the receiving end (HBM The target write data and the target write verification data are sent to a DRAM, and after the receiving end samples the target write data and the target write verification data based on the sampling signal, the target write data is verified by the target write verification data. When the expected sampling of these data is correct, the data of each bit in the obtained verification result is called the first target value; in the present application, based on this feature, the transmission delay of the target write verification data is adjusted, and the transmission delay can affect the offset between the target write verification data and the sampling signal, so as to affect the accuracy of data sampling, and further affect the correctness of the verification result; when the corresponding first bit in the verification result is changed from the first target value to the second target value, it indicates that the offset between the sampling signal and the write verification data is at the critical point of the sampling error at this time, and the transmission mode of the write verification data to be transmitted is set based on the delay parameter determined at this time, which can effectively control the offset between the write verification data to be transmitted and the sampling signal when the chip is initially working, so as to ensure that the write verification data to be transmitted received by the receiving end can be accurately sampled, thereby ensuring the accuracy of the verification.

[0046] Other features and advantages of the present application will be described in the subsequent description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 An optional schematic diagram of a sending end initiating a write operation to a receiving end in an embodiment of the present application;

[0049] Figure 2A A schematic diagram of the first alignment relationship between write verification data and sampling signals in an embodiment of the present application;

[0050] Figure 2B A schematic diagram of the alignment relationship between the second write verification data and the sampling signal in an embodiment of the present application;

[0051] Figure 2C A schematic diagram of the alignment relationship between the third write verification data and the sampling signal in the embodiment of the present application;

[0052] Figure 3 A schematic diagram of an application scenario of an embodiment of the present application;

[0053] Figure 4 A flowchart of a data transmission configuration method provided in an embodiment of the present application;

[0054] Figure 5 A basic structural diagram of a PAR training circuit in an embodiment of the present application;

[0055] Figure 6 A schematic diagram of a sending process of a write instruction in an embodiment of the present application;

[0056] Figure 7 A schematic diagram of a write PAR path delay control circuit in an embodiment of the present application;

[0057] Figure 8 A schematic diagram of the connection relationship between a step counter and a delay unit in an embodiment of the present application;

[0058] Fig. 9A A schematic diagram of transmission between write data and write verification data in an embodiment of the present application;

[0059] Fig. 9B A schematic diagram of another transmission situation between write data and write verification data in an embodiment of the present application;

[0060] Fig. 10A This is a schematic diagram of a DERR error in an embodiment of the present application;

[0061] Fig. 10B A schematic diagram of two DERR errors in an embodiment of the present application;

[0062] Fig. 10C A schematic diagram of three DERR errors in an embodiment of the present application;

[0063] Fig.11 A schematic diagram of an initial state of target writing verification data in an embodiment of the present application;

[0064] Fig.12 A schematic diagram of a method for determining a delay parameter in an embodiment of the present application;

[0065] Fig.13 A schematic diagram of an alignment result of a target write verification data and a sampling signal in an embodiment of the present application;

[0066] Fig.14 A schematic diagram of another alignment result of target write verification data and sampling signal in an embodiment of the present application;

[0067] Fig.15 A schematic diagram of the structure of a data transmission configuration device in an embodiment of the present application;

[0068] Fig.16 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0069] Fig.17 A schematic diagram of the structure of a computing device to which an embodiment of the present application is applied. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solution of the present application, rather than all of the embodiments. Based on the embodiments recorded in the application documents, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present application.

[0071] The following is an introduction to some concepts involved in the embodiments of the present application.

[0072] Write data: refers to the data that needs to be written into the HBM DRAM at the receiving end. In this article, the write data includes at least a DQ signal, and may further include at least one of a data bus inversion (DBI) signal and a data mask (DM) signal. Specifically, the write data in this application can be divided into two categories: target write data and write data to be transmitted. The target write data refers to the data that needs to be written into the HBM DRAM at the receiving end during the PAR pin training phase before the initial operation of the HBM chip, and the write data to be transmitted generally refers to the data that needs to be written into the HBM DRAM at the receiving end during the application process after the PAR pin training is completed, which depends on the actual situation.

[0073] Write verification data: refers to the data used to verify the write data, that is, the parity bit (Parity), which refers to an extra bit added to the byte during data storage and transmission to detect errors. It often generates a redundant data from two or more original data, and the redundant data can be reconstructed from one original data. Of course, it can also be set in other ways, which is not specifically limited in this article. Specifically, the write verification data in this application can also be divided into two categories: target write verification data and write verification data to be transmitted. Among them, the target write verification data corresponds to the target write data, and refers to the data used to verify the target write data during the PAR pin training stage before the initial operation of the HBM chip. The write verification data to be transmitted corresponds to the write data to be transmitted, and generally refers to the data used to verify the write data to be transmitted in the application process after the PAR pin training is completed, which depends on the actual situation.

[0074] Verification result: refers to the result obtained by performing a parity check on the write data (this article takes even parity as an example) after the receiving end receives the write data and the write verification data. It is generally divided into two situations: correct verification and incorrect verification.

[0075] Sampling signal: refers to the clock signal when the receiving end samples the write data and write verification data sent by the sending end. This article uses the sampling signal as the write data selection pulse (Write DQ Strobe, WDQS) as an example for explanation.

[0076] The first target value refers to the result obtained by verifying through the Parity mechanism based on the receiving end that the target write data and the target write verification data can be correctly sampled based on the sampling signal (that is, the sampled data is the correct value).

[0077] The second target value refers to the result obtained by the receiving end through the Parity mechanism based on the sampling signal, on the basis that the target write data and the target write verification data cannot be correctly sampled (that is, the sampled data is an erroneous value).

[0078] Error Correcting Code (ECC): The parity mechanism is to check the correctness of the current 8-bit data by adding a data bit on the basis of the original data bit. With each increase of 8 bits of data, the check bit needs to increase by 1 bit. When the amount of data is 256 bytes, 256 bits are required, and the erroneous data cannot be recovered. As a result, a storage error detection and correction mechanism has emerged, which is ECC. ECC also makes error judgments by adding check bits, but can correct errors. ECC has more check bits and stronger fault tolerance.

[0079] DRAM: The most common type of computer memory. It usually uses one transistor and one capacitor to represent one bit. Unlike firmware memory such as ROM and PROM, the two main types of random access memory (dynamic and static) lose the stored data when the power is removed.

[0080] Eye diagram: In communication, an eye diagram is a series of digital signals accumulated and displayed on an oscilloscope. It contains a wealth of information. The effects of inter-symbol crosstalk and noise can be observed from the eye diagram, reflecting the overall characteristics of the digital signal, thereby estimating the quality of the system. Therefore, eye diagram analysis is the core of signal integrity analysis of high-speed interconnection systems. In addition, this diagram can also be used to adjust the characteristics of the receiving filter to reduce inter-symbol crosstalk and improve the transmission performance of the system. An eye diagram refers to a diagram observed on an oscilloscope when using experimental methods to estimate and improve (adjust) the performance of a transmission system.

[0081] Burst signal: Burst refers to the way that adjacent storage cells in the same row transmit data continuously. The number of storage cells (columns) involved in the continuous transmission is the burst length (SDRAM), referred to as BL (burst length).

[0082] Transmission delay: refers to the time that the sender needs to delay the sending of write verification data before sending the write verification data to the receiver. For example, the initial state is set to send the write verification data at time t0. After setting the transmission delay t1, the write verification data needs to be sent at time t2=t0+t1. Generally, for a write operation, the delay between the write verification data and the write data can be set by the parity latency (PL) parameter. PL is a parameter that can support programming control of the HBM Host. This parameter reflects the number of delay cycles between the write verification data PAR signal and the related write data signal. The transmission delay in this application refers to the time that needs to be further delayed for the PAR signal based on PL.

[0083] Tap interface: A tap refers to a wire end drawn from a winding for wiring. In the embodiment of the present application, each delay unit includes a tap interface after it, which can be used to output the data passing through the corresponding delay unit. When different tap interfaces are selected to output data, the number of corresponding delay units passed is different, and the transmission delay is also different.

[0084] The following is a brief introduction to the design concept of the embodiment of the present application:

[0085] With the continuous development of processors, memory bandwidth has become a key limiting factor in the overall performance of processors. HBM uses 3D stacked storage layers to vertically integrate multiple layers of DRAM devices in the package, greatly improving the bandwidth of the storage system and gradually becoming the mainstream storage technology for high-performance processors. It is suitable for application scenarios with high memory bandwidth requirements, such as graphics processors, network switching and forwarding equipment such as routers and switches, etc.

[0086] HBM DRAM includes a set of PAR pins to support the DQ Parity check function. In the write direction, when the HBM Host at the sending end initiates a write operation to the HBM DRAM at the receiving end, Figure 1 As shown, it is an optional schematic diagram of an HBM Host initiating a write operation to the HBM DRAM in an embodiment of the present application. The HBM Host will first send a row activation instruction (active, ACT) on the R instruction to activate the row being written this time (if the row is already in the activated state, there is no need to activate it again), and send a WR instruction on the C instruction (such as Figure 1 After a certain write latency (WriteLatency, WL), the HBM Host will write the data DATA (such as Figure 1 DATA0, DATA1, DATA2) and write verification data (such as Figure 1 PAR0, PAR1, PAR2) in HBM DRAM are written into HBM DRAM at the same time. PRE (percharge) is a precharge instruction, WR0 is used to write DATA0 and PAR0, WR1 is used to write DATA1 and PAR1, and WR2 is used to write DATA2 and PAR2.

[0087] It should be noted that the WL parameter reflects the number of delay cycles between the write data signal and the related write instruction WR, and the PL parameter reflects the number of delay cycles between the PAR signal and the related write data signal. Figure 1 Taking PL=0 as an example, that is, the number of delay cycles between the PAR signal and the write data signals DQ, DBI, DM is 0.

[0088] After receiving the write command from the HBM Host, the HBM DRAM receives the data and PAR signal written by the HBM Host. The HBM DRAM samples the data based on the sampling signal WDQS, and then verifies the written data based on the sampled PAR signal. If the verification is correct, the data error signal (DWORD Error, DERR) pin is 0, and if the verification is wrong, the DERR pin is 1.

[0089] Taking HBM 2E as a reference, according to the relevant HBM protocols, the data read and write speed of HBM 2E devices can reach a baud rate of up to 3.6GHz, that is, the write PAR pin of HBM can operate at a sampling frequency of up to 3.6GHz. Since HBM is based on a dual-edge data transmission method, HBM reads and writes data on both the rising and falling edges of the clock, so the actual HBM 2E communication clock frequency is up to 1.8GHz. At such a high operating frequency, if the transmission of the write Parity check data is interfered by noise on the data communication link, or crosstalk occurs between the data lines, the write Parity check data and the sampling signal WDQS will be offset, resulting in write Parity check data sampling errors.

[0090] like Figure 2A , Figure 2B and Figure 2C As shown in FIG. 1 , several schematic diagrams of offset situations between write verification data and sampling signal WDQS are listed respectively.

[0091] Specifically, Figure 2A FIG. 1 is a schematic diagram of the first alignment relationship between write verification data and sampling signal in the embodiment of the present application, and the schematic diagram is an expected alignment relationship between write verification data and WDQS. Figure 2A In the process, the rising edge of WDQS (WDQS is triggered by the rising edge, also referred to as the sampling edge below) is aligned to the center position of the write verification data, and the writing at this time is the most accurate.

[0092] Figure 2B FIG. 1 is a schematic diagram of a second alignment relationship between write verification data and a sampling signal in an embodiment of the present application. The schematic diagram is an unexpected alignment relationship between write verification data and WDQS. Figure 2B In the case of WDQS, the sampling edge will drift out of the write verification data window; Figure 2C FIG. 1 is a schematic diagram of a third alignment relationship between write verification data and a sampling signal in an embodiment of the present application, and is also a schematic diagram of an unexpected alignment relationship between write verification data and WDQS. Figure 2C Although the WDQS sampling does not drift out of the write verification data window, the sampling edge and the data establishment (or cancellation) edge are too close, resulting in a setup timing (or hold timing) violation in this sampling. Figure 2B and Figure 2C The above-mentioned situations will lead to sampling errors in writing verification data.

[0093] When sampling errors occur in the verification data written to the receiving end, errors will occur in the HBM Host during the verification of writing DQ, DM, and DBI, which will affect the correct execution of the entire HBM subsystem, and in severe cases even affect the normal operation of the entire chip.

[0094] In view of this, the embodiments of the present application propose a data transmission configuration method, device, electronic device and storage medium. Because the present application uses a method of adjusting the transmission delay of the write verification data before the HBM chip starts initial operation, the offset between the write verification data and the sampling signal is adjusted. Specifically, the target write data and the target write verification data are used as sample data for training, and the target write verification data is sent to the receiving end (HBM The target write data and the target write verification data are sent to a DRAM, and after the receiving end samples the target write data and the target write verification data based on the sampling signal, the target write data is verified by the target write verification data. When the expected sampling of these data is correct, the data of each bit in the obtained verification result is called the first target value; in the present application, based on this feature, the transmission delay of the target write verification data is adjusted, and the transmission delay can affect the offset between the target write verification data and the sampling signal, so as to affect the accuracy of data sampling, and further affect the correctness of the verification result; when the corresponding first bit in the verification result is changed from the first target value to the second target value, it indicates that the offset between the sampling signal and the write verification data is at the critical point of the sampling error at this time, and the transmission mode of the write verification data to be transmitted is set based on the delay parameter determined at this time, which can effectively control the offset between the write verification data to be transmitted and the sampling signal when the chip is initially working, so as to ensure that the write verification data to be transmitted received by the receiving end can be accurately sampled, thereby ensuring the accuracy of the verification.

[0095] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application may be combined with each other if there is no conflict.

[0096] like Figure 3 As shown, it is a schematic diagram of an application scenario of an embodiment of the present application. The application scenario diagram includes a sending end 310 and a receiving end 320.

[0097] Taking the HBM subsystem as an example, in the HBM subsystem, the transmitting end 310 may be an HBM Host, and the receiving end 320 may be an HBM DRAM. The HBM DRAM includes a set of PAR pins for the DQ Parity verification function. The data transmission configuration method proposed in this application can be used to train the PAR pins.

[0098] In an embodiment of the present application, the transmitting end HBM Host may send the target write data to be written (which may be DQ, DBI, DM signals) and the target write verification data (PAR signal) used to verify the target write data to the receiving end HBM DRAM; the HBM Host receives the verification result (DERR signal) returned by the HBM DRAM, and the verification result is obtained after the HBM DRAM samples and verifies the target write data and the target write verification data based on the sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data one by one; then, the HBM Host repeats the above-mentioned process of sending the target write data and the target write verification data and receiving the corresponding verification result, and in this process, continuously adjusts the transmission delay of each second bit, and obtains the delay parameters corresponding to each second bit when the corresponding first bit in the verification result is changed from the first target value to the second target value; then, based on the delay parameters corresponding to each second bit in the target write verification data, the transmission mode of the write verification data to be transmitted is set.

[0099] Specifically, the data transmission configuration method in the embodiment of the present application can be applied to various electronic devices with high memory bandwidth requirements, such as graphics processors, network switching and forwarding equipment such as routers, switches, etc., and can also be terminal devices deployed with HBM, servers, etc.

[0100] In the embodiments of the present application, terminal devices include but are not limited to mobile phones, tablet computers, laptop computers, desktop computers, e-book readers, intelligent voice interaction devices, smart home appliances, vehicle-mounted terminals, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0101] It should be noted that the data transmission configuration method in each embodiment of the present application can be executed by an electronic device, which can be a terminal device or server deployed with HBM, or other HBM-related devices, which is not specifically limited in this document.

[0102] In addition, the embodiments of the present application can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, smart transportation, assisted driving and other scenarios.

[0103] The following describes the data transmission configuration method provided by the exemplary embodiment of the present application in combination with the application scenarios described above and with reference to the accompanying drawings. It should be noted that the above application scenarios are only shown to facilitate understanding of the spirit and principles of the present application, and the implementation methods of the present application are not limited in this regard.

[0104] The following is a detailed introduction using the example of the sending end being the HBM Host and the receiving end being the HBM DRAM.

[0105] See also Figure 4 As shown, it is an implementation flow chart of a data transmission configuration method provided in an embodiment of the present application. Taking the execution subject as the sending end HBM Host as an example, the specific implementation process of the method is as follows:

[0106] S41: Sending target write data to be written and target write verification data for verifying the target write data to a receiving end.

[0107] In the embodiment of the present application, write data refers to data to be written into the HBM DRAM at the receiving end, and write verification data is used to perform data verification on the write data.

[0108] Specifically, the write data and write parity check pins of a single channel of HBM DRAM include the following related interfaces, as shown in Table 1:

[0109] Table 1

[0110]

[0111]

[0112] In Table 1, HBM write data contains 3 groups of signals, namely DQ, DM and DBI. DQ is a 128-bit write data signal, DM is a 16-bit write data mask signal (DM signal can be configured as ECC signal by Mode Register register, at this time DM function will no longer be supported, instead write ECC data into the chip for error correction and detection), DBI is a 16-bit DBI data bus flip signal of write data. The corresponding relationship between DM, DBI and DQ data is shown in Table 2:

[0113] Table 2

[0114] DQ DBI DM DQ[7:0] DBI0 DM0 DQ[15:8] DBI1 DM1 DQ[23:16] DBI2 DM2 DQ[31:24] DBI3 DM3 DQ[39:32] DBI4 DM4 DQ[47:40] DBI5 DM5 DQ[55:48] DBI6 DM6 DQ[63:56] DBI7 DM7 DQ[71:64] DBI8 DM8 DQ[79:72] DBI9 DM9 DQ[87:80] DBI10 DM10 DQ[95:88] DBI11 DM11 DQ[103:96] DBI12 DM12 DQ[111:104] DBI13 DM13 DQ[119:112] DBI14 DM14 DQ[127:120] DBI15 DM15

[0115] As can be seen from Table 2, every 8 bits of DQ correspond to 1 bit of DBI and DM, such as DQ[7:0] corresponds to the 0th bit of DBI and DM, DQ[15:8] corresponds to the 1st bit of DBI and DM, and so on.

[0116] It should be noted that DQ, DBI, and DM are all data write signals and can participate in PAR verification. Among them, DQ will definitely participate in the verification, while DBI and DM can be determined according to the actual situation. It is necessary to analyze the specific situation according to whether the relevant pins are enabled. The following mainly takes DQ, DBI, and DM all participating in PAR verification as an example for detailed explanation.

[0117] S42: Receive the verification result returned by the receiving end.

[0118] The verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on the sampling signal, and each first bit of the verification result corresponds one-to-one to each second bit of the target write verification data.

[0119] In the embodiment of the present application, during the data writing process, HBM needs to write PAR data (write verification data) into HBM DRAM together with DQ (write data). HBM DRAM will use WDQS signal as the sampling signal for sampling write data and write verification data. After sampling the write data and write verification data, the write data is verified based on the write verification data to obtain the corresponding verification result. In the present application, DERR is used to represent the verification result, and the data bit width is 4 bits, that is, HBM DRAM needs to return DERR to HBMHost. If the verification is correct, DERR is returned as 0; if the verification is wrong, DERR is returned as 1.

[0120] Specifically, the DERR pin of HBM is divided into 4 bits. When the Parity operation is correct, the corresponding bit of DERR will output 0. When the Parity operation is wrong, the corresponding bit of DERR will output 1. The corresponding relationship between DERR and data is:

[0121] DQ[31:0], DBI[3:0], DM[3:0] correspond to DERR0;

[0122] DQ[63:32], DBI[7:4], DM[7:4] correspond to DERR1;

[0123] DQ[95:64], DBI[11:8], DM[11:8] correspond to DERR2;

[0124] DQ[127:96], DBI[15:12], DM[15:12] correspond to DERR3.

[0125] As described in Table 3, the DWORD check functions supported by HBM DRAM are shown in the table (DQ must be enabled). The table only lists the correspondence between DQ 0 to 31 bits, DBI 0 to 3 bits, DM, and ECC 0 to 3 bits. The remaining DQs have similar check relationships with 4-bit signals of DBI / DM / ECC corresponding to every 32 bits, which will not be repeated in this article.

[0126] Table 3

[0127]

[0128]

[0129] As can be seen from Table 3, if the ECC function is disabled, if the XOR result of all bits of DQ[31:0], DBI[3:0] and DM[3:0] is an even number, if PAR is low, the DERR output is 0; if PAR is high, the DERR output is 1.

[0130] If ECC is enabled, the ECC data does not participate in the parity check. If the XOR result of all bits of DQ[31:0] and DBI[3:0] is an even number, if PAR is low, the DERR output is 0; if PAR is high, the DERR output is 1.

[0131] In addition, if DBI is disabled, DBI data does not participate in the Parity operation. If ECC is enabled or DM is disabled, DM data does not participate in the Parity operation.

[0132] In the embodiments of the present application, the detailed description is mainly based on the example that DQ, DBI and DM all participate in the Parity operation, that is, both DBI and DM are enabled.

[0133] S43: Determine the delay parameters corresponding to the second bits when the corresponding first bit in the check result is changed from the first target value to the second target value by adjusting the transmission delay of the second bits respectively.

[0134] The first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly.

[0135] That is, the first target values ​​corresponding to the four first bits in DERR respectively represent the verification results obtained when the target write verification data of the corresponding second bit can be correctly sampled and the target write data is verified based on the correct target write verification data. For example, DERR0 means that when PAR0 can be correctly sampled, the target write data (DQ[31:0], DBI[3:0], DM[3:0]) is verified based on the correctly sampled PAR0. Similarly, DERR1 means that when PAR1 can be correctly sampled, the target write data (DQ[63:32], DBI[7:4], DM[7:4]) is verified based on the correctly sampled PAR1, and so on.

[0136] The second target values ​​corresponding to the four first bits in DERR respectively represent the verification results obtained when the target write verification data of the corresponding second bit is sampled incorrectly, based on the erroneous target write verification data. For example, DERR0 means that when PAR0 is sampled incorrectly, the target write data (DQ[31:0], DBI[3:0], DM[3:0]) is verified based on PAR0 obtained by erroneous sampling, and the result is obtained. Similarly, DERR1 means that when PAR1 is sampled incorrectly, the target write data (DQ[63:32], DBI[7:4], DM[7:4]) is verified based on PAR1 obtained by erroneous sampling, and so on.

[0137] In an embodiment of the present application, DERR can be represented as four-bit binary data, so the data on each first bit is either 0 or 1, and the first target value is different from the second target value, that is, the first target value is 1 and the second target value is 0; or, the first target value is 0 and the second target value is 1.

[0138] In addition, the target write data and target write verification data in the embodiment of the present application are used to train the write PAR pin before the HBM chip is brought up for initial operation, so that when the chip is initially operated subsequently, if the back-end timing does not converge and the HBM chip is produced at a fault, resulting in a sampling error in the chip write PAR path, the configuration method in the embodiment of the present application can be used to ensure that the write PAR data received by the HBM DRAM is accurate during the initial operation of the chip, thereby ensuring that no error occurs in the process of verifying the write data by the HBM Host.

[0139] Therefore, the target write data and the target write verification data can be set as data with fixed verification errors to facilitate training. Since the PAR verification method is even verification, the target write data can be set to all 0s and the target write verification data can be set to all 1s. In this case, the first target value represents the verification result when the expected sampling is correct, that is, the target write data and the target write verification data can be sampled correctly. When the target write data is verified based on the correct target write verification data, the verification result obtained should indicate a verification error (that is, 1), and the second target value should indicate a correct verification (that is, 0).

[0140] That is, the values ​​of DQ, DM, and DBI are all set to 0, the XOR result is an even number: 0, and PAR is all 1, as shown in Table 3, so it is expected that the value of DERR is 1 (all four bits are 1). If 0 is sampled (at least one bit is 0), it means that the data sampling on the path of writing PAR has drifted.

[0141] Similarly, the target write data and the target write verification data can also be set as fixed verification correct data, such as the target write data and the target write verification data can be set to all 0. In this case, the first target value represents the verification result when the expected sampling is correct, that is, the target write data and the target write verification data can be correctly sampled, then the target write data is verified based on the correct target write verification data, and the obtained verification result should indicate a correct verification (i.e., 0), and the second target value should indicate a verification error (i.e., 1).

[0142] That is, the values ​​of DQ, DM, and DBI are all set to 0, the XOR result is an even number: 0, and PAR is also all 0, so it is expected that DERR will be sampled to be 0 (all four bits are 0). If 1 is sampled (at least one bit is 1), it means that the data sampling on the path of writing PAR has drifted.

[0143] It should be noted that the target write data and target write verification data listed above are just simple examples, and any one of them is applicable to the embodiments of the present application. This document does not make specific limitations, and the following mainly describes in detail using a fixed verification error as an example.

[0144] In an embodiment of the present application, by continuously adjusting the transmission delay corresponding to each second bit in the target write verification data, the phase of the sampling clock edge (i.e., the sampling edge) of the write verification data and the sampling signal can be affected. Based on this, the transmission parameters of the write verification data to be transmitted are set, which can effectively improve the accuracy of data verification.

[0145] It should be noted that, in the process of continuously adjusting the transmission delays corresponding to the second bits in the target write verification data, step S41 and step S42 need to be continuously repeated.

[0146] S44: Setting a transmission mode of the write verification data to be transmitted based on the delay parameters corresponding to the second bits in the target write verification data.

[0147] In the embodiment of the present application, the target write verification data is equivalent to the sample data in the write PAR pin training phase, and the write verification data to be transmitted is equivalent to the data required to be used in the application phase after the write PAR pin training is completed. In the application phase, the write verification data to be transmitted can be sent to the receiving end based on the set transmission mode, so that when the receiving end receives the write verification data to be transmitted, it can ensure that the sampling signal is aligned to the eye center of the write verification data to be transmitted, and the write verification data to be transmitted can be correctly sampled, and then based on the correctly sampled write verification data to be transmitted, the write data to be transmitted can be accurately verified.

[0148] Since HBM generally works at a fixed operating frequency (such as 3.6GHz listed above), on this basis, the operating frequencies of the write verification data (PAR signal) and the sampling signal are generally unchanged. Therefore, in order to verify the phase between the sampling signal and the write verification data, the transmission delay of the write verification data can be adjusted. In this way, the offset between the Parity verification data written by the HBM device and the sampling signal WDQS is adjusted back to ensure that WDQS is aligned to the eye center of the write Parity verification data, thereby ensuring the correctness of the read Parity verification data.

[0149] See also Figure 5 As shown, it is a basic structural diagram of a write PAR training circuit in an embodiment of the present application, which specifically includes two parts: HBM Host and HBM DRAM.

[0150] In the embodiment of the present application, the HBM Host includes a write instruction sending unit, a write data sending unit, a write PAR path delay control circuit, a write PAR sending unit, a DERR receiving unit and a write PAR training unit; the implementation on the HBM DRAM side is the internal behavior of the HBM DRAM, Figure 5 The internal structure of the HBM DRAM is a simple example for easy understanding and is not specifically limited in this article.

[0151] The following is a detailed introduction to each unit in the HBM Host:

[0152] 1. Write command sending unit, used to send write commands to HBM DRAM. The sending timing of write commands is as follows: Figure 6 As shown, it is a schematic diagram of the sending process of a write instruction in an embodiment of the present application.

[0153] In the embodiment of the present application, the write operation of the HBM device is generally organized in the form of burst, and the initiation of the write burst operation is marked by the sending of the WRITE instruction, such as Figure 6 As shown, a WRITE instruction is sent.

[0154] Among them, BA stands for bank address, which defines which bank can use ACT, READ, WRITE, PRE and other commands, and also determines which mode register to access under the MODE REGISTER SET command. CA stands for column address, SID stands for stack ID. EN AP stands for Enable Auto Precharge, and DIS AP stands for Disable Auto Precharge.

[0155] CK_t and CK_s are clock signals, which are differential clock inputs. All address, command, and control input signals will be sampled at the intersection of the positive edge of CK_t and the negative edge of CK_s. Clock enable (CKE), when CKE is high, starts the internal clock signal, device input buffer, and output driver unit. PAR is the command and address bus parity input, which can be turned off or enabled through the mode register.

[0156] 2. The write data sending unit is a sending unit for DQ, DM and DBI data in the embodiment of the present application. Since the PAR check method is an even check, the following mainly uses the example that the values ​​of DQ, DM and DBI are all set to 0 for illustration.

[0157] 3. A write PAR path delay control circuit, referred to as a delay control circuit, can support dynamic adjustment of the delay circuit on the write PAR transmission path, and support increasing or decreasing the delay on the read data path. Steps S43 and S44 in the embodiment of the present application both involve related settings of transmission delay, which can be implemented based on the write PAR path delay control circuit. Therefore, a delay circuit for adjusting the path delay of the bit can be added for each write PAR bit on the write PAR transmission path.

[0158] like Figure 7As shown, it is a result schematic diagram of a write PAR path delay control circuit in an embodiment of the present application, wherein the write PAR path includes a total of 4 second bits, PAR3, PAR2, PAR1, and PAR0, and the delay control circuit includes delay unit groups corresponding to each second bit, such as S71, and each delay unit group includes a plurality of delay units (DelayElement, DE), such as S72, wherein each DE is used to increase the transmission delay of the passing data by a fixed value, and thus, the corresponding transmission delay can be adjusted by changing the number of DEs passed by each second bit in the PAR.

[0159] In an optional implementation manner, when adjusting the transmission delay of each second bit of the target write verification data, the following can be used: Figure 7 The delay control circuit shown is implemented, specifically: the target write verification data is input Figure 7 The delay control circuit shown then adjusts the transmission delay of each second bit by adjusting the number of delay units that the second bit passes through in the corresponding delay unit group.

[0160] For example, if PAR0 is set to pass through 3 DEs, the corresponding transmission delay is 3DE, if PAR1 is set to pass through 5 DEs, the corresponding transmission delay is 5DE, if PAR2 is set to pass through 10 DEs, the corresponding transmission delay is 10DE, if PAR3 is set to pass through 13 DEs, the corresponding transmission delay is 13DE, and so on.

[0161] Optionally, the delay control circuit is a circuit including four inverters, wherein each DE in the delay unit group includes a tap interface, such as Figure 8 As shown, it is a schematic diagram of the connection relationship between a step counter and a delay unit in an embodiment of the present application, wherein the dotted box S80 shows a tap interface, and the step counter (StepCounter) can be used to control the value of each bit of the write PAR to be connected from a tap outlet. Therefore, the selection of the tap interface for outputting a second bit in the delay unit group is controlled by the StepCounter to adjust the transmission delay of a second bit.

[0162] Specifically, when connected from different tap outlets, the number of delay units that the second bit passes through in the corresponding delay unit group can be controlled to achieve different transmission delay settings. For example, if PAR0 is connected to the tap outlet after the first DE in the delay unit group, the delay for PAR0 is 1DE. If it is connected to the tap outlet after the second DE, the corresponding delay is 2DE, and so on.

[0163] Based on this, the purpose of adjusting the path delay of the write PAR can be achieved, that is, the relative position of the write PAR and the WDQS sampling edge can be moved and adjusted.

[0164] Fourth, the write PAR sending unit sends the write PAR data based on the delay tap provided by the write PAR path delay circuit. In the embodiment of the present application, the PAR value sent by the write PAR sending unit is a fixed high level of 1 for 1 cycle as an example. Since DQ, DM and DBI are all 0, if a PAR high level window lasting for 1 cycle is sampled, it is expected that a write data verification error will occur, and DERR will be returned as a high level.

[0165] In addition, it should be noted that when writing the PAR sending unit, the PL parameter reflects the number of delay cycles between the PAR signal and the related DQ data signal, which can be configured to be 0 to 3 CK_c cycles. This content is controlled by the HBM mode register 4 (ModeRegister 4, MR4), as shown in the following table:

[0166] Table 4

[0167]

[0168] See also Fig. 9A and Fig. 9B As shown, the transmission conditions between write data and write verification data are listed respectively when PL is 0 and PL is 1.

[0169] like Fig. 9A As shown, in this example, BL=2, PL=0. In this figure, WL is 4, and the write data will arrive at the rising edge of the clock at time T4. Since PL=0, the PAR data will also arrive at the rising edge of the clock at time T4.

[0170] like Fig. 9B As shown, in this example, BL=2, PL=1. In this figure, WL is 4, and the write data will arrive at the rising edge of the clock at time T4. Since PL=1, the PAR data will arrive at the rising edge of the clock at time T5.

[0171] It should be noted that, for ease of understanding, this article uses PL as 0, that is, PL=0 as an example for illustration.

[0172] 5. DERR receiving unit, used to receive the DERR signal returned from HBM DRAM. Since the data sent by HBM Host contains fixed check errors (DQ, DM, DBI are all 0, and PAR is all 1), it is expected that DERR will be sampled to be 1. If 0 is sampled, it means that the data sampling on the path of writing PAR has drifted.

[0173] Specifically, when HBM writes data, it needs to write PAR data into HBM DRAM along with DQ. After receiving DQ and PAR data, HBM DRAM starts to check the Parity of the data. If the check is correct, DERR is returned as 0; if the check is wrong, DERR is returned as 1. Whether the PAR data can be sampled correctly will also affect the value of DERR.

[0174] See also Fig. 10A , Fig. 10B and Fig. 10C As shown, the situations of 1 DERR error, 2 EERR errors and 3 consecutive DERR errors are listed respectively. The DERR signal will be returned to the HBM Host after the tPARDQ time delay after the HBM DRAM samples the PAR check error. The tPARDQ in this application will take 2 CK_c (CK_t) cycles as an example.

[0175] exist Fig. 10A In the example, if the Da data and Pa check data sent at time T0 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T2.

[0176] exist Fig. 10B In the example, if the Da data and Pa check data sent at time T0 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T2. If the Dc data and Pc check data sent at time T2 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T4.

[0177] exist Fig. 10C In the example, if the Da data and Pa check data sent at time T0 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T2. If the Db data and Pb check data sent at time T1 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T3. If the Dc data and Pc check data sent at time T2 have check errors, then after a delay of 2 clock cycles of tPARDQ, a DERR signal of 1 clock cycle is returned at time T4.

[0178] 6. Write PAR training unit is used to control the remaining five modules and detect the read DERR to complete the entire write PAR training process.

[0179] It should be noted that 9A to 10CIn these five figures, the data sampling on the path of writing PAR is taken as an example, and the rising edge of WDQS can be aligned to the center of the eye diagram of PAR (the center inside the high level window). In the embodiment of the present application, this purpose can be achieved by training the write PAR pin to ensure that PAR can be correctly sampled, thereby ensuring the accuracy of data verification.

[0180] The following is a detailed description of the PAR writing training process in the embodiment of the present application:

[0181] The write PAR training algorithm in the embodiment of the present application includes two stages: stage one: Per bit training stage, stage two: Per Slice training stage. Specifically, the training process of the present application is as follows:

[0182] Step 1: HBM Host initiates HBM write operation;

[0183] Step 2: The HBM Host sends DQ, DM, and DBI as 0, but PAR is 4 bits of 1; that is, it sends the target write data (all 0s) and the target write verification data (all 1s) with fixed verification errors.

[0184] Step 3: Enter the per bit training phase and repeat steps 1 and 2. By adjusting the delay circuit of each bit of the target write verification data, the purpose of training each bit is achieved and the alignment of each bit is achieved, that is, the WDQS sampling edge in the window is aligned to the center position inside the high-level window of the PAR data of each bit.

[0185] Step 4: Enter the per slice training phase and repeat steps 1 and 2 to achieve overall data alignment by adjusting the delay circuit of the misaligned bits, that is, aligning all write PARs to the same WDQS sampling edge.

[0186] The following is a detailed description of the above two stages:

[0187] Phase 1: Per bit training phase.

[0188] like Fig.11 As shown, it is a schematic diagram of the initial state of a target write verification data in an embodiment of the present application. In the Per bit training stage, Fig.11 On this basis, the write PAR signal of each bit of the 4-bit PAR is aligned respectively, and the WDQS sampling edge in the window is aligned to the center position inside the high-level window of the PAR data of each bit.

[0189] Specifically, through stage one, the transmission delay of each second bit of the target write verification data can be adjusted respectively to obtain the delay parameters of each second bit of the target write verification data, that is, the parameters determined when the corresponding verification result changes from the first target value to the second target value.

[0190] See also FIG. 2A to FIG. 2C In the examples listed, when the sampling edge of WDQS is located at a non-edge position within the high-level window of the target write verification data, the HBM DRAM can correctly sample the target write verification data based on WDQS (here, it means that the HBM chip can correctly sample before starting the initial operation and is not affected by PVT, crosstalk between signals, etc.), among which, the sampling is most accurate when the sampling edge of WDQS is located at the center position within the high-level window of the target write verification data (for example, Figure 2A As shown), when the sampling edge of WDQS is located within the high level window of the target write verification data (for example Figure 2C As shown), it will cause problems in the HBM DRAM's sampling of the target write verification data, affecting the verification result DERR. Therefore, by detecting the critical point where the verification result changes from the first target value to the second target value, it can be determined whether the sampling edge of WDQS is located at an edge within the high level window of the target write verification data.

[0191] In an optional implementation, the delay parameter corresponding to each second bit position includes: a delay parameter to be adjusted up and a delay parameter to be adjusted down. The delay parameter of each second bit position can be determined in the following manner, and the following operations can be performed for each second bit position:

[0192] For a second bit, the transmission delay corresponding to the second bit is gradually increased. When the corresponding first bit in the check result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be increased for the second bit.

[0193] Specifically, this article takes a fixed check error as an example to explain in detail, taking PAR bit0 as an example. Fig.12As shown, it is a schematic diagram of a method for determining a delay parameter in an embodiment of the present application, wherein clock represents the sampling signal WDQS, and the initial state of the bit of the write PAR is phase 0 (i.e., it indicates that no transmission delay adjustment is made, and the WDQS sampling edge should be within the high-level window of the bit, and the state of correct sampling is possible). At this time, the value of the read-back DERR should be 1 (the first target value). By adjusting the Step Counter to continuously increase the circuit delay of the bit, eventually, the read-back value of the DERR should be 0 (the second target value). At this time, the state of the bit of the write PAR is recorded as phase 1, and the value of the Step Counter is recorded as R_CNT, which means that by increasing the transmission delay of the target write verification data of the bit, the arrival of PAR bit0 is delayed, and the left boundary of the high-level window of PAR bit0 is aligned with the sampling edge of WDQS, the parameters are determined.

[0194] It should be noted that the value of Step Counter represents the tap outlet from which the value of the corresponding bit of the write PAR should be taken. In fact, this value and the actual transmission delay need to be converted through the fixed value corresponding to the delay unit DE. For example, the fixed value corresponding to a DE is 1. Therefore, R_CNT can indicate that the bit needs to pass through R_CNT DEs, and can also indicate that the bit needs to pass through R_CNT delays. R_CNT can be recorded as the delay parameter to be adjusted. Of course, if the fixed value corresponding to a DE is other values, the corresponding conversion can be performed. For example, if the fixed value corresponding to a DE is 2, the delay parameter to be adjusted can represent the number of DEs, that is, set to R_CNT; it can also represent a specific delay value, that is, set to 2R_CNT (1 DE is 2, R_CNT DEs are 2R_CNT). The L_CNT in the following text is not specifically limited. The following is a detailed explanation based on the example of a fixed value corresponding to a DE of 1.

[0195] Similarly, when the transmission delay corresponding to the second bit is gradually reduced and the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be reduced for the second bit.

[0196] Still Fig.12For example, the process needs to first set the last adjusted PAR bit0 to the initial state from Phase1 to Phase0, and then continuously reduce the circuit delay of the bit by adjusting the Step Counter. Finally, the value of the read-back DERR should be 0 (the second target value). At this time, the state of the bit that writes PAR is recorded as phase 2. At this time, the value of the Step Counter is recorded as L_CNT, which means that by reducing the transmission delay of the target write verification data of the bit, PAR bit0 arrives in advance, and the right boundary of the high-level window of PAR bit0 is aligned with the sampling edge of WDQS, the parameters are determined.

[0197] Through the above adjustment, it can be calculated that when the circuit delay of the bit is (R_CNT+L_CNT) / 2, the sampling clock edge of the sampling signal and the high level center of the write verification data can be aligned for the bit.

[0198] Next, continue to adjust and calculate the circuit delay of each bit according to the above method, so that the sampling WDQS edge of each bit of write PAR can be aligned with the write PAR. At this point, the Per bit training phase ends.

[0199] In an optional implementation, before step S43, the method further includes:

[0200] If the second target value exists in each first bit of the verification result returned by the receiving end, it means that the sampling signal of the receiving end fails to correctly sample the target write verification data. Figure 2B As shown, the sampling edge of WDQS is outside the PAR high level window. In this case, the transmission frequency of the target write verification data can be gradually reduced until all the first bits of the verification result are the first target value.

[0201] Specifically, it can be achieved by lowering the operating frequency of HBM (the transmission frequency of the target write verification data is the same as the operating frequency of HBM), such as starting from 1.8GHz and then lowering it little by little. During the lowering process, the width of the high-level window corresponding to the corresponding data (or signal) is also increasing little by little. Therefore, by adjusting the frequency, the relative position of the sampling edge of WDQS and the high-level window of PAR can be gradually changed until the sampling edge of WDQS is located inside the high-level window of PAR, PAR can be correctly sampled, and all the first bits of the verification result become the first target value. Furthermore, on this basis, R_CNT and L_CNT can be further determined in the above manner to align each bit with the sampling edge of WDQS individually.

[0202] In the embodiment of the present application, after the delay parameters R_CNT and L_CNT corresponding to each second bit in the target write verification data are calculated in the above manner, the transmission mode of the write verification data to be transmitted can be set based on the delay parameters corresponding to each second bit in the target write verification data. The specific setting process is as follows:

[0203] First, the intermediate transmission delay corresponding to the target write verification data, ie, the circuit delay of each bit mentioned above, is determined according to the average values ​​of the delay parameters to be adjusted up and the delay parameters to be adjusted down corresponding to each second bit position.

[0204] In this step, the intermediate transmission delay corresponding to the target write verification data includes the intermediate transmission delay corresponding to each second bit position. Therefore, for each second bit position, it is first necessary to determine the average value of the delay parameter to be adjusted up and the delay parameter to be adjusted down corresponding to the second bit position; then, the transmission delay corresponding to the second bit position is adjusted up or down according to the average value to obtain the intermediate transmission delay corresponding to the second bit position. The following is an example of the upward adjustment.

[0205] For example, the delay parameters corresponding to PAR bit0 are R_CNT0 and L_CNT0. Therefore, the circuit delay of PAR bit0 can be increased by (R_CNT0+L_CNT0) / 2 to obtain the corresponding intermediate transmission delay.

[0206] The delay parameters corresponding to PAR bit1 are R_CNT1 and L_CNT1. Therefore, the circuit delay of PAR bit1 can be increased by (R_CNT1+L_CNT1) / 2 to obtain the corresponding intermediate transmission delay.

[0207] The delay parameters corresponding to PAR bit2 are R_CNT2 and L_CNT2. Therefore, the circuit delay of PAR bit2 can be increased by (R_CNT2+L_CNT2) / 2 to obtain the corresponding intermediate transmission delay.

[0208] The delay parameters corresponding to PAR bit3 are R_CNT3 and L_CNT3. Therefore, the circuit delay of PAR bit3 can be increased by (R_CNT3+L_CNT3) / 2 to obtain the corresponding intermediate transmission delay.

[0209] By setting the above circuit delay, the center of the high-level window of each bit of PAR can be aligned to the WDQS sampling edge. However, in this case, only the individual alignment of each bit is achieved, and PAR has a total of 4 bits. The center of the high-level window of these 4 bits may not be able to be aligned to the same sampling edge of WDQS.

[0210] There are two specific situations:

[0211] Case 1: After stage 1, the centers of the high-level windows of the four bits of PAR are aligned to the sampling edge of WDQS, and are the same sampling edge. In this case, there is no need to further execute stage 2.

[0212] like Fig.13 As shown, it is a schematic diagram of the alignment result of the target write verification data and the sampling signal in an embodiment of the present application. The schematic diagram shows an adjustment result of the first stage, and PAR bit0, PAR bit1, PAR bit2 and PAR bit3 are aligned to the same sampling edge of WDQS.

[0213] In this case, when the target write verification data is transmitted according to the intermediate transmission delay determined above, all first bits of the corresponding verification result are the first target value, and thus the write verification data to be transmitted can be set to be transmitted according to the intermediate transmission delay.

[0214] That is, for the write verification data to be transmitted, the circuit delay of PAR bit0 increases by (R_CNT0+L_CNT0) / 2 on the basis of the initial state, the circuit delay of PAR bit1 increases by (R_CNT1+L_CNT1) / 2 on the basis of the initial state, the circuit delay of PAR bit2 increases by (R_CNT2+L_CNT2) / 2 on the basis of the initial state, and the circuit delay of PAR bit3 increases by (R_CNT3+L_CNT3) / 2 on the basis of the initial state.

[0215] Case 2: After stage 1, the centers of the high-level windows of the four bits of PAR are aligned to the sampling edge of WDQS, but not to the same sampling edge of WDQS. In this case, stage 2 needs to be further executed.

[0216] like Fig.14 As shown, it is a schematic diagram of another alignment result of the target write verification data and the sampling signal in an embodiment of the present application, that is, a schematic diagram of another adjustment result of the first stage. The schematic diagram shows that PAR bit0, PAR bit1 and PAR bit3 are aligned to the same sampling edge of WDQS, that is, Fig.14 The sampling edge 1 in PAR bit2 is aligned to the other sampling edge of WDQS, that is, Fig.14 The sampling edge in 2.

[0217] In this case, when the target write verification data is transmitted according to the intermediate transmission delay, there is a second target value in each first bit of the corresponding verification result (such as the verification result DERR bit2 corresponding to PAR bit2 is 0), then it is necessary to adjust the corresponding transmission delay again according to the delay parameters (R_CNT2 and L_CNT2) of each target second bit (i.e., PAR bit2) until the target transmission delay corresponding to the target write verification data is obtained, so that when the target write verification data is transmitted according to the target transmission delay, all the first bits of the corresponding verification result are the first target value; and then, the write verification data to be transmitted is set to be transmitted according to the target transmission delay.

[0218] The following is a detailed introduction to the specific adjustment process of Phase 2:

[0219] Phase 2: Per Slice training phase.

[0220] like Fig.14 As shown in the figure, after the first stage, since the write PAR data of each bit has been aligned to the edge of the sampling WDQS, it can be guaranteed that each bit can be sampled correctly. However, there may be a situation where the bits within the 4 bits of the read PAR are not aligned, so this stage is used to solve the problem of misalignment between bits and align all write PARs to the same WDQS sampling edge.

[0221] Specifically, in the Per Slice training phase, first read the full write data, then:

[0222] If the first read DERR data is all 1, the bits have been aligned and this stage ends, which is the case 1 listed above;

[0223] If the read full-read data is a mixture of 0 and 1, which is the second case listed above, the path of the bit with a sampling value of 0 will continue to be moved until the read DERR value of this bit is 1; this step is repeated until the sampling value of the full-read data is all 1, and this stage ends.

[0224] Since different bits are aligned to the sampling edge of WDQS, but not the same sampling edge, an optional implementation is to move the path of the bit with a sampling value of 0 (that is, when the transmission delay of the target second bit continues to be adjusted). The movement value can be the result of (R_CNT+L_CNT) of the recorded bit, and the movement can be a left shift or a right shift.

[0225] In summary, an optional implementation is to perform the following operations for each target second bit:

[0226] For a target second bit position, the sum of the delay parameter to be adjusted up and the delay parameter to be adjusted down corresponding to the target second bit is used as the adjustment step, that is, R_CNT+L_CNT listed above; then, according to the adjustment step, based on the intermediate transmission delay corresponding to the target second bit position, the transmission delay of the target second bit position is continued to be adjusted until the corresponding first bit position in the verification result is the first target value.

[0227] like Fig.14 In the example, there is only one target second bit, which is PAR bit2. The corresponding intermediate transmission delay is (R_CNT2+L_CNT2) / 2, and the adjustment step is (R_CNT2+L_CNT2). Therefore, on the basis of (R_CNT2+L_CNT2) / 2, the transmission delay can be continuously increased or decreased with (R_CNT2+L_CNT2) as the adjustment step. Each time the adjustment is made, a full read of DERR is performed to determine whether the check result corresponding to the bit is changed to 1.

[0228] As shown in the PAR bit 2 listed above, it is obvious that the sampling edge 2 is only one clock cycle away from the sampling edge 1. For bit 2, the target write verification data of this bit needs to be Fig.14 Based on the initial state, it arrives one clock cycle earlier. Therefore, it is necessary to subtract (R_CNT2+L_CNT2) / 2 from (R_CNT2+L_CNT2). That is, the circuit delay of PAR bit2 is reduced by (R_CNT2+L_CNT2) / 2 from the initial state, while the circuit delays of the other three bits are increased by the corresponding average values ​​from the initial state. Finally, it can be achieved Fig.13 The effect described.

[0229] It should be noted that the above is only an example of a target second bit. If multiple 0s are found during the full read, such as bit0 and bit2, that is, the DERR obtained by the full read is 0101, then in the actual adjustment process, you can first check whether the check result corresponding to bit0 is read as zero according to the order of the bits. If so, you need to continue to adjust the transmission delay of bit0 and perform a full read. After adjusting the check result corresponding to bit0 to 1 (that is, the DERR obtained by the full read is 1101), then continue to check whether the check result corresponding to bit1 is read as 0. If not, continue to check whether the check result corresponding to bit2 is read as 0. If so, repeat the above adjustment process. After adjusting the check result corresponding to bit2 to 1 (that is, the DERR obtained by the full read is 1111), at this time, all the first bits of the obtained check results are the corresponding first target values, and the training can be terminated.

[0230] It should be noted that the several adjustment methods listed above are just simple examples. In actual practice, any method of making corresponding adjustments based on changes in verification results is applicable to the embodiments of the present application, and this article does not make specific limitations.

[0231] Based on the above implementation, the mechanism of the present application can be used to train the write PAR pin before the HBM chip brings up the initial work, so that when the chip is initially working, if the back-end timing does not converge and the HBM chip production failure causes the sampling error of the chip write PAR path, it can ensure that when the chip is initially working, the write PAR data received by the HBM DRAM is accurate, thereby ensuring that the HBM Host will not make mistakes in the process of verifying the write data. In addition, the mechanism of regular write PAR training included in the hardware can be used to regularly train the HBM chip to read PAR, so as to ensure that the chip will not make write PAR sampling errors during the working process.

[0232] It should also be noted that the above embodiment adopts an automatic training method implemented by a hardware circuit. In addition to this method, the entire training process can also be completed by using software to configure registers, that is, the value of the Step counter can be manually configured using the registers configured by the software, and the Host can be configured to send a write command and its write data and write PAR data, and the value of the DERR returned by the HBM DRAM can be verified. Therefore, the software can independently initiate each step of the single-step training of the write PAR, which will not be repeated in this article.

[0233] Based on the above implementation, when the HBM chip detects that the PVT has obvious drift, the software can configure the chip to train the write PAR pin to ensure that the chip will not cause data transmission errors in the chip write PAR path due to the drift of PVT. In addition, since the present application supports single-step write PAR training configured by software, the write PAR training of the entire chip can also be completed by software configuration alone. Since the software can complete this action when the system is not busy, it can ensure that the write PAR pin will not have sampling errors while ensuring the efficiency of the entire system.

[0234] Based on the same inventive concept, the embodiment of the present application also provides a data transmission configuration device. Fig.15 As shown, it is a schematic diagram of the structure of a data transmission configuration device 1500, which may include:

[0235] The first transmission unit 1501 is used to send the target write data to be written and the target write verification data used to verify the target write data to the receiving end;

[0236] The second transmission unit 1502 is used to receive the verification result returned by the receiving end, where the verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on the sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data one by one;

[0237] An adjusting unit 1503 is configured to determine, by adjusting the transmission delay of each second bit, the delay parameter corresponding to each second bit when the corresponding first bit in the verification result is changed from a first target value to a second target value; the first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly;

[0238] The configuration unit 1504 is used to set a transmission mode of the write verification data to be transmitted based on the delay parameters corresponding to the second bits in the target write verification data.

[0239] Optionally, the delay parameter includes a delay parameter to be adjusted up and a delay parameter to be adjusted down;

[0240] The adjustment unit 1503 is specifically used for:

[0241] For each second bit, perform the following operations:

[0242] For a second bit, gradually increase the transmission delay corresponding to the second bit, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as a delay parameter to be increased for a second bit; and

[0243] The transmission delay corresponding to a second bit is gradually reduced, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as a delay parameter to be reduced for a second bit.

[0244] Optionally, the delay parameter includes a delay parameter to be adjusted up and a delay parameter to be adjusted down;

[0245] The configuration unit 1504 is specifically used for:

[0246] Determine the intermediate transmission delay corresponding to the target write verification data according to the average values ​​of the delay parameters to be adjusted up and the delay parameters to be adjusted down corresponding to the second bits respectively;

[0247] If, when the target write verification data is transmitted according to the intermediate transmission delay, the second target value exists in each first bit of the corresponding verification result, the corresponding transmission delay is adjusted again according to the delay parameter of each target second bit until the target transmission delay corresponding to the target write verification data is obtained, so that when the target write verification data is transmitted according to the target transmission delay, each first bit of the corresponding verification result is all the first target value;

[0248] The write verification data to be transmitted is set to be transmitted according to the target transmission delay.

[0249] Optionally, the intermediate transmission delay corresponding to the target write verification data includes the intermediate transmission delay corresponding to each second bit position;

[0250] The configuration unit 1504 is specifically used for:

[0251] For each second bit, perform the following operations:

[0252] For a second bit, determining an average value of a delay parameter to be adjusted up and a delay parameter to be adjusted down corresponding to the second bit;

[0253] The transmission delay corresponding to a second bit is adjusted upward or downward according to the average value to obtain an intermediate transmission delay corresponding to the second bit.

[0254] Optionally, the configuration unit 1504 is further configured to:

[0255] If the target write verification data is transmitted according to the intermediate transmission delay, and the first bits of the corresponding verification result are all the first target values, the write verification data to be transmitted is set to be transmitted according to the intermediate transmission delay.

[0256] Optionally, the configuration unit 1504 is specifically configured to:

[0257] For each target second bit, perform the following operations:

[0258] For a target second bit, the sum of the delay parameter to be adjusted upward and the delay parameter to be adjusted downward corresponding to the target second bit is used as the adjustment step length;

[0259] The transmission delay of a target second bit is continuously adjusted according to the adjustment step size until the corresponding first bit in the verification result reaches the first target value.

[0260] Optionally, the adjusting unit 1503 is further configured to:

[0261] When determining that the corresponding first bit in the verification result is changed from the first target value to the second target value by adjusting the transmission delay of each second bit respectively, before the delay parameters corresponding to each second bit, if the second target value exists in each first bit of the verification result returned by the receiving end, the transmission frequency of the target write verification data is gradually reduced until all the first bits of the verification result are the first target value.

[0262] Optionally, the target write data and the target write verification data are data with fixed verification errors, the first target value indicates a verification error, and the second target value indicates a verification success; or

[0263] The target write data and the target write verification data are fixed data that have been verified to be correct. The first target value indicates that the verification is correct, and the second target value indicates that the verification is wrong.

[0264] Optionally, the adjusting unit 1503 is specifically configured to:

[0265] Inputting the target write verification data into a delay control circuit, wherein the delay control circuit includes a delay unit group corresponding to each second bit position;

[0266] For each second bit, perform the following operations:

[0267] For a second bit, the transmission delay of the second bit is adjusted by adjusting the number of delay units that the second bit passes through in the corresponding delay unit group; wherein each delay unit is used to increase the transmission delay of the passing data by a fixed value.

[0268] Optionally, each delay unit in the delay unit group corresponds to a tap interface; the adjustment unit 1503 is specifically used for:

[0269] The selection of the tap interface for outputting a second bit in the delay unit group is controlled by a step counter to adjust the transmission delay of the second bit.

[0270] Because the present application uses a method of adjusting the transmission delay of the write verification data before the HBM chip starts initial operation, the offset between the write verification data and the sampling signal is adjusted. Specifically, the target write data and the target write verification data are used as sample data for training, and the target write verification data is sent to the receiving end (HBM The target write data and the target write verification data are sent to a DRAM, and after the receiving end samples the target write data and the target write verification data based on the sampling signal, the target write data is verified by the target write verification data. When the expected sampling of these data is correct, the data of each bit in the obtained verification result is called the first target value; in the present application, based on this feature, the transmission delay of the target write verification data is adjusted, and the transmission delay can affect the offset between the target write verification data and the sampling signal, so as to affect the accuracy of data sampling, and further affect the correctness of the verification result; when the corresponding first bit in the verification result is changed from the first target value to the second target value, it indicates that the offset between the sampling signal and the write verification data is at the critical point of the sampling error at this time, and the transmission mode of the write verification data to be transmitted is set based on the delay parameter determined at this time, which can effectively control the offset between the write verification data to be transmitted and the sampling signal when the chip is initially working, so as to ensure that the write verification data to be transmitted received by the receiving end can be accurately sampled, thereby ensuring the accuracy of the verification.

[0271] For the convenience of description, the above parts are divided into modules (or units) according to their functions and described separately. Of course, when implementing this application, the functions of each module (or unit) can be implemented in the same or multiple software or hardware.

[0272] After introducing the data transmission configuration method and device according to the exemplary embodiment of the present application, next, an electronic device according to another exemplary embodiment of the present application is introduced.

[0273] Those skilled in the art will appreciate that various aspects of the present application may be implemented as a system, method or program product. Therefore, various aspects of the present application may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to as "circuit", "module" or "system" herein.

[0274] Based on the same inventive concept as the above method embodiment, an electronic device is also provided in the embodiment of the present application. In this embodiment, the structure of the electronic device can be as follows: Fig.16 As shown, it includes a memory 1601 , a communication module 1603 and one or more processors 1602 .

[0275] The memory 1601 is used to store computer programs executed by the processor 1602. The memory 1601 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and programs required for running the instant messaging function, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.

[0276] The memory 1601 may be a high bandwidth memory HBM. In addition, the memory 1601 may be a volatile memory, such as a random access memory (RAM); the memory 1601 may also be a non-volatile memory, such as a read-only memory, a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); or the memory 1601 is any other medium that can be used to carry or store a desired computer program in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 1601 may be a combination of the above memories.

[0277] The processor 1602 may include one or more central processing units (CPU) or a digital processing unit, etc. The processor 1602 is configured to implement the above data transmission configuration method when calling the computer program stored in the memory 1601 .

[0278] The communication module 1603 is used to communicate with terminal devices and other servers.

[0279] The specific connection medium between the memory 1601, the communication module 1603 and the processor 1602 is not limited in the embodiment of the present application. Fig.16 In the embodiment, the memory 1601 and the processor 1602 are connected via a bus 1604. The bus 1604 is connected to the processor 1602 via a bus 1604. Fig.16 The connections between the other components are only for illustration and are not intended to be limiting. The bus 1604 can be divided into an address bus, a data bus, a control bus, etc. For ease of description, Fig.16 The diagram shows that only one thick line is used, but this does not mean that there is only one bus or only one type of bus.

[0280] The memory 1601 stores a computer storage medium, and the computer storage medium stores computer executable instructions, and the computer executable instructions are used to implement the data transmission configuration method of the embodiment of the present application. The processor 1602 is used to execute the above-mentioned data transmission configuration method, such as Figure 4 shown.

[0281] In some possible implementations, a computing device is also provided according to the present application, and the computing device may include at least one processor and at least one memory. The memory stores program code, and when the program code is executed by the processor, the processor executes the steps in the method for training a recommendation probability prediction model or the steps in the recommendation probability prediction method described above in this specification according to various exemplary implementations of the present application. For example, the processor may execute the following steps: Figure 4 Follow the steps shown in .

[0282] Refer to the following Fig.17 hereinafter, a computing device 170 according to this embodiment of the present application is described. Fig.17 The computing device 170 is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0283] like Fig.17 The computing device 170 is in the form of a general computing device. The components of the computing device 170 may include, but are not limited to: at least one processing unit 171, at least one storage unit 172, and a bus 173 connecting different system components (including the storage unit 172 and the processing unit 171).

[0284] Bus 173 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

[0285] The storage unit 172 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 1721 and / or a cache memory 722 , and may further include a read-only memory (ROM) 1723 .

[0286] The storage unit 172 may also include a program / utility 1725 having a set (at least one) of program modules 1724, such program modules 1724 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0287] The computing device 170 may also communicate with one or more external devices 174 (e.g., keyboards, pointing devices, etc.), one or more devices that enable a user to interact with the computing device 170, and / or any device that enables the computing device 170 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 175. In addition, the computing device 170 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 176. As shown, the network adapter 176 communicates with other modules for the computing device 170 via a bus 173. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the computing device 170, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0288] In some possible implementations, various aspects of the data transmission configuration method provided in the present application may also be implemented in the form of a program product, which includes a computer program. When the program product is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of the data transmission configuration method according to various exemplary implementations of the present application described above in this specification. For example, the electronic device may execute the following steps: Figure 4 Follow the steps shown in .

[0289] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0290] The program product of the embodiment of the present application may adopt a portable compact disk read-only memory (CD-ROM) and include a computer program, and can be run on an electronic device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium containing or storing a program, which can be used by or in combination with a command execution system, apparatus, or device.

[0291] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, wherein a readable computer program is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with a command execution system, apparatus, or device.

[0292] The computer program embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0293] The computer program for performing the operation of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and also conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer program can be executed entirely on the user electronic device, partially on the user electronic device, as a separate software package, partially on the user electronic device and partially on a remote electronic device, or entirely on a remote electronic device or server. In the case of a remote electronic device, the remote electronic device can be connected to the user electronic device through any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external electronic device (for example, using an Internet service provider to connect through the Internet).

[0294] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided into multiple units to be embodied.

[0295] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0296] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain a computer-usable computer program.

[0297] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program commands. These computer program commands can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the commands executed by the processor of the computer or other programmable data processing device generate commands for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0298] These computer program commands may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the commands stored in the computer readable memory produce an article of manufacture comprising a command device, the command device implementing the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0299] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0300] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data transmission configuration method, characterized in that: The method includes: Sending to a receiving end target write data to be written and target write verification data for verifying the target write data; receiving a verification result returned by the receiving end, wherein the verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on a sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data in a one-to-one manner; Determine, by adjusting the transmission delay of each of the second bits, the delay parameter corresponding to each of the second bits when the corresponding first bit in the verification result is changed from the first target value to the second target value; the first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly; Based on the delay parameters corresponding to the second bits in the target write verification data, a transmission mode of the write verification data to be transmitted is set.

2. The method according to claim 1, characterized in that The delay parameters include a delay parameter to be adjusted upward and a delay parameter to be adjusted downward; The respectively adjusting the transmission delays of the respective second bits to determine when the corresponding first bit in the verification result is changed from the first target value to the second target value, the delay parameters corresponding to the respective second bits include: For each second bit, the following operations are performed respectively: For a second bit, gradually increase the transmission delay corresponding to the second bit, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be increased for the second bit; and The transmission delay corresponding to the one second bit is gradually reduced, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be reduced of the one second bit.

3. The method according to claim 1 or 2, characterized in that The delay parameters include a delay parameter to be adjusted upward and a delay parameter to be adjusted downward; The step of setting a transmission mode of the write verification data to be transmitted based on the delay parameters corresponding to the second bits in the target write verification data includes: Determine the intermediate transmission delay corresponding to the target write verification data according to the delay parameters to be adjusted up and the average values ​​of the delay parameters to be adjusted down corresponding to the second bits respectively; If, when the target write verification data is transmitted according to the intermediate transmission delay, the corresponding first bits of the verification result have a second target value, the corresponding transmission delay is adjusted again according to the delay parameter of each target second bit until the target transmission delay corresponding to the target write verification data is obtained, so that when the target write verification data is transmitted according to the target transmission delay, the corresponding first bits of the verification result are all the first target values; The write verification data to be transmitted is set to be transmitted according to the target transmission delay.

4. The method according to claim 3, characterized in that The intermediate transmission delay corresponding to the target write verification data includes the intermediate transmission delay corresponding to each of the second bits; The determining the intermediate transmission delay corresponding to the target write verification data according to the delay parameters to be adjusted up and the average values ​​of the delay parameters to be adjusted down corresponding to the second bits respectively includes: For each second bit, the following operations are performed respectively: For a second bit position, determining an average value of the delay parameter to be adjusted upward and the delay parameter to be adjusted downward corresponding to the second bit position; The transmission delay corresponding to the one second bit is adjusted upward or downward according to the average value to obtain an intermediate transmission delay corresponding to the one second bit.

5. The method according to claim 3, characterized in that The method further comprises: If, when the target write verification data is transmitted according to the intermediate transmission delay, all first bits of the corresponding verification result are first target values, the write verification data to be transmitted is set to be transmitted according to the intermediate transmission delay.

6. The method according to claim 3, characterized in that The step of adjusting the corresponding transmission delay again according to the delay parameter of each target second bit until a target transmission delay corresponding to the target write verification data is obtained includes: For each target second bit, perform the following operations: For a target second bit, the sum of the delay parameter to be adjusted upward and the delay parameter to be adjusted downward corresponding to the target second bit is used as the adjustment step size; According to the adjustment step, the transmission delay of the target second bit continues to be adjusted until the corresponding first bit in the verification result is the first target value.

7. The method according to claim 1, characterized in that When determining that the corresponding first bit in the verification result is changed from the first target value to the second target value by adjusting the transmission delay of each second bit respectively, before the delay parameters corresponding to each second bit respectively, the method further includes: If the second target value exists in each first bit of the verification result returned by the receiving end, the transmission frequency of the target write verification data is gradually reduced until all the first bits of the verification result are the first target value.

8. The method according to any one of claims 1 to 2, 4 to 7, characterized in that: The target write data and the target write verification data are data with fixed verification errors, the first target value indicates a verification error, and the second target value indicates a verification success; or The target write data and the target write verification data are fixedly verified correct data, the first target value indicates a correct verification, and the second target value indicates a verification error.

9. The method according to any one of claims 1 to 2, 4 to 7, characterized in that: The respectively adjusting the transmission delay of each of the second bits comprises: Inputting the target write verification data into a delay control circuit, wherein the delay control circuit includes a delay unit group corresponding to each of the second bits; For each second bit, perform the following operations: For a second bit, the transmission delay of the second bit is adjusted by adjusting the number of delay units that the second bit passes through in the corresponding delay unit group; wherein each delay unit is used to increase the transmission delay of the passing data by a fixed value.

10. The method according to claim 9, characterized in that Each delay unit in the delay unit group corresponds to a tap interface; and adjusting the transmission delay of the second bit by adjusting the number of delay units passed by the second bit in the corresponding delay unit group includes: The selection of the tap interface for outputting the one second bit in the delay unit group is controlled by a step counter to adjust the transmission delay of the one second bit.

11. A data transmission configuration device, characterized in that: include: A first transmission unit, used for sending target write data to be written and target write verification data for verifying the target write data to a receiving end; a second transmission unit, configured to receive a verification result returned by the receiving end, wherein the verification result is obtained after the receiving end performs sampling verification on the target write data and the target write verification data based on a sampling signal, and each first bit of the verification result corresponds to each second bit of the target write verification data in a one-to-one correspondence; an adjusting unit, configured to determine, by adjusting the transmission delays of the second bits, the delay parameters corresponding to the second bits when the corresponding first bit in the verification result is changed from a first target value to a second target value; the first target value is the verification result when the corresponding second bit is expected to be sampled correctly, and the second target value is the verification result when the corresponding second bit is expected to be sampled incorrectly; A configuration unit is used to set a transmission mode of the write verification data to be transmitted based on the delay parameters corresponding to each second bit position in the target write verification data.

12. The device according to claim 11, characterized in that The delay parameters include a delay parameter to be adjusted upward and a delay parameter to be adjusted downward; The adjustment unit is specifically used for: For each second bit, the following operations are performed respectively: For a second bit, gradually increase the transmission delay corresponding to the second bit, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be increased for the second bit; as well as The transmission delay corresponding to the one second bit is gradually reduced, and when the corresponding first bit in the verification result is changed from the first target value to the second target value, the corresponding transmission delay is used as the delay parameter to be reduced of the one second bit.

13. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of any one of the methods of claims 1 to 10.

14. A computer-readable storage medium, characterized in that: The method comprises a computer program. When the computer program is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of any one of the methods of claims 1 to 10.

15. A computer program product, characterized in that The method comprises a computer program stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device executes the steps of any one of the methods described in claims 1 to 10.

Images