A circuit and method for implementing data bus polling to avoid the rising edge of PCIe_RST.

Abstract

This invention proposes a circuit for implementing data bus polling to avoid the rising edge of PCIe_RST. The circuit includes a logic delay circuit and a data bus buffer chip. The input of the logic delay circuit is connected to the PCIe slot and the PCIe_RST pin of the PCIe device, respectively. The output of the logic delay circuit is connected to the control terminal of the data bus buffer chip. The data input of the data bus buffer chip is connected to the data bus, and the data output is connected to the bus device. The logic delay circuit is configured to output a high-level signal after a delay when a PCIe device is inserted into the connected PCIe slot and the PCIe_RST pin transitions from low to high. The data bus buffer chip is configured to control the conduction of the data bus and the bus device in response to receiving the high-level signal. This invention can specifically implement data bus polling to avoid the rising edge of PCIe_RST for a specific PCIe slot without affecting devices in other slots. Furthermore, because it does not rely on program code, it is safer and more reliable.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a circuit and method for implementing data bus polling to avoid the rising edge of PCIE_RST. Background Technology

[0002] PCIe (Eeripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard with very strict timing requirements. Some PCIe devices, such as certain RAID (Redundant Arrays of Independent Disks) cards, require that no data transmission occur on the SMBUS bus during the rising edge of PCIe_RST; that is, data transmission is not allowed on the data bus connected to the card during its reset process. During server boot, the BMC (Baseboard Management Controller) polls and the BIOS (Basic Input Output System) initializes. The BMC polling process polls all PCIe devices via the data bus, while the BIOS initialization process resets all PCIe devices. Since the BMC polling and BIOS initialization processes are independent, there is a certain probability that during a server boot, data transmission may occur on the SMBUS bus at the rising edge of PCIe_RST, causing the server to crash.

[0003] To prevent SMBUS bus polling from the rising edge of PCIE_RST, BMC needs to adapt a new version of BMC firmware for this specific RAID card model to disable polling of PCIE devices during boot. However, since a server has multiple PCIE interfaces, a specific RAID card may be installed in any PCIE slot due to different configurations. BMC cannot release a separate firmware for each PCIE slot to disable polling for that slot. Therefore, the current approach is to indiscriminately disable polling of all SMBUS channels involving PCIE slots during boot. However, this can cause some channels that need to maintain constant polling to malfunction. Summary of the Invention

[0004] To address the issue that BMC cannot release a separate firmware for each PCIe slot to block it, it indiscriminately blocks polling of all SMBUS channels involving PCIe slots during boot, causing anomalies in channels that require constant polling. To solve this problem, in a first aspect of this invention, a circuit is proposed to implement data bus polling to avoid the rising edge of PCIe_RST, comprising: a logic delay circuit and a data bus buffer chip. The input of the logic delay circuit is connected to the PCIe slot and the PCIe_RST terminal of the PCIe device, respectively. The output of the logic delay circuit is connected to the control terminal of the data bus buffer chip. The data input of the data bus buffer chip is connected to the data bus, and the data output is connected to the bus device. The logic delay circuit is configured to delay and output a high-level signal when a PCIe device is inserted into the connected PCIe slot and the PCIe_RST terminal transitions from low to high. The data bus buffer chip is configured to control the conduction of the data bus and the bus device in response to receiving the high-level signal.

[0005] In one or more embodiments, the logic delay circuit includes: a NOT gate, an AND gate, a capacitor, and a resistor; wherein, the input terminal of the NOT gate is connected to the PCIe slot, the output terminal is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is connected to the PCIe_RST terminal, the output terminal of the AND gate is connected to the control terminal of the data bus buffer chip through the resistor, one end of the capacitor is connected to the control terminal of the data bus buffer chip, and the other end is connected to the ground terminal of the data bus buffer chip.

[0006] In one or more embodiments, the logic delay circuit is further configured to: when a PCIe device is inserted into the PCIe slot connected thereto, the NOT gate outputs a high-level signal; when the PCIe_RST terminal changes from low to high, the AND gate is turned on, the capacitor is charged and pulls down the control terminal of the data bus buffer chip, keeping the control terminal of the data bus buffer chip in a low-level state; when the capacitor is fully charged, the capacitor disconnects the ground, allowing the control terminal of the data bus buffer chip to obtain a high-level signal.

[0007] In one or more embodiments, the logic delay circuit is further configured to: when no PCIe device is inserted into the PCIe slot connected thereto, the NOT gate outputs a low level, causing the AND gate to output a low level signal, causing the control terminal of the data bus buffer chip to remain in a low level state, and causing the data bus to remain disconnected from the PCIe slot.

[0008] In one or more embodiments, the data bus includes an SMBUS bus or a PCIE bus, and the bus device includes a PCIE device or an I2C device.

[0009] In one or more embodiments, the data bus buffer chip includes multiple data buffer channels.

[0010] In one or more embodiments, multiple resistors are connected in parallel between the input and output terminals of the plurality of data buffer channels.

[0011] In a second aspect of the invention, a method for polling a data bus to avoid the rising edge of PCIE_RST is provided. The method includes: setting a data bus buffer chip between the data bus and the bus device; controlling the conduction of the data bus buffer chip by the signal of the PCIE_RST terminal of the PCIE device and the presence signal of the PCIE device, such that when a PCIE device is inserted into the PCIE slot and the PCIE_RST terminal transitions from low to high, a high-level signal is output to the control terminal of the data bus buffer chip after a delay, so as to control the data bus buffer chip to delay the conduction of the data bus and the bus device.

[0012] In one or more embodiments, the method further includes: when a PCIe device is not inserted into the PCIe slot, controlling the output of a low-level signal to keep the control terminal of the data bus buffer chip in a low-level state, thereby keeping the data bus disconnected from the PCIe slot.

[0013] In one or more embodiments, the data bus includes an SMBUS bus or a PCIE bus, and the bus device includes a PCIE device or an I2C device.

[0014] The beneficial effects of this invention include: The circuit or method for implementing data bus polling to avoid the rising edge of PCIE_RST eliminates the need for firmware upgrades. Instead, it allows for targeted data bus polling to avoid the rising edge of PCIE_RST for specific PCIE slots, without affecting devices in other slots. This avoids the problem that firmware upgrades indiscriminately block polling of all SMBUS channels involving PCIE slots during boot, which can cause abnormalities in channels that require constant polling. Furthermore, since this invention does not rely on program code, it is more secure and reliable. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0016] Figure 1 The circuit diagram for the present invention to implement data bus polling to avoid the rising edge of PCIE_RST;

[0017] Figure 2 This is a flowchart illustrating the method for implementing data bus polling to avoid the rising edge of PCIE_RST according to the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0019] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0020] To address the issue that BMC cannot release a separate firmware update for each PCIe slot to disable it, it indiscriminately blocks polling of all SMBUS channels involving PCIe slots during boot, causing malfunctions in channels that require constant polling. To solve this problem, this invention proposes a circuit that enables data bus polling to avoid the rising edge of PCIe_RST, thus resolving the issue without firmware upgrades.

[0021] Figure 1 This is a circuit diagram illustrating the circuitry for implementing data bus polling to avoid the rising edge of PCIE_RST according to the present invention. Figure 1As shown, the circuit for polling the data bus to avoid the rising edge of PCIE_RST according to the present invention includes: a logic delay circuit 100 and a data bus buffer chip 200. The input terminal of the logic delay circuit 100 is connected to the PCIE slot (PRSNT_N) and the PCIE_RST terminal of the PCIE device, respectively. The output terminal of the logic delay circuit 100 is connected to the control terminal of the data bus buffer chip 200. The data input terminal of the data bus buffer chip 200 is connected to the data bus, and the data output terminal is connected to the bus device. Furthermore, the logic delay circuit 100 is configured to delay and output a high-level signal when a PCIE device is inserted into the PCIE slot connected to it and the PCIE_RST terminal changes from low to high. The data bus buffer chip 200 is configured to control the conduction of the data bus and the bus device in response to receiving the high-level signal.

[0022] Specifically, the data bus buffer chip 200 of this invention has multiple data buffer channels, which are controlled to be turned on or off by the control terminal of the data bus buffer chip 200. Specifically, whenever the control terminal of the data bus buffer chip 200 receives a high-level pulse, it controls the multiple data buffer channels to be turned on or off once. In the scheme of this invention, initially, the multiple data buffer channels are all in an off state, that is, the data bus remains disconnected from the bus devices. When the control terminal of the data bus buffer chip receives a high-level signal for the first time, the multiple data buffer channels will be turned on under control. To achieve data bus polling to avoid the rising edge of PCIE_RST, this invention sets a logic delay circuit 100 so that whenever the first reset signal received after a PCIE device is inserted into the PCIE slot (i.e., the PCIE_RST terminal will generate a rising edge) is received, a high-level signal will be output after a delay to delay the control of the multiple data buffer channels, thereby delaying the BMC's polling operation on the aforementioned PCIE device. The data bus includes an SMBUS bus or a PCIE bus, and the bus devices include PCIE devices or I2C devices.

[0023] As described above, the technical solution of this invention eliminates the need for firmware upgrades to achieve data bus polling avoidance of the PCIE_RST rising edge. Instead, it can specifically target specific PCIE slots to achieve data bus polling avoidance of the PCIE_RST rising edge without affecting devices in other slots. This avoids the problem that firmware upgrades indiscriminately block all SMBUS channel polling involving PCIE slots during boot, which can cause abnormalities in channels that require constant polling. Furthermore, since this invention does not rely on program code, it is more secure and reliable.

[0024] In one specific embodiment, the logic delay circuit 100 includes: a NOT gate 101, an AND gate 102, a capacitor 103, and a resistor 104. The input terminal of the NOT gate 101 is connected to the PCIe slot (PRSNT_N), and its output terminal is connected to the first input terminal of the AND gate 102. The second input terminal of the AND gate 102 is connected to the PCIe_RST terminal. The output terminal of the AND gate 102 is connected to the control terminal of the data bus buffer chip 200 through the resistor 104. One end of the capacitor 103 is connected to the control terminal of the data bus buffer chip 200, and the other end is connected to the ground terminal of the data bus buffer chip 200. During use, the ground terminal of the data bus buffer chip must be grounded.

[0025] Specifically, the working principle of the logic delay circuit 100 includes: when a PCIe device is inserted into the PCIe slot connected to it, the NOT gate 101 outputs a high-level signal; when the PCIe_RST terminal changes from low to high, the AND gate 102 is turned on, the capacitor 103 is charged and pulls down the control terminal of the data bus buffer chip 200, keeping the control terminal of the data bus buffer chip 200 in a low-level state; when the capacitor 103 is fully charged, the ground is disconnected by the capacitor 103, so that the control terminal of the data bus buffer chip 200 receives a high-level signal.

[0026] It should be noted that the combination of NOT and AND gates in the logic delay circuit of this invention is not the only solution. The purpose of the logic delay circuit is to ensure that when a PCIe device is detected to be present and when the PCIe device receives a reset signal, the delayed output controls multiple data buffer channels of the data bus buffer chip to be turned on, thereby enabling the data bus to connect with the bus device. Therefore, the combination of NOT and AND gates can be replaced by other more complex logic circuits that achieve the same function. This paper will not elaborate further on other more complex logic circuits that achieve the same function.

[0027] In a further embodiment, the logic delay circuit is configured to: when no PCIe device is inserted into the PCIe slot connected thereto, the NOT gate outputs a low level, causing the AND gate to output a low level signal, which in turn causes the control terminal of the data bus buffer chip to remain in a low level state, thereby keeping the data bus disconnected from the PCIe slot.

[0028] In a further embodiment, the data bus in the present invention includes an SMBUS bus or a PCIE bus, and the bus device includes a PCIE device or an I2C device.

[0029] Specifically, SMBUS and PCIe are two commonly used PCIe device buses. SMBUS allows the BMC or other devices to manage and interact with PCIe devices via SMBUS. Although in this embodiment, the solution of the present invention is mainly applied to controlling PCIe devices to achieve data bus polling to avoid the rising edge of PCIe_RST, it is also applicable to other I2C devices with strict timing requirements, and can similarly achieve data bus polling to avoid the reset operation of the I2C device.

[0030] In a further embodiment, multiple resistors are connected in parallel between the input and output terminals of the multiple data buffer channels.

[0031] Figure 2 This is a flowchart illustrating the method for avoiding the rising edge of PCIE_RST during data bus polling according to the present invention. Figure 2 The flowchart of the method for polling the data bus to avoid the rising edge of PCIE_RST according to the present invention includes: step S1, setting a data bus buffer chip between the data bus and the bus device; step S2, controlling the conduction of the data bus buffer chip by the signal of the PCIE_RST terminal of the PCIE device and the presence signal of the PCIE device, and causing a delay in outputting a high-level signal to the control terminal of the data bus buffer chip when the PCIE slot is inserted into the PCIE device and the PCIE_RST terminal changes from low level to high level, so as to control the data bus buffer chip to delay the conduction of the data bus and the bus device.

[0032] In a further embodiment, the method of the present invention for polling the data bus to avoid the rising edge of PCIE_RST further includes: when a PCIE device is not inserted into the PCIE slot, controlling the output of a low-level signal to keep the control terminal of the data bus buffer chip in a low-level state, so that the data bus remains disconnected from the PCIE slot.

[0033] The method for avoiding the rising edge of PCIe_RST during data bus polling, as described in this invention, eliminates the need for firmware upgrades. Instead, it targets specific PCIe slots, allowing for targeted avoidance of PCIe_RST polling without affecting devices in other slots. This avoids the problem where firmware upgrades indiscriminately block polling of all SMBUS channels involving PCIe slots during boot, potentially causing issues with channels requiring constant polling. Furthermore, because this invention does not rely on program code, it is more secure and reliable.

[0034] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0035] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0036] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A circuit for implementing data bus polling to avoid the rising edge of PCIe_RST, characterized in that, include: The system includes a logic delay circuit and a data bus buffer chip. The input terminal of the logic delay circuit is connected to the PCIe slot and the PCIe_RST terminal of the PCIe device, respectively. The output terminal of the logic delay circuit is connected to the control terminal of the data bus buffer chip. The data input terminal of the data bus buffer chip is connected to the data bus, and the data output terminal is connected to the bus device. The logic delay circuit is configured to delay outputting a high-level signal when a PCIe device is inserted into the PCIe slot connected to it and the PCIe_RST terminal changes from low to high. The data bus buffer chip is configured to control the connection of the data bus and the bus device in response to receiving the high-level signal.

2. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 1, characterized in that, The logic delay circuit includes: NOT gates, AND gates, capacitors, and resistors; The input terminal of the NOT gate is connected to the PCIe slot, and the output terminal is connected to the first input terminal of the AND gate. The second input terminal of the AND gate is connected to the PCIe_RST terminal. The output terminal of the AND gate is connected to the control terminal of the data bus buffer chip through the resistor. One end of the capacitor is connected to the control terminal of the data bus buffer chip, and the other end is connected to the ground terminal of the data bus buffer chip.

3. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 2, characterized in that, The logic delay circuit configuration is also used for: When a PCIe device is inserted into the PCIe slot connected to it, the NOT gate outputs a high-level signal; When the PCIE_RST terminal changes from low to high, the AND gate circuit is turned on, the capacitor is charged and pulls the control terminal of the data bus buffer chip low, so that the control terminal of the data bus buffer chip remains in a low state. When the capacitor is fully charged, it disconnects from the ground, allowing the control terminal of the data bus buffer chip to receive a high-level signal.

4. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 2, characterized in that, The logic delay circuit configuration is also used for: When no PCIe device is inserted into the PCIe slot connected to it, the NOT gate outputs a low level, which causes the AND gate to output a low level signal, keeping the control terminal of the data bus buffer chip at a low level, thus keeping the data bus disconnected from the PCIe slot.

5. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 1, characterized in that, The data bus includes an SMBUS bus or a PCIE bus, and the bus device includes a PCIE device or an I2C device.

6. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 1, characterized in that, The data bus buffer chip includes multiple data buffer channels.

7. The circuit for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 6, characterized in that, Multiple resistors are connected in parallel between the input and output terminals of the multiple data buffer channels.

8. A method for implementing data bus polling to avoid the rising edge of PCIe_RST, characterized in that, The method includes: A data bus buffer chip is installed between the data bus and the bus devices; The signal at the PCIE_RST terminal of the PCIE device and the presence signal of the PCIE device control the conduction of the data bus buffer chip, so that when a PCIE device is inserted into the PCIE slot and the PCIE_RST terminal transitions from low to high, a high-level signal is output to the control terminal of the data bus buffer chip after a delay, thereby controlling the data bus buffer chip to conduct the data bus and the bus device after a delay.

9. The method for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 8, characterized in that, The method further includes: When no PCIe device is inserted into the PCIe slot, the control output is low, causing the control terminal of the data bus buffer chip to remain low, thus keeping the data bus disconnected from the PCIe slot.

10. The method for implementing data bus polling to avoid the rising edge of PCIE_RST according to claim 8, characterized in that, The data bus includes an SMBUS bus or a PCIE bus, and the bus device includes a PCIE device or an I2C device.

Images