Semiconductor memory and data protection method

Abstract

The present disclosure provides a semiconductor memory and a data protection method. The semiconductor memory includes a memory array, a switch circuit, a control circuit, and a power cut-off monitoring circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power cut-off monitoring circuit is coupled to the control circuit and the power supply voltage. The power cut-off monitoring circuit is used to determine whether the power supply voltage drops below a first power cut-off detection level during writing, so as to output a trigger signal to the control circuit. The control circuit executes a reset procedure of the semiconductor memory according to the trigger signal. The first power cut-off detection level is lower than the minimum value of the power supply voltage recorded in the data table of the semiconductor memory.

Description

Technical Field

[0001] The present disclosure relates to a storage device, and more particularly to a semiconductor memory and a data protection method. Background Art

[0002] A general NAND flash memory has a problem of power failure interference. In this regard, the problem of power failure interference may be caused by unexpected power failure during data writing of the memory. Specifically, during the period when the memory performs a data program on the current page in the memory array of the memory, if the power supply voltage of the memory drops momentarily, the data cannot be successfully written to the current page in the memory array, and the data previously recorded in the previous page or other adjacent pages of the memory array may be lost or damaged. Therefore, regarding how to provide a data protection function to protect the data previously written in the memory when the power supply drops unexpectedly to stop operating, the following provides solutions of several embodiments. Summary of the invention

[0003] The present disclosure relates to a semiconductor memory and a data protection method, and can operate an effective data protection function.

[0004] The semiconductor memory disclosed in the present invention comprises a memory array, a switch circuit, a control circuit and a power cut-off monitoring circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power cut-off monitoring circuit is coupled to the control circuit and the power supply voltage. The power cut-off monitoring circuit is used to determine whether the power supply voltage drops below a first power cut-off detection level during writing, so as to output a trigger signal to the control circuit. The control circuit executes a reset procedure of the semiconductor memory according to the trigger signal. The first power cut-off detection level is lower than the minimum value of the power supply voltage recorded in the data sheet of the semiconductor memory.

[0005] The data protection method of the semiconductor memory disclosed in the present invention includes the following steps: executing a write operation of the semiconductor memory during the write period by a control circuit; determining whether the power supply voltage drops below a first power supply cut-off detection level during the write period by a power supply cut-off monitoring circuit; when the power supply voltage drops below the first power supply cut-off detection level, outputting a trigger signal to the control circuit by the power supply cut-off monitoring circuit; and executing a reset procedure of the semiconductor memory according to the trigger signal by the control circuit, wherein the first power supply cut-off detection level is lower than the minimum value of the power supply voltage recorded in the data table of the semiconductor memory.

[0006] Based on the above, according to the semiconductor memory and data protection method of the present disclosure, during writing, the semiconductor memory can automatically monitor whether the power supply voltage unexpectedly drops below the first power cutoff detection level to automatically perform data protection to prevent instantaneous power failure.

[0007] In order to make the foregoing content more easily understood, several embodiments are described in detail below with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 2 is a schematic diagram showing a semiconductor memory according to an embodiment of the present disclosure.

[0009] Figure 2 A schematic diagram showing a memory array and its peripheral circuits according to an embodiment of the present disclosure.

[0010] Figure 3 The flowchart is a data protection method according to an embodiment of the present disclosure.

[0011] Figure 4 FIG. 4 is a voltage waveform diagram showing a power supply voltage according to an embodiment of the present disclosure.

[0012] Figure 5 FIG. 1 is a schematic diagram showing a power cut-off monitoring circuit according to an embodiment of the present disclosure.

[0013] Figure 6 FIG. 4 is a voltage relationship diagram showing a power supply voltage and an output voltage according to another embodiment of the present disclosure.

[0014] Figure 7 FIG. 4 is a flowchart illustrating a reset procedure according to an embodiment of the present disclosure.

[0015]

Explanation of symbols

[0016] 100: Semiconductor memory

[0017] 110: Control circuit

[0018] 120: Power cut monitoring circuit

[0019] 121: Voltage Divider

[0020] 122: Voltage generator

[0021] 123: Comparator

[0022] 130: Charge pump circuit

[0023] 131: first charge pump

[0024] 132: Second charge pump

[0025] 140: Switching circuit

[0026] 141: First Decoder

[0027] 142: Second decoder

[0028] 143: Third Decoder

[0029] 150:Memory array

[0030] 151_1~151_P: Page buffer

[0031] BLSe, BLSo: bit line selection signal

[0032] C(0,0)~C(n,m): memory area

[0033] CS1_1~CS1_K、CS2_1~CS2_K、SD_0~SD_m、SS_0~SS_m、BLe_1~BLe_P、BLo_1~BLo_P:Selection switch

[0034] GSGD, GSGS: Global selection gate lines

[0035] GWL0~GWLn: global word line

[0036] LWL0~LWLn: local word line

[0037] PASV: Select signal

[0038] S310, S320, S330, S340, S710, S720, S730: Steps

[0039] SGD, SGS: select gate line

[0040] SL: Select Line

[0041] t0: time

[0042] VCC: power supply voltage

[0043] V_div: divided voltage

[0044] V_Max: Maximum voltage level

[0045] V_min: minimum voltage level

[0046] Vo: output signal

[0047] V_ref: reference voltage

[0048] V_Typ: Central voltage level

[0049] V_th: First power cut detection level DETAILED DESCRIPTION

[0050] It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. In addition, it should be understood that the idioms and terms used herein are for descriptive purposes and should not be considered restrictive. The use of "comprising," "including," or "having," and variations thereof herein is meant to encompass the items listed thereafter and their equivalents as well as additional items. Unless otherwise limited, the terms "connect," "couple," and "electrically connected," and variations thereof herein are used broadly and encompass direct and indirect connections, couplings, and mountings.

[0051] Figure 1 FIG. 1 is a schematic diagram showing a semiconductor memory according to an embodiment of the present disclosure. Figure 1 , the semiconductor memory 100 includes a control circuit 110, a power cut-off monitoring circuit 120, a charge pump circuit 130, a switch circuit 140, and a memory array 150. The semiconductor memory 100 may be a NAND gate flash memory. The control circuit 110 is coupled to the power cut-off monitoring circuit 120, the charge pump circuit 130, and the switch circuit 140. The switch circuit 140 is coupled to the charge pump circuit 130 and the memory array 150. The control circuit 110 controls the charge pump circuit 130 and the switch circuit 140 to perform access operations of the memory array 150. For example, the control circuit 110 may perform a write operation or an erase operation on the memory array 150 to read data or write data into the memory array 150. The write signal (write voltage) of the write operation and the erase signal (erase voltage) of the erase operation are generated by the charge pump circuit 130. In the present embodiment, the charge pump circuit 130 provides a plurality of word line voltages to the memory array 150 via the switch circuit 140 during the write period.

[0052] In the present embodiment, the power cut-off monitoring circuit 120 is used to detect whether the power supply voltage VCC unexpectedly drops to 0 or a voltage level at which the memory cannot operate normally during the writing period of the semiconductor memory 100, so as to automatically perform a reset procedure of the semiconductor memory 100 to prevent the previously recorded (written) data in the memory array 150 from being lost. It should be noted that in the present embodiment, the power cut-off monitoring circuit 120 is only enabled during the writing period, but the present disclosure is not limited thereto. In another embodiment, the power cut-off monitoring circuit 120 may be enabled during the erasing period or other operation period of the semiconductor memory 100.

[0053] Figure 2 FIG. 1 is a schematic diagram showing a memory array and its peripheral circuits according to an embodiment of the present disclosure. Figure 1 and Figure 2, the charge pump circuit 130 includes a first charge pump 131 and a second charge pump 132. The switch circuit 140 includes a first decoder 141, a second decoder 142, a third decoder 143, and a plurality of selection switches CS1_1 to CS1_K and CS2_1 to CS2_K, where K is a positive integer greater than 0. The first charge pump 131 is coupled to the control circuit 110 and the first decoder 141. The second charge pump 132 is coupled to the control circuit 110, the second decoder 142, and the third decoder 143. A plurality of first terminals of the selection switches CS1_1 to CS1_K are coupled to the global selection gate line GSGD, the global selection gate line GSGS, and a plurality of global word lines GWL0 to GWLn, and a plurality of second terminals of the selection switches CS1_1 to CS1_K are coupled to the first decoder 141. A plurality of control terminals of the selection switches CS1_1 to CS1_K are coupled to the second decoder 142. The third decoder 143 is coupled between the second charge pump 132 and a plurality of control terminals of the selection switches CS2_1 to CS2_K.

[0054] In this embodiment, one of the memory regions of the memory array 150 may be Figure 2As shown in , one of the memory areas of the memory array 150 may include a plurality of memory cells C(0,0) to C(n,m), where n and m are positive integers greater than 0. In the present embodiment, the global selection gate line GSGD, the global selection gate line GSGS, and the global word lines GWL0 to GWLn are coupled to the selection gate line SGD and the selection gate line SGS and the plurality of local word lines LWL0 to LWLn via the selection switches CS2_1 to CS2_K. The selection gate line SGD is coupled to the plurality of control terminals of the plurality of selection switches SD_0 to SD_m, and the selection gate line SGS is coupled to the plurality of control terminals of the plurality of selection switches SS_0 to SS_m. The local word lines LWL0 to LWLn are coupled to the memory cells C(0,0) to C(n,m). In the present embodiment, each row of memory cells C(0,0) to memory cells C(n,m) is coupled to one of a plurality of global bit lines GBL0 to GBLm via selection switches SD_0 to SD_m, and memory cells C(0,0) to memory cells C(n,m) are coupled to selection lines SL via selection switches SS_0 to SS_m. Even-numbered global bit lines are coupled to a plurality of page buffers 151_1 to 151_P via selection switches BLe_1 to BLe_P, and odd-numbered global bit lines are coupled to page buffers 151_1 to 151_P via selection switches BLo_1 to BLo_P, where P is a positive integer greater than 0. Each of page buffers 151_1 to 151_P is coupled to one even-numbered global bit line and one odd-numbered global bit line. The selection switches BLe_1 to BLe_P and the selection switches BLo_1 to BLo_P are controlled by the bit line selection signals BLSe and BLSo.

[0055] In a write operation of the semiconductor memory 100, the control circuit 110 may control the first charge pump 131 and the first decoder 141 to provide a write signal (word line voltage) via the selection switches CS1_1 to CS1_K, and control the second charge pump 132, the second decoder 142, and the third decoder 143 to provide a plurality of turn-on signals (control voltages) and a selection signal PASV (control voltage) to selectively turn on the plurality of selection switches CS1_1 to CS1_K and CS2_1 to CS2_K to write data into the plurality of memory cells C(0,0) to C(n,m). In addition, when the control circuit 110 performs a write operation of the first data page, the memory cells C(0,0), C(0,2) to C(0,m-1) of the first column and the memory cells C(0,0) to C(n,m) of the even rows may be written with data by corresponding write signals. Next, when the control circuit 110 performs a write operation of the second data page, the memory cells C(0,1), C(0,3) to C(0,m) of the first column and the memory cells C(0,0) to C(n,m) of the odd rows can be written with data by corresponding write signals. Next, when the control circuit 110 performs a write operation of the third data page, the memory cells C(1,0), C(1,2) to C(1,m-1) of the second column and the memory cells C(0,0) to C(n,m) of the even rows can be written with data by corresponding write signals. Similarly, the control circuit 110 can sequentially and periodically write data to different data pages of the memory cells C(0,0) to the memory cells C(n,m).

[0056] However, for example, during writing, when the control circuit 110 performs a write operation of the second data page, if the power supply voltage VCC unexpectedly drops to 0 or a voltage level at which the memory cannot operate normally, the unexpected power cut-off of the memory cells C(0,0), C(0,2) to C(0,m-1) may affect the memory cells C(0,1), C(0,3) to C(0,m) because the memory cells C(0,0), C(0,2) to C(0,m-1) are adjacent to the memory cells C(0,1), C(0,3) to C(0,m). In other words, not only the second data page has not been written yet, but also the memory cells C(0,0), C(0,2) to C(0,m-1) that have previously recorded the first data page may be damaged and lose data. Therefore, the control circuit 110 of the present disclosure may perform the data protection operation of the following embodiments to effectively protect the previously written data.

[0057] Figure 3 The flowchart is a data protection method according to an embodiment of the present disclosure. Figure 42 is a voltage waveform diagram showing a power supply voltage according to an embodiment of the present disclosure. Figure 1 , Figure 3 as well as Figure 4 , the semiconductor memory 100 may perform the following steps S310 to S340 to implement the data protection function. In step S310, the control circuit 110 may perform a write operation of the semiconductor memory 100 during the write period. In step S320, the power supply cut-off monitoring circuit 120 may determine whether the power supply voltage VCC drops below the first power supply cut-off detection level V_th during the write period. Specifically, if Figure 4 As shown in , the power supply voltage VCC may have a central voltage level V_Typ and swing up and down between a maximum voltage level V_Max and a minimum voltage level V_min. The power cut monitoring circuit 120 may detect whether the power supply voltage VCC drops below a first power cut detection level V_th. The minimum voltage level V_min is defined in a data sheet of the semiconductor memory, and the first power cut detection level V_th is lower than the level V_min of the power supply voltage VCC. In step S330, when the power supply voltage drops below the first power cut detection level V_th, the power cut monitoring circuit 120 may output a trigger signal to the control circuit 110. In step S340, the control circuit 110 executes a reset procedure of the semiconductor memory 100 according to the trigger signal.

[0058] In this embodiment, at time t0, the reset procedure may include the control circuit 110 controlling the charge pump circuit 130 to stop providing the word line voltage to the word line. Figure 2As shown in FIG. 1 , the first charge pump 131 stops supplying the word line voltage to the global word lines GWL0 to GWLn, but the second charge pump 132 can continuously supply the control voltage to the control terminals of the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K. Therefore, the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K are controlled to keep operating in a turned-on state, so that the residual voltage on the global word lines GWL0 to GWLn can be effectively released (discharged). However, in another embodiment, when the first charge pump 131 stops providing the word line voltage to the global word lines GWL0 to GWLn, the second charge pump 132 may also synchronously stop providing the control voltage to the control ends of the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K to synchronously disconnect the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K. In yet another embodiment, when the first charge pump 131 stops supplying the word line voltage to the global word lines GWL0 to GWLn, the second charge pump 132 may stop supplying the control voltage to the control terminals of the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K when the power supply voltage drops below the second power supply cut-off detection level, so as to disconnect the selection switches CS1_1 to CS1_K and the selection switches CS2_1 to CS2_K, wherein the second power supply cut-off detection level is lower than the first power supply cut-off detection level V_th. Therefore, the influence of the abnormal voltage change VCC on the data previously recorded in a portion of the memory cells of the memory array 150 may be reduced or avoided. In addition, the reset procedure may further include the control circuit 110 executing a preset reset command (e.g., an FFh reset command) of the semiconductor memory 100 to perform a reset operation of the semiconductor memory 100.

[0059] Figure 5 FIG. 1 is a schematic diagram showing a power cut-off monitoring circuit according to an embodiment of the present disclosure. Figure 6 FIG. 2 is a voltage relationship diagram showing a power supply voltage and an output voltage according to another embodiment of the present disclosure. Figure 5 and Figure 6The power cut-off monitoring circuit 120 includes a voltage divider 121, a voltage generator 122 and a comparator 123. The voltage divider 121 is coupled to the power supply voltage VCC, and is used to output a divided voltage V_div according to the power supply voltage VCC. The voltage divider 121 can be composed of a plurality of voltage divider resistors, but the present disclosure is not limited thereto. The voltage generator 122 is used to output a reference voltage V_ref according to a first power cut-off detection level V_th. The comparator 123 is coupled to the voltage divider 121 and the voltage generator 122 via a first input terminal and a second input terminal of the comparator 123. The comparator 123 is used to output an output signal Vo for generating a trigger signal to the control circuit 110 via an output terminal of the comparator 123. Figure 6 As shown in , the reference voltage V_ref can be designed according to the first power cut-off detection level V_th. In this embodiment, when the divided voltage V_div crosses the reference voltage V_ref, the output signal Vo of the comparator 123 can change from a high voltage level to a low voltage level. Therefore, the power cut-off monitoring circuit 120 can generate a trigger signal to the control circuit 110 according to the voltage change of the output signal Vo.

[0060] Figure 7 FIG. 1 is a flowchart showing a reset procedure according to an embodiment of the present disclosure. Figure 5 The design concept of the power cut-off monitoring circuit 120, Figure 1 The power cut monitoring circuit 120 may further include more of the above related circuits to set the second power cut detection level and the third power cut detection level, and the second power cut detection level and the third power cut detection level can be used for data protection operations at the above different stages in the reset procedure. Figure 1 , Figure 2 as well as Figure 7 , the control circuit 110 may perform a reset procedure with different stages (such as the following steps S710 to S730). In step S710, when the power supply voltage VCC drops below the first power cut-off detection level during writing, the control circuit 110 may cause the first charge pump 131 to stop outputting a plurality of word line voltages to a plurality of word lines. In step S720, when the power supply voltage VCC drops below the second power cut-off detection level during writing, the control circuit 110 may further cause the second charge pump 132 to stop outputting a plurality of control voltages to a plurality of first switches to disconnect a plurality of selection switches CS1_1 to CS1_K. In step S730, when the power supply voltage VCC drops below the third power cut-off detection level during writing, the control circuit 110 may execute a preset reset command (e.g., an FFh reset command) of the semiconductor memory 100. The third power cut-off detection level is lower than the second power cut-off detection level, and the second power cut-off detection level is lower than the first power cut-off detection level.

[0061] That is, in the present embodiment, the control circuit 110 may first stop providing the word line voltage to the word line, and then may disconnect the selection switches CS1_1 to CS1_K after a time interval. Therefore, the residual voltage on the global word lines GWL0 to GWLn may be effectively released (discharged). Finally, the control circuit 110 may execute the preset reset command of the semiconductor memory 100. Therefore, the semiconductor memory 100 executing the above steps S710 to S730 is able to protect the data previously recorded (written) in the memory array 150 that can be effectively protected.

[0062] In summary, the semiconductor memory and data protection method disclosed herein can additionally design a power cut-off monitoring circuit to automatically detect the power supply voltage during the writing period of the semiconductor memory, and utilize one or more data protection operations of the reset program to protect the data previously recorded (written) in the memory array. Therefore, the semiconductor memory and data protection method disclosed herein can effectively protect the data previously recorded (written) in the memory array when the power supply voltage unexpectedly drops during the writing period of the semiconductor memory so that the semiconductor memory cannot operate normally.

[0063] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations provided that the modifications and variations are within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor memory, comprising: Memory array; a switch circuit coupled to the memory array; a control circuit coupled to the switch circuit; a power cut-off monitoring circuit coupled to the control circuit and the power supply voltage; as well as a charge pump circuit coupled to the switch circuit and the control circuit, The power cut-off monitoring circuit is used to determine whether the power supply voltage drops below a first power cut-off detection level during writing, so as to output a trigger signal to the control circuit, and the control circuit executes a reset procedure of the semiconductor memory according to the trigger signal, wherein the first power cut-off detection level is lower than the minimum value of the power supply voltage recorded in a data table of the semiconductor memory, The reset procedure includes the control circuit controlling the charge pump circuit to stop providing a plurality of word line voltages.

2. The semiconductor memory according to claim 1, wherein the power supply cutoff monitoring circuit is enabled only during the writing period.

3. The semiconductor memory according to claim 1, wherein the reset procedure includes the control circuit executing a preset reset command of the semiconductor memory.

4. The semiconductor memory according to claim 1, The charge pump circuit is used to provide the plurality of word line voltages to the memory array via the switch circuit during the writing period.

5. The semiconductor memory device according to claim 4, wherein the charge pump circuit comprises a first charge pump, and the first charge pump is coupled to a plurality of word lines via a plurality of selection switches of the switch circuit, and the first charge pump is used to output the plurality of word line voltages to the plurality of word lines during the writing period, When the power supply voltage drops below the first power supply cutoff detection level during the writing period, the first charge pump stops outputting the plurality of word line voltages to the plurality of word lines.

6. The semiconductor memory according to claim 5, wherein during the writing period when the power supply voltage drops below the first power supply cutoff detection level, the plurality of selection switches are controlled to keep operating in an on state.

7. The semiconductor memory device according to claim 5, wherein the charge pump circuit further comprises a second charge pump, the second charge pump being coupled to the control terminals of the plurality of selection switches, and the second charge pump being used to output a plurality of control voltages to the control terminals of the plurality of selection switches during the writing period, When the power supply voltage drops below a second power supply cutoff detection level during the writing period, the second charge pump stops outputting the plurality of control voltages to the plurality of selection switches to turn off the plurality of selection switches.

8. The semiconductor memory according to claim 7, wherein the second power supply cut-off detection level is lower than the first power supply cut-off detection level.

9. The semiconductor memory according to claim 8, wherein the reset procedure further comprises the control circuit executing a preset reset command of the semiconductor memory when the power supply cutoff monitoring circuit determines that the power supply voltage drops below a third power supply cutoff detection level during the writing period, The third power cutoff detection level is lower than the second power cutoff detection level.

10. The semiconductor memory according to claim 1, wherein the power supply cut-off monitoring circuit comprises: a voltage divider coupled to the power supply voltage and configured to output a divided voltage according to the power supply voltage; a voltage generator, configured to output a reference voltage according to the first power cut-off detection level; as well as The comparator is coupled to the voltage divider and the voltage generator via a first input terminal and a second input terminal, and is used for outputting an output signal for generating the trigger signal to the control circuit via an output terminal.

11. A data protection method for a semiconductor memory, comprising: executing a write operation of the semiconductor memory during a write period by means of a control circuit; determining, by a power cut-off monitoring circuit, whether the power supply voltage drops below a first power cut-off detection level during the writing period; When the power supply voltage drops below the first power cut detection level, the power cut monitoring circuit outputs a trigger signal to the control circuit; The control circuit performs a reset procedure of the semiconductor memory according to the trigger signal, wherein the first power cut-off detection level is lower than the minimum value of the power supply voltage recorded in the data table of the control circuit, The reset procedure includes: The control circuit controls the charge pump circuit to stop providing a plurality of word line voltages.

12. The data protection method of a semiconductor memory according to claim 11, wherein the power cutoff monitoring circuit is enabled only during the writing period.

13. The data protection method of a semiconductor memory as claimed in claim 11, wherein the resetting procedure comprises: The control circuit executes a preset reset command of the semiconductor memory.

14. The data protection method of a semiconductor memory according to claim 11, wherein the writing operation comprises: During the writing period, the charge pump circuit provides the plurality of word line voltages to the memory array via the switch circuit.

15. The data protection method of a semiconductor memory as claimed in claim 14, wherein the step of providing the plurality of word line voltages to the memory array via the switch circuit by the charge pump circuit during the writing period comprises: During the writing period, the plurality of word line voltages are output to a plurality of word lines by a first charge pump of the charge pump circuit; and The step of controlling the charge pump circuit to stop providing the plurality of word line voltages by the control circuit comprises: When the power supply voltage drops below the first power supply cutoff detection level during the writing period, the first charge pump is caused to stop outputting the plurality of word line voltages to the plurality of word lines.

16. The data protection method of a semiconductor memory as claimed in claim 15, wherein the step of controlling the charge pump circuit to stop providing the plurality of word line voltages by the control circuit further comprises: A plurality of selection switches controlling the switch circuit remain operated in an on state.

17. The data protection method of a semiconductor memory as claimed in claim 16, wherein the step of providing the plurality of word line voltages to the memory array via the switch circuit by the charge pump circuit during the writing period comprises: During the writing period, a second charge pump of the charge pump circuit outputs a plurality of control voltages to control terminals of the plurality of selection switches; and The reset procedure also includes: When the power supply voltage drops below a second power supply cutoff detection level during the writing period, the second charge pump stops outputting the plurality of control voltages to the plurality of selection switches to turn off the plurality of selection switches.

18. The data protection method of a semiconductor memory according to claim 17, wherein the second power cutoff detection level is lower than the first power cutoff detection level.

19. The data protection method of the semiconductor memory as claimed in claim 18, wherein the resetting procedure further comprises: When the power supply voltage drops below a third power cut-off detection level during the writing period, the control circuit executes a preset reset command of the semiconductor memory. The third power cutoff detection level is lower than the second power cutoff detection level.

20. The data protection method of a semiconductor memory according to claim 11, wherein the step of outputting the trigger signal to the control circuit by the power cut monitoring circuit when the power supply voltage drops below the first power cut detection level comprises: Outputting a divided voltage according to the power supply voltage by a voltage divider; Outputting a reference voltage according to the first power cut-off detection level by a voltage generator; as well as According to the divided voltage and the reference voltage received by the first input terminal and the second input terminal of the comparator, an output signal for generating the trigger signal is output to the control circuit through the output terminal of the comparator.

Images