Bump packaging structure and method for manufacturing the same

Abstract

Embodiments of the present application provide a bump packaging structure and a preparation method thereof, and relate to the technical field of semiconductor packaging. The bump packaging structure comprises a chip, a protective layer, a substrate adhesion layer, a conductive combined layer, an electrical bump and a cap layer. The substrate adhesion layer is a multilayer graphene material, which can enhance the stability and hydrophobicity of the bottom structure, and avoid the undercut problem. In addition, the substrate adhesion layer is formed with an arc-shaped groove, which can improve the contact surface between adjacent layers, thereby improving the bonding force. Compared with the prior art, the bump packaging structure provided by the present application can avoid the undercut opening formed by excessive corrosion, and has a more stable structure, better bonding force of the bottom structure, and better heat dissipation and conductivity performance, effectively alleviating the failure hidden danger caused by electromigration and thermal migration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a bump packaging structure and a preparation method of the bump packaging structure. BACKGROUND

[0002] With the rapid development of the semiconductor industry, flip-chip packaging structures are widely used in the semiconductor industry. Flip-chip packaging utilizes bumps to electrically connect chips and substrates. The bumps include copper pillars, metal layers (UBM: under bump metalization), protective layers (polyimide), and tin caps (Sn Cap). After the metal layer UBM is fabricated, the excess metal layer needs to be etched and removed. Since the polyimide material is extremely water-absorbing, the etching liquid residue on the sidewall of the UBM at the bottom of the copper pillar causes excessive corrosion undercuts at the bottom of the copper pillar bump, which in turn causes the copper pillar bump to easily fall off during reliability testing of the chip. The existing technology completely connects the bottom of the copper pillar bump to the chip electrode, and usually uses a planarization structure, which causes the stress on the copper pillar bump to directly act on the chip electrode, resulting in a problem of cracking of the chip electrode. The contact area between the metal layers is small, and the bonding force is poor. Moreover, under the influence of the electric current, the metal atoms at the connection of the bottom of the copper pillar simultaneously bear the electric field and thermal field due to the Joule heating effect, and the electromigration and thermomigration at the interconnection interface are abnormally active, which significantly reduces the service life and causes potential failure hazards. SUMMARY

[0003] The present application aims to provide a bump packaging structure and a preparation method of the bump packaging structure, which can avoid the undercut openings caused by excessive corrosion, have a more stable structure, better bonding force at the bottom, and better heat dissipation and conductivity, and effectively alleviate the failure hazards caused by electromigration and thermomigration.

[0004] Embodiments of the present application can be implemented as follows:

[0005] In a first aspect, the present application provides a bump packaging structure, comprising:

[0006] a chip, the front surface of the chip being provided with a solder pad;

[0007] a protective layer provided on the front surface of the chip, the protective layer being provided with a protective opening corresponding to the solder pad;

[0008] a base adhesive layer provided in the protective opening;

[0009] a conductive combined layer provided on the base adhesive layer;

[0010] an electrically conductive column disposed on the conductive combination layer;

[0011] a cap layer disposed on the electrically conductive column;

[0012] The base adhesive layer comprises a plurality of graphene layers, a top edge of the base adhesive layer extends outwardly to the protective layer and covers an edge of the protective opening, and an arc-shaped groove is disposed on a side surface of the base adhesive layer away from the chip.

[0013] In an optional embodiment, the conductive combination layer comprises a barrier layer and a wetting layer, the barrier layer is disposed on the base adhesive layer, and the wetting layer is disposed on the barrier layer.

[0014] In an optional embodiment, a thickness H1 of the part of the base adhesive layer extending to the protective layer is 4-8 μm, a thickness H2 of the barrier layer is 4-6 μm, and a thickness H3 of the wetting layer is 2-4 μm.

[0015] In an optional embodiment, the thicknesses of the part of the base adhesive layer extending to the protective layer, the barrier layer, and the wetting layer are the same.

[0016] In an optional embodiment, a width L1 of the part of the base adhesive layer extending to the protective layer is 4-8 μm, and projections of the base adhesive layer, the barrier layer, and the wetting layer on the front surface of the chip overlap.

[0017] In an optional embodiment, the side surface of the base adhesive layer away from the chip is at least partially concave, and forms the arc-shaped groove, so that the barrier layer and the wetting layer are both arched toward the chip, and the electrically conductive column is at least partially convex on a side surface close to the chip.

[0018] In an optional embodiment, the arc-shaped groove extends to an edge of the base adhesive layer, so that the side surface of the base adhesive layer away from the chip is concave.

[0019] In an optional embodiment, a stop layer is further disposed on a side of the electrically conductive column away from the chip, the stop layer is disposed between the cap layer and the electrically conductive column, and is used to block diffusion atoms between the cap layer and the electrically conductive column.

[0020] In an optional embodiment, a conductive adhesive layer is further disposed on a side of the electrically conductive column away from the chip, the conductive adhesive layer is disposed between the stop layer and the electrically conductive column, and the conductive adhesive layer is a graphene layer.

[0021] In an optional embodiment, the electrically-conductive protrusion is at least partially concave towards the side surface of the chip, so that the stop layer and the conductive adhesive layer are both arched towards the chip, and the cap layer is at least partially convex towards the side surface of the chip.

[0022] In a second aspect, the present application provides a method for manufacturing a bump package structure, for manufacturing the bump package structure according to any one of the preceding embodiments, comprising:

[0023] providing a chip with a solder pad on the front surface thereof;

[0024] forming a protection layer on the front surface of the chip;

[0025] forming a protection opening by slotting the protection layer at a position corresponding to the solder pad;

[0026] forming a base adhesive layer in the protection opening;

[0027] forming a conductive composite layer on the base adhesive layer;

[0028] forming an electrically-conductive protrusion on the conductive composite layer;

[0029] forming a cap layer on the electrically-conductive protrusion;

[0030] wherein the base adhesive layer comprises a plurality of layers of graphene material, the top edge of the base adhesive layer extends outwardly onto the protection layer and covers the edge of the protection opening, and the side surface of the base adhesive layer away from the chip is provided with an arc-shaped groove, and the conductive composite layer is at least partially accommodated in the arc-shaped groove.

[0031] The beneficial effects of the embodiments of the present application include, for example:

[0032] The embodiment of the present application provides a bump packaging structure, a protective layer is arranged on the front surface of a chip, a protective opening is arranged on the protective layer, a base adhesive layer is arranged in the protective opening, a conductive combination layer is arranged on the base adhesive layer, an electric bump and a cap layer are sequentially arranged on the conductive combination layer, the base adhesive layer comprises multilayer graphene material, the top edge of the base adhesive layer extends outward to the protective layer, the stability and hydrophobicity of the bottom structure can be enhanced by adopting the multilayer graphene material. The top edge of the base adhesive layer extends outward to the protective layer and covers the edge of the protective opening, when a micro-etching process is performed, whether a chemical etching method or a plasma etching method is adopted, the base adhesive layer can avoid the undercut problem caused by the removal of the UBM layer in the traditional micro-etching process. Moreover, the thermal expansion coefficient CTE of the graphene material is only 1 / 10-1 / 20 of copper and aluminum, the deformation of the UBM layer at the bottom of the conductive column can be better avoided, the solder pad at the bottom and the metal structure at the bottom of the conductive column can be protected. The conductive performance of the graphene material is far higher than that of metal, and the heat conduction performance is superior, the thermal conductivity and the heat conduction of the multilayer graphene structure formed along with the increase of the volume of the graphene are further improved, the conductive performance and the heat dissipation performance are greatly improved, the problem that the service life of the copper column bump is significantly reduced due to the abnormal activity of electromigration and thermal migration and potential failure hidden dangers are avoided. Meanwhile, the stability of the graphene is utilized, the problem that the copper column causes great stress in the package body to damage the brittle material layer, such as the rupture of the chip pad at the bottom of the copper column, the delamination of the UBM metal layer or the reduction of the solder joint fatigue life is solved, so that the stability of the structure is ensured. In addition, the surface of the base adhesive layer is provided with an arc-shaped groove, the conductive combination layer is partially accommodated in the arc-shaped groove, the contact area between the conductive combination layer and the base adhesive layer can be improved, so that the bonding force of the two is improved, the stability of the structure is further improved, and the electric bump is prevented from falling off. Compared with the prior art, the bump packaging structure provided by the present application can avoid the undercut opening formed by excessive corrosion, the structure is more stable, the bonding force of the bottom structure is better, and the heat dissipation and conductive performance are better, and the failure hidden danger caused by electromigration and thermal migration is effectively alleviated. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0034] Figure 1 A schematic diagram of the bump packaging structure provided by the first embodiment of the present application;

[0035] Figure 2 A schematic diagram of the bump packaging structure provided by the first embodiment of the present application;Figure 1 A partial enlarged view of the middle II;

[0036] Figures 3 to 8 A process flow chart of a method for manufacturing the bump package structure of the first embodiment of the present application;

[0037] Figure 9 A schematic view of the bump package structure of the second embodiment of the present application;

[0038] Figure 10 A schematic view of the bump package structure of the third embodiment of the present application;

[0039] Figure 11 A partial enlarged view of the middle IX. Figure 10 A partial enlarged view of the middle IX.

[0040] Figure: 100-bump package structure; 110-chip; 111-solder pad; 120-protective layer; 121-protective opening; 130-substrate adhesive layer; 140-conductive combination layer; 141-barrier layer; 143-wetting layer; 150-electricity protrusion; 160-cap layer; 170-stop layer; 180-conductive adhesive layer. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0043] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, thus, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0044] In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the product of the present application is used, only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0045] In addition, if the terms "first", "second" and the like appear, they are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0046] As disclosed in the background art, the prior art has the following objective defects:

[0047] 1. The protective layer is usually made of polyimide material. Since polyimide material is extremely easy to absorb water, the UBM sidewall at the bottom of the metal pillar is prone to residual etching liquid, which in turn causes excessive corrosion undercut opening at the bottom of the copper pillar bump. When the bump chip is subjected to reliability testing, the copper pillar bump may fall off.

[0048] 2. In the existing copper pillar bump, the bottom of the copper pillar bump is directly and completely connected with the chip electrode, which has poor buffering capacity, causing the stress on the copper pillar bump to directly act on the chip electrode, which may cause the chip electrode to crack.

[0049] In order to solve the above problems, the present application provides a new bump packaging structure and a preparation method of the bump packaging structure. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0050] First embodiment

[0051] Referring to Figure 1 and Figure 2 , the present embodiment provides a bump packaging structure 100 which can avoid the undercut opening caused by excessive corrosion, and has a more stable structure, better bonding force at the bottom, and better heat dissipation and conductivity performance, effectively alleviating the failure risks caused by electromigration and thermal migration.

[0052] The bump package structure 100 provided by the embodiment comprises a chip 110, a protective layer 120, a base adhesive layer 130, a conductive combined layer 140, an electrical bump 150 and a cap layer 160. The front surface of the chip 110 is provided with a solder pad 111. The protective layer 120 is arranged on the front surface of the chip 110, and the protective layer 120 is provided with a protective opening 121 corresponding to the solder pad 111. The size of the protective opening 121 is slightly smaller than the size of the solder pad 111, so that the solder pad 111 can be exposed to the protective layer 120. The base adhesive layer 130 is arranged in the protective opening 121 and covers the protective opening 121. The conductive combined layer 140 is arranged on the base adhesive layer 130. The electrical bump 150 is arranged on the conductive combined layer 140. The cap layer 160 is arranged on the electrical bump 150. The base adhesive layer 130 comprises a plurality of layers of graphene material. The top edge of the base adhesive layer 130 extends outwardly to the protective layer 120 and covers the edge of the protective opening 121. The side surface of the base adhesive layer 130 away from the chip 110 is provided with an arc-shaped groove. The conductive combined layer 140 is at least partially accommodated in the arc-shaped groove.

[0053] In the embodiment, the protective layer 120 is arranged on the front surface of the chip 110, the protective opening 121 is arranged on the protective layer 120, the base adhesive layer 130 is arranged in the protective opening 121, the conductive combination layer 140 is arranged on the base adhesive layer 130, and the electrically conductive column 150 and the cap layer 160 are sequentially arranged on the conductive combination layer 140. The base adhesive layer 130 includes a plurality of graphene materials, and the top edge of the base adhesive layer 130 extends outwardly to the protective layer 120. The use of the plurality of graphene materials can enhance the stability and hydrophobicity of the bottom structure. The top edge of the base adhesive layer 130 extends outwardly to the protective layer 120 and covers the edge of the protective opening 121. In the micro-etching process, whether chemical etching or plasma etching is used, the base adhesive layer 130 can avoid the undercut problem caused by the removal of the UBM layer in the traditional micro-etching process. The thermal expansion coefficient CTE of the graphene material is only 1 / 10-1 / 20 of that of copper and aluminum, which can better avoid the deformation of the UBM layer at the bottom of the conductive column, and can protect the solder pad 111 at the bottom and the metal structure at the bottom of the conductive column. The conductive performance of the graphene material is much higher than that of the metal, and the thermal conductivity is superior. With the increase of the volume of the graphene, the thermal conductivity and thermal conductivity of the multi-layer graphene structure are further improved, which greatly improves the conductive performance and heat dissipation performance, avoids the problem that the life of the copper column bump is significantly reduced due to the abnormal activity of electromigration and thermal migration, and causes potential failure hidden trouble. At the same time, the stability of the graphene is used to solve the problem that the copper column in the traditional technology causes a large stress in the package body to cause damage to the brittle material layer, such as rupture of the chip 110 pad at the bottom of the copper column, delamination of the UBM metal layer, or reduction of the solder fatigue life, thereby ensuring the stability of the structure. In addition, the surface of the base adhesive layer 130 is provided with an arc-shaped groove, and the conductive combination layer 140 is partially accommodated in the arc-shaped groove, which can improve the contact area between the conductive combination layer 140 and the base adhesive layer 130, thereby improving the bonding force therebetween and further improving the stability of the structure to avoid the electrically conductive column 150 from falling off.

[0054] In the embodiment, the depth of the arc-shaped groove is less than the thickness of the base adhesive layer 130, so that the arc-shaped groove does not penetrate to the solder pad 111, and the conductive combination layer 140 is arranged on the base adhesive layer 130, so that the conductive combination layer 140 is accommodated in the arc-shaped groove and forms an arch shape towards the chip 110, which can further improve the structural strength.

[0055] In the embodiment, the conductive combination layer 140 comprises a barrier layer 141 and a wetting layer 143, the barrier layer 141 covers the substrate adhesive layer 130, and the wetting layer 143 covers the barrier layer 141. Specifically, the barrier layer 141 and the wetting layer 143 are both made of conductive metal material, for example, the barrier layer 141 can be made of at least one of nickel, vanadium, and chromium, and the wetting layer 143 and the conductive stud are both made of copper material. The barrier layer 141 can block atomic diffusion between the conductive stud and the bottom substrate adhesive layer 130, and the wetting layer 143 can improve the wettability of the bottom of the conductive stud, thereby improving the bonding strength.

[0056] In the embodiment, the thickness H1 of the part of the substrate adhesive layer 130 extending to the protective layer 120 is 4-8 μm; the thickness H2 of the barrier layer 141 is 4-6 μm; and the thickness H3 of the wetting layer 143 is 2-4 μm. Specifically, the thickness H1 of the substrate adhesive layer 130 protruding from the protective layer 120 is 4-8 μm, preferably 4 μm, which can completely avoid the etching residual liquid from entering the edge of the protective opening 121, thereby further avoiding the undercut phenomenon. At the same time, the barrier layer 141 is an equal-thickness layer with a thickness of 4 μm, and the wetting layer 143 is also an equal-thickness layer with a thickness of 4 μm. By reasonably setting the thicknesses of the substrate adhesive layer 130, the barrier layer 141, and the wetting layer 143, the structural strength of the connection can be ensured while the conductive performance is ensured.

[0057] In the embodiment, the thicknesses of the part of the substrate adhesive layer 130 extending to the protective layer 120, the barrier layer 141, and the wetting layer 143 are the same. That is, the thicknesses of the part of the substrate adhesive layer 130 extending to the protective layer 120, the barrier layer 141, and the wetting layer 143 are all 4 μm, which can ensure the structural strength and functional characteristics (such as conductivity, barrier property, and wettability) while as low as possible the height of the overall stud structure, which is conducive to reducing the height of the solder structure.

[0058] In the embodiment, the width L1 of the part of the substrate adhesive layer 130 extending to the protective layer 120 is 4-8 μm, and the projections of the substrate adhesive layer 130 on the front surface of the chip 110, the projections of the barrier layer 141 on the front surface of the chip 110, and the projections of the wetting layer 143 on the front surface of the chip 110 are overlapped. Preferably, the width L1 of the part of the substrate adhesive layer 130 extending to the protective layer 120 is 6 μm, and the edges of the barrier layer 141, the edges of the wetting layer 143, and the edges of the substrate adhesive layer 130 are flush, so that the same mask can be used for etching, thereby simplifying the process steps.

[0059] In the embodiment, the substrate bonding layer 130 is at least partially concave on the side surface away from the chip 110, and forms an arc-shaped groove, so that the barrier layer 141 and the wetting layer 143 are both arched towards the chip 110, and the electrical bump 150 is at least partially convex on the side surface close to the chip 110. Specifically, the edges of the substrate bonding layer 130 are kept horizontal and overlap the protective layer 120, and the central part of the substrate bonding layer 130 is concave to form an arc-shaped groove, which can further increase the contact area between the barrier layer 141 and the substrate bonding layer 130, thereby improving the bonding force.

[0060] In the embodiment, the width of the arc-shaped groove is the same as the width of the protective opening 121. Specifically, the edges of the substrate bonding layer 130 are kept horizontal and overlap the surface of the protective layer 120, so that the edges of the substrate bonding layer 130 are flattened and can completely cover the edges of the protective opening 121, thereby further preventing the occurrence of undercut phenomenon and better realizing the same thickness of the part of the substrate bonding layer 130 extending to the protective layer 120, the barrier layer 141 and the wetting layer 143. Further, since the barrier layer 141 and the wetting layer 143 are both equal-thickness layers, the central parts of the barrier layer 141 and the wetting layer 143 are arched towards the chip 110, thereby increasing the contact area between the layers and enhancing the bonding force. Meanwhile, the edges of the barrier layer 141 and the wetting layer 143 are both horizontal, so that the substrate bonding layer 130, the barrier layer 141 and the wetting layer 143 at the edges are more uniformly stressed.

[0061] In the embodiment, the electrical bump 150 away from the chip 110 is further provided with a stop layer 170, which is arranged between the cap layer 160 and the electrical bump 150 and used to block the diffusion atoms between the cap layer 160 and the electrical bump 150. Specifically, the stop layer 170 can be at least one of nickel, vanadium and chromium, and the end surface of the electrical bump 150 away from the chip 110 is horizontal, so that the stop layer 170 is horizontally laid on the end surface of the electrical bump 150, and the cap layer 160 is laid on the stop layer 170.

[0062] The embodiment further provides a preparation method of the bump packaging structure 100, which is used for preparing the aforementioned bump packaging structure 100, and includes the following steps:

[0063] S1: providing a chip 110 with a solder pad 111 on the front surface.

[0064] Referring to Figure 3 Specifically, first, a chip 110 with a solder pad 111 on the front surface is provided, the chip 110 has a wiring layer inside, and the solder pad 111 is electrically connected to the wiring layer.

[0065] S2: Forming a protective layer 120 on the front surface of the chip 110.

[0066] Referring to Figure 4 , specifically, a liquid protective material, such as polyimide, can be uniformly spin-coated on the front surface of the chip 110, and then soft-baked by a hot plate to shape the film and form a protective layer 120.

[0067] S3: Forming a protective opening 121 by slotting the protective layer 120 at a position corresponding to the solder pad 111.

[0068] Referring to Figure 5 , specifically, the protective layer 120 can be covered at the predetermined opening position by a mask, and then the unexposed area can be removed by spraying a developing solution to expose the aluminum solder pad 111 opening position, and then the protective layer 120 can be cured to a stable state by heating in an oven. The surface of the protective layer 120 can be cleaned of contaminants or residues using a plasma residue removal machine. Of course, the protective layer 120 can also be a silicon nitride material.

[0069] S4: Forming a substrate adhesion layer 130 in the protective opening 121.

[0070] Referring to Figure 6 , specifically, the substrate adhesion layer 130 includes a plurality of graphene materials, the top edge of the substrate adhesion layer 130 extends outwardly onto the protective layer 120 and covers the edge of the protective opening 121, and the side surface of the substrate adhesion layer 130 away from the chip 110 is provided with an arc-shaped groove.

[0071] After the preparation of the protective opening 121 is completed, graphene material is coated on the protective layer 120 to form a multi-layer graphene structure, wherein the graphene material fills the protective opening 121 and covers the surface of the protective layer 120 with a thickness of 4-8 μm, and then the graphene material is accelerated to a stable state by heating in an oven to form the substrate adhesion layer 130. Then, the graphene in the protective opening 121 is etched using an etching process to form an inner concave arc surface on the substrate adhesion layer 130 and form an arc-shaped groove.

[0072] S5: Forming a conductive combination layer 140 on the substrate adhesion layer 130.

[0073] Referring to Figure 7 , specifically, after the preparation of the arc-shaped groove is completed, a barrier layer 141 can be formed by electroplating metal on the inner concave arc surface, the material of the barrier layer 141 can be at least one of nickel, vanadium, and chromium, and the thickness is 4-6 μm, and then a wetting layer 143 can be formed by electroplating, the wetting layer 143 can be a copper layer with a thickness of 2-4 μm.

[0074] S6: Forming the electric protrusion 150 on the conductive combination layer 140.

[0075] Referring to Figure 8 , specifically, after forming the wetting layer 143, then coating the surface with protective glue, then using photolithography process to open the copper column opening, and then using the sputtering copper layer on the arc-shaped wetting layer 143 by electroplating process, forming a copper column, that is, forming an electric protrusion 150, the bottom of the electric protrusion 150 is in the shape of an arc-shaped protrusion, which can improve the bonding force between it and the lower structure.

[0076] After forming the electric core protrusion, a stop layer 170 can be formed on the electric protrusion 150.

[0077] S7: Forming the cap layer 160 on the electric protrusion 150.

[0078] Please continue to refer to Figure 1 , specifically, the solder layer can be formed on the stop layer 170 by using electroplating or ball planting process, and the cap layer 160 can be formed after reflow. The cap layer 160 can be a tin cap layer 160.

[0079] In summary, the bump packaging structure 100 and the preparation method of the bump packaging structure 100 provided by the embodiment have the following advantages. The protective layer 120 is arranged on the front surface of the chip 110, the protective opening 121 is arranged on the protective layer 120, the base adhesive layer 130 is arranged in the protective opening 121, the conductive combination layer 140 is arranged on the base adhesive layer 130, and the electrically conductive bump 150 and the cap layer 160 are sequentially arranged on the conductive combination layer 140. The top edge of the base adhesive layer 130 extends outwardly to the protective layer 120 and covers the edge of the protective opening 121. In the micro-etching process, whether chemical etching or plasma etching is used, the base adhesive layer 130 can avoid the undercut problem caused by the removal of the UBM layer in the traditional micro-etching process. The thermal expansion coefficient CTE of the graphene material is only 1 / 10-1 / 20 of that of copper and aluminum, which can better avoid the deformation of the UBM layer at the bottom of the conductive column, and can protect the solder pad 111 at the bottom and the metal structure at the bottom of the conductive column. The electrical conductivity of the graphene material is much higher than that of the metal, and the thermal conductivity is superior. As the volume of the graphene increases, the thermal conductivity and thermal conductivity of the multi-layer graphene structure are further improved, which greatly improves the electrical conductivity and heat dissipation performance, avoids the problem that the life of the copper column bump is significantly reduced due to the abnormal activity of electromigration and thermal migration, and causes potential failure hazards. At the same time, the stability of the graphene is used to solve the problem that the copper column in the traditional technology causes a large stress in the package body, which leads to damage to the brittle material layer, such as rupture of the chip 110 pad at the bottom of the copper column, delamination of the UBM metal layer, or reduction of the solder fatigue life, thereby ensuring the stability of the structure. In addition, the surface of the base adhesive layer 130 is provided with an arc-shaped groove, and the conductive combination layer 140 is partially accommodated in the arc-shaped groove, which can improve the contact area between the conductive combination layer 140 and the base adhesive layer 130, thereby improving the bonding force therebetween and further improving the stability of the structure to avoid the electrically conductive bump 150 from falling off.

[0080] Second embodiment

[0081] Reference Figure 9 The bump packaging structure 100 provided by the embodiment has the same basic structure, principle, and technical effects as the first embodiment. For brevity, the part not mentioned in the embodiment can be referred to the corresponding content in the first embodiment.

[0082] In the embodiment, the electrically conductive column 150 away from the chip 110 side is also provided with a stop layer 170, the stop layer 170 is arranged between the cap layer 160 and the electrically conductive column 150, for blocking the diffusion atoms between the cap layer 160 and the electrically conductive column 150, further, the electrically conductive column 150 away from the chip 110 side is also provided with a conductive adhesive layer 180, the conductive adhesive layer 180 is arranged between the stop layer 170 and the electrically conductive column 150, and the conductive adhesive layer 180 is a graphene layer.

[0083] It should be noted that the conductive adhesive layer 180 adopts graphene material, which can better realize heat dissipation and conduction.

[0084] In the embodiment, the surface of the electrically conductive column 150 away from the chip 110 side is at least partially concave, so that the stop layer 170 and the conductive adhesive layer 180 are both arched towards the chip 110, and the surface of the cap layer 160 close to the chip 110 is at least partially convex. Specifically, the end surface of the electrically conductive column 150 away from the chip 110 is concave, which can be formed into a circular arc structure by etching, cooperating with the lower arc-shaped groove, forming a double circular arc structure, shaping the top of the electrically conductive column 150 into a groove shape, and the bottom is a structure with a convex and flat edge, so that the bottom of the electrically conductive column 150 can play a better supporting role. At the same time, the conductive adhesive layer 180 and the stop layer 170 are equal-thickness layers, which can form an arched structure protruding towards the chip 110, improve the contact area and improve the bonding force.

[0085] The bump packaging structure 100 provided in the embodiment is further provided with a conductive adhesive layer 180 of graphene material between the stop layer 170 and the electrically conductive column 150, cooperating with the lower substrate adhesive layer 130, which can realize a double-layer graphene structure, thereby realizing better heat dissipation and conduction characteristics. And, the circular arc structure is adopted, which can improve the contact area between the conductive adhesive layer 180 and the electrically conductive column 150, between the stop layer 170 and the conductive adhesive layer 180, and between the cap layer 160 and the stop layer 170, thereby improving the bonding force and ensuring the overall structural strength. At the same time, the stop layer 170 can well prevent the atomic diffusion problem of the cap layer 160 downward. And, the downward recessed circular arc structure makes the end of the electrically conductive column 150 away from the chip 110 better lock the solder, preventing solder overflow. At the same time, the double-layer circular arc structure is adopted, the recess directions of the double-layer circular arc structure are the same, which can realize better stress release to buffer structural stress and avoid electrode cracking.

[0086] Third embodiment

[0087] Reference Figure 10 and Figure 11The embodiment provides a bump packaging structure 100, the basic structure and principle and the generated technical effect and the first embodiment are same, for brief description, the part not mentioned in the embodiment can be referred to the corresponding content in the first embodiment.

[0088] In the embodiment, the arc-shaped groove extends to the edge of the substrate bonding layer 130, so that the side surface of the substrate bonding layer 130 away from the chip 110 is an arc-shaped concave surface. Specifically, the width of the arc-shaped groove is greater than the width of the protection opening 121, so that there is no flat structure at the edge of the substrate bonding layer 130, and the arc-shaped concave surface directly extends to the edge of the substrate bonding layer 130.

[0089] In the embodiment, the barrier layer 141 and the wetting layer 143 are also equal-thickness layers, so the edges of the barrier layer 141 and the wetting layer 143 also have flat structures, and the barrier layer 141 and the wetting layer 143 as a whole are arched and arch upwardly in the direction close to the chip 110.

[0090] In the embodiment, the electrically conductive bump 150 away from the chip 110 is also provided with a stop layer 170, the stop layer 170 is arranged between the cap layer 160 and the electrically conductive bump 150, and is used for blocking diffusion atoms between the cap layer 160 and the electrically conductive bump 150. Further, the electrically conductive bump 150 away from the chip 110 is also provided with a conductive bonding layer 180, the conductive bonding layer 180 is arranged between the stop layer 170 and the electrically conductive bump 150, and the conductive bonding layer 180 is a graphene layer. The conductive bonding layer 180 and the stop layer 170 are both flat structures, that is, the end surface of the electrically conductive bump 150 away from the chip 110 is a plane.

[0091] In the embodiment, the edge thickness H1 of the substrate bonding layer 130 can be the sum of the thickness H2 of the barrier layer 141 and the thickness H3 of the wetting layer 143, that is, H1=H2+H3, so that the residual chemical reagent after etching can be prevented from being side-climbed to the barrier layer 141, the wetting layer 143 and the electrically conductive bump by capillary action. The substrate bonding layer 130 is a graphene material, and the hydrophobicity and stability of the graphene can prevent the undercut problem.

[0092] The above merely describes specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, and should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A bump package structure, comprising: The chip is provided with a solder pad on the front surface thereof. A protective layer is arranged on the front surface of the chip, and the protective layer is provided with a protective opening corresponding to the solder pad. A base adhesive layer is arranged in the protective opening. A conductive combined layer is arranged on the base adhesive layer. An electrical stud is arranged on the conductive combined layer. A cap layer is arranged on the electrical stud. The base adhesive layer comprises a plurality of graphene materials, the top edge of the base adhesive layer extends outwardly to the protective layer and covers the edge of the protective opening, and the side surface of the base adhesive layer away from the chip is provided with an arc-shaped groove, and the conductive combined layer is at least partially accommodated in the arc-shaped groove. The base adhesive layer is made of graphene materials coated on the protective layer and is fixed by an oven, and the base adhesive layer is used to enhance the stability and hydrophobicity of the bottom structure; the conductive combined layer comprises a barrier layer and a wetting layer, the barrier layer is arranged on the base adhesive layer, and the wetting layer is arranged on the barrier layer. The side surface of the base adhesive layer away from the chip is at least partially concave, and the arc-shaped groove is formed, so that the barrier layer and the wetting layer are both arched towards the chip, and the electrical stud is at least partially convex towards the side surface of the chip. The edge thickness H1 of the base adhesive layer is the sum of the thickness H2 of the barrier layer and the thickness H3 of the wetting layer. The width L1 of the part of the base adhesive layer extending to the protective layer is 4-8 μm, and the projection of the base adhesive layer on the front surface of the chip, the projection of the barrier layer on the front surface of the chip and the projection of the wetting layer on the front surface of the chip are overlapped.

2. The bump package structure of claim 1, wherein, The side of the electrical stud away from the chip is further provided with a stop layer, the stop layer is arranged between the cap layer and the electrical stud, and is used to block the diffusion atoms between the cap layer and the electrical stud.

3. The bump package structure of claim 1, wherein, The side of the electrical stud away from the chip is further provided with a conductive adhesive layer, the conductive adhesive layer is arranged between the stop layer and the electrical stud, and the conductive adhesive layer is a graphene layer.

4. The bump package structure of claim 3, wherein, The side surface of the electrical stud away from the chip is at least partially concave, so that the stop layer and the conductive adhesive layer are both arched towards the chip, and the cap layer is at least partially convex towards the side surface of the chip.

5. The bump package structure of claim 4, wherein, The chip is provided with a solder pad on the front surface thereof.

6. A method for manufacturing a bump package structure according to any one of claims 1 to 5, characterized by, A protective layer is arranged on the front surface of the chip. A protective opening is formed on the protective layer by slotting at a position corresponding to the solder pad. A base adhesive layer is formed in the protective opening. An arc-shaped groove is etched on the base adhesive layer. A conductive combined layer is formed on the base adhesive layer. An electrical stud is formed on the conductive combined layer. A cap layer is formed on the electrical stud. ​ ​ The base adhesive layer includes a plurality of layers of graphene material, a top edge of the base adhesive layer extends outwardly onto the protective layer and covers an edge of the protective opening, and the electrically conductive assembly is at least partially housed within the arcuate recess.

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