Semiconductor memory devices

Abstract

The embodiments provide a semiconductor memory device capable of achieving high integration. The semiconductor memory device of the embodiments includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, a second semiconductor layer, a first insulating layer, and a second insulating layer. Two of the plurality of first semiconductor layers are designated as the third and fourth semiconductor layers. The width of the third semiconductor layer is designated as a first width, the distance between the third semiconductor layer and the first insulating layer is designated as a first distance, and the distance between the third semiconductor layer and the second insulating layer is designated as a second distance. The width of the fourth semiconductor layer is designated as a second width, the distance between the fourth semiconductor layer and the first insulating layer is designated as a third distance, and the distance between the fourth semiconductor layer and the second insulating layer is designated as a fourth distance. A smaller of the first distance and the second distance is less than a smaller of the third distance and the fourth distance, and the first width is greater than the second width.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-049127 (filed on March 23, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The embodiments described below relate to semiconductor memory devices. Background Technology

[0004] A known semiconductor memory device comprises a substrate, a plurality of gate electrodes stacked in a direction intersecting the surface of the substrate, a semiconductor layer opposite to the plurality of gate electrodes, and a gate insulating layer disposed between the gate electrodes and the semiconductor layer. The gate insulating layer comprises a storage section capable of storing data, such as a charge storage section with insulating properties, such as silicon nitride (Si3N4), or a charge storage section with conductive properties, such as a floating gate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that can achieve high integration.

[0006] A semiconductor memory device according to one embodiment includes: a first conductive layer extending along a first direction; a second conductive layer disposed at a distance from the first conductive layer in a second direction intersecting the first direction and extending along the first direction; a third conductive layer disposed at a distance from both the first and second conductive layers in the second direction and extending along the first direction; a plurality of first semiconductor layers disposed between the first and second conductive layers, arranged in the first direction, and opposite to the first and second conductive layers; a plurality of first memory cells disposed between the first conductive layer and the plurality of first semiconductor layers; a plurality of second memory cells disposed between a second conductive layer and the plurality of first semiconductor layers; and a plurality of second semiconductor layers disposed between the second and third conductive layers and arranged in the first direction. Opposite to the second conductive layer and the third conductive layer; a plurality of third memory cells disposed between the second conductive layer and the plurality of second semiconductor layers; a plurality of fourth memory cells disposed between the third conductive layer and the plurality of second semiconductor layers; a first insulating layer disposed between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer, wherein the width in a second direction is greater than the width in a second direction of the plurality of first semiconductor layers and the plurality of second semiconductor layers; and a second insulating layer disposed between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer, wherein the position in a first direction is different from that of the first insulating layer, and the width in a second direction is greater than the width in a second direction of the plurality of first semiconductor layers and the plurality of second semiconductor layers. Two of the plurality of first semiconductor layers are designated as the third semiconductor layer and the fourth semiconductor layer. The width of the third semiconductor layer in the first direction is designated as the first width. The distance between the third semiconductor layer and the first insulating layer in the first direction is designated as the first distance. The distance between the third semiconductor layer and the second insulating layer in the first direction is designated as the second distance. The width of the fourth semiconductor layer in the first direction is designated as the second width. The distance between the fourth semiconductor layer and the first insulating layer in the first direction is designated as the third distance. The distance between the fourth semiconductor layer and the second insulating layer in the first direction is designated as the fourth distance. The smaller of the first distance and the second distance is less than the smaller of the third distance and the fourth distance, and the first width is greater than the second width. Attached Figure Description

[0007] Figure 1 This is a schematic equivalent circuit diagram of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic top view of the semiconductor memory device.

[0009] Figure 3 This is a schematic cross-sectional view of the semiconductor memory device.

[0010] Figure 4 This is a schematic cross-sectional view of the semiconductor memory device.

[0011] Figure 5 This is a schematic cross-sectional view of the semiconductor memory device.

[0012] Figure 6 This is a schematic cross-sectional view of the semiconductor memory device.

[0013] Figure 7 This is a schematic cross-sectional view of the semiconductor memory device.

[0014] Figure 8 This is a schematic cross-sectional view of the semiconductor memory device.

[0015] Figure 9 This is a schematic cross-sectional view of the semiconductor memory device.

[0016] Figure 10 This is a schematic cross-sectional view of the semiconductor memory device.

[0017] Figure 11 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device.

[0018] Figure 12 It is a schematic cross-sectional view illustrating the manufacturing method.

[0019] Figure 13 It is a schematic cross-sectional view illustrating the manufacturing method.

[0020] Figure 14 It is a schematic cross-sectional view illustrating the manufacturing method.

[0021] Figure 15 It is a schematic cross-sectional view illustrating the manufacturing method.

[0022] Figure 16 It is a schematic cross-sectional view illustrating the manufacturing method.

[0023] Figure 17 It is a schematic cross-sectional view illustrating the manufacturing method.

[0024] Figure 18 It is a schematic cross-sectional view illustrating the manufacturing method.

[0025] Figure 19 It is a schematic cross-sectional view illustrating the manufacturing method.

[0026] Figure 20 It is a schematic cross-sectional view illustrating the manufacturing method.

[0027] Figure 21 It is a schematic cross-sectional view illustrating the manufacturing method.

[0028] Figure 22 It is a schematic cross-sectional view illustrating the manufacturing method.

[0029] Figure 23 It is a schematic cross-sectional view illustrating the manufacturing method.

[0030] Figure 24 It is a schematic cross-sectional view illustrating the manufacturing method.

[0031] Figure 25 It is a schematic cross-sectional view illustrating the manufacturing method.

[0032] Figure 26 It is a schematic cross-sectional view illustrating the manufacturing method.

[0033] Figure 27 It is a schematic cross-sectional view illustrating the manufacturing method.

[0034] Figure 28 It is a schematic cross-sectional view illustrating the manufacturing method.

[0035] Figure 29 It is a schematic cross-sectional view illustrating the manufacturing method.

[0036] Figure 30 It is a schematic cross-sectional view illustrating the manufacturing method.

[0037] Figure 31 It is a schematic cross-sectional view illustrating the manufacturing method.

[0038] Figure 32 It is a schematic cross-sectional view illustrating the manufacturing method.

[0039] Figure 33 It is a schematic cross-sectional view illustrating the manufacturing method.

[0040] Figure 34 It is a schematic cross-sectional view illustrating the manufacturing method.

[0041] Figure 35 It is a schematic cross-sectional view illustrating the manufacturing method.

[0042] Figure 36 It is a schematic cross-sectional view illustrating the manufacturing method.

[0043] Figure 37 It is a schematic cross-sectional view illustrating the manufacturing method.

[0044] Figure 38 It is a schematic cross-sectional view illustrating the manufacturing method.

[0045] Figure 39It is a schematic cross-sectional view illustrating the manufacturing method.

[0046] Figure 40 It is a schematic cross-sectional view illustrating the manufacturing method.

[0047] Figure 41 It is a schematic cross-sectional view illustrating the manufacturing method.

[0048] Figure 42 It is a schematic cross-sectional view illustrating the manufacturing method.

[0049] Figure 43 It is a schematic cross-sectional view illustrating the manufacturing method.

[0050] Figure 44 It is a schematic cross-sectional view illustrating the manufacturing method.

[0051] Figure 45 It is a schematic cross-sectional view illustrating the manufacturing method.

[0052] Figure 46 It is a schematic cross-sectional view illustrating the manufacturing method.

[0053] Figure 47 It is a schematic cross-sectional view illustrating the manufacturing method.

[0054] Figure 48 It is a schematic cross-sectional view illustrating the manufacturing method.

[0055] Figure 49 It is a schematic cross-sectional view illustrating the manufacturing method.

[0056] Figure 50 It is a schematic cross-sectional view illustrating the manufacturing method.

[0057] Figure 51 This is a schematic cross-sectional view showing the etching progress of the sacrificial layer 110A over time.

[0058] Figure 52 This is a schematic cross-sectional view showing the etching progress of the sacrificial layer 110A over time.

[0059] Figure 53 This is a schematic cross-sectional view showing the memory cell MC, which is close to the insulating layer STH.

[0060] Figure 54 This is a schematic cross-sectional view showing the memory cell MC, which is relatively far from the insulating layer STH.

[0061] Figure 55 This is a schematic cross-sectional view of a modified semiconductor memory device. Detailed Implementation

[0062] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are illustrative, and for ease of explanation, some structures may be omitted. Furthermore, common parts in multiple embodiments are given the same reference numerals, and descriptions may be omitted in some cases.

[0063] Furthermore, when the term "semiconductor memory device" is used in this specification, it sometimes means a memory die, and sometimes it means a memory system including the control die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes means the structure of a smartphone, tablet, personal computer, or similar device, including the mainframe computer.

[0064] Furthermore, when this specification states that the first structure is "electrically connected" to the second structure, it can mean that the first structure is directly connected to the second structure, or that the first structure is connected to the second structure through wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0065] Furthermore, when this specification states that the first structure is "connected" to the second and third structures, it may mean that the first, second, and third structures are connected in series, and the second structure is connected to the third structure via the first structure.

[0066] Furthermore, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0067] Furthermore, in this specification, the direction along a defined surface is referred to as the first direction, the direction along the defined surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the defined surface is referred to as the third direction. These first, second, and third directions may or may not correspond to one of the X, Y, and Z directions.

[0068] Furthermore, in this specification, the terms "upper" and "lower," etc., are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it means the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it means the surface or end of the structure on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0069] [First Implementation]

[0070] [structure]

[0071] Figure 1 This is a schematic equivalent circuit diagram of the semiconductor memory device according to the first embodiment.

[0072] The semiconductor memory device of this embodiment includes a memory cell array (MCA) and a control unit (CU) for controlling the memory cell array (MCA).

[0073] The memory cell array (MCA) has multiple memory cells (MUs). Each of these memory cells (MUs) has two electrically independent memory strings (MSa and MSb). One end of each memory string (MSa and MSb) is connected to a drain-side select transistor (STD) and then to a common bit line (BL). The other end of each memory string (MSa and MSb) is connected to a source-side select transistor (STS) and then to a common source line (SL).

[0074] Memory strings MSa and MSb each have multiple memory cells MC connected in series. Each memory cell MC is a field-effect transistor with a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer has a charge storage section capable of storing data. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage section. The gate electrode is part of the word line WL.

[0075] A selection transistor (STD, STS) is a field-effect transistor that has a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of a drain-side selection transistor (STD) is part of the drain-side select gate line (SGD). The gate electrode of a source-side selection transistor (STS) is part of the source-side select gate line (SGS).

[0076] The control unit (CU) generates, for example, the voltages required for read, write, and delete operations, and supplies them to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS). The control unit (CU) may include, for example, multiple transistors and wiring disposed on the same substrate as the memory cell array (MCA), or multiple transistors and wiring disposed on a different substrate from the memory cell array (MCA).

[0077] Figure 2 This is a schematic top view illustrating a structural example of the semiconductor memory device according to this embodiment.

[0078] The semiconductor memory device of this embodiment includes a semiconductor substrate 100. In the illustrated example, the semiconductor substrate 100 has four memory cell array regions R arranged in the X and Y directions. MCA In each memory cell array region R MCA There are multiple memory blocks BLK arranged in the Y direction. Each memory block BLK extends along the X direction.

[0079] The semiconductor substrate 100 is, for example, a semiconductor substrate made of single-crystal silicon (Si). The semiconductor substrate 100 has, for example, an n-type impurity layer on its upper surface, and further, a double-well structure having a p-type impurity layer within this n-type impurity layer. Additionally, a control unit CU may be provided on the surface of the semiconductor substrate 100. Figure 1 At least a portion of the transistors, wiring, etc.

[0080] Figure 3 It represents the memory cell array region R. MCA A schematic XY cross-sectional view of a portion of the structure. Figure 4 It means Figure 3 A schematic XY cross-sectional view of the structure of region Rc shown. Figure 5 It is Figure 4 The structure shown is a schematic YZ sectional view taken when cut along line A-A′ and viewed in the direction of the arrow. Figure 6 It means Figure 3 The diagram shows a schematic XY cross-sectional view of the structure of region Rs. Figure 7 It is Figure 6 The structure shown is a schematic YZ sectional view taken when cut along line B-B′ and viewed in the direction of the arrow. Figure 8 It means Figure 3 A schematic enlarged view of a portion of the structure. Figure 9 It is Figure 8 The structure shown is a schematic YZ cross-sectional view taken when cut along the C-C′ line and viewed in the direction of the arrow.

[0081] The semiconductor memory device of this embodiment is, for example, such as Figure 3 , Figure 4 ,as well as Figure 6 As shown, the semiconductor substrate 100 includes multiple laminated structures LS and multiple trench structures AT. The multiple laminated structures LS are arranged along the Y direction on the semiconductor substrate 100. The multiple trench structures AT are respectively disposed between the multiple laminated structures LS.

[0082] Layered structure LS ( Figure 5 , Figure 7 It includes multiple conductive layers 110, semiconductor layers 115, and semiconductor layers 116. The multiple conductive layers 110, semiconductor layers 115, and semiconductor layers 116 are stacked in the Z direction via an insulating layer 101 such as silicon oxide (SiO2).

[0083] Trench construction AT ( Figure 3 It has multiple storage hole regions R arranged in the X direction. MH and two adjacent storage hole regions R in the X direction MH The trapezoidal ladder region R between LD .

[0084] Storage hole area R MH It includes multiple semiconductor layers 120 arranged in the X direction. The multiple semiconductor layers 120 are, for example, as shown in... Figure 3 As shown, they are arranged in a periodic P1 along the X direction. Furthermore, gate insulating layers 130 are provided between the plurality of semiconductor layers 120 and the plurality of conductive layers 110. An insulating layer 150, such as silicon oxide (SiO2), is provided between two adjacent semiconductor layers 120 along the X direction.

[0085] Trapezoidal region R LD It may or may not contain an insulating layer (STH) such as silicon dioxide (SiO2). An insulating layer (STH) is, for example... Figure 3 As shown, they are arranged in the X direction with a period P2. Period P2 is greater than period P1. Furthermore, the width Y_STH of the insulating layer STH in the Y direction is greater than the width Y_120 of the semiconductor layer 120 in the Y direction.

[0086] In addition, for example, Figure 3 As shown, multiple insulating layers STH can also be arranged in an alternating pattern in the XY section. In this case, sometimes the insulating layer STH provided in the odd-numbered trench structure AT counting from one side in the Y direction is called insulating layer STH_O. Furthermore, sometimes the insulating layer STH provided in the even-numbered trench structure AT counting from one side in the Y direction is called insulating layer STH_E. Multiple insulating layers STH_O can also be provided in the odd-numbered trapezoidal region R counting from one side in the X direction. LDHowever, it was not set in the even-numbered trapezoidal region R. LD Multiple insulating layers STH_O can also be arranged in the Y direction. Multiple insulating layers STH_E can also be located in the even-numbered trapezoidal region R counting from one side in the X direction. LD However, it was not set in the odd-numbered trapezoidal region R. LD Multiple insulating layers STH_E can also be arranged in the Y direction.

[0087] Multiple conductive layers 110, for example, Figure 5 as well as Figure 7 As shown, they are arranged in the Z direction. The conductive layer 110 extends along the X direction. The conductive layer 110 is, for example, as shown in... Figure 9 The image shows a stacked film comprising a barrier conductive layer 111 such as titanium nitride (TiN) and a metal film 112 such as tungsten (W). A portion of the conductive layer 110 serves as the word line WL and the memory cell MC. Figure 1 The gate electrode of the conductive layer 110 functions as a gate line. Furthermore, a portion of the conductive layer 110 disposed above these conductive layers 110 serves as the drain-side selected gate line SGD and the drain-side selected transistor STD. Figure 1 The gate electrode of the device functions. Additionally, as... Figure 9 As shown, insulating metal oxide layers 113, such as aluminum oxide (AlO), may also be provided on the upper surface, lower surface, and side surface of the conductive layer 110 in a manner that covers these portions.

[0088] Semiconductor layer 115 ( Figure 5 , Figure 7 The semiconductor layer 115 is disposed below the plurality of conductive layers 110. The semiconductor layer 115 extends along the X direction. The semiconductor layer 115 is, for example, a semiconductor layer comprising polysilicon (Si). The semiconductor layer 115 serves as the source-side selected gate line (SGS) and the source-side selected transistor (STS). Figure 1 The gate electrode of the ) performs its function.

[0089] Semiconductor layer 116 is disposed below semiconductor layer 115. Semiconductor layer 116 extends along the X direction. Semiconductor layer 116 is, for example, a semiconductor layer containing polysilicon (Si). Semiconductor layer 116 serves as the source line SL. Figure 1 It plays a part of the function.

[0090] Furthermore, in the following description, considering two adjacent laminated structures LS in the Y direction, the plurality of conductive layers 110 contained in one of the laminated structures LS are referred to as conductive layers 110a. Figure 4 , Figure 6In addition, there are cases where the multiple conductive layers 110 contained in the other party's laminated structure LS are referred to as conductive layers 110b. Figure 4 , Figure 6 In this case, conductive layer 110a and conductive layer 110b are electrically independent. Therefore, different voltages can be supplied to conductive layer 110a and conductive layer 110b. Conductive layer 110a functions as the gate electrode of the memory cell MC included in the memory string MSa, or as the gate electrode of the drain-side selection transistor STD included in the memory string MSa. Conductive layer 110b functions as the gate electrode of the memory cell MC included in the memory string MSb, or as the gate electrode of the drain-side selection transistor STD included in the memory string MSb.

[0091] Semiconductor layer 120 extends along the Z direction ( Figure 5 , Figure 7 The semiconductor layer 120 is, for example, an undoped polycrystalline silicon (Si) semiconductor layer. The semiconductor layer 120 has a generally bottomed, quadrangular cylindrical shape, and an insulating layer 125 such as silicon oxide (SiO2) is provided in the central portion. The region of the semiconductor layer 120 opposite to the plurality of conductive layers 110a serves as the memory string MSa. Figure 1 The channel regions of the multiple memory cells MC contained in the semiconductor layer 120, as well as the channel regions of the drain-side select transistor (STD) and source-side select transistor (STS), function as memory strings (MSb). The region in the semiconductor layer 120 opposite to the multiple conductive layers 110b serves as the memory string (MSb). Figure 1 The channel regions of the multiple memory cells MC contained therein, as well as the channel regions of the drain-side select transistor STD and the source-side select transistor STS, function as such.

[0092] At the upper end of the semiconductor layer 120, a semiconductor layer 121 containing N-type impurities such as phosphorus (P) is provided. Figure 5 The semiconductor layer 121 is connected to the bit line BL extending in the Y direction via a bit line contact BLC made of tungsten (W) or the like.

[0093] In the illustrated example, the lower end of semiconductor layer 120 is connected to semiconductor layer 116.

[0094] Gate insulating layer 130 ( Figure 8 , Figure 9 It includes a tunnel insulating layer 131, a charge storage layer 132, and a block insulating layer 133 disposed from the semiconductor layer 120 side toward the conductive layer 110 side.

[0095] The tunnel insulation layer 131 may comprise, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or other insulating layers. The tunnel insulation layer 131 may include, for example,... Figure 5As shown, it can extend along the Z-direction along the outer peripheral surface of the semiconductor layer 120. Additionally, the tunnel insulating layer 131 can also be formed on the side surfaces of the charge accumulation layer 132 in the Y-direction.

[0096] The charge storage layer 132 is, for example, a floating gate containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). However, the charge storage layer 132 may also be an insulating charge storage section containing silicon nitride (SiN).

[0097] Additionally, in the following explanations, for example... Figure 4 as well as Figure 6 As shown, the plurality of charge storage layers 132 disposed between the conductive layer 110a and the plurality of semiconductor layers 120 are sometimes referred to as charge storage layer 132a. In addition, the plurality of charge storage layers 132 disposed between the conductive layer 110b and the plurality of semiconductor layers 120 are sometimes referred to as charge storage layer 132b.

[0098] For example, the barrier insulating layer 133 Figure 8 as well as Figure 9 As shown, it includes an insulating layer 134, a high dielectric constant layer 135, and an insulating layer 136.

[0099] The insulating layer 134 is, for example, a laminated film comprising silicon oxide (SiO2) or titanium nitride (TiN) and silicon oxide (SiO2). The insulating layer 134 is, for example... Figure 8 As shown, it is configured to cover a portion of the outer peripheral surface of the charge accumulation layer 132 in the XY section. Furthermore, the insulating layer 134 is as follows... Figure 9 As shown, the upper surface, lower surface, and side surface of the charge accumulation layer 132, as well as the side surface of the conductive layer 110, are covered in the YZ cross section.

[0100] High dielectric constant layer 135, for example, is an insulating material containing hafnium silicate (HfSiO) and having a relatively high relative dielectric constant. High dielectric constant layer 135, such as... Figure 8 As shown, the charge accumulation layer 132 is arranged such that it covers a portion of the outer peripheral surface of the charge accumulation layer 132 in the XY section, separated by an insulating layer 134. Furthermore, the high dielectric constant layer 135 is as follows... Figure 9 As shown, the upper surface, lower surface, and side surface of the insulating layer 134, as well as the side surface of the conductive layer 110, are covered in the YZ cross section.

[0101] Insulating layer 136 may be, for example, an insulating layer comprising silicon oxide (SiO2) or the like. Insulating layer 136 may be... Figure 8 As shown, the charge accumulation layer 132 is arranged such that it covers a portion of the outer peripheral surface of the charge accumulation layer 132 in the XY section, separated by a high dielectric constant layer 135. The insulating layer 136 is as follows... Figure 9As shown, the upper surface, lower surface, and side surface of the high dielectric constant layer 135, as well as the side surface of the conductive layer 110, are covered in the YZ cross section.

[0102] Insulation layer STH ( Figure 6 , Figure 7 It extends along the Z direction and is opposed to multiple conductive layers 110 in the X and Y directions. The insulating layer STH includes, for example, an insulating layer such as silicon oxide (SiO2).

[0103] [Width of semiconductor layer 120]

[0104] Next, refer to Figure 10 The width of the multiple semiconductor layers 120 in the X direction is described. Figure 10 It represents the memory cell array region R. MCA A schematic XY cross-sectional view of a portion of the structure.

[0105] like Figure 10 As shown, in the semiconductor memory device of this embodiment, among the plurality of semiconductor layers 120, the memory hole region R... MH The closer the semiconductor layer is to the center in the X direction, the smaller its width in the X direction, compared to the memory hole region R. MH The further away a semiconductor layer is from its center in the X direction, the wider it is in the X direction.

[0106] The following will provide a detailed explanation of this point. Furthermore, in the following description, one of the conductive layers 110 extending along the X direction will be referred to as conductive layer 110_a1. Additionally, a conductive layer 110 disposed away from conductive layer 110_a1 in the Y direction and extending along the X direction will be referred to as conductive layer 110_b2. Furthermore, a conductive layer 110 disposed away from conductive layers 110_a1 and 110_b2 in the Y direction and extending along the X direction will be referred to as conductive layer 110_a3. A plurality of semiconductor layers 120 disposed between conductive layers 110_a1 and 110_b2, arranged in the X direction, and opposite conductive layers 110_a1 and 110_b2 will be referred to as a plurality of semiconductor layers 120_1. The plurality of semiconductor layers 120 disposed between conductive layer 110_b2 and conductive layer 110_a3, arranged in the X direction and opposite to conductive layer 110_b2 and conductive layer 110_a3 are referred to as the plurality of semiconductor layers 120_2.

[0107] Furthermore, in the following description, the storage hole area R will be... MH The included multiple semiconductor layers 120_1, and the memory hole region R MH The semiconductor layer closest to one end in the X direction and the semiconductor layer closest to the other end in the X direction are respectively referred to as semiconductor layer 120_11. Furthermore, it will be connected to the memory hole region R.MH The semiconductor layer closest to one end in the X direction and the semiconductor layer closest to the other end in the X direction are respectively referred to as semiconductor layer 120_12. Similarly, below, the memory hole region R will be referred to as... MH The semiconductor layer closest to one end in the X direction (n is an integer greater than or equal to 1) and the semiconductor layer closest to the other end in the X direction are respectively referred to as semiconductor layer 120_1n. Furthermore, the width of semiconductor layer 120_1n is referred to as width X1n. Width X1n is greater than width X1(n+1).

[0108] For example, this represents the cases where n is 1 and 2. Semiconductor layer 120_11 and semiconductor layer 120_12 are provided with widths of X11 and X12 respectively in the X direction. Width X11 is greater than width X12.

[0109] Furthermore, the distance in the X direction between semiconductor layer 120_11 and insulating layer STH_O is referred to as distance D_SO_11, and the distance in the X direction between semiconductor layer 120_11 and insulating layer STH_E is referred to as distance D_SE_11. Similarly, the distance in the X direction between semiconductor layer 120_12 and insulating layer STH_O is referred to as distance D_SO_12, and the distance in the X direction between semiconductor layer 120_12 and insulating layer STH_E is referred to as distance D_SE_12. In this case, the smaller of distances D_SO_11 and D_SE_11 is smaller than the smaller of distances D_SO_12 and D_SE_12.

[0110] Furthermore, in the following description, the storage hole area R will be... MH The included multiple semiconductor layers 120_2, and the memory hole region R MH The semiconductor layer approaching the m-th end (m is an integer greater than or equal to 1) in the X direction and the semiconductor layer approaching the m-th end in the other X direction are respectively referred to as semiconductor layer 120_2m. Furthermore, the width of semiconductor layer 120_2m is referred to as width X2m. Width X2m is greater than width X2(m+1).

[0111] For example, this represents the cases where m is 1 and 2. Semiconductor layer 120_21 and semiconductor layer 120_22 are provided with widths of X21 and X22 respectively in the X direction. Width X21 is greater than width X22.

[0112] Furthermore, the distance in the X direction between semiconductor layer 120_21 and insulating layer STH_O is referred to as distance D_SO_21, and the distance in the X direction between semiconductor layer 120_21 and insulating layer STH_E is referred to as distance D_SE_21. Similarly, the distance in the X direction between semiconductor layer 120_22 and insulating layer STH_O is referred to as distance D_SO_22, and the distance in the X direction between semiconductor layer 120_22 and insulating layer STH_E is referred to as distance D_SE_22. In this case, the smaller of distances D_SO_21 and D_SE_21 is smaller than the smaller of distances D_SO_22 and D_SE_22.

[0113] Furthermore, in the above structure, the plurality of semiconductor layers 120_1 may also be opposed to the plurality of conductive layers 110_a1 and the plurality of conductive layers 110_b2 arranged in the Z direction, respectively. In addition, the plurality of semiconductor layers 120_2 may also be opposed to the plurality of conductive layers 110_b2 and the plurality of conductive layers 110_a3 arranged in the Z direction, respectively.

[0114] [Width of charge accumulation layer 132]

[0115] like Figure 10 As shown, in the semiconductor memory device of this embodiment, among the plurality of charge accumulation layers 132, the storage hole region R... MH The closer the charge accumulation layer is to the center in the X direction, the smaller its width in the X direction, compared to the storage aperture region R. MH The farther the charge accumulation layer is from the center in the X direction, the wider it is in the X direction.

[0116] [Manufacturing Method]

[0117] Next, refer to Figures 11 to 50 The manufacturing method of the semiconductor memory device according to this embodiment will be described.

[0118] Figure 11 , Figure 13 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 45 , Figure 49 This is a schematic XY sectional view used to illustrate the manufacturing method, corresponding to Figure 4 The part shown. Figure 15 , Figure 39 , Figure 41 , Figure 43 , Figure 47 This is a schematic XY sectional view used to illustrate the manufacturing method, corresponding to Figure 6 The part shown.

[0119] Figure 12 , Figure 14 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 46 , Figure 50 This is a schematic YZ sectional view used to illustrate the manufacturing method, corresponding to Figure 5 The part shown. Figure 16 , Figure 40 , Figure 42 , Figure 44 , Figure 48 This is a schematic YZ sectional view used to illustrate the manufacturing method, corresponding to Figure 7 The part shown.

[0120] like Figure 11 as well as Figure 12 As shown, in this manufacturing method, semiconductor layer 116, semiconductor layer 115, sacrificial layer 110A, and multiple insulating layers 101 are alternately stacked on a semiconductor substrate 100 (not shown). The sacrificial layer 110A is, for example, made of silicon nitride (SiN). The insulating layer 103 is, for example, made of silicon oxide (SiO2). This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0121] Next, as Figures 13-16 As shown, a trench ATT′ is formed on a laminated structure including insulating layer 103, insulating layer 101, and sacrificial layer 110A. In this process, in... Figure 12 The upper surface of the structure shown is formed with an insulating layer, for example, having openings in the portion corresponding to the trench ATT′, which is then used as a mask for RIE (Reactive Ion Etching). Figure 13 as well as Figure 15 As shown, the trenches ATT′ extend along the X direction for a specified length and are provided in multiples at specified intervals. Furthermore, as... Figure 14 as well as Figure 16As shown, the trench ATT′ extends along the Z direction, penetrating the insulating layer 103, multiple insulating layers 101, and multiple sacrificial layers 110A, thus separating these structures in the Y direction.

[0122] Next, as Figure 17 as well as Figure 18 As shown, an insulating layer 170 is formed on the upper surface of the insulating layer 103 and on the bottom and side surfaces of the trench ATT′. The insulating layer 170 is made of, for example, silicon oxide (SiO2). This process is performed, for example, by a method such as CVD. Furthermore, a carbon film 171 embedded in the trench ATT′ is formed on the upper surface of the insulating layer 170. The carbon film 171 is formed, for example, by spin-coating a coating-type carbon material. Then, the upper part of the carbon film 171 is removed until it reaches the same position as the upper surface of the insulating layer 170. The removal of the carbon film 171 is performed, for example, by a refining process called RIE.

[0123] Next, as Figure 19 as well as Figure 20 As shown, in Figure 18 The upper surface of the structure shown is formed with a hard mask 172 and a photoresist 173. The hard mask 172 is made of, for example, silicon oxide (SiO2). The hard mask 172 is formed, for example, by CVD. The photoresist 173 is formed by spin coating of the photoresist material. Furthermore, an opening AHa′ is formed using the photoresist 173 as a mask. The opening AHa′ penetrates the hard mask 172 and the insulating layer 170, exposing the carbon film 171. The opening AHa′ is formed, for example, by photolithography and RIE.

[0124] Next, as Figure 21 as well as Figure 22 As shown, the portion of the carbon film 171 and the insulating layer 170 located at the position corresponding to the opening AHa′ is removed to form the opening AHa. The process of removing the carbon film 171 is performed, for example, by RIE (Residual Etching). The process of removing the insulating layer 170 is performed, for example, by chemical dry etching. Hereinafter, the multiple portions of the trench ATT′ divided by the multiple openings AHa arranged in the X direction will be referred to as the trench ATT.

[0125] Next, as Figure 23 as well as Figure 24 As shown, from Figure 22 The resist 173, hard mask 172, and insulating layer 170 are removed from the upper surface of the structure shown. This process is performed, for example, by ashing or RIE.

[0126] Furthermore, an insulating layer 174 of silicon oxide (SiO2) or the like is formed on the bottom and side surfaces of the opening AHa. Additionally, a semiconductor layer 175 of amorphous silicon (Si) or the like, embedded in the opening AHa, is formed on the upper surface of the insulating layer 174. The insulating layer 174 and the semiconductor layer 175 are formed, for example, by a method such as CVD. Furthermore, the upper portions of the insulating layer 174 and the semiconductor layer 175 are removed until they reach the same position as the upper surface of the insulating layer 103. The removal of the insulating layer 174 and the semiconductor layer 175 is performed, for example, by a re-emulation (RIE) method.

[0127] Next, as Figure 25 as well as Figure 26 As shown, the carbon film 171 and the insulating layer 170 are removed from the interior of the trench ATT. This process is performed, for example, by ashing or RIE. Furthermore, an insulating layer 150 is formed inside the trench ATT, and the upper surface of the insulating layer 150 is removed until the upper surface of the insulating layer 103 is reached. This process is performed, for example, by CVD or RIE.

[0128] Next, as Figure 27 as well as Figure 28 As shown, the semiconductor layer 175 is removed from the interior of the opening AHa. This process is performed, for example, by wet etching. Furthermore, the insulating layer 174 is removed from the interior of the opening AHa, and then the bottom of the opening AHa is removed until the bottom surface of the opening AHa is aligned with the upper surface of the semiconductor layer 116. This process is performed, for example, by RIE (Residual Insulation).

[0129] Next, as Figure 29 as well as Figure 30 As shown, a portion of the sacrificial layer 110A is removed through opening AHa to form opening AHb. This process exposes portions of the upper and lower surfaces of the insulating layer 101 located near opening AHa. This process is performed, for example, by wet etching.

[0130] Next, as Figure 31 as well as Figure 32 As shown, an insulating layer 133' and a charge accumulation layer 132 are sequentially formed on the side of the opening AHb via the opening AHb. The insulating layer 133' is formed by sequentially depositing an insulating layer 136 (not shown), a high dielectric constant layer 135, and an insulating layer 134. Furthermore, a semiconductor layer of the same material as the charge accumulation layer 132, such as polycrystalline silicon (Si), is deposited on the side of the opening AHb via the opening AHb, and then a portion of the semiconductor layer is removed, thereby forming a plurality of charge accumulation layers 132 arranged in the Z direction corresponding to the sacrificial layer 110A. This process is performed, for example, by CVD or wet etching.

[0131] Next, as Figure 33 as well as Figure 34 As shown, a tunnel insulating layer 131 is formed on the inner peripheral surface of the opening AHb. Furthermore, the portion of the tunnel insulating layer 131 and the insulating layer 133' that covers the bottom surface of the opening AHb is removed to form a barrier insulating layer 133. This process is performed, for example, by CVD or RIE.

[0132] Next, as Figure 35 as well as Figure 36 As shown, a semiconductor layer 120′ and an insulating layer 177 are formed inside the opening AHb. This process is performed, for example, by CVD.

[0133] Next, as Figure 37 as well as Figure 38 As shown, inside the opening AHb, a portion of the insulating layer 177 is removed until it reaches a position below the upper surface of the insulating layer 103, forming an insulating layer 125. Furthermore, inside the opening AHb, a portion of the semiconductor layer 120' is removed, and a semiconductor layer 121 is formed on top of it. This process is performed, for example, by RIE, CVD, etc. Additionally, in the processes up to this point, such as... Figure 39 as well as Figure 40 As shown, between adjacent trenches ATT in the X direction, there is a region of sacrificial layer 110A that is not separated in the Y direction.

[0134] Next, as Figure 41 as well as Figure 42 As shown, an opening STHa is formed between adjacent grooves ATT in the X direction. In this process, for example, in... Figure 40 The structure shown has an insulating layer formed on its upper surface with openings corresponding to the STHa opening, which is used as a mask for RIE (Reactive Ion Etching), etc. Figure 41 as well as Figure 42 As shown, the opening STHa extends along the Z direction, penetrating the insulating layer 103, multiple insulating layers 101, and multiple sacrificial layers 110A, thus separating these structures in the Y direction.

[0135] Next, as Figures 43-46 As shown, multiple sacrificial layers 110A are removed via the opening STHa to form multiple voids 110c. The process of removing the sacrificial layers 110A is performed, for example, by wet etching. Furthermore, as described later, this wet etching is performed from the region close to the opening STHa outwards.

[0136] Next, as Figures 47-50 As shown, multiple conductive layers 110 are formed via the opening STHa. The conductive layers 110 are as follows... Figure 6As shown, it is formed by forming a metal oxide layer 113, a barrier conductive layer 111, and a metal film 112 on the upper and lower surfaces of the insulating layer 101. This process is performed, for example, by CVD.

[0137] Then, silicon oxide (SiO2) and the like are deposited in the opening STHa to form an insulating layer STH, and bit line contacts BLC, bit lines BL, etc. are formed, thereby manufacturing the semiconductor memory device of the first embodiment.

[0138] [Wet etching of sacrificial layer 110A]

[0139] The following refers to Figures 43-46 The wet etching process for the sacrificial layer 110A is described in detail.

[0140] Examples of etching methods will be described, such as the sacrificial layer 110A being made of silicon nitride (SiN), the barrier insulating layer 133 not being etched, and the insulating layer 150 being made of silicon oxide (SiO2). In such a wet etching process, it is suitable to select a etching solution that has a fast etching rate for silicon nitride (SiN) being etched and a slow etching rate for silicon oxide (SiO2) not being etched. Furthermore, the etching solution can be, for example, phosphoric acid (H3PO4), or other suitable solutions.

[0141] Figure 51 as well as Figure 52 It is a schematic cross-sectional view showing the etching progress of the sacrificial layer 110A over time. Figure 51 This indicates the situation where the etching process begins from the start of the etching of the sacrificial layer 110A and proceeds to the imaginary line L1 after a specified time. Figure 52 This indicates the situation where, after a specified time has elapsed since the etching progressed to the imaginary line L1, the etching has progressed to the imaginary line L3. Thus, the etching begins near the opening STHa and, from the start to the end, proceeds gradually from the region closer to the opening STHa towards the region farther away over time.

[0142] In this etching process, the memory cells MC near the opening STHa are etched earlier. Therefore, the barrier insulating layer 133 of the memory cells MC near the opening STHa is exposed to the etching solution for a longer period. On the other hand, the memory cells MC far from the opening STHa are etched at a later stage. Therefore, the barrier insulating layer 133 of the memory cells MC far from the opening STHa is exposed to the etching solution for only a shorter period.

[0143] Regarding the shape of the memory cell MC after such a process, using... Figure 53 as well as Figure 54 Please provide an explanation. Figure 53 It is the YZ cross section of the memory cell MC, which is closer to the insulating layer STH. Figure 54 It is the YZ cross section of the memory cell MC, which is farther away from the insulating layer STH.

[0144] In the memory cell MC (which is close to the insulating layer STH) Figure 53 In the process, the insulating layer 133 is exposed to the liquid solution for a prolonged period, resulting in a thinning of the film thickness T11 in both the X and Y directions of the insulating layer 136. On the other hand, in the memory cell MC (located further from the insulating layer STH)... Figure 54 In this process, the insulating layer 133 is exposed to the liquid for only a short time. As a result, the film thickness T12 in the X and Y directions of the insulating layer 136 is thicker than the film thickness T11. Consequently, the memory cell MC that is closer to the opening STHa has a thinner insulating layer 136 in the X and Y directions.

[0145] [Effects of the first embodiment]

[0146] With the increasing integration of semiconductor memory devices, the density of memory cell (MC) configurations in the X and Y directions is being increased. To achieve this increased density, more memory cells (MCs) need to be configured on the XY plane, referring to… Figure 3 The trapezoidal region R, as described above, includes the opening STHa used to remove the sacrificial layer 110A. LD The quantity is preferably small. However, if the trapezoidal region R is made... LD If the quantity decreases, then in reference Figures 43-46 In the described process, there are cases where the distance between adjacent openings STHa in the X direction becomes longer.

[0147] When adjacent insulating layers STHs in the X direction are far apart, there are memory cells MCs that are close to and far from each other, as shown in the reference. Figure 53 as well as Figure 54 This explains the case where the thickness difference between the film thickness T11 and film thickness T12 of the insulating layer 136 increases.

[0148] Here, the effect of such film thickness difference on write operation characteristics is described. During the write operation, a specified write voltage is applied between the conductive layer 110 and the semiconductor layer 120, causing the charge accumulation layer 132 to accumulate the charge in the semiconductor layer 120, thereby adjusting the threshold voltage of the memory cell MC. The thin insulating layer 136 of the memory cell MC... Figure 53 In the storage cell MC (with a thick insulating layer 136), a strong electric field is applied to the charge accumulation layer 132, thus facilitating charge accumulation. Figure 54In this process, only a relatively weak electric field is applied to the charge accumulation layer 132, making it difficult for charge to accumulate. Thus, sometimes a distance-dependent relationship with the insulating layer STH occurs, where charge accumulation becomes increasingly difficult with greater distance from the STH. In such cases, there can be significant deviations in the threshold voltage of memory cells MC after a write operation among multiple memory cells MC.

[0149] Therefore, in the first embodiment, as referred to Figure 10 As explained, the farther the memory cell MC is from the insulating layer STH, the smaller the width of the semiconductor layer 120 in the X direction becomes. This is because, due to the phenomenon described later, the smaller the width of the semiconductor layer 120 in the X direction, the easier it is to accumulate charge in the charge accumulation layer 132.

[0150] Next, the phenomenon that the smaller the width of the semiconductor layer 120 in the X direction, the easier it is for charge to accumulate will be explained. In the XY section ( Figure 8 In this configuration, the charge storage layer 132 and the conductive layer 110 are opposed in the Y direction, but the opposing portions are included at both ends in the X direction. In this configuration, the smaller the width of the semiconductor layer 120 in the X direction, the greater the proportion of the opposing portions at both ends in the X direction. Therefore, the smaller the width of the semiconductor layer 120 in the X direction, the greater the ratio of the opposing area of ​​the charge storage layer 132 and the conductive layer 110 to the opposing area of ​​the charge storage layer 132 and the semiconductor layer 120.

[0151] Next, consider the ratio of the electrostatic capacitance between the charge storage layer 132 and the conductive layer 110 to the electrostatic capacitance between the charge storage layer 132 and the semiconductor layer 120 under this condition. Since the smaller the width of the semiconductor layer 120 in the X direction, the greater the ratio of the opposing areas of the charge storage layer 132 and the conductive layer 110, the higher the aforementioned electrostatic capacitance ratio. Thus, the higher the electrostatic capacitance ratio on the conductive layer 110 side where the voltage is applied, the easier it is for charge to accumulate in the charge storage layer 132.

[0152] Therefore, the farther the memory cell MC is from the insulating layer STH, the smaller the width of the semiconductor layer 120 in the X direction becomes. This counteracts the effect that the farther the memory cell MC is from the insulating layer STH, the thicker the insulating layer 133 becomes, and the more difficult it is for charge to accumulate. As a result, a semiconductor memory device can be provided that provides consistent characteristics of the memory cells MC in the XY cross section, suppresses operational deviations, and enables high-precision write operations.

[0153] [Modifications of the first embodiment]

[0154] Figure 55This is a schematic cross-sectional view of a semiconductor memory device according to a variation of the first embodiment. The semiconductor memory device of this variation is configured essentially the same as that of the first embodiment. However, unlike the first embodiment, the semiconductor memory device of this variation does not arrange the plurality of semiconductor layers 120 in a periodic P1 arrangement in the X direction, but rather arranges them with a spacing S1 between each semiconductor layer 120 and its adjacent counterparts. In this structure, the smaller the width of the semiconductor layer 120 in the X direction, the smaller the distance between the centers of the plurality of semiconductor layers 120. In this structure, the bit lines BL extending along the Y direction can be arranged either equally spaced or not equally spaced in the X direction.

[0155] [other]

[0156] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0157] Explanation of reference numerals in the attached figures

[0158] 100……Semiconductor substrate, 110……Conductive layer, 120……Semiconductor layer, 130……Gate insulating layer, 131……Tunnel insulating layer, 132……Charge storage layer, 133……Barrier insulating layer, 150……Insulating layer.

Claims

1. A semiconductor memory device, wherein, have: The first conductive layer extends along the first direction; The second conductive layer is disposed at a distance from the first conductive layer in a second direction intersecting the first direction and extends along the first direction; The third conductive layer is disposed at a distance from the first conductive layer and the second conductive layer in the second direction and extends along the first direction; A plurality of first semiconductor layers are disposed between the first conductive layer and the second conductive layer, arranged in the first direction, and opposite to the first conductive layer and the second conductive layer; A plurality of first memory cells are disposed between the first conductive layer and the plurality of first semiconductor layers; A plurality of second memory cells are disposed between the second conductive layer and the plurality of first semiconductor layers; A plurality of second semiconductor layers are disposed between the second conductive layer and the third conductive layer, arranged in the first direction, and opposite to the second conductive layer and the third conductive layer; A plurality of third memory cells are disposed between the second conductive layer and the plurality of second semiconductor layers; A plurality of fourth memory cells are disposed between the third conductive layer and the plurality of second semiconductor layers; A first insulating layer is disposed between at least one of the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer, wherein the width of the first insulating layer in the second direction is greater than the width of the plurality of first semiconductor layers and the plurality of second semiconductor layers in the second direction; as well as A second insulating layer is disposed between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer at least one of the two locations. The position of the second insulating layer in the first direction differs from that of the first insulating layer, and the width of the second insulating layer in the second direction is greater than the widths of the plurality of first semiconductor layers and the plurality of second semiconductor layers in the second direction. Two of the plurality of first semiconductor layers are designated as third semiconductor layers and fourth semiconductor layers. The width of the third semiconductor layer in the first direction is set as the first width. The distance in the first direction between the third semiconductor layer and the first insulating layer is defined as the first distance. The distance between the third semiconductor layer and the second insulating layer in the first direction is defined as the second distance. The width of the fourth semiconductor layer in the first direction is set as the second width. The distance between the fourth semiconductor layer and the first insulating layer in the first direction is defined as the third distance. When the distance in the first direction between the fourth semiconductor layer and the second insulating layer is defined as the fourth distance, The smaller of the first distance and the second distance is less than the smaller of the third distance and the fourth distance. The first width is greater than the second width.

2. The semiconductor memory device as claimed in claim 1, wherein, Two of the plurality of second semiconductor layers are designated as the fifth semiconductor layer and the sixth semiconductor layer. The width of the fifth semiconductor layer in the first direction is set as the third width. The distance between the fifth semiconductor layer and the first insulating layer in the first direction is defined as the fifth distance. The distance between the fifth semiconductor layer and the second insulating layer in the first direction is defined as the sixth distance. The width of the sixth semiconductor layer in the first direction is set as the fourth width. The distance between the sixth semiconductor layer and the first insulating layer in the first direction is defined as the seventh distance. When the distance in the first direction between the sixth semiconductor layer and the second insulating layer is set as the eighth distance, The smaller of the fifth distance and the sixth distance is less than the smaller of the seventh distance and the eighth distance. The third width is greater than the fourth width.

3. The semiconductor memory device as claimed in claim 2, wherein, have: The plurality of the first conductive layers are arranged in a third direction intersecting the first direction and the second direction; Multiple second conductive layers are arranged in the third direction; as well as Multiple third conductive layers are arranged in the third direction. The plurality of first semiconductor layers are respectively opposed to the plurality of first conductive layers and the plurality of second conductive layers. The plurality of second semiconductor layers are respectively opposed to the plurality of second conductive layers and the plurality of third conductive layers.

4. The semiconductor memory device as claimed in claim 3, wherein, The first insulating layer and the second insulating layer extend along the third direction and are opposite to the plurality of first conductive layers or the plurality of third conductive layers and the plurality of second conductive layers.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein, have: A plurality of first charge storage layers are disposed between the first conductive layer and the plurality of first semiconductor layers; and Multiple second charge storage layers are disposed between the second conductive layer and the multiple first semiconductor layers.

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