Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments of the present application provide a semiconductor storage device capable of achieving an improvement in electrical characteristics and a manufacturing method of a semiconductor storage device. The semiconductor storage device of the present embodiment has a first wiring, a second wiring, a first storage layer, and a first insulating film. The first insulating film is provided along a part of a surface of the second wiring and a surface of the first storage layer. The first insulating film is formed of Si, N, and O. In the third direction, a position of an end surface of the first storage layer on the side of the second wiring is set as a first position. A position of an end surface of the second wiring on the side opposite to the first storage layer is set as a second position. An atomic ratio (N / O) of N to O of the first insulating film at the first position is 1.0 or more. An atomic ratio (N / O) of N to O of the first insulating film at the second position is less than 1.0.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-044482 (filed on March 18, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] Semiconductor memory devices with cross-point structures that utilize phase-change memory (PCM) are known. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve electrical characteristics.

[0006] The semiconductor memory device of this embodiment includes a first wiring, a second wiring, a first memory layer, and a first insulating film. The first wiring extends along a first direction. The second wiring extends along a second direction intersecting the first direction and is disposed at a position different from the first wiring in a third direction intersecting both the first and second directions. The first memory layer is disposed between the first wiring and the second wiring in the third direction. The first insulating film is disposed along a portion of the surface of the second wiring and the surface of the first memory layer. The first insulating film is formed of Si, N, and O. In the third direction, the position of the end face of the first memory layer on the side of the second wiring is set as a first position. The position of the end face of the second wiring on the side opposite to the first memory layer is set as a second position. The atomic ratio (N / O) of the first insulating film at the first position is 1.0 or higher. The atomic ratio (N / O) of the first insulating film at the second position is less than 1.0. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a perspective view showing the memory cell of the first embodiment.

[0009] Figure 3 It is along Figure 2 The cross-sectional view of the memory cell shown is along line AA′.

[0010] Figure 4is a cross-sectional view taken along the line B-B' of the memory cell shown in Figure 2

[0011] Figure 5 is a graph showing the relationship between the position in the memory cell of the first embodiment and the measurement result of EDX.

[0012] Figure 6 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0013] Figure 7 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0014] Figure 8 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0015] Figure 9 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0016] Figure 10 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0017] Figure 11 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0018] Figure 12 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0019] Figure 13 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0020] Figure 14 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0021] Figure 15 is a cross-sectional view showing one example of the manufacturing process of the plurality of memory cells of the first embodiment.

[0022] Figure 16 is a perspective view showing the memory cell of the second embodiment.

[0023] Figure 17 is a cross-sectional view taken along the line A-A' of the memory cell shown in Figure 16

[0024] Figure 18 is a cross-sectional view taken along the line​​Figure 16 Cross-sectional view of the memory cell taken along the line B-B' shown in FIG. 1.

[0025] Figure 19 is a perspective view showing the memory cell of the third embodiment.

[0026] Figure 20 is a cross-sectional view of the memory cell taken along the line A-A' shown in FIG. 2. Figure 19 Cross-sectional view of the memory cell taken along the line B-B' shown in FIG. 2.

[0027] Figure 21 is a cross-sectional view of the memory cell taken along the line A-A' shown in FIG. 3. Figure 19 Cross-sectional view of the memory cell taken along the line B-B' shown in FIG. 3.

[0028] Figure 22 is a cross-sectional view of a plurality of memory cells of the fourth embodiment.

[0029] Explanation of symbols

[0030] 1 semiconductor storage device,

[0031] 11 silicon substrate,

[0032] 12 interlayer insulating layer,

[0033] 20 first conductive layer,

[0034] 30 storage layer,

[0035] 40 second conductive layer,

[0036] 50 selector layer,

[0037] 60 third conductive layer,

[0038] 70 pad film,

[0039] 72 N region,

[0040] 73 O region,

[0041] 74 boundary,

[0042] WL word line,

[0043] BL bit line,

[0044] MC memory cell,

[0045] G1 first position,

[0046] G2 second position,

[0047] G3 third position,

[0048] G4 fourth position DETAILED DESCRIPTION

[0049] Hereinafter, a semiconductor storage device of an embodiment is described with reference to the drawings. In the following description, the same reference signs are attached to the configurations having the same or similar functions as each other. The configurations having the same or similar functions as each other are sometimes not described repeatedly. In addition, "parallel", "orthogonal", "identical" and "equivalent" described in this specification respectively include "substantially parallel", "substantially orthogonal", "substantially identical" and "substantially equivalent".

[0050] "Connection" described in this specification is not limited to the case of physical connection, and includes the case of electrical connection. That is, so-called "connection" is not limited to the case where two members directly contact each other, and includes the case where another member is interposed between the two members. "Contact" described in this specification means direct contact. "Overlap", "face" and "adjacent" described in this specification are not limited to the case where two members directly face each other or contact each other, and include the case where a member different from the two members exists between the two members. So-called "on XX" means above XX, and includes the case where not contacting XX.

[0051] (First Embodiment)

[0052] Hereinafter, the configuration of the semiconductor storage device 1 of the first embodiment is described using the drawings. Figure 1 is a schematic perspective view showing the semiconductor storage device 1. In the following description, the X direction (second direction) is a direction parallel to the surface 11a of the silicon substrate 11, and is a direction in which the word line WL extends. The Y direction (first direction) is a direction parallel to the surface 11a of the silicon substrate 11, and is a direction intersecting the X direction, and is a direction in which the bit line BL extends. For example, the Y direction is substantially orthogonal to the X direction. The Z direction (third direction) is a direction of the thickness of the silicon substrate 11, and is a direction intersecting the X direction and the Y direction. For example, the Z direction is substantially orthogonal to the X direction and the Y direction. The direction downward in the Z direction means a direction along the Z direction toward the silicon substrate 11. The direction upward in the Z direction means a direction along the Z direction opposite to the direction toward the silicon substrate 11. Note that, in this specification, "upper" and "lower" are expressions for convenience of explanation, and do not specify the direction of gravity.

[0053] (Semiconductor Storage Device 1)

[0054] The semiconductor storage device 1 is, for example, a so-called cross-point type semiconductor storage device using a phase change memory (PCM). The semiconductor storage device 1 has, for example, a silicon substrate 11, an interlayer insulating layer 12, a plurality of word lines WL, a plurality of bit lines BL and a plurality of memory cells MC.

[0055] On the surface 11a of the silicon substrate 11, a drive circuit (not shown) for driving the semiconductor memory device 1 is formed. An interlayer insulating layer 12 is formed on the surface 11a of the silicon substrate 11 and covers the drive circuit. The interlayer insulating layer 12 is formed of, for example, silicon oxide (SiO2) or the like.

[0056] The plurality of bit lines BL are each formed in a strip shape along the Y direction and extend along the Y direction (first direction). The plurality of bit lines BL are arranged with an empty space in the X direction (second direction) and the Z direction (third direction). The plurality of bit lines BL are provided at different positions from the word lines WL in the Z direction crossing the X direction and the Y direction. The plurality of bit lines BL arranged along the X direction are at the same position in the Z direction and constitute one bit line layer 25. The bit line BL is formed of, for example, tungsten (W) or the like. The bit line BL is one example of "first wiring".

[0057] The plurality of word lines WL are each formed in a strip shape along the X direction and extend along the X direction. The plurality of word lines WL are arranged with an empty space in the Y direction and the Z direction. If described in detail, the plurality of word lines WL arranged in the Y direction are at the same position in the Z direction and constitute one word line layer 27. That is, the word line (second wiring) WL extends along the second direction crossing the first direction and is provided at a different position from the bit line (first wiring) BL in the third direction crossing the first direction and the second direction. The plurality of word line layers 27 are arranged with an empty space in the Z direction. The word line WL is formed of, for example, tungsten (W) or the like. The word line WL is one example of "second wiring". However, it is also possible that the bit line BL corresponds to one example of "second wiring" and the word line WL corresponds to one example of "first wiring". The word line WL adjacent to the word line as the second wiring in the Y direction is one example of "third wiring".

[0058] The bit line layer 25 is provided between two word line layers 27 adjacent in the Z direction and is spaced apart from the two word line layers 27 in the Z direction. The plurality of word line layers 27 and the plurality of bit line layers 25 are alternately arranged one layer by one layer in the Z direction.

[0059] The width in the Y direction of each word line WL and the width in the X direction of each bit line BL are equal to the minimum feature size F of the semiconductor memory device 1. An interlayer insulating film 38 (refer to FIG. 2) is interposed between the plurality of word lines WL adjacent in each word line layer 27 and between the plurality of bit lines BL adjacent in each bit line layer 25. Figure 3 ).

[0060] The word lines WL and the bit lines BL are arranged so as to cross each other when viewed in the Z direction. The word lines WL and the bit lines BL are, for example, orthogonal to each other when viewed in the Z direction. In the overlapping portion CP in which the word line WL and the bit line BL overlap when viewed in the Z direction, the memory cell MC is provided. The memory cell MC is interposed between the word line WL and the bit line BL of the overlapping portion CP in the Z direction. That is, a plurality of memory cells MC are arranged in a three-dimensional matrix shape so as to be spaced apart from each other in the X direction, the Y direction, and the Z direction by being provided in a plurality of overlapping portions CP.

[0061] Figure 2 is a perspective view of the memory cell MC. As shown in Figure 2 , the memory cell MC is constituted by a substantially corner pillar-shaped pillar 31 in which the Z direction is set as a length direction. One end surface 31a of the pillar 31 is in contact with the bit line BL in the entire overlapping portion CP. The other end surface 31b of the pillar 31 is in contact with the word line WL in the entire overlapping portion CP. Note that, between the memory cells MC adjacent in the X direction and the Y direction, an interlayer insulating film 38 (refer to Figure 3 ) is provided. In addition, a pad film 70 (refer to Figure 3 ) described later covers the periphery of the memory cell MC, a portion of the word line WL, and a portion of the bit line BL.

[0062] The memory cell MC is described using Figure 3 and Figure 4 . Figure 3 is a cross-sectional view along the A-A' line of the memory cell MC shown in Figure 2 . In addition, Figure 4 is a cross-sectional view along the B-B' line of the memory cell MC shown in Figure 2 . The memory cell MC has, for example, the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60. The memory cell MC is covered with the pad film 70, and further, the interlayer insulating film 38 is provided between the memory cells MC. Note that, one memory cell is set as a first memory cell MC, a memory cell adjacent in the Y direction via the interlayer insulating film 38 is set as a second memory cell MCy, and a memory cell adjacent in the X direction via the interlayer insulating film 38 is set as a third memory cell MCx.

[0063] The interlayer insulating film 38 is provided between the pad film 70 covering the first memory cell MC and the pad film 70 covering the second memory cell MCy in the Y direction. Also, the interlayer insulating film 38 is provided between the pad film 70 covering the first memory cell MC and the pad film 70 covering the third memory cell MCx in the X direction. The interlayer insulating film 38 can be thicker than the pad film 70 in the width in the Y direction and the X direction. Also, between the first memory cell MC and the second memory cell MCy, the sum of the width in the Y direction of the pad film 70 covering the first memory cell MC, the width in the Y direction of the interlayer insulating film 38, and the width in the Y direction of the pad film 70 covering the second memory cell MCy is equal to the width in the Y direction of the first memory cell MC. In the Z direction, the interlayer insulating film 38 is provided between the position of the surface of the pad film 70 in contact with the interlayer insulating layer 12 or the surface of the pad film in contact with the upper surface of the word line WL and the position of the upper surface of the bit line BL (the end surface of the bit line BL on the side opposite to the first conductive layer 20). Between the interlayer insulating film 38 and the interlayer insulating layer 12, the pad film 70 is present.

[0064] The first conductive layer 20 is provided between the word line WL and the bit line BL in the Z direction. The first conductive layer 20 is interposed between the storage layer 30 and the bit line BL in the Z direction. The first conductive layer 20 has a function as an electrode with respect to the storage layer 30. Also, the first conductive layer 20 has a function of suppressing alloying of the storage layer 30 and the bit line BL. The first conductive layer 20 can be, for example, carbon (C), or carbon nitride (CN), or the like, can be tungsten (W), or the like, can be polysilicon into which an N-type impurity such as phosphorus (P) is implanted, or the like, or can be another conductive layer such as tungsten carbide (WC), tungsten carbonitride (WCN), or tungsten carbonitride silicide (WCNSi). The thickness (for example, the maximum thickness) of the first conductive layer 20 in the Z direction is, for example, thinner than the thickness (for example, the maximum thickness) of the storage layer 30 in the Z direction.

[0065] The storage layer 30 stores information by a change in state of a material constituting the storage layer 30 or the like. The storage layer 30 is formed of, for example, a PCM. In the case where the storage layer 30 is formed of a PCM, it is formed of, for example, a chalcogenide alloy of germanium (Ge), antimony (Sb), and tellurium (Te) called GST. The composition ratio of Ge to Sb to Te is, for example, 2:2:5. The storage layer 30 becomes a crystalline state by heating at a temperature lower than a melting temperature and slow cooling, and becomes a low-resistance state. The storage layer 30 becomes an amorphous state by heating at a temperature higher than the melting temperature and rapid cooling, and becomes a high-resistance state. The thickness (for example, the maximum thickness) of the storage layer 30 in the Z direction is, for example, larger than the thickness (for example, the maximum thickness) of the selector layer 50, and is, for example, smaller than the thickness of the word line WL in the Z direction. Note that the storage layer 30 in the 1st memory cell MC is an example of a "1st storage layer". The storage layer 30 in the 2nd memory cell MCy is an example of a "3rd storage layer".

[0066] That is, if the voltage applied to the storage layer 30 reaches a prescribed value, the carriers in the inside of the storage layer 30 are multiplied, and the resistance of the storage layer 30 sharply decreases. If a voltage of the prescribed value or more is applied to the storage layer 30, a large current flows, Joule heat is generated, and the temperature of the storage layer 30 rises. If the temperature of the storage layer 30 is kept in the crystallization temperature region by controlling the applied voltage, the storage layer 30 changes to a polycrystalline state, and the resistance of the storage layer 30 decreases. If the storage layer 30 becomes the polycrystalline state, even if the applied voltage becomes zero, the polycrystalline state is maintained, and the resistance of the storage layer 30 is kept low. If a high voltage is applied to the storage layer 30 in the low-resistance state and a large current flows, the temperature of the storage layer 30 exceeds the melting point of the chalcogenide alloy or the like, and the chalcogenide alloy of the storage layer 30 melts. If the applied voltage sharply decreases, the storage layer 30 is sharply cooled, and the resistance of the storage layer 30 is kept high.

[0067] The storage layer 30 is a layer that maintains the above-described low-resistance state or high-resistance state. The storage layer 30 can take at least two different resistance values as bistable states at room temperature by being applied with a voltage or supplied with a current. By writing and reading these two stable resistance values, a memory operation of at least two values can be realized. In the case where the storage layer 30 performs a memory operation of two values, for example, the set state of the storage layer 30 is made to correspond to 1, and the reset state is made to correspond to 0.

[0068] The second conductive layer 40 is provided between the storage layer 30 and the selector layer 50. The second conductive layer 40 has a function of suppressing alloying of the storage layer 30 and the selector layer 50 and a function of electrically connecting the storage layer 30 and the selector layer 50. The second conductive layer 40 is, for example, carbon (C), carbon nitride (CN), or the like, and can be tungsten (W) or the like, and can be polycrystal silicon into which an impurity of N type such as phosphorus (P) is implanted, or another conductive layer such as tungsten carbide (WC), tungsten carbonitride (WCN), or silicon tungsten carbonitride (WCNSi). The thickness (e.g., the maximum thickness) of the second conductive layer 40 in the Z direction is, for example, thinner than the thickness (e.g., the maximum thickness) of the storage layer 30 in the Z direction.

[0069] The selector layer 50 is a film that functions as a selection element of the memory cell MC. The selector layer 50 is provided between the storage layer 30 and the word line (second wiring) WL. The selector layer 50 can also be, for example, a 2-terminal switching element. In a case where a voltage applied across the 2-terminal is below a threshold value, the switching element is in a "high resistance" state, for example, an electrically non-conductive state. In a case where the voltage applied across the 2-terminal is above the threshold value, the switching element changes to a "low resistance" state, for example, an electrically conductive state. The switching element can have this function regardless of the polarity of the voltage. The switching element contains at least one or more chalcogen elements selected from the group consisting of tellurium (Te), selenium (Se), and sulfur (S). The switching element can also contain a compound containing the above chalcogen element, i.e., a chalcogenide. The switching element can contain, in addition to the above elements, at least one or more elements selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), and antimony (Sb). The thickness (e.g., the maximum thickness) of the second conductive layer 40 in the Z direction is, for example, thinner than the thickness (e.g., the maximum thickness) of the storage layer 30 in the Z direction.

[0070] The third conductive layer 60 is provided between the selector layer 50 and the word line WL. The third conductive layer 60 has a function of electrically connecting the selector layer 50 and the word line WL. The third conductive layer 60 can be, for example, carbon (C), carbon nitride (CN), or the like, and can be tungsten (W) or the like, and can be polycrystal silicon into which an impurity of N type such as phosphorus (P) is implanted, or another conductive layer such as tungsten carbide (WC), tungsten carbonitride (WCN), or silicon tungsten carbonitride (WCNSi). The thickness (e.g., the maximum thickness) of the third conductive layer 60 in the Z direction is, for example, thinner than the thickness (e.g., the maximum thickness) of the storage layer 30 in the Z direction.

[0071] The liner film 70 (first insulating film) is an insulating film that covers the memory cell MC, a portion of the word line WL, and a portion of the bit line BL. The liner film 70 is, for example, a silicon oxide film, a silicon nitride film, or the like. Figure 3 and Figure 4The periphery (peripheral surface in the X direction and the Y direction) of the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60 is covered as shown in FIG. 1. That is, the liner film 70 covers the memory cell MC. In addition, the liner film 70 covers a part of the word line WL and a part of the bit line BL. Specifically, in the X direction, the liner film 70 covers the region of the upper surface and the side surface of the word line WL and the bit line BL in which the memory cell MC is not formed. In the Y direction, the liner film 70 covers the region of the upper surface and the side surface of the word line WL and the bit line BL in which the memory cell MC is not formed. Figure 3 and Figure 4 In the third direction, when the direction close to the bit line BL is set as up and the direction close to the interlayer insulating layer 12 is set as down, the liner film 70 covers the region in which the memory cell MC is not formed in the upper surface and the side surface of the word line WL and the bit line BL. As shown in FIG. 1, the liner film 70 covers the region in which the memory cell MC is not formed in the upper surface and the side surface of the word line WL and the bit line BL in the X direction and the Y direction. Figure 3 As shown in FIG. 1, the thickness (for example, the maximum thickness) of the liner film 70 in the Y direction is, for example, 3 nm to 5 nm.

[0072] The interlayer insulating layer 38 is provided between the liner film 70 covering the first memory cell MC and the liner film 70 covering the second memory cell MCy. The thickness of the liner film 70 in the Y direction in contact with the first memory cell MC is thinner than the thickness of the interlayer insulating film 38 in the Y direction. In addition, the thickness of the liner film 70 in the X direction in contact with the first memory cell MC is thinner than the thickness of the interlayer insulating film 38 in the X direction. The thickness of the liner film 70 is constant and extends in the Z direction along the first memory cell MC. A part of the liner film 70 is provided along the surface of the interlayer insulating layer 12 exposed between the first memory cell MC and the second memory cell MCy.

[0073] The liner film 70 is a SiON film composed of Si, O, and N. The liner film 70 has an N region 72 and an O region 73 and a boundary 74 (boundary at which the N content and the O content are equal) in the third direction. In the N region 72, the atomic ratio of N to O (N / O) is 1.0 or more. That is, the boundary 74 is included in the N region 72. In the O region 73, the atomic ratio of N to O (N / O) is less than 1.0. In the first embodiment, the boundary 74 is located between the end surface of the second conductive layer 40 on the bit line BL side and the end surface of the second conductive layer 40 on the word line WL side in the third direction.

[0074] Figure 5 The relationship between the position of the memory cell of the first embodiment and the result of energy dispersive X-ray analysis is shown in FIG. 6. Figure 5 The upper schematic diagram in FIG. 6 shows the positional relationship of the memory cell, Figure 5 The lower graph in FIG. 6 shows the result obtained by performing energy dispersive X-ray analysis in the direction indicated by the dotted line in the memory cell MC. In Figure 5 In the lower graph in FIG. 6, the vertical axis indicates the ratio of O and N when the unit is set to atomic %, and the horizontal axis indicates the depth.

[0075] In the first embodiment, such as Figure 5 As shown, when the position on the end face of the word line WL side (lower side) of the storage layer 30 is set to position 1 G1 in the Z direction (third direction), the atomic ratio (N / O) of the pad film 70 at position 1 G1 is 1.0 or more. The atomic ratio (N / O) of the pad film 70 at position 1 G1 can also be 1.5 or more. The atomic ratio (N / O) of the pad film 70 at position 1 can also be 7 / 3 or more. It should be noted that position 1 G1 in the first embodiment is the position of the interface between the storage layer 30 and the second conductive layer 40.

[0076] In the Z direction, when the position on the end face (upper end face) of the bit line (first wiring) BL side of the storage layer 30 is set to the third position G3, the atomic ratio (N / O) of the pad film 70 from the first position G1 to the third position G3 in the Z direction is, for example, 1.0 or more. It should be noted that the third position G3 in the first embodiment is the position of the interface between the first conductive layer 20 and the storage layer 30.

[0077] In the first embodiment, in the Z direction, when the position of the end face (lower end face) of the word line (second wiring) WL opposite to the selector layer 50 is set to the second position G2, the atomic ratio (N / O) of the pad film 70 at the second position G2 is less than 1.0. The atomic ratio (N / O) of the pad film 70 at the second position G2 may also be 0.5 or less. It should be noted that the second position G2 in the first embodiment is the position of the interface between the interlayer insulating layer 12 and the word line WL.

[0078] When the minimum thickness of the gasket film 70 in the first direction is set to the first distance, in the Z direction, the position from the second position G2 toward the bit line BL at a distance of the first distance is set to the fourth position G4. Within the range from the second position G2 to the fourth position G4 in the Z direction, the atomic ratio of N to O (N / O) of the gasket film 70 is, for example, less than 1.0. Within the range of the first distance (G2 to G4) from the second position G2 toward the bit line BL in the Z direction, the atomic ratio of N to O (N / O) of the gasket film 70 can also be less than 0.5.

[0079] In the Z direction, within the range from the second position G2 to the bit line BL side end face of the selector layer 50, for example, the atomic ratio of N to O (N / O) of the pad film 70 is less than 1.0.

[0080] The content (atomic %) of each atom of Si, N, and O in the cushion film 70 can be measured by energy dispersive X-ray spectroscopy (EDX) attached to a transmission electron microscope (TEM). From the content (atomic %) of each element, the above-mentioned atomic ratio can be calculated.

[0081] (Method for manufacturing semiconductor storage device)

[0082] A method for manufacturing the semiconductor storage device 1 will be described. Figure 6 One example of a manufacturing process of the memory cell MC is a cross-sectional view of a stack for forming the word line WL and the pillar 31. From the upper part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the X direction. From the lower part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the Y direction. Figures 6 to 15 One example of a manufacturing process of the memory cell MC is a cross-sectional view of a stack for forming the word line WL and the pillar 31. From the upper part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the X direction. From the lower part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the Y direction. Figures 6 to 15 One example of a manufacturing process of the memory cell MC is a cross-sectional view of a stack for forming the word line WL and the pillar 31. From the upper part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the X direction. From the lower part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the Y direction.

[0083] As shown in FIG. 6B, the interlayer insulating layer 12, the 2nd wiring film WL1, the 3rd conductive film 61, the selector layer forming film 51, the 2nd conductive film 41, the storage layer forming film 31, and the 1st conductive film 21 extending in the X direction and the Y direction are stacked in the Z direction. The 2nd wiring film WL1 is, for example, tungsten (W). The interlayer insulating layer 12 is formed of, for example, SiO2. Here, although not shown, the interlayer insulating layer 12 is formed on the silicon substrate 11. Figure 6

[0084] One example of a manufacturing process of the memory cell MC is a cross-sectional view of a stack for forming the word line WL and the pillar 31. From the upper part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the X direction. From the lower part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the Y direction. Figure 7 As shown in FIG. 6B, the interlayer insulating layer 12, the 2nd wiring film WL1, the 3rd conductive film 61, the selector layer forming film 51, the 2nd conductive film 41, the storage layer forming film 31, and the 1st conductive film 21 extending in the X direction and the Y direction are stacked in the Z direction. The 2nd wiring film WL1 is, for example, tungsten (W). The interlayer insulating layer 12 is formed of, for example, SiO2. Here, although not shown, the interlayer insulating layer 12 is formed on the silicon substrate 11. Figure 7

[0085] One example of a manufacturing process of the memory cell MC is a cross-sectional view of a stack for forming the word line WL and the pillar 31. From the upper part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the X direction. From the lower part of each drawing in FIG. 6A, the cross-sectional view of the constituent parts in each manufacturing process is observed in the Y direction. Figure 8 Figure 8 ​As shown, a silicon oxide film (SiO film) 75 is formed on the first conductive film 21, the storage layer forming film 31, the second conductive film 41, the selector layer forming film 51, the third conductive film 61, and the word line WL, which are exposed when viewed from the Z direction, with a specified thickness.

[0086] Figure 9 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the nitriding process. For example, this is achieved through plasma nitriding, such as... Figure 9 As shown, the N-region 72 is formed by nitriding a portion of the silicon oxide film (SiO film) 75. Specifically, in the SiO film 75, when a portion covering a side of the word line WL is designated as the first portion and a portion covering the side of the storage layer 30 is designated as the second portion, nitrogen is supplied to the second portion in such a way that it contains more nitrogen than the first portion. In the nitriding process, by adjusting the pressure, bias conditions, and processing time, the SiO film in contact with the first conductive layer 20 and the storage layer 30 can be selectively nitrided.

[0087] Figure 10 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the formation of the interlayer insulating film. This can be achieved, for example, through ALD or CVD methods. Figure 10 As shown, the interlayer insulating film 38 is stacked in such a way that the entire support 92 is embedded. The interlayer insulating film 38 is formed, for example, from SiO2. In this case, the size of the interlayer insulating film 38 in the Z direction is larger than the size of the support 92 in the Z direction.

[0088] Figure 11 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the process of partially removing the interlayer insulating film. For example, this is achieved through CMP (Chemical Mechanical Polishing). Figure 11 As shown, the interlayer insulating film 38 is removed while grinding towards the interlayer insulating layer 12 in the Z direction until the first conductive film 21 begins to be exposed. Through this partial removal process of the interlayer insulating film, multiple pillars 31 are formed by leaving gaps at the positions where they overlap with the word lines WL in the Y direction, with the interlayer insulating film 38 positioned between adjacent word lines WL and pillars 31 in the Y direction. The end faces of the interlayer insulating film 38 and the first conductive film 21 on the opposite side of the word lines WL in the Z direction are aligned on the same plane and are smooth to each other.

[0089] Figure 12An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the first wiring film formation process for forming the bit line (BL). This can be achieved, for example, by PVD (Physical Vapor Deposition) or CVD methods, such as... Figure 12 As shown, a first wiring film BL1 is stacked on the end faces of the interlayer insulating film 38 and the first conductive film 21, which are exposed when viewed from the Z direction. The first wiring film BL1 is, for example, tungsten (W).

[0090] Figure 13 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the bit line formation process. This is achieved, for example, through patterning, such as... Figure 13 As shown, a predetermined interval is left open in the X direction, and multiple grooves Gr2 are formed in the Z direction, penetrating the third conductive film 61, the selector layer forming film 51, the second conductive film 41, the storage layer forming film 31, the first conductive film 21, and the first wiring film BL1. This forms the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60. Through this bit line formation process, multiple bit lines BL are formed with a predetermined interval left open in the X direction.

[0091] Figure 14 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the second SiO film formation process. This can be achieved, for example, through plasma-enhanced Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). Figure 14 As shown, a SiO film 75 is formed on the bit line BL, the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, the third conductive layer 60, and the word line WL, which are exposed when viewed from the Z direction, with a specified thickness.

[0092] Figure 15 An example of the manufacturing process of a memory cell (MC) is a cross-sectional view showing the second nitriding process. For example, this is achieved through plasma nitriding, such as... Figure 15 As shown, an N region 72 is formed by nitriding a portion of the SiO film 75. Thus, a pad film 70 is obtained.

[0093] By performing the above-mentioned processes, it is possible to manufacture Figure 3 and Figure 4 The memory cell MC shown is formed by performing a known preprocessing step before the above-described steps and a known post-processing step after the above-described steps. However, the manufacturing method of the semiconductor memory device 1 is not limited to the method described above.

[0094] Next, the effects of the semiconductor storage device 1 of the first embodiment described above will be described. According to the semiconductor storage device 1, since the atomic ratio (N / O) of N to O of the pad film 70 at the first position G1 is 1.0 or more, the intrusion of H2O and O into the storage layer 30 can be suppressed. Therefore, the influence of H2O and O from the interlayer insulating film 38 on the storage layer can be suppressed. In addition, at the second position G2, since the atomic ratio (N / O) of N to O of the pad film 70 is less than 1.0, excellent voltage resistance can be obtained, and RC delay can be suppressed.

[0095] The first embodiment has been described above. In the first embodiment described above, the first conductive layer 20, the second conductive layer 40, and the third conductive layer 60 are provided, but the first conductive layer 20, the second conductive layer 40, and the third conductive layer 60 can not be provided. Note that, in the case where the first conductive layer 20 is not provided, the third position G3 becomes the interface between the bit line BL and the storage layer 30. In the case where the second conductive layer 40 is not provided, the first position G1 becomes the interface between the storage layer 30 and the selector layer 50.

[0096] In addition, in the first embodiment, a fourth conductive layer, which is not illustrated, can be provided between the first conductive layer 20 and the storage layer 30. The fourth conductive layer can be composed of tungsten, for example.

[0097] In the first embodiment, the atomic ratio (N / O) of N to O of the pad film 70 in contact with the first conductive layer 20 can be 1.0 or more, for example.

[0098] In the manufacturing method of the semiconductor storage device of the first embodiment, the SiO film forming step and the nitriding treatment step can be continuously performed by one apparatus.

[0099] (Second Embodiment)

[0100] Next, the second embodiment will be described. Although not illustrated, the semiconductor storage device of the second embodiment is also a so-called cross-point type semiconductor storage device using PCM, like the semiconductor storage device 1 of the first embodiment. The semiconductor storage device of the second embodiment includes a silicon substrate 11, an interlayer insulating layer 12, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC, for example. Hereinafter, for the constituent components of the semiconductor storage device of the second embodiment, only the contents different from the constituent components of the semiconductor storage device 1 will be described, and the detailed description of the contents common to the constituent components of the semiconductor storage device 1 will be omitted.

[0101] Figure 16 is a perspective view of the memory cell MC2 of the second embodiment, Figure 17 is a view taken alongFigure 16 A-A' line of the memory cell MC2 shown in FIG. 2. In addition, Figure 18 is along Figure 16 A cross-sectional view of a B-B' line shown in FIG. 2. Note that one memory cell is set to be the memory cell MC2, a memory cell adjacent to the memory cell MC2 in the Y direction through the interlayer insulating film 38 is set to be the memory cell MC2y, and a memory cell adjacent to the memory cell MC2 in the X direction through the interlayer insulating film 38 is set to be the memory cell MC2x.

[0102] The liner film 70a (first insulating film) is an insulating film covering the memory cell MC2, part of the word line WL, and part of the bit line BL. The liner film 70a covers the periphery of the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60 as shown in FIGS. 2 and 3. That is, the liner film 70a covers the periphery of the memory cell MC2. The liner film 70a covers part of the word line WL and part of the bit line BL. Specifically, in FIGS. 2 and 3, the liner film 70a covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in the region where the memory cell MC is not formed. Figure 17 and Figure 18 The liner film 70a covers the periphery of the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60 as shown in FIGS. 2 and 3. That is, the liner film 70a covers the periphery of the memory cell MC2. The liner film 70a covers part of the word line WL and part of the bit line BL. Specifically, in FIGS. 2 and 3, the liner film 70a covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in the region where the memory cell MC is not formed. Figure 17 and Figure 18 In FIGS. 2 and 3, when the direction close to the bit line BL is set to be up and the direction close to the interlayer insulating layer 12 is set to be down in the third direction, the liner film 70a covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in the region where the memory cell MC is not formed. As shown in FIG. 3, the thickness (e.g., the maximum thickness) of the liner film 70a in the Y direction is, for example, 3 nm to 5 nm. Figure 18

[0103] The interlayer insulating film 38 is provided between the liner film 70a covering the memory cell MC2 and the liner film 70a covering the memory cell MC2y. The thickness of the liner film 70a in the Y direction in contact with the memory cell MC2 is thinner than the thickness of the interlayer insulating film 38 in the Y direction. In addition, the thickness of the liner film 70a in the X direction in contact with the memory cell MC2 is thinner than the thickness of the interlayer insulating film 38 in the X direction. The thickness of the liner film 70a is constant along the memory cell MC2 and extends in the Z direction. Part of the liner film 70a is provided along the surface of the interlayer insulating layer 12 exposed between the memory cell MC2 and the memory cell MC2y.

[0104] The liner film 70a is a SiON film composed of Si, O, and N. The liner film 70a has an N region 72 and an O region 73 and a boundary 74 (boundary where the N content and the O content are equal) in the third direction. In the N region 72, the atomic ratio of N to O (N / O) is 1.0 or more. That is, the boundary 74 is included in the N region 72. In the O region 73, the atomic ratio of N to O (N / O) is less than 1.0.

[0105] ​In the second embodiment, in the Z direction (the third direction), when a position in the end surface of the side of the word line WL (the side of the second wiring) of the storage layer 30 is set as the first position Gl, the atomic ratio (N / O) of N and O of the liner film 70a at the first position Gl is 1.0 or more. The atomic ratio (N / O) of N and O of the liner film 70a at the first position Gl can also be 1.5 or more. The atomic ratio (N / O) of N and O of the liner film 70 at the first position can also be 7 / 3 or more. Note that the first position Gl becomes a position of the interface of the storage layer 30 and the second conductive layer 40 in the second embodiment.

[0106] In the Z direction, when a position in the end surface (the lower end surface) of the side of the word line (the second wiring) WL of the selector layer 50 is set as the fifth position G5, the atomic ratio (N / O) of N and O of the liner film 70a in the range from the third position G3 to the fifth position G5 in the Z direction is, for example, 1.0 or more. Note that the fifth position G5 becomes a position of the interface of the selector layer 50 and the third conductive layer 60 in the second embodiment.

[0107] In the Z direction, in the range from the position of the end surface of the side of the word line WL of the storage layer 30 to the second position G2, the atomic ratio (N / O) of N and O of the liner film 70 is less than 1.0. Here, the position of the end surface of the side of the word line WL of the storage layer 30 is a position of the interface of the third conductive layer 60 and the word line WL.

[0108] In the range of the Y direction from the surface of the word line WL by the second distance or more, the atomic ratio (N / O) of N and O of the liner film 70a is 1.0 or more. Here, the second distance is the minimum thickness of the liner film 70 in the Y direction.

[0109] In the second embodiment, in the Z direction, when a position of the end surface of the side opposite to the selector layer 50 of the word line (the second wiring) WL is set as the second position G2, in the range of the Y direction from the surface of the word line WL by the first distance or less, and the atomic ratio (N / O) of N and O of the liner film 70a at the second position G2 is less than 1.0. The atomic ratio (N / O) of N and O of the liner film 70a at the second position G2 can also be 0.5 or less. Note that the second position G2 becomes a position of the interface of the interlayer insulating layer 12 and the word line WL in the second embodiment.

[0110] The content (atomic %) of each atom of Si, N, and O in the liner film 70a can be measured by energy dispersive X-ray spectroscopy (EDX) attached to a transmission electron microscope (TEM) as described above. The atomic ratio described above can be calculated from the content (atomic %) of each element.

[0111] A manufacturing method of the memory cell MC2 of the semiconductor storage device of the second embodiment will be described. The memory cell MC2 of the semiconductor storage device of the second embodiment can be manufactured by the same processes as the manufacturing method of the semiconductor storage device 1 except for the nitriding process.

[0112] In the manufacturing method of the semiconductor storage device of the second embodiment, a part of the SiO film 75 is nitrided by, for example, plasma nitriding. In this nitriding process, by adjusting the pressure, the bias conditions, the processing time, the SiO film in contact with the first conductive layer 20, the storage layer 30, the second conductive layer 40, and the selector layer 50 can be selectively nitrided. In addition, by controlling the anisotropy of the nitriding process, as shown in FIG. 6, the range of the pad film 70a in contact with the interlayer insulating layer 12 can be nitrided. Figure 17

[0113] The effect of the semiconductor storage device of the second embodiment described above will be described. According to the semiconductor storage device of the second embodiment, since the atomic ratio (N / O) of N to O of the pad film 70 in the range of the third position G3 to the fifth position G5 is 1.0 or more, the intrusion of H2O and O into the storage layer 30 and the selector layer 50 can be suppressed. Therefore, the influence of H2O and O from the interlayer insulating film 38 on the storage layer can be further suppressed. In addition, since in the Z direction, in the range from the position of the end surface of the storage layer 30 on the side of the word line WL to the second position G2, the atomic ratio (N / O) of N to O of the pad film 70 is less than 1.0, excellent voltage resistance can be obtained, and RC delay can be suppressed.

[0114] (Third Embodiment)

[0115] Next, the third embodiment will be described. Although not shown, the semiconductor storage device of the third embodiment is a so-called cross-point type semiconductor storage device using PCM, like the semiconductor storage device 1 of the first embodiment. The semiconductor storage device of the third embodiment has, for example, a silicon substrate 11, an interlayer insulating layer 12, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Hereinafter, for the constituent parts of the semiconductor storage device of the third embodiment, only the contents different from the constituent parts of the semiconductor storage device 1 will be described, and the detailed description of the contents common to the constituent parts of the semiconductor storage device 1 will be omitted.

[0116] Figure 19 is a perspective view of the memory cell MC3 of the third embodiment, Figure 20 is a cross-sectional view of the memory cell MC3 along the A-A' line of Figure 19 Figure 21 is a cross-sectional view of the memory cell MC3 along the B-B' line of Figure 19 ​​A cross-sectional view of the B-B' line of the memory cell MC3. Note that a memory cell adjacent to the memory cell MC3 in the Y direction through the interlayer insulating film 38 is referred to as a memory cell MC3y, and a memory cell adjacent to the memory cell MC3 in the X direction through the interlayer insulating film 38 is referred to as a memory cell MC3x.

[0117] The liner film 70b (first insulating film) is an insulating film covering a part of the word line WL, a part of the bit line BL, and the memory cell MC3. The liner film 70b covers, as shown in FIG. 1A, the periphery of the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60. That is, the liner film 70b covers the periphery of the memory cell MC3. The liner film 70b covers a part of the word line WL and a part of the bit line BL. Specifically, in the first direction, the liner film 70b covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in a region where the memory cell MC is not formed. Figure 20 Figure 21 The liner film 70b covers, as shown in FIG. 1A, the periphery of the first conductive layer 20, the storage layer 30, the second conductive layer 40, the selector layer 50, and the third conductive layer 60. That is, the liner film 70b covers the periphery of the memory cell MC3. The liner film 70b covers a part of the word line WL and a part of the bit line BL. Specifically, in the first direction, the liner film 70b covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in a region where the memory cell MC is not formed. Figure 20 Figure 21 In the first direction, when the direction close to the bit line BL is set as up and the direction close to the interlayer insulating layer 12 is set as down, the liner film 70b covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in a region where the memory cell MC is not formed. As shown in FIG. 1A, the liner film 70b covers, for example, the upper surface and the side surface of the word line WL and the bit line BL in a region where the memory cell MC is not formed. Figure 20 As shown in FIG. 1A, the thickness (e.g., the maximum thickness) of the liner film 70b in the Y direction is, for example, 3 nm to 5 nm.

[0118] The liner film 70b is composed of Si, O, and N. The liner film 70b has, in the first direction, an N region 72 and an O region 73 and a boundary 74 (boundary where the N content and the O content are equal). In the N region 72, the atomic ratio of N to O (N / O) is 1.0 or higher. That is, the boundary 74 is included in the N region 72. In the O region 73, the atomic ratio of N to O (N / O) is lower than 1.0.

[0119] The interlayer insulating layer 38 is provided between the liner film 70b covering the memory cell MC3 and the liner film 70b covering the memory cell MC3y. The thickness of the liner film 70b in the Y direction in contact with the memory cell MC3 is thinner than the thickness of the interlayer insulating film 38 in the Y direction. In addition, the thickness of the liner film 70b in the X direction in contact with the memory cell MC3 is thinner than the thickness of the interlayer insulating film 38 in the X direction. The thickness of the liner film 70b is constant and extends in the Z direction along the memory cell MC3. A part of the liner film 70b is provided along the surface of the interlayer insulating layer 12 exposed between the memory cell MC3 and the memory cell MC3y.

[0120] ​​In the third embodiment, in the Z direction (third direction), when a position in an end surface of the word line WL side (second wiring line side) of the storage layer 30 is set as a first position Gl, an atomic ratio (N / O) of N and O of the liner film 70b at the first position Gl is 1.0 or more. The atomic ratio (N / O) of N and O of the liner film 70b at the first position Gl can also be 1.5 or more. The atomic ratio (N / O) of N and O of the liner film 70b at the first position can also be 7 / 3 or more. Note that the first position Gl becomes a position of an interface of the storage layer 30 and the second conductive layer 40 in the third embodiment.

[0121] In the third embodiment, the atomic ratio (N / O) of N and O of the liner film 70b at the second position G2 is less than 1.0. The atomic ratio (N / O) of N and O of the liner film 70b at the second position G2 can also be 0.5 or less. Note that the second position G2 becomes a position of an interface of the interlayer insulating layer 12 and the word line WL in the third embodiment.

[0122] In a range from the second position G2 to the fourth position G4 in the Z direction, the atomic ratio (N / O) of N and O of the liner film 70b is, for example, less than 1.0.

[0123] In a range from the third position G3 to the fourth position G4 in the Z direction except for the fourth position G4, the atomic ratio (N / O) of N and O of the liner film 70b is, for example, 1.0 or more.

[0124] The content (atomic %) of each atom of Si, N, and O in the liner film 70b can be measured by energy dispersive X-ray spectroscopy (EDX) attached to a transmission electron microscope (TEM) as described above. The atomic ratio described above can be calculated from the content (atomic %) of each element.

[0125] A manufacturing method of the memory cell MC3 of the semiconductor storage device of the third embodiment will be described. The memory cell MC3 of the semiconductor storage device of the third embodiment can be manufactured by the same processes as the manufacturing method of the semiconductor storage device 1 except for a nitriding process.

[0126] In the manufacturing method of the semiconductor storage device of the third embodiment, the nitriding process selectively nitrides a part of the SiO film 75 by, for example, plasma nitriding. In the nitriding process, by adjusting the pressure, bias conditions, and processing time, the SiO film in contact with a part of the first conductive layer 20, the storage layer 30, the second conductive layer 40, and the selector layer 50 and the word line WL can be selectively nitrided.

[0127] The effect of the semiconductor storage device of the above-described third embodiment will be described. According to the semiconductor storage device of the third embodiment, since the atomic ratio (N / O) of N and O of the liner film 70 in contact with the first conductive layer 20, the second conductive layer 40, the selector layer 50, the third conductive layer 60, and a part of the word line WL is 1.0 or more, the intrusion of H2O and O into the storage layer 30, the selector layer 50, and the word line WL can be suppressed. Therefore, the influence of H2O and O from the interlayer insulating film 38 can be further suppressed. Further, since the atomic ratio (N / O) of N and O of the liner film 70 is less than 1.0 in the range from the second position G2 to the fourth position G4 in the Z direction, excellent voltage resistance can be obtained, and RC delay can be suppressed.

[0128] (4th Embodiment)

[0129] The fourth embodiment will be described next. Although not illustrated, the semiconductor storage device of the fourth embodiment is also a so-called cross-point type semiconductor storage device using PCM, like the semiconductor storage device 1 of the first embodiment. The semiconductor storage device of the fourth embodiment has, for example, a silicon substrate 11, an interlayer insulating layer 12, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Hereinafter, for the constituent members of the semiconductor storage device of the fourth embodiment, only the content different from the constituent members of the semiconductor storage device 1 will be described, and the detailed description of the content common to the constituent members of the semiconductor storage device 1 will be omitted.

[0130] Figure 22 is a view showing a plurality of memory cells MC arranged in the Y direction in the semiconductor storage device of the fourth embodiment. As shown in the view, the memory cells MC are arranged in the Y direction in the semiconductor storage device of the fourth embodiment. The memory cells MC are arranged in the Y direction in the semiconductor storage device of the fourth embodiment. The memory cells MC are arranged in the Y direction in the semiconductor storage device of the fourth embodiment. Figure 22A memory cell shown in FIG. 1 is set as a memory cell MCA. A memory cell which is adjacent to the memory cell MCA with the interlayer insulating film 38 interposed therebetween is set as a memory cell MCB. Of the memory cells which are adjacent to the memory cell MCB with the interlayer insulating film 38 interposed therebetween in the Y direction, a memory cell which is located on the opposite side of the memory cell MCA in the Y direction is set as a memory cell MCC. Of the memory cells which are adjacent to the memory cell MCC with the interlayer insulating film 38 interposed therebetween in the Y direction, a memory cell which is located on the opposite side of the memory cell MCB in the Y direction is set as a memory cell MCD. Hereinafter, for the constituent parts of the memory cell MCA, A is added to the end of the symbol of the constituent part thereof. For the constituent parts of the memory cell MCB, B is added to the end of the symbol of the constituent part thereof. For the constituent parts of the memory cell MCC, C is added to the end of the symbol of the constituent part thereof. For the constituent parts of the memory cell MCD, D is added to the end of the symbol of the constituent part thereof. The word line WLB is an example of the "4th word line". The word line WLC is an example of the "5th word line". The storage layer 30B is an example of the "2nd storage layer". The pad film 70 which is in contact with one side surface of the memory cell MCA is set as a pad film 70c. The pad film which is between the memory cell MCA and the memory cell MCB is set as a pad film 70d. The pad film which is between the memory cell MCB and the memory cell MCC is set as a pad film 70e. The pad film which is between the memory cell MCC and the memory cell MCD is set as a pad film 70f. The pad film which is in contact with the memory cell MCD and is located on the opposite side of the pad film 70f in the Y direction is set as a pad film 70g. The pad film 70e is an example of the "2nd insulating film".

[0131] The semiconductor storage device of the 4th embodiment has a wiring pattern A in which the wiring interval distance of the word line WL is narrow and a wiring pattern B in which the wiring interval distance of the word line WL is wide. In the wiring pattern A, for example, the wiring interval distance dl of the word line WL is 30 nm or less. In the wiring pattern B, for example, the wiring interval distance d2 of the word line WL exceeds 30 nm.

[0132] In the wiring pattern B, the atomic ratio (N / O) of N to O of the pad film 70e at the 1st position Gl is 1.0 or more.

[0133] In the wiring pattern B, the atomic ratio (N / O) of N to O of the pad film 70e at the 2nd position G2 is 1.0 or more.

[0134] In the wiring pattern B, the atomic ratio (N / O) of N to O of the pad film 70e which exists between the word lines WL in the Y direction (1st direction) is 1.0 or more. Here, the "between the word lines WL in the Y direction" means the word lines which are adjacent to each other in the Y direction via the interlayer insulating film 38.Figure 22 In the case of the semiconductor storage device of the fourth embodiment, in the opposite faces of the WLB and the WLC, when the position in the Y direction of one face (here, the WLBa) is set to Dl and the position in the Y direction of the other face (here, the WLCa) is set to D2, the range of Dl to D2 in the Y direction.

[0135] In the wiring pattern A, the distribution of the atomic ratio of Si, N, and O of the pad film 70d is, for example, the same distribution as the pad film 70 of the first embodiment.

[0136] The manufacturing method of the semiconductor storage device of the fourth embodiment will be described. The memory cell MC3 of the semiconductor storage device of the fourth embodiment can be manufactured by the same processes as the manufacturing method of the semiconductor storage device 1 except for the groove forming process and the nitriding treatment process.

[0137] When the plurality of grooves Gr are formed in the groove forming process, by forming a groove with a narrow width and a groove with a wide width, the two kinds of wiring patterns like the semiconductor storage device of the fourth embodiment can be formed.

[0138] In the manufacturing method of the semiconductor storage device of the fourth embodiment, in the nitriding treatment process, a part of the SiO film 75 is nitrided, for example, by plasma nitriding treatment. In this nitriding treatment process, by adjusting the pressure, the bias conditions, and the treatment time, in the wiring pattern B with a wide width, the nitriding of the pad film existing in the Y direction between the word lines WL can be performed.

[0139] The effect of the semiconductor storage device of the fourth embodiment described above will be described. According to the semiconductor storage device of the fourth embodiment, in the region of the wiring pattern A in which the wiring-to-wiring distance is narrow and the withstand voltage is required, the protection of the memory layer 30 and the withstand voltage can be considered. In the region of the wiring pattern B in which the wiring-to-wiring distance is wide and the withstand voltage is not required, since the pad film 70e is nitrided entirely, the oxidation of the wiring can be suppressed, and the stability is further improved.

[0140] The semiconductor storage device of the fourth embodiment has been described above. In the fourth embodiment described above, the case in which the wiring-to-wiring distance is different between the second wiring and the first wiring has been described, but the same configuration can be set even in the case in which the wiring-to-wiring distance is different between the first wiring and the second wiring. In this case, the second wiring (word line) WL and the first wiring (bit line) BL are replaced, and the first direction (Y direction) is replaced into the second direction (X direction) in the description of the fourth embodiment described above.

[0141] In the semiconductor storage device of the fourth embodiment, as an example of the distribution of the composition of the pad film 70d in the wiring pattern A, the composition distribution of the first embodiment is cited, but the composition distribution of the second embodiment or the third embodiment can be set.

[0142] According to at least one embodiment described above, a first wiring, a second wiring, a first storage layer, and a first insulating film are provided. The first wiring extends in a first direction. The second wiring extends in a second direction intersecting the first direction, and is provided at a position different from the first wiring in a third direction intersecting the first direction and the second direction. The first storage layer is provided between the first wiring and the second wiring in the third direction. The first insulating film is provided along a part of a surface of the second wiring and a surface of the first storage layer. The first insulating film is formed of Si, N, and O. In the third direction, a position of an end surface of the first storage layer on the second wiring side is set as a first position. A position of an end surface of the second wiring on the opposite side from the first storage layer is set as a second position. An atomic ratio (N / O) of N to O of the first insulating film at the first position is 1.0 or more. An atomic ratio (N / O) of N to O of the first insulating film at the second position is less than 1.0. According to this configuration, improvement of electrical characteristics can be sought.

[0143] The embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope and gist of the application, and are also included in the scope of the application and equivalents thereof recited in the claims.

[0144] For example, the semiconductor storage device of the present application can be used for a semiconductor storage device having a structure in which a cell other than PCM, such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and the like, is stacked.

Claims

1. A semiconductor memory device comprising: The first wiring extends along the first direction; The second wiring extends along a second direction that intersects the first direction, and is positioned at a different location from the first wiring in a third direction that intersects both the first and second directions; A first storage layer, disposed in the third direction between the first wiring and the second wiring; and A first insulating film is disposed along a portion of the surface of the second wiring and the surface of the first storage layer, wherein... The first insulating film is formed of Si, N and O. In the third direction, the position of the end face of the second wiring side of the first storage layer is set as the first position. When the position of the end face opposite to the first storage layer of the second wiring is set to the second position, The atomic ratio of N to O in the first insulating film at the first position is 1.0 or higher. The atomic ratio of N to O in the first insulating film at the second position is less than 1.

0.

2. The semiconductor memory device according to claim 1, wherein, In the third direction, when the position in the end face of the first wiring side of the storage layer is set to the third position, Within the range from the first position to the third position in the third direction, The atomic ratio of N to O in the first insulating film is 1.0 or higher.

3. The semiconductor memory device according to claim 2, wherein, The atomic ratio of N to O in the first insulating film at the first position is 7 / 3 or more.

4. The semiconductor memory device according to claim 3, wherein, The minimum thickness of the first insulating film in the first direction is set as the first distance. In the third direction, when the position is set as the fourth position, which is a distance from the first distance from the second position toward the first wiring, Within the range from the second position to the fourth position in the third direction, The atomic ratio of N to O in the first insulating film is less than 1.

0.

5. The semiconductor memory device according to any one of claims 1 to 4, further comprising a selector layer disposed in the third direction between the first wiring and the memory layer, or disposed in the third direction between the memory layer and the second wiring. In the third direction, when the position in the end face of the second wiring side of the selector layer is set to the fifth position, The atomic ratio of N to O in the first insulating film at the fifth position is 1.0 or higher.

6. The semiconductor memory device according to any one of claims 1 to 4, further comprising: A third wiring, wherein the third wiring is disposed at a different position from the second wiring in the first direction, and extends along the second direction; and A third storage layer is disposed in the third direction between the first wiring and the third wiring. The first insulating film is located between the second wiring and the third wiring in the second direction.

7. The semiconductor memory device according to any one of claims 1 to 4, wherein in the third direction, within the range from the position of the end face on the side of the first memory layer of the second wiring to the second position, The atomic ratio of N to O in the first insulating film is less than 1.

0. The minimum thickness of the first insulating film in the first direction is set as the second distance. In the first direction, within a range greater than or equal to the second distance from the surface of the second wiring, The atomic ratio of N to O in the first insulating film is 1.0 or higher.

8. The semiconductor memory device according to any one of claims 1 to 4, comprising: The fourth wiring is disposed at a different position from the second and third wirings in the first direction and extends along the second direction; A second storage layer is disposed between the first wiring and the fourth wiring; The fifth wiring is disposed at a different position from the second, third and fourth wirings in the first direction and extends along the second direction; and A second insulating film is located between the fourth wiring and the fifth wiring in the second direction, and is disposed along the surface of the fourth wiring and the surface of the second storage layer, wherein... The atomic ratio of N to O in the second insulating film at the first position is 1.0 or higher. The atomic ratio of N to O in the second insulating film at the second position is 1.0 or higher.

9. A method for manufacturing a semiconductor memory device, wherein, An interlayer insulating layer is formed on a silicon substrate. Wiring is formed on the interlayer insulating layer. A storage layer is formed on the wiring. A silicon oxide film is formed, the silicon oxide film comprising a first portion covering a portion of the side of the wiring and a second portion covering a side of the storage layer. Nitrogen is supplied to the second portion of the silicon oxide film in such a manner that the second portion of the silicon oxide film contains more nitrogen than the first portion of the silicon oxide film.

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