Semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device in which damage due to current concentration is suppressed. The semiconductor device of the embodiments includes a semiconductor layer having a first surface and a second surface facing the first surface; a transistor region including a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer; and a neighboring region including the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second surface side of the semiconductor layer and having an absolute value of a threshold voltage smaller than an absolute value of a threshold voltage of the second transistor.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application 2021-44115 (filed on March 17, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] As an example of a semiconductor device for power applications, there is an Insulated Gate Bipolar Transistor (IGBT). An IGBT, for example, has a p-type contact region, an n-type drift region, and a p-type base region on its contact electrode. Furthermore, a gate electrode is disposed within a trench extending from the p-type base region to the n-type drift region, with a gate insulating film sandwiched in between. Furthermore, an n-type emitter region, connected to the emitter electrode, is provided in a region of the trench adjacent to the surface of the p-type base region.

[0005] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode allows current to flow in the opposite direction to the on-state current of the IGBT. Integrating the IGBT and freewheeling diode on the same semiconductor chip offers several advantages, such as reduced chip size due to the commonality of the termination area and the dispersion of heat dissipation points.

[0006] In an RC-IGBT, a boundary region without both the IGBT and diode is provided between the IGBT region containing the IGBT and the diode region containing the diode. By providing this boundary region, interference between the IGBT and diode operations and degradation of the RC-IGBT's characteristics are suppressed. However, for example, due to holes injected from the back side of the boundary region, current concentrates at the end of the IGBT region, posing a risk of IGBT damage. Summary of the Invention

[0007] Embodiments of the present invention provide a semiconductor device that suppresses damage caused by current concentration.

[0008] The semiconductor device of the embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a transistor region including a first transistor having a first gate electrode disposed on the first surface side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second surface side of the semiconductor layer; and an adjacent region including the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and disposed on the second surface side of the semiconductor layer and having an absolute value of a threshold voltage smaller than the absolute value of the threshold voltage of the second transistor. Attached Figure Description

[0009] Figure 1 (a) and (b) are schematic top views of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is an explanatory diagram of the driving method of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0014] Figure 6 (a) and (b) are schematic top views of the semiconductor device according to the fourth embodiment.

[0015] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0016] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Detailed Implementation

[0017] The following is a reference to the appendix. Figure 1 The embodiments of the present invention will be described below. Furthermore, in the following description, the same or similar components will be marked with the same symbols, and descriptions of components previously described will be omitted as appropriate.

[0018] In this specification, there are n + Type, n-type, n - When describing a type, it refers to using n + Type, n-type, n - The order of impurities is as follows: n-type impurities decrease in concentration. Additionally, there is p... + Type, p type, p- When describing a type, it refers to p + Type, p type, p - The order of impurities is p-type, with the concentration of p-type impurities decreasing.

[0019] In this specification, the distribution and absolute value of impurity concentration in the semiconductor region can be determined, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitude of impurity concentration in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentration can be determined, for example, using spreading resistance analysis (SRA). In SCM and SRA, the relative magnitude or absolute value of carrier concentration in the semiconductor regions can be obtained. By assuming the activation rate of the impurities, the relative magnitude of impurity concentration between the two semiconductor regions, the distribution of impurity concentration, and the absolute value of impurity concentration can be determined from the results of SCM and SRA measurements.

[0020] (First Implementation)

[0021] The semiconductor device according to the first embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a transistor region including a first transistor having a first gate electrode disposed on the first surface side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second surface side of the semiconductor layer; and an adjacent region including the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and disposed on the second surface side of the semiconductor layer and having an absolute value of a threshold voltage smaller than the absolute value of the threshold voltage of the second transistor.

[0022] The semiconductor device in the first embodiment is an RC-IGBT100 in which an IGBT and a return diode are formed on the same semiconductor chip. Furthermore, the RC-IGBT100 is an IGBT with a double-gate structure having gate electrodes on both the surface and back sides of the semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be used as an example for explanation.

[0023] Figure 1 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 1 (a) is a top view of the RC-IGBT100 viewed from the surface side of the semiconductor layer. Figure 1 (b) is a top view of the RC-IGBT100 viewed from the back side of the semiconductor layer. Figure 1A diagram showing the layout of the RC-IGBT100.

[0024] The RC-IGBT 100 includes an IGBT region 100a, a diode region 100b, and a boundary region 100c. Additionally, the RC-IGBT 100 includes a first electrode pad 101 and a second electrode pad 102. The IGBT region 100a is an example of a transistor region. The boundary region 100c is an example of an adjacent region.

[0025] A boundary region 100c is provided between the IGBT region 100a and the diode region 100b. The boundary region 100c is adjacent to the IGBT region 100a. The boundary region 100c suppresses interference between the operation of the IGBT in the IGBT region 100a and the operation of the diode in the component region, thus preventing the degradation of the RC-IGBT 100 characteristics.

[0026] The first electrode pad 101 is disposed, for example, on the surface side of the semiconductor layer. The second electrode pad 102 is disposed, for example, on the back side of the semiconductor layer.

[0027] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 for Figure 1 (a) AA' section.

[0028] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a virtual gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a virtual gate electrode 34, a surface interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0029] IGBT region 100a operates as an IGBT. Diode region 100b operates as a return current diode. The return current diode is, for example, a Fast Recovery Diode (FRD).

[0030] IGBT region 100a includes a first transistor having a first gate electrode 31 and a second transistor having a second gate electrode 32. Boundary region 100c includes a third transistor having a third gate electrode 33.

[0031] The first transistor is controlled by a voltage applied to the first gate electrode 31. The second transistor is controlled by a voltage applied to the second gate electrode 32. The third transistor is controlled by a voltage applied to the third gate electrode 33.

[0032] The first transistor is disposed on the first surface P1 side of the semiconductor layer 10. The first transistor has a trench gate structure with the gate electrode disposed in a trench. The first transistor is an IGBT.

[0033] The second transistor is disposed on the second surface P2 side of semiconductor layer 10. The second transistor has a planar gate structure. The second transistor is a so-called back-side transistor. The second transistor is an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with electrons as charge carriers.

[0034] The third transistor is disposed on the second surface P2 side of semiconductor layer 10. The third transistor has a planar gate structure. The third transistor is a so-called back-side transistor. The third transistor is an n-type MOSFET with electrons as charge carriers.

[0035] The first, second, and third transistors are not structurally distinct from the others. For example, Figure 2 The area enclosed by the dashed line X corresponds to one cell of the first transistor. Additionally, for example... Figure 2 The region enclosed by the dashed line Y corresponds to one cell of the second transistor. Additionally, for example, Figure 2 The area enclosed by the dashed line Z in the diagram corresponds to one cell of the third transistor.

[0036] The semiconductor layer 10 includes a main gate trench 51 (first trench), a virtual gate trench 52, an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first contact region 64 (fourth semiconductor region), a p-type second contact region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78.

[0037] The upper electrode 12 is an example of a first electrode. The lower electrode 14 is an example of a second electrode. The main gate trench 51 is an example of a first trench. The first drain region 60 is an example of a sixth semiconductor region. The second drain region 62 is an example of a seventh semiconductor region. The first contact region 64 is an example of a fourth semiconductor region. The second contact region 66 is an example of a fifth semiconductor region. The drift region 70 is an example of a first semiconductor region. The base region 72 is an example of a second semiconductor region. The emitter region 74 is an example of a third semiconductor region.

[0038] The semiconductor layer 10 has a first surface P1 and a second surface P2 facing the first surface P1. The first surface P1 is the surface of the semiconductor layer 10, and the second surface P2 is the back surface of the semiconductor layer 10. The semiconductor layer 10 is, for example, single-crystal silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm to 700 μm.

[0039] In this specification, the direction parallel to the first surface P1 is referred to as the first direction. Furthermore, the direction parallel to the first surface P1 and orthogonal to the first direction is referred to as the second direction. Additionally, in this specification, "depth" is defined as the distance from the first surface P1 towards the second surface P2.

[0040] The upper electrode 12 is disposed on the first surface P1 side of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface P1 of the semiconductor layer 10.

[0041] The upper electrode 12 functions as the emitter electrode of the first transistor in the IGBT region 100a. The upper electrode 12 also functions as the anode electrode of the diode in the diode region 100b. The upper electrode 12 is, for example, made of metal.

[0042] The upper electrode 12 is electrically connected to the emitter region 74 in the IGBT region 100a. The upper electrode 12 is in contact with the emitter region 74 in the IGBT region 100a.

[0043] The upper electrode 12 is electrically connected to the anode region 78 in the diode region 100b. The upper electrode 12 is in contact with the anode region 78 in the diode region 100b.

[0044] An emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage is, for example, 0V.

[0045] The lower electrode 14 is disposed on the second surface P2 side of the semiconductor layer 10. At least a portion of the lower electrode 14 is in contact with the second surface P2 of the semiconductor layer 10.

[0046] The lower electrode 14 functions as a contact electrode of the first transistor in the IGBT region 100a. The lower electrode 14 also functions as the cathode electrode of the diode in the diode region 100b. The lower electrode 14 is, for example, made of metal.

[0047] The lower electrode 14 is electrically connected to the first contact region 64 in the IGBT region 100a. The lower electrode 14 contacts the first contact region 64 in the IGBT region 100a.

[0048] The lower electrode 14 is electrically connected to the cathode region 76 in the diode region 100b. The lower electrode 14 is in contact with the cathode region 76 in the diode region 100b.

[0049] The lower electrode 14 is electrically connected to the second contact region 66 in the boundary region 100c. The lower electrode 14 is in contact with the second contact region 66 in the boundary region 100c.

[0050] A collector voltage (Vc) is applied to the lower electrode 14. The collector voltage is, for example, 200V to 6500V.

[0051] The drift region 70 is an n-type semiconductor region. The drift region 70 is located in the IGBT region 100a, the diode region 100b, and the boundary region 100c.

[0052] The drift region 70 serves as a path for the on-state current when the first transistor is in the on state. The drift region 70 is depleted when the IGBT is in the off state, thus maintaining the IGBT's withstand voltage.

[0053] The drift region 70 becomes the path for the on-state current when the diode is in the ON state. The drift region 70 is depleted when the diode is in the OFF state, thus maintaining the diode's withstand voltage.

[0054] The base region 72 is a p-type semiconductor region. The base region 72 is disposed between the IGBT region 100a and the boundary region 100c. The base region 72 is located between the drift region 70 and the first surface P1. Furthermore, the p-type impurity concentration of the base region 72 in the boundary region 100c can be the same as or different from the p-type impurity concentration of the base region 72 in the IGBT region 100a. Additionally, the p-type impurity concentration of the base region 72 in the boundary region 100c can be the same as or different from the p-type impurity concentration of the anode region 78 in the diode region 100b.

[0055] In the base region 72, in the region facing the first gate electrode 31, an n-type inversion layer is formed when the first transistor is in the ON state. The base region 72 functions as the channel region of the first transistor. The base region 72 is electrically connected to the upper electrode 12. The base region 72 is connected to the upper electrode 12 by a portion not shown.

[0056] The emitter region 74 is an n-type semiconductor region. The emitter region 74 is located in the IGBT region 100a. The emitter region 74 is not located in the diode region 100b or the boundary region 100c.

[0057] The emitter region 74 is located in the IGBT region 100a, between the base region 72 and the first surface P1. The n-type impurity concentration in the emitter region 74 is higher than that in the drift region 70.

[0058] The emitter region 74 is electrically connected to the upper electrode 12. The emitter region 74 is in contact with the upper electrode 12. The emitter region 74 becomes a source of electrons when the first transistor is in the ON state.

[0059] The first contact region 64 is a p-type semiconductor region. The first contact region 64 is located in the IGBT region 100a. The first contact region 64 is located between the drift region 70 and the second surface P2. The first contact region 64 is in contact with the second surface P2.

[0060] The first contact region 64 is electrically connected to the lower electrode 14. The first contact region 64 contacts the lower electrode 14. The first contact region 64 becomes a source of holes when the first transistor is in the ON state.

[0061] A portion of the first contact region 64 faces the second gate electrode 32. A channel for the second transistor, controlled by the second gate electrode 32, is formed in the first contact region 64 facing the second gate electrode 32.

[0062] The second contact region 66 is a p-type semiconductor region. The second contact region 66 is located in the boundary region 100c. The second contact region 66 is located between the drift region 70 and the second surface P2. The second contact region 66 is in contact with the second surface P2.

[0063] The second contact region 66 is electrically connected to the lower electrode 14. The second contact region 66 contacts the lower electrode. When the first transistor is in the ON state, the second contact region 66 becomes a source of holes.

[0064] A portion of the second contact region 66 faces the third gate electrode 33. A channel for the third transistor, controlled by the third gate electrode 33, is formed in the second contact region 66 facing the third gate electrode 33.

[0065] The p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32. Furthermore, the contact region spanning the IGBT region 100a and the boundary region 100c can be either the first contact region 64 or the second contact region 66.

[0066] The first drain region 60 is an n-type semiconductor region. The first drain region 60 is disposed in the IGBT region 100a. The first drain region 60 is disposed between the first contact region 64 and the second surface P2. The first drain region 60 is in contact with the second surface P2.

[0067] A portion of the first drain region 60 faces the second gate electrode 32. A portion of the first drain region 60 is in contact with the lower electrode 14.

[0068] The first drain region 60 functions as the drain of the second transistor. The n-type impurity concentration in the first drain region 60 is higher than that in the drift region 70.

[0069] The second drain region 62 is an n-type semiconductor region. The second drain region 62 is disposed in the boundary region 100c. The second drain region 62 is disposed between the second contact region 66 and the second surface P2. The second drain region 62 is in contact with the second surface P2.

[0070] A portion of the second drain region 62 faces the second gate electrode 32. A portion of the second drain region 62 is in contact with the lower electrode 14.

[0071] The second drain region 62 functions as the drain of the third transistor. The n-type impurity concentration in the second drain region 62 is higher than that in the drift region 70.

[0072] The buffer region 68 is an n-type semiconductor region. The buffer region 68 is located in the IGBT region 100a, the boundary region 100c, and the diode region 100b.

[0073] A buffer region 68 is disposed between the drift region 70 and the first contact region 64. A buffer region 68 is disposed between the drift region 70 and the first contact region 64. A buffer region 68 is disposed between the drift region 70 and the cathode region 76.

[0074] A portion of the buffer region 68 contacts the second surface P2. A portion of the buffer region 68 faces the second gate electrode 32. A portion of the buffer region 68 faces the third gate electrode 33.

[0075] The concentration of n-type impurities in buffer region 68 is higher than that in drift region 70.

[0076] The buffer region 68 has a lower resistance compared to the drift region 70. By providing the buffer region 68, when the second and third transistors are turned on, electrons are facilitated to be discharged from the drift region 70 to the lower electrode 14 of the second and third transistors.

[0077] In addition, the buffer region 68 also has the function of suppressing the extension of the depletion layer when the RC-IGBT100 is in the off state. Alternatively, the configuration may not include the buffer region 68.

[0078] Cathode region 76 is an n-type semiconductor region. Cathode region 76 is disposed in diode region 100b. Cathode region 76 is disposed between buffer region 68 and second surface P2.

[0079] The concentration of n-type impurities in cathode region 76 is higher than that in buffer region 68.

[0080] The cathode region 76 is electrically connected to the lower electrode 14. The cathode region 76 is in contact with the lower electrode 14.

[0081] The anode region 78 is a p-type semiconductor region. The anode region 78 is located in the diode region 100b. The anode region 78 is located between the drift region 70 and the first surface P1.

[0082] The anode region 78 is electrically connected to the upper electrode 12. The anode region 78 is in contact with the upper electrode 12.

[0083] The main gate trench 51 is disposed in the IGBT region 100a. The main gate trench 51 is disposed on the first surface P1 side of the semiconductor layer 10 in contact with the base region 72.

[0084] The main gate trench 51 is a trench disposed in the semiconductor layer 10. The main gate trench 51 is a part of the semiconductor layer 10.

[0085] The main gate trench 51 extends in a first direction parallel to the first surface P1. The main gate trench 51 has a stripe shape. A plurality of main gate trenches 51 are repeatedly arranged in a second direction orthogonal to the first direction.

[0086] The main gate trench 51 extends through the base region 72 to reach the drift region 70.

[0087] The first gate electrode 31 is disposed in the IGBT region 100a. The first gate electrode 31 is disposed on the first surface P1 side of the semiconductor layer 10. The first gate electrode 31 is disposed in the main gate trench 51.

[0088] The first gate electrode 31 is, for example, a semiconductor or a metal. The first gate electrode 31 is, for example, amorphous silicon or polysilicon containing n-type or p-type impurities. The first gate electrode 31 is electrically connected to the first electrode pad 101.

[0089] A first gate insulating film 21 is disposed between the first gate electrode 31 and the semiconductor layer 10. The first gate insulating film 21 is disposed between the first gate electrode 31 and the drift region 70, between the first gate electrode 31 and the base region 72, and between the first gate electrode 31 and the emitter region 74. The first gate insulating film 21 contacts the drift region 70, the base region 72, and the emitter region 74. The first gate insulating film 21 is, for example, silicon oxide.

[0090] A virtual gate trench 52 is provided in the boundary region 100c and the diode region 100b. The virtual gate trench 52 is provided on the first surface P1 side of the semiconductor layer 10. Alternatively, the virtual gate trench 52 may not be provided in the boundary region 100c or the diode region 100b.

[0091] The virtual gate trench 52 is a trench disposed in the semiconductor layer 10. The virtual gate trench 52 is a part of the semiconductor layer 10.

[0092] The virtual gate trench 52 extends in a first direction parallel to the first surface P1. The virtual gate trench 52 has a stripe shape. A plurality of virtual gate trenches 52 are repeatedly arranged in a second direction orthogonal to the first direction.

[0093] The virtual gate trench 52 extends through the base region 72 and reaches the drift region 70. The virtual gate trench 52 also extends through the anode region 78 and reaches the drift region 70. A virtual gate electrode 34 is disposed within the virtual gate trench 52. The virtual gate electrode 34 is, for example, a semiconductor or a metal. The virtual gate electrode 34 is, for example, amorphous silicon or polysilicon containing n-type or p-type impurities.

[0094] The virtual gate electrode 34 is electrically connected to the upper electrode 12, for example. Alternatively, the virtual gate electrode 34 can be in a floating state where it is not fixed to a specific potential.

[0095] A virtual gate insulating film 24 is disposed between the virtual gate electrode 34 and the semiconductor layer 10. In the boundary region 100c, the virtual gate insulating film 24 is disposed between the virtual gate electrode 34 and the drift region 70, and between the virtual gate electrode 34 and the base region 72. In the diode region 100b, the virtual gate insulating film 24 is disposed between the virtual gate electrode 34 and the drift region 70, and between the virtual gate electrode 34 and the anode region 78. The virtual gate insulating film 24 is, for example, silicon oxide.

[0096] The second gate electrode 32 is disposed in the IGBT region 100a. The second gate electrode 32 is disposed on the second side of the semiconductor layer 10.

[0097] The second gate electrode 32 is, for example, a semiconductor or a metal. The second gate electrode 32 is, for example, amorphous silicon or polysilicon containing n-type or p-type impurities. The second gate electrode 32 is electrically connected to the second electrode pad 102.

[0098] The second gate insulating film 22 is disposed between the second gate electrode 32 and the semiconductor layer 10. The second gate insulating film 22 is disposed between the second gate electrode 32 and the first contact region 64, between the second gate electrode 32 and the first drain region 60, and between the second gate electrode 32 and the buffer region 68. The second gate insulating film 22 contacts the first contact region 64, the first drain region 60, and the buffer region 68. The second gate insulating film 22 is, for example, silicon oxide.

[0099] The third gate electrode 33 is disposed in the boundary region 100c. The third gate electrode 33 is disposed on the second side of the semiconductor layer 10.

[0100] The third gate electrode 33 is, for example, a semiconductor or a metal. The third gate electrode 33 is, for example, amorphous silicon or polysilicon containing n-type or p-type impurities. The third gate electrode 33 is electrically connected to the second electrode pad 102.

[0101] The third gate insulating film 23 is disposed between the third gate electrode 33 and the semiconductor layer 10. The third gate insulating film 23 is disposed between the third gate electrode 33 and the second contact region 66, between the third gate electrode 33 and the second drain region 62, and between the third gate electrode 33 and the buffer region 68. The third gate insulating film 23 contacts the second contact region 66, the second drain region 62, and the buffer region 68. The third gate insulating film 23 is, for example, silicon oxide.

[0102] An interlayer insulating layer 42 is disposed between the first gate electrode 31 and the upper electrode 12. The interlayer insulating layer 42 electrically separates the first gate electrode 31 from the upper electrode 12. The interlayer insulating layer 42 is, for example, silicon oxide.

[0103] A back-side interlayer insulating layer 44 is disposed between the second gate electrode 32 and the lower electrode 14. The back-side interlayer insulating layer 44 electrically separates the second gate electrode 32 from the lower electrode 14. A back-side interlayer insulating layer 44 is disposed between the third gate electrode 33 and the lower electrode 14. The back-side interlayer insulating layer 44 electrically separates the third gate electrode 33 from the lower electrode 14. The back-side interlayer insulating layer 44 is, for example, silicon oxide.

[0104] A first electrode pad 101 is disposed on the first surface P1 side of the semiconductor layer 10. The first electrode pad 101 is electrically connected to the first gate electrode 31. The first electrode pad 101 and the first gate electrode 31 are connected, for example, by a metal wiring (not shown). A first gate voltage (Vg1) is applied to the first electrode pad 101.

[0105] The second electrode pad 102 is disposed on the second surface P side of the semiconductor layer 10. The second electrode pad 102 is electrically connected to the second gate electrode 32 and the third gate electrode 33. The second electrode pad 102 and the second gate electrode 32 and the third gate electrode 33 are connected, for example, by metal wiring (not shown). A second gate voltage (Vg2) is applied to the second electrode pad 102.

[0106] The absolute value of the threshold voltage of the third transistor in the RC-IGBT100 is lower than that of the second transistor. In the RC-IGBT100, both the second and third transistors are n-type MOSFETs. Therefore, the threshold voltages of both the second and third transistors are positive. Consequently, the threshold voltage of the third transistor is lower than that of the second transistor.

[0107] The threshold voltage of the third transistor having the third gate electrode 33 is, for example, less than two-thirds of the threshold voltage of the second transistor having the second gate electrode 32.

[0108] The p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32. Because the p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32, the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0109] Next, the driving method of RC-IGBT100 will be explained.

[0110] Figure 3 This is an explanatory diagram of the driving method of the semiconductor device according to the first embodiment. Figure 3 This is a timing diagram of the first gate voltage (Vg1) applied to the first electrode pad 101 and the second gate voltage (Vg2) applied to the second electrode pad 102.

[0111] When the RC-IGBT100 is in the off state, an emitter voltage (Ve) is applied to the upper electrode 12. For example, at time t0, an emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage (Ve) is, for example, 0V.

[0112] With the RC-IGBT100 in the off state, a collector voltage (Vc) is applied to the lower electrode 14. The collector voltage (Vc) is, for example, 200V to 6500V. The collector-emitter voltage (Vce) applied between the lower electrode 14 and the upper electrode 12 is, for example, 200V to 6500V.

[0113] Furthermore, the first gate voltage (Vg1) is a voltage referenced to the emitter voltage (Ve). Additionally, the second gate voltage (Vg2) is a voltage referenced to the collector voltage (Vc).

[0114] First, the time of change of the first gate voltage (Vg1) applied to the first transistor will be explained.

[0115] For example, at time t0, a first turn-off voltage (Voff1) is applied as a first gate voltage (Vg1). The first turn-off voltage (Voff1) refers to a voltage below the threshold voltage at which the first transistor is not in the on state.

[0116] The first shutdown voltage (Voff1) is, for example, 0V or a negative voltage. Figure 3 The example illustrates the case where the first shutdown voltage (Voff1) is 0V.

[0117] At time t1, a first turn-on voltage (Von1) is applied as the first gate voltage (Vg1). The first turn-on voltage (Von1) is a positive voltage that exceeds the threshold voltage of the first transistor. Figure 3The example illustrates the case where the first turn-on voltage (Von1) is 15V.

[0118] The RC-IGBT100 is turned on when a first turn-on voltage (Von1) is applied to the first transistor. The RC-IGBT100 is then turned on at time t1.

[0119] By applying a first turn-on voltage (Von1) to the first transistor, an n-type inversion layer is formed near the interface between the p-type base region 72 and the first gate insulating film 21. By forming the n-type inversion layer, electrons are injected from the n-type emitter region 74 into the n-type drift region 70 through the n-type inversion layer.

[0120] Electrons injected into the n-type drift region 70 forward bias the pn junction formed between the n-type buffer region 68 and the p-type first contact region 64, and between the n-type buffer region 68 and the p-type second contact region 66. Upon reaching the lower electrode 14, electrons induce hole injection from the p-type first contact region 64 and the p-type second contact region 66. Therefore, the RC-IGBT 100 is in the ON state.

[0121] At time t2, a first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). By applying the first turn-off voltage (Voff1) to the first transistor, the RC-IGBT100 becomes the off state. During the period from time t1 to time t2, the RC-IGBT100 is in the on state.

[0122] Next, the variation time of the second gate voltage (Vg2) applied to the second and third transistors, which are back-side transistors, will be explained.

[0123] For example, at time t0, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) refers to the voltage below the threshold voltage at which the second and third transistors are not in the on state.

[0124] The second shutdown voltage (Voff2) is, for example, 0V or a negative voltage. Figure 3 The example illustrates the case where the second shutdown voltage (Voff2) is 0V.

[0125] At time tx after time t1, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) is a positive voltage that exceeds the threshold voltages of the second and third transistors. Figure 3 The example illustrates the case where the second turn-on voltage (Von2) is 15V.

[0126] Furthermore, time tx can be before or after time t2. Figure 3 The example illustrates the case where time tx is before time t2.

[0127] By applying a second turn-on voltage (Von2) to the second transistor, an n-type inversion layer is formed near the interface between the p-type first contact region 64 and the second gate insulating film 22. Additionally, by applying a second turn-on voltage (Von2) to the third transistor, an n-type inversion layer is formed near the interface between the p-type second contact region 66 and the third gate insulating film 23.

[0128] By forming an n-type inversion layer near the interface between the p-type first contact region 64 and the second gate insulating film 22, a pathway is formed to discharge electrons from the n-type buffer region 68 of the IGBT region 100a to the lower electrode 14 through the n-type inversion layer and the n-type first drain region 60.

[0129] In addition, by forming an n-type inversion layer near the interface between the p-type second contact region 66 and the third gate insulating film 23, a pathway is formed to discharge electrons from the n-type buffer region 68 of the boundary region 100c through the n-type inversion layer and the n-type second drain region 62 to the lower electrode 14.

[0130] That is, a short circuit occurs between the n-type buffer region 68 of the IGBT region 100a and the boundary region 100c and the lower electrode 14, which is called an anode-short circuit.

[0131] By causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the IGBT region 100a through the p-type first contact region 64. Therefore, the injection of holes from the p-type first contact region 64 into the drift region 70 of the IGBT region 100a is suppressed.

[0132] Similarly, by causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the boundary region 100c through the p-type second contact region 66. Therefore, the injection of holes from the p-type second contact region 66 into the drift region 70 of the boundary region 100c is suppressed.

[0133] Furthermore, in the RC-IGBT 100 of the first embodiment, the threshold voltage of the third transistor in the boundary region 100c is lower than the threshold voltage of the second transistor in the IGBT region 100a. Therefore, at time tx, when a second turn-on voltage (Von2) is applied to both the second gate electrode 32 and the third gate electrode 33, the third transistor with the lower threshold voltage turns on earlier than the second transistor.

[0134] Therefore, the injection of holes into the drift region 70 of the boundary region 100c is suppressed earlier than the injection of holes into the drift region 70 of the IGBT region 100a. Consequently, the amount of holes in the drift region 70 of the boundary region 100c decreases earlier than the amount of holes in the drift region 70 of the IGBT region 100a.

[0135] Then, at time t3, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2) to turn off the second transistor and the third transistor.

[0136] Next, the function and effects of the semiconductor device in the first embodiment will be explained.

[0137] The RC-IGBT 100 of the first embodiment has a second transistor as a back-side transistor on the back side of the semiconductor layer 10 of the IGBT region 100a. During the turn-off operation of the RC-IGBT 100, by keeping the second transistor in the on state, the injection of holes into the drift region 70 of the IGBT region 100a is suppressed. By suppressing the injection of holes into the drift region 70, turn-off losses are reduced compared to the case without a back-side transistor. Therefore, the power consumption of the RC-IGBT 100 can be reduced.

[0138] Furthermore, the RC-IGBT 100 of the first embodiment has a boundary region 100c between the IGBT region 100a and the diode region 100b, which does not contain the first transistor or the diode. The boundary region 100c suppresses interference between the operation of the IGBT in the IGBT region 100a and the operation of the diode in the element region, thus preventing characteristic degradation of the RC-IGBT 100. For example, it suppresses the influence of carriers injected from the IGBT region 100a during diode recovery operation, thereby reducing the increase in diode recovery loss.

[0139] When the RC-IGBT100 is in the ON state, the on-state current also flows between the upper electrode 12 and the lower electrode 14 of the boundary region 100c. Therefore, when the RC-IGBT100 is in the ON state, charge carriers also accumulate in the drift region 70 of the boundary region 100c. In other words, when the RC-IGBT100 is in the ON state, the charge carriers extend to the boundary region 100c where the first transistor does not exist on the surface.

[0140] During the turn-off operation of the RC-IGBT 100, it is necessary to discharge the carriers accumulated in the drift region 70 of the boundary region 100c. However, there is no carrier discharge path on the surface side of the boundary region 100c. Therefore, the carriers are concentrated at the end of the IGBT region 100a and discharged. Consequently, current concentration occurs at the end of the IGBT region 100a. Therefore, there is a risk of damage to the RC-IGBT 100 due to current concentration.

[0141] The RC-IGBT 100 of the first embodiment has a third transistor on the back side of the semiconductor layer 10 in the boundary region 100c, which is activated earlier by the second transistor due to its low threshold voltage. By turning on the third transistor at time tx, the injection of holes into the drift region 70 of the boundary region 100c is suppressed earlier than the injection of holes into the drift region 70 of the IGBT region 100a. As a result, the amount of holes in the drift region 70 of the boundary region 100c decreases earlier than the amount of holes in the drift region 70 of the IGBT region 100a.

[0142] Therefore, current concentration at the end of IGBT region 100a can be suppressed during the turn-off operation of RC-IGBT100. This helps to prevent damage to RC-IGBT100 caused by current concentration.

[0143] From the viewpoint of suppressing damage to the RC-IGBT100 caused by current concentration, the threshold voltage of the third transistor having the third gate electrode 33 is preferably less than two-thirds, more preferably less than one-half, of the threshold voltage of the second transistor having the second gate electrode 32.

[0144] The first variation of the semiconductor device according to the first embodiment differs from the semiconductor device according to the first embodiment in that the thickness of the third gate insulating film 23 is thinner than the thickness of the second gate insulating film 22. In the first variation of the semiconductor device according to the first embodiment, for example, the p-type impurity concentration of the second contact region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first contact region 64 facing the second gate electrode 32.

[0145] In a first variation of the semiconductor device according to the first embodiment, the threshold voltage of the third transistor is lower than that of the second transistor because the thickness of the third gate insulating film 23 is thinner than that of the second gate insulating film 22.

[0146] The second variation of the semiconductor device according to the first embodiment differs from the semiconductor device according to the first embodiment in that the channel length of the third transistor is shorter than the channel length of the second transistor. Specifically, for example, the channel length of the third transistor is shorter than the channel length of the second transistor by making the second directional distance between the second drain region 62 and the buffer region 68 of the boundary region 100c shorter than the second directional distance between the first drain region 60 and the buffer region 68 of the IGBT region 100a. In the second variation of the semiconductor device according to the first embodiment, for example, the p-type impurity concentration of the second contact region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first contact region 64 facing the second gate electrode 32.

[0147] In a second variation of the semiconductor device according to the first embodiment, by making the channel length of the third transistor shorter than that of the second transistor, the threshold voltage of the third transistor is lower than that of the second transistor due to the short-channel effect.

[0148] The above-described RC-IGBT, based on the first embodiment and its variations, can suppress damage caused by current concentration.

[0149] (Second Implementation)

[0150] The semiconductor device according to the second embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a transistor region including a first transistor having a first gate electrode disposed on the first surface side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second surface side of the semiconductor layer; and an adjacent region including the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and having a predetermined area occupying a higher proportion than the predetermined area occupying a proportion of the second gate electrode and disposed on the second surface side of the semiconductor layer.

[0151] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the proportion of the predetermined area of ​​the third gate electrode is higher than the proportion of the predetermined area of ​​the second gate electrode. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0152] The semiconductor device in the second embodiment is an RC-IGBT200 in which an IGBT and a return diode are formed on the same semiconductor chip. Furthermore, the RC-IGBT200 is an IGBT with a double-gate structure having gate electrodes on both the surface and back sides of the semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be used as an example for explanation.

[0153] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 4 It is the semiconductor device of the first embodiment. Figure 2 The corresponding diagram.

[0154] The RC-IGBT 200 of the second embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a virtual gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a virtual gate electrode 34, a surface interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0155] The semiconductor layer 10 includes a main gate trench 51 (first trench), a virtual gate trench 52, an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first contact region 64 (fourth semiconductor region), a p-type second contact region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78.

[0156] The area occupied by the third gate electrode 33 in the boundary region 100c of the RC-IGBT200 is higher than the area occupied by the second gate electrode 32 in the IGBT region 100a. In other words, the density of the third gate electrode 33 in the boundary region 100c is higher than that of the second gate electrode 32 in the IGBT region 100a. That is, the density of the third transistor in the boundary region 100c is higher than that of the second transistor in the IGBT region 100a.

[0157] In the RC-IGBT200, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the proportion of the specified area occupied by the third gate electrodes 33 in the boundary region 100c is higher than the proportion of the specified area occupied by the second gate electrodes 32 in the IGBT region 100a.

[0158] The specified area refers to the area on the second surface P2 that can include the boundary region 100c. For example, the specified area is 50μm × 50μm.

[0159] The proportion of the area occupied by the third gate electrode 33 in the boundary region 100c is, for example, more than 1.5 times the proportion of the area occupied by the second gate electrode 32 in the IGBT region 100a.

[0160] In the RC-IGBT200, the threshold voltage of the third transistor is, for example, the same as the threshold voltage of the second transistor. In the RC-IGBT200, for example, the p-type impurity concentration of the second contact region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first contact region 64 facing the second gate electrode 32.

[0161] RC-IGBT200 through the first embodiment Figure 3 The driving method shown is used for driving.

[0162] At time tx, by applying a second turn-on voltage (Von2) to the second and third transistors, an anode-short circuit occurs, similar to the RC-IGBT100 in the first embodiment.

[0163] By causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the IGBT region 100a through the p-type first contact region 64. Therefore, the injection of holes from the p-type first contact region 64 into the drift region 70 of the IGBT region 100a is suppressed.

[0164] Similarly, by causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the boundary region 100c through the p-type second contact region 66. Therefore, the injection of holes from the p-type second contact region 66 into the drift region 70 of the boundary region 100c is suppressed.

[0165] In the RC-IGBT 200 of the second embodiment, the density of the third transistor in the boundary region 100c is higher than the density of the second transistor in the IGBT region 100a. Therefore, at time tx, when the second turn-on voltage (Von2) is simultaneously applied to the second gate electrode 32 and the third gate electrode 33, the reduction in hole injection in the drift region 70 of the boundary region 100c is greater than the reduction in hole injection in the drift region 70 of the IGBT region 100a. Therefore, the amount of holes in the drift region 70 of the boundary region 100c decreases earlier than the amount of holes in the drift region 70 of the IGBT region 100a.

[0166] Therefore, during the turn-off operation of the RC-IGBT200, current concentration at the end of the IGBT region 100a can be suppressed. This, in turn, prevents damage to the RC-IGBT200 caused by current concentration.

[0167] From the viewpoint of suppressing damage to the RC-IGBT200 caused by current concentration, the proportion of the specified area of ​​the third gate electrode 33 in the boundary region 100c is preferably 1.5 times or more, and more preferably 2 times or more, the proportion of the specified area of ​​the second gate electrode 32 in the IGBT region 100a.

[0168] According to the second embodiment, an RC-IGBT that suppresses damage caused by current concentration can be realized.

[0169] (Third Implementation)

[0170] The semiconductor layer of the semiconductor device in the third embodiment further includes a second trench and a third trench disposed on the second surface side, and the second gate electrode is disposed in the second trench and the third gate electrode is disposed in the third trench, which differs from the semiconductor device of the second embodiment. Hereinafter, descriptions that are repeated in the first or second embodiments will sometimes be omitted.

[0171] The semiconductor device in the third embodiment is an RC-IGBT 300 in which an IGBT and a return diode are formed on the same semiconductor chip. Furthermore, the RC-IGBT 300 is an IGBT with a double-gate structure having gate electrodes on both the surface and back sides of the semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be used as an example for explanation.

[0172] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 5 For the semiconductor device of the first embodiment Figure 2 The corresponding diagram.

[0173] The RC-IGBT 300 of the third embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a virtual gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a virtual gate electrode 34, a surface interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0174] The semiconductor layer 10 includes a main gate trench 51 (first trench), a virtual gate trench 52, a first back trench 53 (second trench), a second back trench 54 (third trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first contact region 64 (fourth semiconductor region), a p-type second contact region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78.

[0175] The main gate groove 51 is an example of the first groove. The first back groove 53 is an example of the second groove. The second back groove 54 is an example of the third groove.

[0176] The first transistor is disposed on the first surface P1 side of the semiconductor layer 10. The first transistor has a trench gate structure with the gate electrode disposed in a trench. The first transistor is an IGBT.

[0177] The second transistor is disposed on the second surface P2 side of semiconductor layer 10. The second transistor has a trench gate structure. The second transistor is a so-called back-side transistor. The second transistor is an n-type MOSFET with electrons as charge carriers.

[0178] The third transistor is disposed on the second surface P2 side of semiconductor layer 10. The third transistor has a trench gate structure. The third transistor is a so-called back-side transistor. The third transistor is an n-type MOSFET with electrons as charge carriers.

[0179] The first, second, and third transistors are not structurally distinct from the others. For example, Figure 5 The area enclosed by the dashed line X corresponds to one cell of the first transistor. Additionally, for example... Figure 5 The region enclosed by the dashed line Y corresponds to one cell of the second transistor. Additionally, for example, Figure 5 The area enclosed by the dashed line Z in the diagram corresponds to one cell of the third transistor.

[0180] The area occupied by the third gate electrode 33 in the boundary region 100c of the RC-IGBT300 is higher than the area occupied by the second gate electrode 32 in the IGBT region 100a. That is, the density of the third transistor in the boundary region 100c is higher than the density of the second transistor in the IGBT region 100a.

[0181] In the RC-IGBT 300, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the proportion of the specified area occupied by the third gate electrodes 33 in the boundary region 100c is higher than the proportion of the specified area occupied by the second gate electrodes 32 in the IGBT region 100a.

[0182] RC-IGBT300 through the first embodiment Figure 3 The driving method shown is used for driving.

[0183] In the third embodiment of the RC-IGBT 300, the density of the third transistor in the boundary region 100c is higher than the density of the second transistor in the IGBT region 100a. Therefore, similar to the RC-IGBT 200 in the second embodiment, current concentration at the end of the IGBT region 100a can be suppressed during the turn-off operation of the RC-IGBT 300. Thus, damage to the RC-IGBT 300 caused by current concentration can be suppressed.

[0184] According to the third embodiment, an RC-IGBT that suppresses damage caused by current concentration can be realized.

[0185] (Fourth Implementation)

[0186] The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that it is a semiconductor device having a terminal region. Hereinafter, some descriptions that are repeated with the first embodiment will be omitted.

[0187] The semiconductor device of the fourth embodiment is an IGBT 400 with a double-gate structure having gate electrodes on both the surface and back sides of the semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

[0188] Figure 6 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 6 (a) is a top view taken from the surface side of the semiconductor layer of the IGBT400. Figure 6 (b) is a top view taken from the back side of the semiconductor layer of the IGBT400. Figure 6 A diagram showing the layout of the IGBT400.

[0189] The IGBT400 has an IGBT region 400a and a terminal region 400b. The terminal region 400b surrounds the IGBT region 400a. The terminal region 400b is adjacent to the IGBT region 400a.

[0190] Additionally, the IGBT400 includes a first electrode pad 101 and a second electrode pad 102. The first electrode pad 101 is, for example, disposed on the surface side of the semiconductor layer. The second electrode pad 102 is, for example, disposed on the back side of the semiconductor layer.

[0191] IGBT region 400a is an example of a transistor region. Termination region 400b is an example of an adjacent region.

[0192] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 7 for Figure 6 (a) BB' section.

[0193] The IGBT 400 of the fourth embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a surface interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0194] IGBT region 400a operates as an IGBT. Terminal region 400b has the function of suppressing the voltage drop at the end of IGBT region 400a.

[0195] IGBT region 400a includes a first transistor having a first gate electrode 31 and a second transistor having a second gate electrode 32. Terminal region 400b includes a third transistor having a third gate electrode 33.

[0196] The first transistor is controlled by a voltage applied to the first gate electrode 31. The second transistor is controlled by a voltage applied to the second gate electrode 32. The third transistor is controlled by a voltage applied to the third gate electrode 33.

[0197] The first transistor is disposed on the first surface P1 side of the semiconductor layer 10. The first transistor has a trench gate structure with the gate electrode disposed in a trench. The first transistor is an IGBT.

[0198] The second transistor is disposed on the second surface P2 side of semiconductor layer 10. The second transistor has a planar gate structure. The second transistor is a so-called back-side transistor. The second transistor is an n-type MOSFET with electrons as charge carriers.

[0199] The third transistor is disposed on the second surface P2 side of semiconductor layer 10. The third transistor has a planar gate structure. The third transistor is a so-called back-side transistor. The third transistor is an n-type MOSFET with electrons as charge carriers.

[0200] The first, second, and third transistors are not structurally distinct from the others. For example, Figure 7 The area enclosed by the dashed line X corresponds to one cell of the first transistor. Additionally, for example... Figure 7 The region enclosed by the dashed line Y corresponds to one cell of the second transistor. Additionally, for example, Figure 7 The area enclosed by the dashed line Z in the diagram corresponds to one cell of the third transistor.

[0201] The semiconductor layer 10 includes a main gate trench 51 (first trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first contact region 64 (fourth semiconductor region), a p-type second contact region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), a p-type intermediate region 80, and a p-type guard ring region 82.

[0202] The upper electrode 12 is an example of a first electrode. The lower electrode 14 is an example of a second electrode. The main gate trench 51 is an example of a first trench. The first drain region 60 is an example of a sixth semiconductor region. The second drain region 62 is an example of a seventh semiconductor region. The first contact region 64 is an example of a fourth semiconductor region. The second contact region 66 is an example of a fifth semiconductor region. The drift region 70 is an example of a first semiconductor region. The base region 72 is an example of a second semiconductor region. The emitter region 74 is an example of a third semiconductor region.

[0203] The semiconductor layer 10 has a first surface P1 and a second surface P2 facing the first surface P1.

[0204] The upper electrode 12 is disposed on the first surface P1 side of the semiconductor layer 10. The upper electrode 12 functions as the emitter electrode of the first transistor.

[0205] The upper electrode 12 is electrically connected to the emitter region 74 in the IGBT region 400a. An emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage is, for example, 0V.

[0206] The lower electrode 14 is disposed on the second surface P2 side of the semiconductor layer 10. The lower electrode 14 functions as a contact electrode of the first transistor within the IGBT region 400a. The lower electrode 14 is electrically connected to the first contact region 64 within the IGBT region 400a.

[0207] The lower electrode 14 is electrically connected to the second contact region 66 in the terminal region 400b. A collector voltage (Vc) is applied to the lower electrode 14. The collector voltage is, for example, 200V to 6500V.

[0208] The drift region 70 is an n-type semiconductor region. The drift region 70 is located in the IGBT region 400a and the termination region 400b.

[0209] The base region 72 is a p-type semiconductor region. The base region 72 is located in the IGBT region 400a.

[0210] Emitter region 74 is an n-type semiconductor region. Emitter region 74 is located in IGBT region 400a. Emitter region 74 is not located in termination region 400b.

[0211] The emitter region 74 is electrically connected to the upper electrode 12. The emitter region 74 is in contact with the upper electrode 12.

[0212] The first contact region 64 is a p-type semiconductor region. The first contact region 64 is located in the IGBT region 400a.

[0213] The first contact area 64 is electrically connected to the lower electrode 14. The first contact area 64 is in contact with the lower electrode 14.

[0214] A portion of the first contact region 64 faces the second gate electrode 32. A channel for the second transistor, controlled by the second gate electrode 32, is formed in the first contact region 64 facing the second gate electrode 32.

[0215] The second contact region 66 is a p-type semiconductor region. The second contact region 66 is located in the terminal region 400b.

[0216] The second contact area 66 is electrically connected to the lower electrode 14. The second contact area 66 is in contact with the lower electrode 14.

[0217] A portion of the second contact region 66 faces the third gate electrode 33. A channel for the third transistor, controlled by the third gate electrode 33, is formed in the second contact region 66 facing the third gate electrode 33.

[0218] The p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32.

[0219] The first drain region 60 is an n-type semiconductor region. The first drain region 60 is located in the IGBT region 400a.

[0220] The second drain region 62 is an n-type semiconductor region. The second drain region 62 is located in the termination region 400b.

[0221] The buffer region 68 is an n-type semiconductor region. The buffer region 68 is located in the IGBT region 400a and the terminal region 400b.

[0222] The p-shaped intermediate region 80 is located in the terminal region 400b. The intermediate region 80 is located between the drift region 70 and the first surface P1. The intermediate region 80 surrounds the IGBT region 400a.

[0223] A p-shaped protection ring region 82 is provided in the terminal region 400b. The protection ring region 82 is located between the drift region 70 and the first surface P1. The protection ring region 82 surrounds the intermediate region 80. For example, multiple protection ring regions 82 are provided.

[0224] By setting the intermediate region 80 and the protection ring region 82, the electric field strength at the end of the terminal region 400b is reduced, thus suppressing the decrease in withstand voltage when the IGBT400 is in the off state.

[0225] The main gate trench 51 is located in the IGBT region 400a.

[0226] The first gate electrode 31 is disposed in the IGBT region 400a. The first gate electrode 31 is disposed in the main gate trench 51. The first gate electrode 31 is electrically connected to the first electrode pad 101.

[0227] The first gate insulating film 21 is disposed between the first gate electrode 31 and the semiconductor layer 10.

[0228] The second gate electrode 32 is disposed in the IGBT region 400a. The second gate electrode 32 is disposed on the second side of the semiconductor layer 10. The second gate electrode 32 is electrically connected to the second electrode pad 102.

[0229] The second gate insulating film 22 is disposed between the second gate electrode 32 and the semiconductor layer 10.

[0230] The third gate electrode 33 is disposed in the terminal region 400b. The third gate electrode 33 is disposed on the second side of the semiconductor layer 10. The third gate electrode 33 is electrically connected to the second electrode pad 102.

[0231] The third gate insulating film 23 is disposed between the third gate electrode 33 and the semiconductor layer 10.

[0232] The surface interlayer insulating layer 42 is disposed between the first gate electrode 31 and the upper electrode 12.

[0233] A back-side interlayer insulating layer 44 is disposed between the second gate electrode 32 and the lower electrode 14. A back-side interlayer insulating layer 44 is disposed between the third gate electrode 33 and the lower electrode 14.

[0234] A first electrode pad 101 is disposed on the first surface P1 side of the semiconductor layer 10. The first electrode pad 101 is electrically connected to the first gate electrode 31. The first electrode pad 101 and the first gate electrode 31 are connected, for example, by a metal wiring (not shown). A first gate voltage (Vg1) is applied to the first electrode pad 101.

[0235] The second electrode pad 102 is disposed on the second surface P2 side of the semiconductor layer 10. The second electrode pad 102 is electrically connected to the second gate electrode 32 and the third gate electrode 33. The second electrode pad 102 is connected to the second gate electrode 32 and the third gate electrode 33, for example, through a metal wiring (not shown). A second gate voltage (Vg2) is applied to the second electrode pad 102.

[0236] The threshold voltage of the third transistor in the IGBT400 is lower than the threshold voltage of the second transistor. The threshold voltage of the third transistor having a third gate electrode 33 is lower than the threshold voltage of the second transistor having a second gate electrode 32. For example, the threshold voltage of the third transistor having a third gate electrode 33 is less than two-thirds of the threshold voltage of the second transistor having a second gate electrode 32.

[0237] The p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32. Because the p-type impurity concentration in the second contact region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration in the first contact region 64 facing the second gate electrode 32, the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0238] Next, the driving method of IGBT400 will be explained.

[0239] IGBT400 via the first embodiment Figure 3 The driving method shown is used for driving.

[0240] At time tx, by applying a second turn-on voltage (Von2) to the second and third transistors, an anode-short circuit occurs, similar to the RC-IGBT100 in the first embodiment.

[0241] By causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the IGBT region 400a through the p-type first contact region 64. Therefore, the injection of holes from the p-type first contact region 64 into the drift region 70 of the IGBT region 400a is suppressed.

[0242] Similarly, by causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the terminal region 400b through the p-type second contact region 66. Therefore, the injection of holes from the p-type second contact region 66 into the drift region 70 of the terminal region 400b is suppressed.

[0243] In the fourth embodiment, the IGBT 400 has a second transistor as a back-side transistor on the back side of the semiconductor layer 10 in the IGBT region 400a. During the IGBT 400's turn-off operation, by turning the second transistor on, turn-off losses are reduced. Therefore, the power consumption of the IGBT 400 can be reduced.

[0244] Furthermore, in the fourth embodiment, the IGBT 400 has a terminal region 400b surrounding the IGBT region 400a. The terminal region 400b includes an intermediate region 80 and a guard ring region 82. By providing the intermediate region 80 and the guard ring region 82, the electric field strength at the end of the IGBT region 400a is reduced, suppressing the decrease in withstand voltage when the IGBT 400 is in the off state.

[0245] When the IGBT400 is in the ON state, the on-state current also flows between the upper electrode 12 and the lower electrode 14 of the terminal region 400b. Therefore, when the IGBT400 is in the ON state, charge carriers also accumulate in the drift region 70 of the terminal region 400b. In other words, when the IGBT400 is in the ON state, the charge carriers extend to the terminal region 400b where the first transistor is not present on the surface.

[0246] During the turn-off operation of the IGBT 400, the carriers accumulated in the drift region 70 of the terminal region 400b need to be discharged. However, there is no carrier discharge path on the surface side of the terminal region 400b. Therefore, the carriers are concentrated at the end of the IGBT region 400a and discharged. As a result, current concentration occurs at the end of the IGBT region 400a. Consequently, there is a risk of damage to the IGBT 400 due to current concentration.

[0247] The IGBT 400 of the fourth embodiment has a third transistor on the back side of the semiconductor layer 10 in the termination region 400b, which is activated earlier by the second transistor due to its low threshold voltage. By turning on the third transistor at time tx, the injection of holes into the drift region 70 of the termination region 400b is suppressed earlier than the injection of holes into the drift region 70 of the IGBT region 400a. As a result, the amount of holes in the drift region 70 of the termination region 400b decreases earlier than the amount of holes in the drift region 70 of the IGBT region 400a.

[0248] Therefore, current concentration at the end of IGBT region 400a can be suppressed during the IGBT4000's turn-off operation. This helps to prevent damage to the IGBT400 caused by current concentration.

[0249] From the viewpoint of suppressing damage to the IGBT400 caused by current concentration, the threshold voltage of the third transistor having the third gate electrode 33 is preferably less than two-thirds, more preferably less than one-half, of the threshold voltage of the second transistor having the second gate electrode 32.

[0250] Furthermore, by making the thickness of the third gate insulating film 23 thinner than the thickness of the second gate insulating film 22, the threshold voltage of the third transistor can be made lower than the threshold voltage of the second transistor.

[0251] In addition, by making the channel length of the third transistor shorter than that of the second transistor, the threshold voltage of the third transistor can be made lower than that of the second transistor.

[0252] According to the fourth embodiment, an IGBT that suppresses damage caused by current concentration can be realized.

[0253] (Fifth Implementation)

[0254] The semiconductor device according to the fifth embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a transistor region including a first transistor having a first gate electrode disposed on the first surface side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second surface side of the semiconductor layer; and an adjacent region including the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and having a predetermined area occupying a higher proportion than the predetermined area occupying a proportion of the second gate electrode and disposed on the second surface side of the semiconductor layer.

[0255] The semiconductor device of the fifth embodiment differs from the semiconductor device of the fourth embodiment in that the proportion of the predetermined area of ​​the third gate electrode is higher than the proportion of the predetermined area of ​​the second gate electrode. Hereinafter, some descriptions that are repeated in the fourth embodiment will be omitted.

[0256] The semiconductor device of the fifth embodiment is an IGBT 500 with a double-gate structure having gate electrodes on both the surface and back sides of the semiconductor layer. The following description will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example.

[0257] Like the IGBT 400 in the fourth embodiment, the IGBT 500 includes an IGBT region 400a and a terminal region 400b. The terminal region 400b surrounds the IGBT region 400a. The terminal region 400b is adjacent to the IGBT region 400a.

[0258] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Figure 8 For the semiconductor device of the fourth embodiment Figure 7 The corresponding diagram.

[0259] The IGBT500 of the fifth embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a surface interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0260] The semiconductor layer 10 includes a main gate trench 51 (first trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first contact region 64 (fourth semiconductor region), a p-type second contact region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), a p-type intermediate region 80, and a p-type guard ring region 82.

[0261] The area occupied by the third gate electrode 33 in the terminal region 400b of the IGBT500 is higher than the area occupied by the second gate electrode 32 in the IGBT region 400a. In other words, the density of the third gate electrode 33 in the terminal region 400b is higher than the density of the second gate electrode 32 in the IGBT region 400a. That is, the density of the third transistor in the terminal region 400b is higher than the density of the second transistor in the IGBT region 400a.

[0262] In IGBT500, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the occupancy ratio of the specified area of ​​the third gate electrodes 33 in the terminal region 400b is higher than the occupancy ratio of the specified area of ​​the second gate electrodes 32 in the IGBT region 400a.

[0263] The specified area is the area on the second surface P2 that can include the terminal region 400b. For example, the specified area is 50μm × 50μm.

[0264] The area occupied by the third gate electrode 33 in the terminal region 400b is more than 1.5 times the area occupied by the second gate electrode 32 in the IGBT region 400a as described above.

[0265] In IGBT 500, the threshold voltage of the third transistor is, for example, the same as the threshold voltage of the second transistor. In IGBT 500, for example, the p-type impurity concentration of the second contact region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first contact region 64 facing the second gate electrode 32.

[0266] IGBT500 through the first embodiment Figure 3 The driving method shown is used for driving.

[0267] At time tx, by applying a second turn-on voltage (Von2) to the second and third transistors, an anode-short circuit occurs, similar to that of the IGBT400 in the fourth embodiment.

[0268] By causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the IGBT region 400a through the p-type first contact region 64. Therefore, the injection of holes from the p-type first contact region 64 into the drift region 70 of the IGBT region 400a is suppressed.

[0269] Similarly, by causing an anode-short circuit, electrons are prevented from reaching the lower electrode 14 from the n-type buffer region 68 of the terminal region 400b through the p-type second contact region 66. Therefore, the injection of holes from the p-type second contact region 66 into the drift region 70 of the terminal region 400b is suppressed.

[0270] In the IGBT 500 of the fifth embodiment, the density of the third transistor in the terminal region 400b is higher than the density of the second transistor in the IGBT region 400a. Therefore, at time tx, when the second turn-on voltage (Von2) is simultaneously applied to the second gate electrode 32 and the third gate electrode 33, the reduction in hole injection in the drift region 70 of the terminal region 400b is greater than the reduction in hole injection in the drift region 70 of the IGBT region 400a. Therefore, the amount of holes in the drift region 70 of the terminal region 400b decreases earlier than the amount of holes in the drift region 70 of the IGBT region 400a.

[0271] Therefore, during the turn-off operation of the IGBT500, current concentration at the end of the IGBT region 400a can be suppressed. This, in turn, prevents damage to the IGBT500 caused by current concentration.

[0272] From the viewpoint of suppressing damage to the IGBT500 caused by current concentration, the proportion of the specified area of ​​the third gate electrode 33 in the terminal region 400b is preferably 1.5 times or more, and more preferably 2 times or more, the proportion of the specified area of ​​the second gate electrode 32 in the IGBT region 400a.

[0273] According to the fifth embodiment, an IGBT that suppresses damage caused by current concentration can be realized.

[0274] In the first to fifth embodiments, the case where the semiconductor layer is monocrystalline silicon was described as an example, but the semiconductor layer is not limited to monocrystalline silicon. For example, it can also be other monocrystalline semiconductors such as monocrystalline silicon carbide.

[0275] In the first to fifth embodiments, the case of a stripe shape with parallel grooves was described as an example, but the present invention can also be applied to sieve-shaped grooves with intersecting grooves or dot-shaped grooves.

[0276] In the first to fifth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type is used as an example. However, it is also possible to make the first conductivity type p-type and the second conductivity type n-type.

[0277] In the first to fifth embodiments, the case where the first transistor has a trench gate structure has been described as an example, but the first transistor may also have a planar gate structure.

[0278] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: A semiconductor layer having a first surface and a second surface facing the first surface; A transistor region comprising a first transistor having a first gate electrode disposed on the first side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second side of the semiconductor layer; as well as An adjacent region comprising the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having a third gate electrode electrically connected to the second gate electrode and disposed on the second side of the semiconductor layer and having an absolute value of a threshold voltage smaller than the absolute value of the threshold voltage of the second transistor.

2. The semiconductor device according to claim 1, further comprising a first electrode contacting the first surface and a second electrode contacting the second surface. The semiconductor layer further comprises: First semiconductor region of first conductivity type; A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the first surface and facing the first gate electrode; A third semiconductor region of a first conductivity type is disposed between the second semiconductor region and the first surface and in contact with the first electrode; A fourth semiconductor region of the second conductivity type is disposed between the first semiconductor region and the second surface, facing the second gate electrode and in contact with the second electrode; A fifth semiconductor region of a second conductivity type is disposed between the first semiconductor region and the second surface, facing the third gate electrode and in contact with the second electrode; A sixth semiconductor region of the first conductivity type is disposed between the fourth semiconductor region and the second surface and in contact with the second electrode; as well as A seventh semiconductor region of the first conductivity type is disposed between the fifth semiconductor region and the second surface and in contact with the second electrode. The second conductivity type impurity concentration in the fifth semiconductor region facing the third gate electrode is lower than the second conductivity type impurity concentration in the fourth semiconductor region facing the second gate electrode.

3. The semiconductor device according to claim 1, wherein, The absolute value of the threshold voltage of the third transistor is less than two-thirds of the absolute value of the threshold voltage of the second transistor.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a diode region including the semiconductor layer and a diode, and having an adjacent region between the diode and the transistor region.

5. The semiconductor device according to any one of claims 1 to 3, wherein, The adjacent region surrounds the transistor region.

6. A semiconductor device comprising: A semiconductor layer having a first surface and a second surface facing the first surface; A transistor region comprising a first transistor having a first gate electrode disposed on the first side of the semiconductor layer and a second transistor having a second gate electrode disposed on the second side of the semiconductor layer; An adjacent region comprising the semiconductor layer and a third transistor and adjacent to the transistor region, the third transistor having an area electrically connected to the second gate electrode and having a specified area that occupies a larger proportion than the specified area of ​​the second gate electrode, and having a third gate electrode disposed on the second surface side of the semiconductor layer; as well as A diode region comprising the semiconductor layer and a diode, and having an adjacent region between it and the transistor region. A fourth trench is provided in the adjacent area on the first side, and a fourth gate electrode and an insulating film located between the fourth gate electrode and the semiconductor layer are provided in the fourth trench.

7. The semiconductor device according to any one of claims 1 to 3 and 6, wherein, The semiconductor layer further includes a first trench disposed on the first surface side, and the first gate electrode is disposed in the first trench.

8. The semiconductor device according to any one of claims 1 to 3 and 6, wherein, The semiconductor layer further includes a second trench disposed on the second surface side and a third trench disposed on the second surface side, wherein the second gate electrode is disposed in the second trench and the third gate electrode is disposed in the third trench.

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