Semiconductor device

Abstract

The semiconductor device of the embodiment is provided with a cell region and a terminal region, and includes a first electrode, a semiconductor portion provided on the first electrode, an insulating film provided on the semiconductor portion in the terminal region, a plurality of second electrodes provided on the insulating film, arranged in a first direction from the center of the semiconductor portion toward the outer periphery and separated from each other when viewed from above, a first floating electrode provided in the insulating film, overlapping a gap between an adjacent pair of the second electrodes of the plurality of second electrodes when viewed from above, and facing one of the pair of the second electrodes with the insulating film interposed therebetween, and a second floating electrode provided in the insulating film in a manner separated from the first floating electrode, overlapping the first floating electrode within the gap when viewed from above, the portion overlapping the first floating electrode being positioned below the portion in the first floating electrode overlapping the gap, and facing the other of the pair of the second electrodes with the insulating film interposed therebetween.

Description

[0001] This application claims priority by referencing Japanese Patent Application No. 2021-45947 (filed on March 19, 2021). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0003] Conventionally, there is a known semiconductor device that includes a cell region and a terminal region surrounding the cell region, wherein the cell region is equipped with elements such as diodes or transistors. In such semiconductor devices, a structure has been attempted to suppress the expansion of the depletion layer by providing a terminal region, thereby increasing the breakdown voltage. Summary of the Invention

[0004] The embodiments of the present invention provide a highly reliable semiconductor device.

[0005] The semiconductor device according to the embodiment includes a unit region and a terminal region surrounding the unit region. The semiconductor device comprises: a first electrode; a semiconductor portion disposed on the first electrode; an insulating film disposed on the semiconductor portion in the terminal region; a plurality of second electrodes disposed on the insulating film, arranged in a direction from the center of the semiconductor portion toward the outer periphery when viewed from above, and separated from each other; a first floating electrode disposed in the insulating film, overlapping the gap of an adjacent pair of second electrodes among the plurality of second electrodes when viewed from above, and facing one of the pair of second electrodes across the insulating film; and a second floating electrode disposed in the insulating film separately from the first floating electrode, overlapping the first floating electrode within the gap when viewed from above, the portion overlapping the first floating electrode being located below the portion of the first floating electrode that overlaps the gap, and facing the other of the pair of second electrodes across the insulating film. Attached Figure Description

[0006] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0007] Figure 2 yes Figure 1 A cross-sectional view at line AA′.

[0008] Figure 3 This is a top view showing the semiconductor section of the semiconductor device according to the first embodiment.

[0009] Figure 4 This is a top view showing the semiconductor section and insulating film of the semiconductor device according to the first embodiment.

[0010] Figure 5 is a plan view showing a semiconductor portion, an insulating film, an upper electrode, an EQPR electrode, and a plurality of intermediate electrodes of the semiconductor device according to the first embodiment.

[0011] Figure 6 is a plan view showing a region in which each floating electrode is provided in the semiconductor device according to the first embodiment.

[0012] Figure 7 is a schematic view showing an operation of a terminal region of the semiconductor device according to the first embodiment.

[0013] Figure 8 is a sectional view showing a terminal region of the semiconductor device according to the reference example.

[0014] Figure 9 is a sectional view showing the semiconductor device according to the second embodiment.

[0015] Figure 10 is a sectional view showing the semiconductor device according to the reference example.

[0016] Figure 11 is a graph showing a relationship between a withstand voltage and an electric charge of the semiconductor device according to the second embodiment and the semiconductor device according to the reference example, in which a horizontal axis represents an electric charge generated on a surface of a protective film and a vertical axis represents a withstand voltage.

[0017] Figure 12 is a simulation result showing equipotential lines in a state in which a positive electric charge and a negative electric charge are generated on a surface of a protective film in the semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, each embodiment will be described with reference to the drawings. Note that the drawings are schematic or conceptual views and the ratios of the thicknesses of the layers, the ratios of the dimensions of the portions, and the like, do not correspond to actual ones. In addition, even when similar portions are shown in different drawings, the sizes, the ratios, and the like, of the portions are not limited to the sizes, the ratios, and the like, shown in the drawings. Furthermore, the same portions will be given the same reference numerals and will be described in detail only once.

[0019] In addition, in order to easily understand the description, the XYZ orthogonal coordinate system will be used to describe the arrangement and the composition of each portion. The X axis, the Y axis, and the Z axis are orthogonal to each other. In addition, the direction in which the X axis extends is referred to as the "X direction", the direction in which the Y axis extends is referred to as the "Y direction", and the direction in which the Z axis extends is referred to as the "Z direction". In addition, in order to easily understand the description, the direction of the arrow in the Z direction is set to the upward direction and the opposite direction thereof is set to the downward direction, but these directions have no relation to the direction of gravity.

[0020] Additionally, the following n + n - The expression represents the relative level of impurity concentration in an n-type semiconductor. Specifically, it is expressed as a "+" expression indicating a relatively high impurity concentration compared to a "-" expression. Here, "impurity concentration" represents the true impurity concentration after the cancellation of both donor and acceptor impurities in each region.

[0021] <First Implementation>

[0022] First, the first embodiment will be described.

[0023] Figure 1 This is a top view showing the semiconductor device involved in this embodiment.

[0024] Figure 2 yes Figure 1 A cross-sectional view at line AA′.

[0025] In this embodiment, the semiconductor device 100 is generally rectangular. However, the shape of the semiconductor device is not particularly limited to the shape described above.

[0026] In semiconductor device 100, such as Figure 1 As shown, a unit region CE and a surrounding terminal region EN are defined. Figure 1 In the middle, the innermost area enclosed by a thick double-dotted line is the cell region CE, and the entire area outside the cell region CE in the semiconductor device 100 is the terminal region EN.

[0027] Within the cell region CE, one or more components of the same type, such as diodes or transistors, are provided. Examples of transistors provided in the cell region CE include MOSFETs (metal-oxide-semiconductor field-effect transistors) or IGBTs (insulated gate bipolar transistors). The construction of the termination region EN will be described later.

[0028] Semiconductor device 100, such as Figure 2As shown, the semiconductor device 100 includes a lower electrode 110, a semiconductor section 120, an insulating film 130, an upper electrode 140, an EQPR (equivalent-potential ring) electrode 150, intermediate electrodes 161 and 162, a plurality of first floating electrodes 171, 173, and 175, and a plurality of second floating electrodes 172, 174, and 176. In this embodiment, the lower electrode 110 corresponds to the first electrode, and the upper electrode 140, the EQPR electrode 150, and the intermediate electrodes 161 and 162 each correspond to the second electrodes. The various parts of the semiconductor device 100 will be described in detail below.

[0029] The lower electrode 110 is disposed over approximately the entire area of ​​the lower surface of the semiconductor device 100. That is, the lower electrode 110 is disposed over approximately the entire area of ​​the cell region CE and approximately the entire area of ​​the terminal region EN. The lower electrode 110 is plate-shaped. The shape of the lower electrode 110 as viewed from above is as follows: Figure 1 The shape shown in this embodiment is roughly rectangular. However, the shape of the lower electrode is not limited to the shape described above.

[0030] When a diode is provided in the cell region CE, the lower electrode 110 functions as, for example, the cathode electrode of the diode. When a MOSFET is provided in the cell region CE, the lower electrode 110 functions as, for example, the drain electrode of the MOSFET. When an IGBT is provided in the cell region CE, the lower electrode 110 functions as, for example, the collector electrode of the IGBT.

[0031] like Figure 2 As shown, a semiconductor section 120 is provided on the lower electrode 110 from the unit region CE to the terminal region EN.

[0032] Figure 3 This is a top view showing the semiconductor section of the semiconductor device according to this embodiment.

[0033] Among them, Figure 3 For ease of understanding, in the terminal region EN, the upper surface of the semiconductor section 120 is provided with n, which will be described later. + The regions of the stopper region 121c and the regions of the p-type semiconductor layer 122 are represented by patterns of different dots.

[0034] The semiconductor section 120 includes, for example, silicon (Si). In this embodiment, the semiconductor section 120 is generally rectangular. In this specification, when viewed from above, the term "constant element A is located on the center C side of the semiconductor section compared to constituent element B" is used. Similarly, when viewed from above, the term "constant element A is located on the outer periphery 120e side of the semiconductor section compared to constituent element B" is used. In this embodiment, the center C is located at the intersection of the diagonals of the outer periphery 120e. However, the shape of the semiconductor section is not limited to the shape described above.

[0035] like Figure 2 As shown, the semiconductor section 120 has an n-type semiconductor layer 121 and a p-type semiconductor layer 122. In this embodiment, the n-type semiconductor layer 121 corresponds to the first semiconductor layer, and the p-type semiconductor layer 122 corresponds to the second semiconductor layer.

[0036] n-type semiconductor layer 121 has n + Regions of type 121a, n － Regions 121b and n of type + Type 121c blocking region. In this embodiment, n + Region 121a of type n corresponds to the first semiconductor region, n － Region 121b of type n corresponds to the second semiconductor region, n + The blocking region 121c of the type is equivalent to the third semiconductor region.

[0037] n + The type 121a is set from the unit area CE to the terminal area EN. + Region 121a of type is disposed on the lower electrode 110 in the terminal region EN and is connected to the lower electrode 110. Therefore, n + Region 121a of the type is electrically connected to the lower electrode 110.

[0038] When a diode is provided in the cell region CE, in the portion of the cell region CE where the diode is located, n + Region 121a of type is provided on the lower electrode 110 and connected to the lower electrode 110. When a MOSFET is provided in the cell region CE, in the portion of the cell region CE where the MOSFET is provided, n + Region 121a of type n is disposed on the lower electrode 110 and connected to the lower electrode 110. When an IGBT is disposed in the cell region CE, a p-type semiconductor layer is disposed on the lower electrode 110 in the portion of the cell region CE where the IGBT is disposed. + At least a portion of region 121a of the p-type is disposed on the p-type semiconductor layer.

[0039] n － n + n － n + n

[0040] n + n － n + n － n + n Figure 3 n

[0041] n Figure 2 n － n + n + n Figure 3 n

[0042] n

[0043] n Figure 2 n

[0044] Figure 4 is a plan view showing the semiconductor portion and the insulating film of the semiconductor device according to the present embodiment.

[0045] wherein, in Figure 4 , for easy understanding of the explanation, the region in which the insulating film 130 is provided in the termination region EN is represented by a pattern of dots.

[0046] The insulating film 130 is not particularly limited, and may be made of insulating materials such as oxides like silicon oxide or nitrides like silicon nitrides. In this embodiment, the insulating film 130, viewed from above, is a roughly rectangular ring with chamfered corners. However, the shape of the insulating film is not limited to the shape described above.

[0047] In this embodiment, the inner periphery 130e1 of the insulating film 130, when viewed from above, is located closer to the outer periphery 122e of the p-type semiconductor layer 122. The outer periphery 130e2 of the insulating film 130, when viewed from above, is located closer to the inner periphery 122e of the p-type semiconductor layer 122. + The inner periphery 121ce of the blocking region 121c is located on the outer side. Therefore, in this embodiment, the insulating film 130 overlaps with the outer periphery of the p-type semiconductor layer 122 when viewed from above, and partially overlaps with the portion of the n-type semiconductor layer 121 located on the outer side of the p-type semiconductor layer 122.

[0048] like Figure 2 As shown, an upper electrode 140, an EQPR electrode 150, and a plurality of intermediate electrodes 161 and 162 are provided on the insulating film 130.

[0049] Figure 5 This is a top view showing the semiconductor part, insulating film, upper electrode, EQPR electrode, and multiple intermediate electrodes of the semiconductor device according to this embodiment.

[0050] Among them, Figure 5 In the terminal region EN, the areas where the upper electrode 140, the EQPR electrode 150, and multiple intermediate electrodes 161 and 162 are provided are represented by different dot patterns. The upper electrode 140, the EQPR electrode 150, and the multiple intermediate electrodes 161 and 162 will be described below.

[0051] First, the upper electrode 140 will be explained.

[0052] The upper electrode 140 is not particularly limited, and can be made of a metallic material such as aluminum (Al). Figure 2 As shown, the upper electrode 140 is disposed from the cell region CE to the terminal region EN. Specifically, the upper electrode 140 covers a portion of the upper surface of the p-type semiconductor layer 122, the inner peripheral surface of the insulating film 130, and the inner region of the upper surface of the insulating film 130. The upper electrode 140 is connected to the p-type semiconductor layer 122, thereby being electrically connected to the p-type semiconductor layer 122.

[0053] When a diode is provided in the cell region CE, the upper electrode 140 can function as the anode electrode of the diode in the cell region CE. Furthermore, when a MOSFET is provided in the cell region CE, the upper electrode 140 can function as the source electrode of the MOSFET in the cell region CE. Additionally, when an IGBT is provided in the cell region CE, the upper electrode 140 can function as the emitter electrode of the IGBT in the cell region CE.

[0054] The shape of the outer periphery 140e of the upper electrode 140 as viewed from above is as follows: Figure 5 As shown in this embodiment, the corners are chamfered to form a roughly rectangular shape. When viewed from above, the outer periphery 140e of the upper electrode 140 is located outside the inner periphery 130e1 of the insulating film 130 and the outer periphery 122e of the p-type semiconductor layer 122.

[0055] Next, the EQPR electrode 150 will be explained.

[0056] The EQPR electrode 150 is not particularly limited and may be made of a metallic material such as aluminum (Al). Viewed from above, the EQPR electrode 150 is positioned further outward than the upper electrode 140 and is separate from it. The EQPR electrode 150 is as follows... Figure 2 As shown, the outer region of the upper surface of the insulating film 130, the outer peripheral surface of the insulating film 130, and n + The area exposed from the insulating film 130 on the upper surface of the blocking region 121c of the type. EQPR electrode 150 and n + The blocking region 121c of type n is connected to n. + Type 121c blocking region electrical connection.

[0057] The shape of the EQPR electrode 150 as viewed from above is as follows: Figure 5 As shown, in this embodiment, it is a roughly rectangular ring. The outer periphery of the EQPR electrode 150, viewed from above, roughly coincides with the outer periphery 120e of the semiconductor portion 120. The inner periphery 150e of the EQPR electrode 150, viewed from above, is located between the outer periphery 130e2 and n of the insulating film 130. + The inner periphery 121ce of the type of blocking region 121c is located on the inner side.

[0058] The intermediate electrodes 161 and 162 are not particularly limited, and may be made of a metallic material such as aluminum (Al). Multiple intermediate electrodes 161 and 162 are disposed on the insulating film 130. The multiple intermediate electrodes 161 and 162 are located between the upper electrode 140 and the EQPR electrode 150. Specifically, viewed from above, the intermediate electrode 161 is positioned outside the upper electrode 140 and is separate from it. Viewed from above, the intermediate electrode 162 is positioned outside the intermediate electrode 161 and inside the EQPR electrode 150, and is separate from both the intermediate electrode 161 and the EQPR electrode 150.

[0059] Thus, when viewed from above, the upper electrode 140, the plurality of intermediate electrodes 161, 162, and the EQPR electrode 150 are arranged in a direction from the center C of the semiconductor section 120 toward the outer periphery 120e, and are separated from each other. In this embodiment, the upper electrode 140 and the intermediate electrode 161 correspond to an adjacent pair of second electrodes. Similarly, in this embodiment, the intermediate electrode 161 and the intermediate electrode 162 also correspond to an adjacent pair of second electrodes. Likewise, in this embodiment, the intermediate electrode 162 and the EQPR electrode 150 also correspond to an adjacent pair of second electrodes.

[0060] In this embodiment, the intermediate electrodes 161 and 162, viewed from above, are roughly rectangular rings with chamfered corners. In this embodiment, two intermediate electrodes 161 and 162 are provided to the semiconductor device 100, but the number of intermediate electrodes provided to the semiconductor device can be one, or even three or more. Alternatively, intermediate electrodes may not be provided to the semiconductor device. In this case, the upper electrode and the EQPR electrode correspond to an adjacent pair of second electrodes.

[0061] Therefore, in this embodiment, as Figure 2 as well as Figure 5 As shown, an annular gap S1 is provided between the upper electrode 140 and the intermediate electrode 161. Additionally, an annular gap S2 is provided between the two intermediate electrodes 161 and 162. Furthermore, an annular gap S3 is provided between the intermediate electrode 162 and the EQPR electrode 150.

[0062] like Figure 2 As shown, a plurality of first floating electrodes 171, 173, 175 and a plurality of second floating electrodes 172, 174, 176 are provided in the insulating film 130.

[0063] Figure 6 This is a top view showing the area in the semiconductor device according to this embodiment where each floating electrode is provided.

[0064] Among them, Figure 6In the terminal region EN, the regions where the first floating electrodes 171, 173, and 175 are located and the regions where the second floating electrodes 172, 174, and 176 are located are represented by patterns of different diagonal lines.

[0065] Each floating electrode 171-176 is not particularly limited and is made of conductive materials such as polycrystalline silicon containing impurities or metallic materials. Viewed from above, each floating electrode 171-176 is a roughly rectangular ring with chamfered corners. Multiple floating electrodes 171-176 are arranged as follows... Figure 2 They are separated from each other. Each floating electrode 171 to 176 is entirely covered by an insulating film 130.

[0066] The positions of each floating electrode 171 to 176 are described in detail below.

[0067] First, the position of the first floating electrode 171 will be explained.

[0068] like Figure 2 as well as Figure 6 As shown, when viewed from above, the first floating electrode 171 overlaps with the gap S1 and the upper electrode 140. The first floating electrode 171 is positioned opposite the upper electrode 140 through the insulating film 130. In this specification, "when viewed from above, A and B overlap" means that when A and B are properly viewed from above, at least a portion of A overlaps with at least a portion of B.

[0069] like Figure 6 As shown, when viewed from above, the inner periphery 171e1 of the first floating electrode 171 is located outside the inner periphery 130e1 of the insulating film 130 and inside the outer periphery 122e of the p-type semiconductor layer 122. In this embodiment, when viewed from above, the outer periphery 171e2 of the first floating electrode 171 is located within the gap S1.

[0070] Next, the position of the second floating electrode 172 will be explained.

[0071] like Figure 2 as well as Figure 6 As shown, when viewed from above, the second floating electrode 172 overlaps with the first floating electrode 171 within the gap S1. Furthermore, when viewed from above, the second floating electrode 172 overlaps with the intermediate electrode 161. The second floating electrode 172 is positioned opposite the intermediate electrode 161 through the insulating film 130.

[0072] like Figure 6As shown, when viewed from above, the inner periphery 172e1 of the second floating electrode 172 is located inside the outer periphery 140e of the upper electrode 140. When viewed from above, the outer periphery 172e2 of the second floating electrode 172 is located outside the inner periphery 161e1 of the intermediate electrode 161.

[0073] Next, the position of the first floating electrode 173 will be explained.

[0074] When viewed from above, the first floating electrode 173 is located outside the floating electrodes 171 and 172. For example... Figure 2 as well as Figure 6 As shown, when viewed from above, the first floating electrode 173 overlaps with the gap S2 and the intermediate electrode 161. The first floating electrode 173 is positioned opposite the intermediate electrode 161 through the insulating film 130.

[0075] like Figure 6 As shown, when viewed from above, the inner periphery 173e1 of the first floating electrode 173 is located outside the outer periphery 172e2 of the second floating electrode 172 and inside the outer periphery 161e2 of the intermediate electrode 161. In this embodiment, when viewed from above, the outer periphery 173e2 of the first floating electrode 173 is located within the gap S2.

[0076] Next, the position of the second floating electrode 174 will be explained.

[0077] like Figure 2 as well as Figure 6 As shown, when viewed from above, the second floating electrode 174 overlaps with the first floating electrode 173 within the gap S2. Furthermore, when viewed from above, the second floating electrode 174 overlaps with the intermediate electrode 162. The second floating electrode 174 is positioned opposite the intermediate electrode 162 through the insulating film 130.

[0078] like Figure 6 As shown, when viewed from above, the inner periphery 174e1 of the second floating electrode 174 is located inside the outer periphery 161e2 of the intermediate electrode 161. When viewed from above, the outer periphery 174e2 of the second floating electrode 174 is located outside the inner periphery 162e1 of the intermediate electrode 162.

[0079] Next, the position of the first floating electrode 175 will be explained.

[0080] like Figure 2 as well as Figure 6 As shown, when viewed from above, the first floating electrode 175 is located outside the floating electrodes 173 and 174. When viewed from above, the first floating electrode 175 overlaps with the gap S3 and the intermediate electrode 162. The first floating electrode 175 is positioned opposite the intermediate electrode 162 through the insulating film 130.

[0081] When viewed from above, the inner periphery 175e1 of the first floating electrode 175 is located outside the outer periphery 174e2 of the second floating electrode 174 and inside the outer periphery 162e2 of the intermediate electrode 162. In this embodiment, when viewed from above, the outer periphery 175e2 of the first floating electrode 175 is located within the gap S3.

[0082] Next, the position of the second floating electrode 176 will be explained.

[0083] like Figure 6 as well as Figure 2 As shown, when viewed from above, the second floating electrode 176 overlaps with the floating electrode 175 within the gap S3. Furthermore, when viewed from above, the second floating electrode 176 overlaps with the EQPR electrode 150. The second floating electrode 176 is positioned opposite the EQPR electrode 150 through the insulating film 130.

[0084] like Figure 7 As shown, when viewed from above, the inner periphery 176e1 of the second floating electrode 176 is located inside the outer periphery 162e2 of the intermediate electrode 162. When viewed from above, the outer periphery 176e2 of the second floating electrode 176 is located outside the inner periphery 150e of the EQPR electrode 150 and outside the inner periphery 150e of the EQPR electrode 150. + The inner periphery 121ce of the type of blocking region 121c is located on the inner side.

[0085] The positions of the outer and inner circumferences of each floating electrode 171 to 176 have been described above, but the positions of the outer and inner circumferences of each floating electrode 171 to 176 are not limited to the positions described above.

[0086] Next, the specific shapes of the floating electrodes 171 to 176 will be described.

[0087] In this embodiment, such as Figure 8 As shown, the first floating electrode 171 has a first portion P1 located inside the second floating electrode 172 and adjacent to the second floating electrode 172 in the direction from the center C of the semiconductor portion 120 toward the outer periphery 120e, a second portion P2 located above the second floating electrode 172, and a third portion P3 located between the first portion P1 and the second portion P2 and connected to the first portion P1 and the second portion P2.

[0088] In this embodiment, the first portion P1 and the second portion P2 each extend in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e. In this embodiment, the third portion P3 extends in the Z direction from an outer side end portion of the first portion P1 toward an inner side end portion of the second portion P2. A portion of the second portion P2 overlaps the gap S1 when viewed from above. The first portion P1, another portion of the second portion P2, and the third portion P3 overlap the upper electrode 140 when viewed from above. The other first floating electrodes 173, 175 each have the first portion P1, the second portion P2, and the third portion P3 similarly to the first floating electrode 171.

[0089] In this embodiment, the shape of each of the second floating electrodes 172, 174, 176 is a flat plate shape extending in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e.

[0090] However, the shape of the floating electrodes 171, 172, 173, 174, 175, 176 is not limited to the above-described shape.

[0091] Next, the operation of the termination region EN of the semiconductor device 100 will be described.

[0092] Figure 7 is a schematic view showing the operation of the termination region of the semiconductor device according to the present embodiment.

[0093] In the termination region EN, when a voltage in which the potential of the lower electrode 110 is higher than the potential of the upper electrode 140, that is, a voltage of reverse bias is applied between the lower electrode 110 and the upper electrode 140, a depletion layer extends from the p-type semiconductor layer 122 toward the outer peripheral surface of the semiconductor portion 120. In a case where the outer peripheral surface of the semiconductor portion 120 is a surface formed by cutting or the like, the outer peripheral surface has a defect. Therefore, the vicinity of the outer peripheral surface of the semiconductor portion 120 can not be able to withstand a strong electric field generated by the depletion layer. In this embodiment, the EQPR electrode 150 and the lower electrode 110 are electrically connected through the n + type region 121a, the n － type region 122b, and the n + type blocking region 121c. Therefore, the EQPR electrode 150 and the lower electrode 110 are substantially at the same potential. Thus, it is possible to suppress the depletion layer from reaching the outer peripheral surface of the semiconductor portion 120.

[0094] In addition, an electric field is generated between the p-type semiconductor layer 122 and the n + type blocking region 121c due to the depletion layer extending from the p-type semiconductor layer 122 toward the outer peripheral surface of the semiconductor portion 120. When the electric field is generated, the p-type semiconductor layer 122 and the n +In the case where there is a position where the potential sharply changes between the blocking regions 121c of the same type, that is, in the case where there is a position where equipotential lines are dense, avalanche breakdown can occur at the position.

[0095] Figure 7 is a cross-sectional view showing a terminal region of the semiconductor device according to the reference example.

[0096] The semiconductor device 800 according to the reference example differs from the semiconductor device 100 according to the present embodiment in that the floating electrodes 171 to 176 and the intermediate electrodes 161 and 162 are not provided, and a semi-insulating film 890 is provided in the gap between the upper electrode 140 and the EQPR electrode 150. The semi-insulating film 890 is, for example, a silicon nitride film to which hydrogen is added or the like.

[0097] In the semiconductor device 800 according to the reference example, the semi-insulating film 890 having uniform resistance or the like is provided, and it is expected that the potential is gradually changed from the upper electrode 140 toward the EQPR electrode 150 by the semi-insulating film 890. Thus, in the semiconductor portion 120, the portion between the upper electrode 140 and the EQPR electrode 150 can be suppressed from generating a position where the potential sharply changes. However, in reality, there is a case where the resistance or the like of the semi-insulating film 890 is not uniform, and the above-described effect cannot be sufficiently obtained. In addition, when the semi-insulating film is not provided in the cell region CE, a new dedicated device can be required in order to form the semi-insulating film 890 in the terminal region EN.

[0098] On the contrary, in the present embodiment, as shown in Figure 8 , the upper electrode 140 is capacitively coupled with the first floating electrode 171, the first floating electrode 171 is capacitively coupled with the second floating electrode 172, and the second floating electrode 172 is capacitively coupled with the intermediate electrode 161. Among them, in Figure 7 , in order to easily understand the description, the case where two electrodes are capacitively coupled is represented by connecting the circuit symbols of the two electrodes with a capacitor. Here, "the electrode A is capacitively coupled with the electrode B" means that the electrode A and the electrode B are opposed with an insulator therebetween, and the electrode A, the electrode B, and the insulator therebetween function as a capacitor. In this way, a plurality of capacitors are interposed between the upper electrode 140 and the intermediate electrode 161. Thus, the potential can be changed in steps from the upper electrode 140 to the intermediate electrode 161.

[0099] Similarly, in the present embodiment, the intermediate electrode 161 is capacitively coupled with the first floating electrode 173, the first floating electrode 173 is capacitively coupled with the second floating electrode 174, and the second floating electrode 174 is capacitively coupled with the intermediate electrode 162. Thus, the potential can be changed in steps from the intermediate electrode 161 to the intermediate electrode 162.

[0100] Also, in the present embodiment, the intermediate electrode 162 is capacitively coupled with the first floating electrode 175, the first floating electrode 175 is capacitively coupled with the second floating electrode 176, and the second floating electrode 176 is capacitively coupled with the EQPR electrode 150. Thus, the potential can be stepped between the intermediate electrode 162 and the EQPR electrode 150.

[0101] Further, the plurality of intermediate electrodes 161, 162 are floating electrodes capable of taking an arbitrary potential between the potential of the upper electrode 140 and the potential of the EQPR electrode 150. Thus, the potential can be stepped between the upper electrode 140 and the EQPR electrode 150. As a result, in the semiconductor portion 120, the portion between the upper electrode 140 and the EQPR electrode 150 can be suppressed from generating a position where the potential sharply changes. Further, since the intermediate electrodes 161, 162 and the floating electrodes 171 to 176 are composed of a general material used in the cell region CE, there is no need to prepare a dedicated device for forming these.

[0102] Further, the upper electrode 140 and the intermediate electrode 161, the intermediate electrode 161 and the intermediate electrode 162, and the intermediate electrode 162 and the EQPR electrode 150 can also be capacitively coupled. Further, the first floating electrode 171 and the intermediate electrode 161, the first floating electrode 173 and the intermediate electrode 162, and the first floating electrode 175 and the EQPR electrode 150 can also be capacitively coupled. Further, the p-type semiconductor layer 122 and the first floating electrode 171 can also be capacitively coupled.

[0103] Further, as shown in FIG. 8, in a case where the semiconductor device 800 related to the reference example is mounted to a lead frame or a substrate or the like and is sealed by a sealing member composed of a resin material or the like, sometimes the cation contained in the sealing member is attracted to the upper electrode 140 to generate a positive charge Ql in the vicinity of the surface of the semi-insulating film 890. Also, sometimes the anion contained in the sealing member is attracted to the EQPR electrode 150 to generate a negative charge Q2 in the vicinity of the surface of the semi-insulating film 890. Figure 9 When the charges Ql, Q2 are thus generated in the vicinity of the surface of the semi-insulating film 890, it is expected that the generation of a negative charge Q3 in the upper layer portion of the semiconductor portion 120 due to the influence of the positive charge Ql and the generation of a positive charge Q4 in the upper layer portion of the semiconductor portion 120 due to the influence of the negative charge Q2 are suppressed by the semi-insulating film 890. However, there is a case where the characteristics of the semi-insulating film 890, such as the resistance, are not uniform in practice and the above-described effects cannot be sufficiently obtained.

[0104] In contrast to this, in the present embodiment, as shown in FIG. 1, the intermediate electrode 162 is capacitively coupled with the first floating electrode 175, the first floating electrode 175 is capacitively coupled with the second floating electrode 176, and the second floating electrode 176 is capacitively coupled with the EQPR electrode 150. Thus, the potential can be stepped between the intermediate electrode 162 and the EQPR electrode 150.

[0105] Figure 10 ​As shown, a plurality of intermediate electrodes 161, 162 are provided between the upper electrode 140 and the EQPR electrode 150. In addition, two floating electrodes 171, 172 are provided in a superimposed manner under the gap SI, two floating electrodes 173, 174 are provided in a superimposed manner under the gap S2, and two floating electrodes 175, 176 are provided in a superimposed manner under the gap S3. Thus, by the plurality of intermediate electrodes 161, 162 and the mutually superimposed floating electrodes 171 to 176 functioning as shields, it is possible to suppress the generation of charges Q3, Q4 in the upper layer portion of the semiconductor portion 120 due to the influence of the charges Ql, Q2.

[0106] Next, the effects of the present embodiment will be described.

[0107] In the semiconductor device 100 related to the present embodiment, the insulating film 130 is provided on the semiconductor portion 120 in the terminal region EN. The upper electrode 140, the plurality of intermediate electrodes 161, 162, and the EQPR electrode 150 are provided on the insulating film 130. When viewed from above, these electrodes 140, 161, 162, 150 are arranged in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e and are separated from each other.

[0108] In addition, the first floating electrode 171 and the second floating electrode 172 are provided in the insulating film 130. When viewed from above, the first floating electrode 171 overlaps the gap SI of the adjacent pair of electrodes 140, 161 among the electrodes 140, 161, 162, 150 and opposes the electrode 140 of the adjacent pair of electrodes 140, 161 across the insulating film 130. The second floating electrode 172 is provided in the insulating film 130 in a manner separated from the first floating electrode 171 and overlaps the first floating electrode 171 within the gap SI when viewed from above. The second floating electrode 172 opposes the electrode 161 of the adjacent pair of electrodes 140, 161 across the insulating film 130. The portion of the second floating electrode 172 overlapping the first floating electrode 171 is located below the portion of the first floating electrode 171 overlapping the gap SI.

[0109] Therefore, the electrode 140 of one of the adjacent pair of electrodes 140, 161 is capacitively coupled with the first floating electrode 171, the first floating electrode 171 is capacitively coupled with the second floating electrode 172, and the second floating electrode 172 is capacitively coupled with the electrode 161 of the other of the adjacent pair of electrodes 140, 161. Thus, in the terminal region EN, the potential of the portion of the semiconductor portion 120 between the adjacent pair of electrodes 140, 161 can be made to change in steps. As a result, in the portion of the semiconductor portion 120 between the adjacent pair of electrodes 140, 161, the occurrence of a position where the potential changes sharply can be suppressed. Thus, since the occurrence of avalanche breakdown can be suppressed, the withstand voltage of the semiconductor device 100 can be increased. The same effect can be obtained by the other first floating electrodes 173, 175 and the other second floating electrodes 174, 176.

[0110] In addition, by the first floating electrode 171 and the second floating electrode 172 overlapping each other below the gap S1, the first floating electrode 171 and the second floating electrode 172 function as a shield against the charges Q1, Q2 generated in the vicinity of the surface of the semiconductor device 100, and the generation of charges Q3, Q4 in the upper layer portion of the semiconductor portion 120 can be suppressed. The same effect can be obtained by the other first floating electrodes 173, 175 and the other second floating electrodes 174, 176.

[0111] As described above, a semiconductor device 100 with high reliability can be realized.

[0112] In addition, in the present embodiment, the first floating electrode 171 overlaps the electrode 140 of the adjacent pair of electrodes 140, 161 located on the inner side when viewed from above. In addition, the second floating electrode 172 overlaps the electrode 161 of the adjacent pair of electrodes 140, 161 located on the outer side when viewed from above. Therefore, in the terminal region EN of the semiconductor portion 120, the equipotential lines are easily dispersed. The same effect can be obtained by the other first floating electrodes 173, 175 and the other second floating electrodes 174, 176.

[0113] In addition, in the present embodiment, the first floating electrode 171 has a first portion P1 located on the inner side than the second floating electrode 172 and adjacent to the second floating electrode 172 in the direction from the center C toward the outer periphery 120e of the semiconductor portion 120, a second portion P2 located above the second floating electrode 172, and a third portion P3 located between the first portion P1 and the second portion P2 and connected to the first portion P1 and the second portion P2. Therefore, in the terminal region EN of the semiconductor portion 120, the equipotential lines are easily dispersed. The same effect can be obtained by the other first floating electrodes 173, 175 and the other second floating electrodes 174, 176.

[0114] In addition, in the present embodiment, the semiconductor portion 120 has an n-type semiconductor layer 121 provided on the lower electrode 110, and a p-type semiconductor layer 122 provided on an upper layer portion of the n-type semiconductor layer 121 and located inward of the outer periphery of the n-type semiconductor layer 121. When viewed from above, the insulating film 130 overlaps with an outer periphery portion of the p-type semiconductor layer 122, and overlaps with a portion of the n-type semiconductor layer 121 located outward of the p-type semiconductor layer 122. Furthermore, the innermost electrode 140 of the plurality of electrodes 140, 161, 162, 150 is connected to a portion of the p-type semiconductor layer 122 located inward of the insulating film 130. In addition, the outermost electrode 150 of the plurality of electrodes 140, 161, 162, 150 is connected to a portion of the n-type semiconductor layer 121 located outward of the insulating film 130. Thus, the EQPR electrode 150, the outer periphery portion of the n-type semiconductor layer 121, and the lower electrode 110 are made substantially equipotential, and it is possible to suppress the depletion layer from reaching the outer periphery surface of the semiconductor portion 120. As a result, it is possible to increase the withstand voltage of the semiconductor device 100.

[0115] In addition, in the present embodiment, the n-type semiconductor layer 121 has an n + type region 121a provided on the lower electrode 110, an n + type region 121b having a lower impurity concentration than the n + type region 121a provided on the n － type region 121a, and an n － type blocking region 121c provided in an outer periphery portion of an upper layer portion of the n － type region 121b and having a higher impurity concentration than the n + type region 121b. Furthermore, the outermost electrode 150 is connected to the n + type blocking region 121c. Thus, the EQPR electrode 150, the outer periphery portion of the n-type semiconductor layer 121, and the lower electrode 110 are made substantially equipotential, and it is possible to suppress the depletion layer from reaching the outer periphery surface of the semiconductor portion 120.

[0116] <Second Embodiment>

[0117] Next, the second embodiment will be described.

[0118] Figure 11 is a cross-sectional view showing a semiconductor device according to the present embodiment.

[0119] The configuration of the terminal region EN of the semiconductor device 200 according to the present embodiment is different from the configuration of the terminal region EN of the semiconductor device 100 according to the first embodiment, except for the lower electrode 110 and the semiconductor portion 120.

[0120] Further, in the following description, only the points different from the first embodiment will be described in principle. The matters described below are the same as those of the first embodiment, except for the following.

[0121] The shape of the insulating film 230 according to the present embodiment is different from the shape of the insulating film 130 according to the first embodiment. In the first embodiment, the upper surface of the insulating film 130 is a flat surface and is parallel to the X direction and the Y direction. In contrast, in the present embodiment, the region of the upper surface of the insulating film 230 in which the first floating electrode 271 and the plurality of second floating electrodes 272 are arranged directly below is raised upward.

[0122] Further, the shapes of the upper electrode 240 and the EQPR electrode 250 according to the present embodiment are different from the shapes of the upper electrode 140 and the EQPR electrode 150 according to the first embodiment. In the first embodiment, the shapes of the portions of the upper electrode 140 and the EQPR electrode 150 that are located on the insulating film 130 are flat plate shapes. In contrast, the upper electrode 240 and the EQPR electrode 250 according to the present embodiment are placed on the portions of the upper surface of the insulating film 230 that are raised upward. Therefore, the outer end of the upper electrode 240 and the inner end of the EQPR electrode 250 are curved along the upper surface of the insulating film 230.

[0123] Further, in the first embodiment, an example in which two intermediate electrodes 161 and 162 are provided in the semiconductor device 100 is described, but in the present embodiment, six intermediate electrodes 260 are provided in the semiconductor device 200. In this way, the number of intermediate electrodes provided in the semiconductor device is not particularly limited. The number of intermediate electrodes provided in the semiconductor device can be set, for example, in accordance with the required withstand voltage of the semiconductor device. It is preferable that the greater the required withstand voltage of the semiconductor device, the greater the number of intermediate electrodes provided in the semiconductor device.

[0124] The plurality of intermediate electrodes 260 are provided between the upper electrode 240 and the EQPR electrode 250 on the insulating film 230. When viewed from above, the plurality of intermediate electrodes 260 are arranged in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e and are separated from each other. Further, the innermost intermediate electrode 260 among the plurality of intermediate electrodes 260 is separated from the upper electrode 240. Further, the outermost intermediate electrode 260 among the plurality of intermediate electrodes 260 is separated from the EQPR electrode 250.

[0125] Therefore, a gap S21 is formed between the upper electrode 240 and the innermost intermediate electrode 260. In addition, a gap S22 is formed between the adjacent intermediate electrodes 260. In addition, a gap S23 is formed between the EQPR electrode 250 and the outermost intermediate electrode 260.

[0126] In addition, in the first embodiment, the shape of each intermediate electrode 161, 162 is flat plate shape, but in the present embodiment, the shape of each intermediate electrode 260 is a shape in which the central portion is recessed downward along the upper surface of the insulating film 230. In this way, the shape of each intermediate electrode is not particularly limited as long as a gap is formed between the upper electrode, the other intermediate electrode, or the EQPR electrode.

[0127] In addition, in the present embodiment, a first floating electrode 271 and a second floating electrode 272 are provided directly below each gap S21, S22, S23. In the present embodiment, since the total number of gaps S21, S22, S23 is seven, seven first floating electrodes 271 are also provided in the semiconductor device 200. Similarly, seven second floating electrodes 172 are also provided in the semiconductor device 200. In this way, the number of gaps formed on the insulating film in the termination region is not particularly limited as long as it is one or more. It is preferable that the number of first floating electrodes and the number of second floating electrodes corresponding to the number of gaps be provided in the termination region.

[0128] As in the first embodiment, each floating electrode 271, 272 is composed of a semiconductor material such as polysilicon or a metal material. The shape of each floating electrode 271, 272 as viewed from above is a substantially rectangular ring shape with the corners chamfered, as in the first embodiment. The plurality of floating electrodes 271, 272 are separated from each other. The entire floating electrode 271, 272 is covered with the insulating film 230.

[0129] Hereinafter, the configuration of the first floating electrode 271 and the second floating electrode 272 provided directly below the gap S21 between the upper electrode 240 and the innermost intermediate electrode 260 among the plurality of first floating electrodes 271 and the plurality of second floating electrodes 272 will be described. Since the other first floating electrodes 271 and the other second floating electrodes 272 are configured similarly, the description will be omitted.

[0130] The first floating electrode 271 overlaps the gap S21 and the upper electrode 240 when viewed from above. The first floating electrode 271 faces the upper electrode 240 with the insulating film 230 interposed therebetween. In the first embodiment, the inner periphery 171e1 of the first floating electrode 171 is located inward of the outer periphery 122e of the p-type semiconductor layer 122, but in the present embodiment, the inner periphery 271e1 of the first floating electrode 271 is located outward of the outer periphery 122e of the p-type semiconductor layer 122. In this way, the position of the inner periphery 271e1 is not particularly limited as long as it is located outward of the inner periphery of the insulating film 230 and inward of the outer periphery of the upper electrode 240.

[0131] In the present embodiment, the first floating electrode 271 has a first portion P21 located inward of the second floating electrode 272 and adjacent to the second floating electrode 272 in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e, a second portion P22 located above the second floating electrode 272, and a third portion P23 located between the first portion P21 and the second portion P22 and connecting the first portion P21 and the second portion P22. In the first embodiment, the third portion P3 extends in the Z direction, but in the present embodiment, the third portion P23 extends in a direction inclined with respect to the Z direction. The extension direction of the third portion is not particularly limited as long as it can connect the first portion and the second portion.

[0132] The second floating electrode 272 overlaps the first floating electrode 271 within the gap S21 when viewed from above. In addition, the second floating electrode 272 overlaps the intermediate electrode 260 when viewed from above. The second floating electrode 272 faces the intermediate electrode 260 with the insulating film 230 interposed therebetween.

[0133] In the first embodiment, the inner periphery 172e1 of the second floating electrode 172 is located inward of the outer periphery 140e of the upper electrode 140 when viewed from above, but in the present embodiment, the inner periphery 272e1 of the second floating electrode 272 is located outward of the outer periphery 240e of the upper electrode 240 when viewed from above. In this way, the position of the inner periphery 272e1 is not particularly limited as long as it is located inward of the inner periphery of the intermediate electrode 260 and the outer periphery of the first floating electrode 271 when viewed from above.

[0134] In the semiconductor device 200 related to the present embodiment, one of the pair of adjacent electrodes among the plurality of electrodes 240, 260, 250 is capacitively coupled to the first floating electrode 271. In addition, the first floating electrode 271 is capacitively coupled to the second floating electrode 272. In addition, the second floating electrode 272 is capacitively coupled to the other of the pair of adjacent electrodes.

[0135] Furthermore, the semiconductor device 200 according to this embodiment differs from the first embodiment in that a protective film 280 is provided in the upper electrode 240, the EQPR electrode 250, the plurality of intermediate electrodes 260, and the insulating film 230 to cover the portions exposed from these electrodes 240, 250, and 260. Thus, a protective film 280 can also be provided in the semiconductor device 200. The protective film 280 is made of an insulating material such as resin.

[0136] Figure 12 This is a cross-sectional view of the semiconductor device involved in the reference example.

[0137] Figure 10 This is a graph showing the simulation results of the relationship between the withstand voltage and charge of the semiconductor device according to this embodiment and the semiconductor device according to the reference example, with the horizontal axis representing the charge generated on the surface of the protective film and the vertical axis representing the withstand voltage.

[0138] Figure 12 This is a simulation result of the equipotential lines in the semiconductor device according to this embodiment, showing the state in which positive and negative charges are generated on the surface of the protective film.

[0139] like Figure 12 As shown, the semiconductor device 900 in the reference example is similar to the semiconductor device 200 in this embodiment, including a lower electrode 110, a semiconductor portion 120, an insulating film 930, an upper electrode 940, an EQPR electrode 950, and a protective film 980. The difference between the semiconductor device 900 in the reference example and the semiconductor device 200 in this embodiment is that no intermediate electrode is provided in the gap between the upper electrode 940 and the EQPR electrode 950 on the insulating film 930, and no first floating electrode and second floating electrode are provided in the insulating film 930.

[0140] In this embodiment, as described above, one electrode of an adjacent pair of electrodes among the plurality of electrodes 240, 260, and 250 is capacitively coupled to the first floating electrode 271, the first floating electrode 271 is capacitively coupled to the second floating electrode 272, and the second floating electrode 272 is capacitively coupled to the other electrode of the adjacent pair. Therefore, as Figure 11 As shown, a potential gradient can be achieved between the upper electrode 240 and the EQPR electrode 250. Specifically, as... Figure 12As shown, the equipotential lines within the gap S21 are dispersed between the upper electrode 240 and the first floating electrode 271, between the first floating electrode 271 and the second floating electrode 272, and between the second floating electrode 272 and the middle electrode 260. In this way, the occurrence of a position where the equipotential lines are concentrated, i.e., where the potential sharply changes, in the terminal region EN of the semiconductor portion 120 can be suppressed, and thus the occurrence of avalanche breakdown can be suppressed. As a result, the withstand voltage of the semiconductor device 200 can be increased. Therefore, as shown, the withstand voltage of the semiconductor device 200 according to the present embodiment is higher than that of the semiconductor device 900 according to the reference example. Figure 10

[0141] In particular, in the present embodiment, as shown, the first floating electrode 271 has a first portion P21 located inward of the second floating electrode 272, a second portion P22 located above the second floating electrode 272, and a third portion P23 connecting the first portion and the second portion. Therefore, the equipotential lines within the gap S21 are dispersed between the upper electrode 240 and the first floating electrode 271, between the first floating electrode 271 and the second floating electrode 272, and between the second floating electrode 272 and the middle electrode 260, and extend from the gap S21 through the semiconductor portion 120 toward the center C side of the semiconductor portion 120. Therefore, within the semiconductor portion 120, the equipotential lines are easily dispersed. The same applies to the first floating electrode 271 and the second floating electrode 272 directly below the other gaps S22, S23. Figure 11

[0142] In addition, as shown, in the semiconductor device 200 according to the reference example, the withstand voltage in the case where positive charges Q21 and negative charges Q22 are generated on the surface of the protective film 980 is lower than that in the case where no positive charges Q21 and negative charges Q22 are generated on the surface of the protective film 980. In addition, the larger the absolute values of the positive charges Q21 and the negative charges Q22, the lower the withstand voltage. Figure 10 Figure 12 The same tendency is observed in the semiconductor device 200 according to the present embodiment. In the semiconductor device 900 according to the reference example, as shown, no member that shields the effects of the charges Q21, Q22 on the semiconductor portion 120 is provided between the upper electrode 940 and the EQPR electrode 950. In contrast, as shown, in the semiconductor device 200 according to the present embodiment, the first floating electrode 271 is provided between the upper electrode 240 and the EQPR electrode 250. Therefore, the effects of the charges Q21, Q22 on the semiconductor portion 120 are shielded by the first floating electrode 271.

[0143] Figure 11 ​ ​​​​​As shown, in the semiconductor device 200 according to the present embodiment, a plurality of intermediate electrodes 260 are provided between the upper electrode 940 and the EQPR electrode 950, and the first floating electrode 171 and the second floating electrode 172 overlap each other just below each gap S21, S22, S23. Thus, in the semiconductor device 200 according to the present embodiment, the influence of the charges Q21, Q22 on the semiconductor portion 120 can be shielded. Thus, as shown in FIG. 10, in the semiconductor device 200 according to the present embodiment, the potential of the upper electrode 940 can be prevented from being lowered by the charges Q21, Q22. ​ As shown, in the semiconductor device 200 according to the present embodiment, the amount of decrease AV21 in the withstand voltage when the charges are changed by the prescribed amount AQ is smaller than the amount of decrease AV22 in the withstand voltage when the charges are changed by the prescribed amount AQ in the semiconductor device 900 according to the reference example. That is, the present embodiment is less likely to cause a decrease in the withstand voltage due to the charges Q21, Q22 than the reference example.

[0144] As described above, in the semiconductor device 200 according to the present embodiment, the potential can be stepped between one of a pair of adjacent electrodes among the plurality of electrodes 240, 260, 250 and the other electrode. Thus, since the avalanche breakdown can be suppressed, the withstand voltage of the semiconductor device 200 can be increased.

[0145] In addition, in the present embodiment, the first floating electrode 171 and the second floating electrode 172 that overlap each other just below the gaps S21, S22, S23 function to shield the charges Q21, Q22 generated on the surface of the semiconductor device 200. Thus, the generation of the negative charge Q3 and the positive charge Q4 in the upper layer portion of the semiconductor portion 120 can be suppressed.

[0146] As described above, the semiconductor device 200 with high reliability can be implemented.

[0147] The present application has been described with reference to several embodiments, but these embodiments are merely examples and are not intended to limit the scope of the application. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof, as well as the application encompassed within the scope and spirit of the application, are included in the technical scope of the application described in the claims.

Claims

1. A semiconductor device comprising a unit region and a terminal region surrounding the unit region, characterized in that, The semiconductor device includes: a first electrode; a semiconductor portion provided on the first electrode; an insulating film provided on the semiconductor portion in the terminal region; a plurality of second electrodes provided on the insulating film, arranged in a first direction from the center of the semiconductor portion toward the outer periphery when viewed from above, and separated from each other; a first floating electrode provided in the insulating film, overlapping a first gap between an adjacent pair of the second electrodes in a second direction orthogonal to the first direction, and facing one of the pair of the second electrodes across the insulating film; a second floating electrode provided in the insulating film in a manner separated from the first floating electrode, overlapping the first floating electrode in the second direction within the first gap, a portion of the second floating electrode overlapping the first floating electrode being located below a portion of the first floating electrode overlapping the first gap, the second floating electrode facing the other of the pair of the second electrodes across the insulating film; a third floating electrode provided in the insulating film, overlapping a second gap between the other of the pair of the second electrodes and another second electrode in the second direction, the other second electrode being a second electrode of the plurality of the second electrodes located on the first direction side of the other of the pair of the second electrodes, and facing the other of the pair of the second electrodes across the insulating film; and a fourth floating electrode provided in the insulating film in a manner separated from the third floating electrode, overlapping the third floating electrode in the second direction within the second gap, a portion of the fourth floating electrode overlapping the third floating electrode being located below a portion of the third floating electrode overlapping the second gap, the fourth floating electrode facing the other second electrode across the insulating film.

2. The semiconductor device according to claim 1, wherein an outer periphery of the first floating electrode overlaps the first gap in the second direction.

3. The semiconductor device according to claim 1, wherein the first floating electrode has: a first portion located inward of the second floating electrode, adjacent to the second floating electrode in the first direction.

4. The semiconductor device according to claim 3, wherein the first floating electrode has: a second portion located above the second floating electrode; and a third portion located between the first portion and the second portion, connected to the first portion and the second portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor portion has: a first semiconductor layer of a first conductivity type provided on the first electrode; and a second semiconductor layer of a second conductivity type provided on an upper layer portion of the first semiconductor layer, located inward of an outer periphery of the first semiconductor layer when viewed from above, ​ the insulating film overlaps with a portion of the second semiconductor layer located at a position further outward than the second semiconductor layer and a portion of the first semiconductor layer located at a position further outward than the insulating film in the second direction, an innermost second electrode of the plurality of second electrodes is connected to a portion of the second semiconductor layer located at a position further inward than the insulating film, an outermost second electrode of the plurality of second electrodes is connected to a portion of the first semiconductor layer located at a position further outward than the insulating film.

6. The semiconductor device according to claim 5, wherein the first semiconductor layer has: a first semiconductor region provided over the first electrode; a second semiconductor region provided over the first semiconductor region and having a lower impurity concentration than the first semiconductor region; and a third semiconductor region provided at an outer peripheral portion of the upper portion of the second semiconductor region and having a higher impurity concentration than the second semiconductor region, the outermost second electrode is connected to the third semiconductor region.

7. The semiconductor device according to any one of claims 1 to 4, wherein the first floating electrode and the second floating electrode include polysilicon. ​

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