Semiconductor device

Abstract

A semiconductor device of an embodiment includes first to fourth electrodes, a semiconductor portion, a first insulating film, and a second insulating film. The semiconductor portion includes first to third semiconductor layers. The first semiconductor layer of the first conductivity type is provided over the first electrode, the second semiconductor layer of the second conductivity type is provided over a part of the first semiconductor layer, and the third semiconductor layer of the first conductivity type is provided over the second semiconductor layer. The second electrode is in contact with the third semiconductor layer and is separated from the second semiconductor layer, the third semiconductor layer, and the second electrode. The first insulating film covers the third electrode. The fourth electrode is connected to the second electrode and is separated from the first semiconductor layer and the third electrode. The second insulating film is provided on a side surface of the fourth electrode, faces the first semiconductor layer with a gap therebetween, and has a thickness that increases toward the first direction.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2021-43658 (Filing date: March 17, 2021). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] In, for example, a vertical power semiconductor, there is a power semiconductor in which cells are miniaturized by a trench structure, and an on-resistance is reduced. In addition, there is known a technique in which a field plate electrode is provided in a drift layer by a trench structure, and a withstand voltage at the time of conduction is improved. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device capable of improving reliability.

[0006] A semiconductor device of an embodiment has a first electrode, a semiconductor portion, a second electrode, a third electrode, a first insulating film, a fourth electrode, and a second insulating film. The semiconductor portion is provided above the first electrode. The semiconductor portion has a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is of a first conductivity type, and is provided above the first electrode. The second semiconductor layer is of a second conductivity type, and is provided above a part of the first semiconductor layer. The third semiconductor layer is of the first conductivity type, and is provided above at least a part of the second semiconductor layer. The second electrode is in contact with the third semiconductor layer. The third electrode is separated from the second semiconductor layer, the third semiconductor layer, and the second electrode. The first insulating film covers the third electrode, and is in contact with the second semiconductor layer and the third semiconductor layer. The fourth electrode is provided so as to extend in a first direction from the first electrode toward the second electrode. The fourth electrode is connected to the second electrode, and is separated from the first semiconductor layer and the third electrode. The second insulating film is provided on a side surface of the fourth electrode, and is opposed to the first semiconductor layer with a gap therebetween. The second insulating film has a thickness that increases toward the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a plan view of a semiconductor device of a first embodiment.

[0008] Figure 2 is an enlarged plan view of a region A of Figure 1

[0009] Figure 3 is​Figure 2 The cross-sectional view of line B-B' shown.

[0010] Figure 4 (a) and (b) are schematic diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 5 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 6 This is an enlarged cross-sectional view showing the semiconductor device according to the second embodiment.

[0013] Figure 7 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0014] Figure 8 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a modified example of the second embodiment. Detailed Implementation

[0015] Hereinafter, each embodiment will be described with reference to the accompanying drawings.

[0016] Furthermore, the accompanying drawings are schematic, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in reality. Also, even when representing the same parts, there may be cases where the dimensions and ratios differ depending on the accompanying drawings. Moreover, in this specification and in each drawing, elements that are the same as those described in the previously shown figures are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0017] (First Implementation)

[0018] Figure 1 This is a top view showing the semiconductor device of this embodiment. Figure 2 It means Figure 1 An enlarged top view of region A. Figure 3 yes Figure 2 The cross-sectional view along line B-B' shown. Figures 1 to 3 The protective film and wiring layer have been omitted. For visual clarity, in... Figure 2 In the text, only the inter-electrode insulating film 46, which will be described later, is represented by a double-dotted line.

[0019] The semiconductor device 101 in this embodiment is a power semiconductor device used for controlling current and for being applied with a voltage, for example, 320V or less. The semiconductor device 101 includes a plurality of MOSFETs (metal-oxide-semiconductor field-effect transistors). For example... Figure 1 ,Figure 2 As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i. Figure 2 , Figure 3 As shown in FIG. 1, a pair of MOSFETs 101m is symmetrically disposed with respect to the fourth electrode 14 described later.

[0020] As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i. Figure 1 As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i.

[0021] As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i. Figure 1 , Figure 3 As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i.

[0022] Hereinafter, for convenience of explanation, in the present specification, the direction from the first electrode 11 toward the second electrode 12 is referred to as "up", and the opposite direction thereof is referred to as "down", but this expression is for convenience and is independent of the direction of gravity. The up direction is also referred to as "direction Z". In addition, as shown in FIG. 1, the arrangement direction of the MOSFETs 101m is referred to as "direction X", and the direction orthogonal to the direction Z and the direction X is referred to as "direction Y". The length of the direction X is also referred to as "width". Figure 1

[0023] As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i. Figure 3 As shown in FIG. 1, the semiconductor device 101 is arranged with a plurality of MOSFETs 101m. As shown in FIG. 2, the semiconductor device 101 is arranged with a plurality of IGBTs 101i.

[0024] The buffer layer 24 is in contact with the first electrode 11. The buffer layer 24 is of the first conductivity type, for example, is composed of an n-type semiconductor.

[0025] The drift layer 21 is disposed above the first electrode 11, and in detail, is disposed above the buffer layer 24. The drift layer 21 is of the first conductivity type, for example, is composed of an n - type semiconductor. The impurity concentration of the drift layer 21 is, for example, 4 x 10 15 cm -3 . In addition, the "n - type" indicates a lower carrier concentration than the "n + ​"Type" indicates that the carrier concentration is higher than that of "n-type". The same applies to p-type.

[0026] like Figure 3 As shown, the substrate layer 22 is disposed above a portion of the drift layer 21, specifically above the portion of the drift layer 21 that forms the side of the trench T1. The substrate layer 22 is of a second conductivity type, for example, made of a p-type semiconductor.

[0027] The source layer 23 is disposed above at least a portion of the substrate layer 22, specifically above the portion of the substrate layer 22 that forms the sidewall of the trench T1. The length (thickness) in the Z direction of the source layer 23 is thinner than the length (thickness) in the Z direction of the substrate layer 22. The source layer 23 is in contact with the second electrode 12. The source layer 23 is of a first conductivity type, for example, made of an n-type semiconductor.

[0028] like Figure 3 As shown, trench T1 is a hole extending downward from semiconductor portion 20. The length of trench T1 in direction X is, for example, approximately the same in direction Z. Most of the sidewalls of trench T1 are composed of drift layer 21, which consists of drift layer 21, substrate layer 22, and source layer 23 arranged along direction Z. The bottom surface of trench T1 is composed of drift layer 21. Multiple trenches T1 are arranged in direction X.

[0029] like Figure 3 As shown, the semiconductor device 101 also includes a contact 30, a third electrode 13, a fourth electrode 14, a first insulating film 41, a second insulating film 42, a third insulating film 43, a fourth insulating film 44, a fifth insulating film 45, and an inter-electrode insulating film 46. Figure 3 In order to clearly show the boundaries of the first insulating film 41, the second insulating film 42, the third insulating film 43, the fourth insulating film 44 and the fifth insulating film 45, these boundaries are represented by solid lines. However, in actual semiconductor devices, these boundaries are sometimes not clearly observable.

[0030] like Figure 3 As shown, the contact 30 is disposed on the side of the source layer 23 and the substrate layer 22, contacting the side surfaces of the source layer 23 and the substrate layer 22. Additionally, the contact 30 contacts the second electrode 12. The contact 30 is, for example, an ohmic contact.

[0031] The third electrode 13 is, for example, a gate electrode. The third electrode 13 is disposed in, for example, a trench T1 within the semiconductor portion 20. The third electrode 13 is separated from the semiconductor portion 20 through a first insulating film 41. The third electrode 13 is separated from the upper part of the drift layer 21, the substrate layer 22, and the source layer 23 through the first insulating film 41.

[0032] The fourth electrode 14 is, for example, a field plate electrode. The fourth electrode 14 is arranged in plurality in the direction X. The fourth electrode 14 is provided in the trench T1. As shown in Figure 3 , the fourth electrode 14 is provided extending along the direction Z, and the width is, for example, uniform in the direction Z. The fourth electrode 14 is separated from the drift layer 21 and the third electrode 13. The fourth electrode 14 is connected to the second electrode 12, and is substantially the same potential as the second electrode 12.

[0033] The fourth electrode 14 contains, for example, polysilicon, contains at least any one of neodymium (Nd), phosphorus (P), boron (B), and arsenic (As) as an impurity, and has conductivity. The fourth electrode 14 can contain, for example, a metal such as titanium (Ti).

[0034] The first insulating film 41 is, for example, a gate insulating film, and covers a surface of the third electrode 13 other than the upper surface. The first insulating film 41 is provided between the fourth electrode 14 and the third electrode 13, between the third electrode 13 and the upper portion of the drift layer 21, and between the substrate layer 22 and the source layer 23. The first insulating film 41 is in contact with the substrate layer 22 and the source layer 23. The first insulating film 41 can also be in contact with the upper portion of the drift layer 21. The first insulating film 41 contains, for example, silicon (Si) and oxygen (O), and is, for example, silicon oxide (SiO2).

[0035] As shown in Figure 2 , Figure 3 , the electrode-to-electrode insulating film 46 is provided between the second electrode 12 and the third electrode 13, and between the second electrode 12 and the fourth electrode 14. The electrode-to-electrode insulating film 46 is in contact with the second electrode 12, the third electrode 13, and the fourth electrode 14. The electrode-to-electrode insulating film 46 is in contact with the upper portion of the first insulating film 41. The electrode-to-electrode insulating film 46 is, for example, a silicon oxide film.

[0036] The second insulating film 42 is provided in the trench T1. As shown in Figure 3 , the second insulating film 42 is provided on the side surface of the fourth electrode 14. The second insulating film 42 is provided, for example, on substantially the entire region of the fourth electrode 14 except for the upper end of the side surface. A pair of second insulating films 42 is provided on both side surfaces of one fourth electrode 14. The portion of the second insulating film 42 other than the upper end portion 42b is opposed to the drift layer 21 with a gap G1 therebetween.

[0037] As shown in Figure 3 , the length in the direction X, that is, the thickness of the second insulating film 42 increases as it goes upward in the direction Z. The upper end portion 42b of the second insulating film 42 is in contact with the first insulating film 41. The lower portion 42a of the second insulating film 42 is in contact with the side surface of the fifth insulating film 45, and the lower end is in contact with the end portion of the fourth insulating film 44. The second insulating film 42 contains, for example, silicon and oxygen, and is, for example, silicon oxide.

[0038] The third insulating film 43 is provided in the trench T1. The third insulating film 43 is provided in substantially the entire region of the side surface of the trench T1 except for the upper end. As shown in FIG. 6, the third insulating film 43 is provided on the region of the surface of the drift layer 21 constituting the side surface of the trench T1 and is in contact with the drift layer 21. A pair of the third insulating films 43 is provided on both sides of one fourth electrode 14. Figure 3

[0039] The third insulating film 43 is opposed to the second insulating film 42 with the gap G1 interposed therebetween. The third insulating film 43 is in contact with the gap G1. The length in the direction X, that is, the thickness of the third insulating film 43 increases toward the upper side.

[0040] As shown in FIG. 6, the upper end portion 43b of the third insulating film 43 is in contact with the first insulating film 41 and is in contact with the upper end portion 42b of the second insulating film 42. The lower end portion 43a of the third insulating film 43 is in contact with the end portion of the fourth insulating film 44. The third insulating film 43 contains, for example, silicon and oxygen, and is, for example, silicon oxide. Figure 3

[0041] The fourth insulating film 44 is provided in the trench T1. A pair of the fourth insulating films 44 is provided at the corner portions of the bottom surface of the trench T1. The fourth insulating film 44 is provided on the region of the surface of the drift layer 21 constituting the bottom surface of the trench T1 and is in contact with the drift layer 21. The fourth insulating film 44 is provided between the second insulating film 42 and the third insulating film 43 and is in contact with the gap G1. The thickness, that is, the length in the direction Z of the fourth insulating film 44 is substantially uniform. The fourth insulating film 44 contains, for example, silicon and oxygen, and is, for example, silicon oxide.

[0042] The fifth insulating film 45 is provided in the trench T1. As shown in FIG. 6, the fifth insulating film 45 is provided substantially at the center of the bottom surface of the trench T1. The fifth insulating film 45 is provided on the region of the surface of the drift layer 21 constituting the bottom surface of the trench T1 and is in contact with the drift layer 21. The fifth insulating film 45 is provided between the drift layer 21 and the lower surface of the fourth electrode 14. The width of the fifth insulating film 45 is the same as the width of the lower surface of the fourth electrode 14. The side surface of the fifth insulating film 45 is in contact with the end portion of the fourth insulating film 44. Figure 3

[0043] In addition, the thickness, that is, the length in the direction Z of the fifth insulating film 45 is larger than the thickness of the fourth insulating film 44 and is larger than the width of the lower surface of the gap G1. Thus, the electric field intensity in the vicinity of the lower surface of the fourth electrode 14, which has a tendency to have a higher electric field intensity, is reduced. The fifth insulating film 45 contains, for example, silicon and oxygen, and is, for example, silicon oxide.

[0044] The relative dielectric constant of the second insulating film 42, the third insulating film 43, the fourth insulating film 44, and the fifth insulating film 45 is, for example, 3.0 to 3.9.

[0045] ​​​The fourth electrode 14 is separated from the third electrode 13, the drift layer 21, the base layer 22, and the source layer 23 by the second insulating film 42, the third insulating film 43, the fourth insulating film 44, the fifth insulating film 45, and the void G1, and is insulated.

[0046] The void G1 is a space provided in the trench T1 and is a space between the second insulating film 42 and the third insulating film 43. The void G1 is filled with, for example, air. The width of the void G1 narrows as it goes toward the direction Z. As shown in FIG. 6, the cross-sectional shape of the void G1 is substantially isosceles triangular, and the two sides corresponding to the equal sides are in contact with the second insulating film 42 and the third insulating film 43, and the base is in contact with the fourth insulating film 44. Figure 4

[0047] The lower surface of the void G1 is located at a position lower than the lower surface of the fourth electrode 14. The upper end of the void G1 is located at a position lower than the upper surface of the fourth electrode 14. The relative dielectric constant of the void G1 is about 1.0, which is lower than the relative dielectric constant of the second insulating film 42 and the third insulating film 43.

[0048] The cross-sectional shape of the void G1 can also be a substantially triangular shape in which the apex or the side is deformed. In addition, the cross-sectional shape of the void G1 is not limited to a substantially triangular shape, and can be, for example, a substantially trapezoidal shape, as long as the width on the lower surface side decreases as it goes upward.

[0049] In the case where the void G1 is a substantially trapezoidal shape, the upper end portion 43b of the third insulating film 43 and the upper end portion 42b of the second insulating film 42 do not contact each other, but both are in contact with the first insulating film 41. In this case, the upper end of the void G1 is present between the upper end portion 42b of the second insulating film 42 and the upper end portion 43b of the third insulating film 43.

[0050] Next, the operation of the semiconductor device 101 according to the present embodiment will be described.

[0051] In the semiconductor device 101, at the time of turning off, the second electrode 12 is applied with, for example, 0 V from a power supply device, and the first electrode 11 is applied with, for example, a positive potential from a power supply device. At this time, a depletion layer extends from the side surface of the trench T1 to the drift layer 21 by the fourth electrode 14 as a source electrode.

[0052] ​The depletion layer extends substantially in parallel with respect to the side surface of the trench T1 by adjusting the capacitance between the fourth electrode 14 and the side surface of the trench T1, and thus the withstand voltage of the semiconductor device 101 is improved. The adjustment of the capacitance is performed by the second insulating film 42 and the third insulating film 43 disposed between the fourth electrode 14 and the side surface of the trench T1, and specifically, the total value of the thickness of the second insulating film 42 and the thickness of the third insulating film 43 is made larger on the upper surface side and smaller as it goes downward. Thus, the capacitance between the fourth electrode 14 and the drift layer 21 is larger on the upper surface side where the potential is lower and smaller as it goes toward the bottom surface side where the potential is higher.

[0053] Further, the semiconductor device 101 is configured with the second insulating film 42 and the third insulating film 43 between the fourth electrode 14 and the side surface of the trench T1, and the electric field intensity of the drift layer 21 is improved. Since the integrated value of the electric field intensity is, for example, the withstand voltage, the withstand voltage of the semiconductor device 101 is improved. Further, the total value of the thickness of the second insulating film 42 and the thickness of the third insulating film 43 continuously changes in the vertical direction, and thus the electric field intensity of the drift layer 21 constituting the side surface of the trench T1 also continuously improves, and the withstand voltage is further improved.

[0054] As described above, the withstand voltage of the semiconductor device 101 is improved, and thus even if the impurity concentration of the drift layer 21 is set to be higher in order to reduce the on-resistance, the withstand voltage becomes good. Further, the semiconductor device 101 insulates the fourth electrode 14 using the void G1, and thus the width of the MOSFET 101m can be reduced compared to the case where the void G1 is not provided, and the number of the MOSFET 101m provided in the semiconductor device 101 can be increased. As a result, the on-resistance can be reduced.

[0055] Hereinafter, the manufacturing method of the semiconductor device 101 in the present embodiment will be described.

[0056] Figure 5 (a), (b), and Figure 4 is a schematic view showing the manufacturing method of the semiconductor device of the present embodiment.

[0057] As shown in (a) of Figure 4 is formed in the semiconductor portion 20, the insulating film F1 is formed on the inner surface of the trench T1, and the fourth electrode 14 is formed on the inner surface of the insulating film F1.

[0058] The insulating film F1 is, for example, a silicon oxide film.

[0059] The fourth electrode 14 is formed, for example, of metal or polycrystal silicon to which an impurity is added.

[0060] As shown in (a) of Figure 5As shown in (b), the insulating film F1 located on both sides of the fourth electrode 14 is removed by, for example, reactive ion etching (RIE) or wet etching to form the fifth insulating film 45.

[0061] The fifth insulating film 45 is an insulating film F1 remaining between the lower surface of the fourth electrode 14 and the bottom surface of the trench T1. Spaces are formed on both sides of the fourth electrode 14 and the fifth insulating film 45.

[0062] like Figure 4 As shown, an insulating film F2 is formed in the space between the fourth electrode 14 and the fifth insulating film 45. The insulating film F2 is, for example, a silicon oxide film. The insulating film F2 is formed by LPCVD (Low-Pressure Chemical Vapor Deposition) under specified conditions. Thus, the insulating film F2 is formed on the side and bottom surfaces of the trench T1, the side surfaces of the fifth insulating film 45, and the side surfaces of the fourth electrode 14. The specified conditions, for example, are achieved by setting a gas pressure to allow gas to reach… Figure 5 The bottom of the space shown in (b) is made to have a lower deposition rate at the bottom than at the top of the space. The deposition rate is increased by setting the temperature.

[0063] like Figure 6 As shown, the insulating film F2 becomes thicker as it is formed from the bottom of the space upwards, for example, closing the upper part of the trench T1. The insulating film F2 consists of a second insulating film 42, a third insulating film 43, and a fourth insulating film 44. Thus, the second insulating film 42, the third insulating film 43, and the fourth insulating film 44 are formed in a state of mutual contact.

[0064] The effects of the semiconductor device 101 in this embodiment will be explained below.

[0065] According to the semiconductor device 101 of this embodiment, by distributing a gap G1 with a relatively low permittivity between the side surface of the fourth electrode 14 and the region forming the side surface of the trench T1 on the surface of the drift layer 21, the width of the MOSFET 101m can be reduced, thereby increasing the conduction path of the semiconductor device 101. As a result, the on-resistance can be reduced.

[0066] Furthermore, according to the semiconductor device 101 of this embodiment, by providing the second insulating film 42, the third insulating film 43, and a gap G1 whose width decreases upwards between the side of the fourth electrode 14 and the region forming the trench T1 on the surface of the drift layer 21, the withstand voltage can be improved. With improved withstand voltage, even if the impurity concentration of the drift layer 21 is set high to reduce on-resistance, good withstand voltage performance can still be achieved.

[0067] In the case where the second insulating film 42 and the third insulating film 43 are not provided on the side surface of the fourth electrode 14 as in the present embodiment, specifically, in the case where only the gap is provided between the side surface of the fourth electrode 14 and the region of the surface of the drift layer 21 constituting the side surface of the trench T1, for example, in the case where the voltage of 340 V or less is applied to the set, the impurity concentration of the drift layer is about 3 x 1018cm-3, and the on-resistance becomes about 1250 mΩ mm-1. 15 -3 2 On the other hand, in the case of the semiconductor device of the present embodiment under the same setting, the impurity concentration of the drift layer 21 can be set to, for example, about 5 x 1018cm-3, and the on-resistance becomes, for example, about 720 mΩ mm-1. 15 -3 2

[0068] Thus, according to the semiconductor device 101 of the present embodiment, the withstand voltage can be improved and the current amount can be increased.

[0069] Further, according to the semiconductor device 101 of the present embodiment, by providing the gap G1 between the second insulating film 42 and the third insulating film 43, the generation of stress in the semiconductor portion 20 can be suppressed. Further, the manufacturing process of the second insulating film 42, the third insulating film 43, and the fourth insulating film 44 becomes easier than in the case where the inside of the trench T1 is filled with the insulating film without providing the gap.

[0070] (Second Embodiment)

[0071] In the semiconductor device 102 of the present embodiment, the fourth electrode 14A is formed of polysilicon in which the impurity concentration gradient is set, and the cross-sectional shape of the gap G1 is a substantially right-angled triangle.

[0072] Figure 7 is an enlarged cross-sectional view of the semiconductor device of the present embodiment.

[0073] The fourth electrode 14A contains at least any one of neodymium (Nd), phosphorus (P), boron (B), and arsenic (As) as an impurity, and the impurity concentration is high in the upper portion and becomes lower as it goes downward. The impurity concentration of the fourth electrode 14A continuously becomes higher from the lower portion toward the direction Z.

[0074] The thickness of the second insulating film 42A becomes larger as it goes upward from the lower portion 42Aa. Specifically, the thickness of the lower portion 42Aa of the second insulating film 42A is substantially uniform, and the thickness of the portion above the lower portion 42Aa becomes larger as it goes upward. The upper end portion 42Ab of the second insulating film 42A is in contact with the upper end portion 43Ab of the third insulating film 43A.

[0075] ​​​​​The thickness of the third insulating film 43A is substantially uniform. The thickness of the fourth insulating film 44A is substantially the same as the thickness of the third insulating film 43A.

[0076] In the semiconductor device 102 of this embodiment, the total value of the thickness of the second insulating film 42A and the thickness of the third insulating film 43A is larger on the upper surface side and smaller as it goes downward. The width of the gap G1 is narrower in the lower portion and smaller as it goes upward.

[0077] Next, a manufacturing method of the semiconductor device 102 of this embodiment will be described.

[0078] Figure 7 is a schematic view showing the manufacturing method of the semiconductor device 102 of this embodiment.

[0079] The fourth electrode 14A in this embodiment is formed by the following process: forming polycrystalline silicon not containing impurities on the inner surface of the insulating film formed on the side surface and the bottom surface of the trench T1 and the upper surface, disposing a film containing, for example, a high concentration of impurities on the upper surface of the polycrystalline silicon, and removing the polycrystalline silicon other than inside the trench after thermally diffusing the impurities into the polycrystalline silicon. Thus, the impurity concentration of the fourth electrode 14A is high in the upper portion and continuously lower as it goes downward.

[0080] Next, the insulating films on both sides of the fourth electrode 14A are removed, and spaces are formed on both sides of the fourth electrode 14A and the fifth insulating film 45, as shown in Figure 8 The insulating film F2A is formed by thermal oxidation in the spaces. The insulating film F2A is a silicon oxide film. The deposition rate of the silicon oxide film based on thermal oxidation increases when the impurity concentration is high. The deposition rate of thermal oxidation in the fifth insulating film 45 is lower than, for example, the deposition rate of thermal oxidation in the lower portion of the fourth electrode 14A. Thus, the thickness of the second insulating film 42A in the fourth electrode 14A continuously increases from the lower portion of the fourth electrode 14A toward the upper portion. The thickness of the lower portion 42Aa of the second insulating film 42A is substantially uniform and lower than, for example, the thickness of the second insulating film 42A in the fourth electrode 14A.

[0081] According to the semiconductor device 102 in this embodiment, as in the first embodiment, the withstand voltage can be increased and the current amount can be increased.

[0082] The structures, operations, and effects other than the above in this embodiment are the same as those of the first embodiment.

[0083] (Modified Example of the Second Embodiment)

[0084] The fourth electrode 14A in this modified example is formed of polycrystalline silicon whose impurity concentration is set to, for example, three stages, and the cross-sectional shape of the gap G1 is substantially a right triangle.

[0085] Figure 8 is a schematic view showing a manufacturing method of a semiconductor device of the present modification.

[0086] As Figure 8 shown, the fourth electrode 14A in the present modification includes a lower portion 14A1, an intermediate portion 14A2, and an upper portion 14A3. The impurity concentration of the intermediate portion 14A2 is higher than that of the lower portion 14A1 and lower than that of the upper portion 14A3. In this way, the impurity concentration of the fourth electrode 14A becomes higher as it goes in the direction Z. The fourth electrode 14A contains at least any one of neodymium (Nd), phosphorus (P), boron (B), and arsenic (As) as an impurity.

[0087] The fourth electrode 14A in the present embodiment is formed by depositing polysilicon containing a low concentration of impurities, polysilicon containing a medium concentration of impurities, and polysilicon containing a high concentration of impurities.

[0088] As Figure 8 shown, the fourth electrode 14A in the present modification includes a lower portion 14A1, an intermediate portion 14A2, and an upper portion 14A3. The impurity concentration of the intermediate portion 14A2 is higher than that of the lower portion 14A1 and lower than that of the upper portion 14A3. In this way, the impurity concentration of the fourth electrode 14A becomes higher as it goes in the direction Z. The fourth electrode 14A contains at least any one of neodymium (Nd), phosphorus (P), boron (B), and arsenic (As) as an impurity.

[0089] In this way, the thickness of the insulating film F2A on the side surface of the fourth electrode 14A is larger in the upper portion and gradually becomes smaller as it goes downward. Therefore, the thickness of the second insulating film 42A is also larger in the upper portion 42A3 and gradually becomes smaller as it goes downward. As Figure 8 shown, the second insulating film 42A becomes, for example, 4 stages of thickness in the lower portion 42Aa, the intermediate lower portion 42A1, the intermediate upper portion 42A2, and the upper portion 42A3. The thickness of the intermediate upper portion 42A2 of the second insulating film 42A is larger than that of the intermediate lower portion 42A1 and smaller than that of the upper portion 42A3. The thickness of the lower portion 42Aa of the second insulating film 42A, which contacts the side surface of the fifth insulating film 45, is smaller than that of the intermediate lower portion 42A1.

[0090] As ​ shown, the width of the gap G1 is larger in the lower portion and becomes smaller as it goes upward. The cross-sectional shape of the gap G1 is a substantially right-angled triangular shape, but contains a plurality of steps in the hypotenuse that contacts the second insulating film 42A and the fifth insulating film 45.

[0091] The semiconductor device according to the present embodiment, like the first embodiment, increases the current amount and can increase the withstand voltage.

[0092] The structure, operation, and effects other than the above in this modification example are the same as those of the first embodiment.

[0093] According to the embodiment of the present application, a semiconductor device capable of improving reliability can be provided.

[0094] The above describes the embodiments of the present application with reference to specific examples. However, the embodiments of the present application are not limited to these specific examples. For example, as to the specific configuration, material, and the like of the semiconductor portion, the plurality of electrodes, and the insulating film in the MOSFET included in the semiconductor device, a person skilled in the art appropriately selects from the known range, thereby implementing the present application similarly, as long as the same effects are obtained, and this is included in the scope of the present application. A scheme in which any two or more elements of each specific example are combined within a technically feasible range is included in the scope of the present application as long as the scheme includes the gist of the present application.

Claims

1. A semiconductor device comprising: First electrode; A first semiconductor layer of a first conductivity type is disposed above the first electrode; A second semiconductor layer of a second conductivity type is disposed above a portion of the first semiconductor layer; A third semiconductor layer of a first conductivity type is disposed above at least a portion of the second semiconductor layer; The second electrode is in contact with the third semiconductor layer; The third electrode is separated from the second semiconductor layer, the third semiconductor layer and the second electrode; A first insulating film covers the third electrode and is in contact with the second semiconductor layer and the third semiconductor layer; The fourth electrode extends in a first direction from the first electrode toward the second electrode, is connected to the second electrode, and is separate from the first semiconductor layer and the third electrode; as well as A second insulating film is disposed on the side surface of the fourth electrode, facing the first semiconductor layer through a gap. The thickness of the second insulating film increases as it faces the first direction. The width of the gap decreases as it moves toward the first direction. The width of the upper end of the gap is smaller than the width of the lower end of the gap.

2. The semiconductor device according to claim 1, wherein, It also includes a third insulating film, which is in contact with the first semiconductor layer and faces the second insulating film across the gap. The thickness of the third insulating film is uniform.

3. The semiconductor device according to claim 2, wherein, It also has a fourth insulating film, which is in contact with the first semiconductor layer and the gap between the second insulating film and the third insulating film.

4. The semiconductor device according to claim 1, wherein, It also includes a third insulating film, which is in contact with the first semiconductor layer and faces the second insulating film across the gap. The thickness of the third insulating film increases as it moves toward the first direction.

5. The semiconductor device according to claim 4, wherein, It also has a fourth insulating film, which is in contact with the first semiconductor layer and the gap between the second insulating film and the third insulating film.

6. The semiconductor device according to any one of claims 1 to 5, wherein, It also has a fifth insulating film, which is disposed between the lower surface of the fourth electrode and the first semiconductor layer.

7. The semiconductor device according to claim 6, wherein, The second insulating film has a lower portion that contacts the fifth insulating film.

8. The semiconductor device according to any one of claims 1 to 5, wherein, The fourth electrode is made of polycrystalline silicon containing at least one of neodymium, phosphorus, boron and arsenic as impurities, the concentration of which increases as it moves toward the first direction.

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