Semiconductor Wafer and Light-Emitting Device

Abstract

The present disclosure provides a semiconductor wafer and a light-emitting device. The semiconductor wafer includes a semiconductor stack and a passivation layer. The semiconductor stack includes a top surface, a bottom surface, and a plurality of sidewalls located between the opposite top and bottom surfaces. The passivation layer conformally covers the top surface and the sidewalls of the semiconductor stack. When viewed from the bottom surface, the top view profile of the semiconductor stack includes a plurality of edges and a plurality of corners, each corner being defined by two adjacent edges. The top view profile of the passivation layer surrounds the top view profile of the semiconductor stack, and the top view profile of the passivation layer includes protrusions adjacent to one of the plurality of corners and protruding outward from the top view profile of the passivation layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor wafer and a light-emitting device. Background Art

[0002] In recent years, various new types of displays have gradually emerged. Most of these displays are developed towards increasing resolution and energy conservation. Micro light-emitting diodes (μLEDs) are an important development type among them.

[0003] Micro light-emitting diodes reduce the size of traditional light-emitting diodes to an order of magnitude of about 100 micrometers or less, even dozens of micrometers. At this order of magnitude, the number of light-emitting diodes in the same area increases rapidly. Therefore, the yield of transferring the light-emitting diodes from the growth substrate to the display board needs to reach more than 99%. With current manufacturing technologies, there are still many technical problems to be solved in this mass transfer. Summary of the Invention

[0004] In some embodiments of the present disclosure, the semiconductor wafer includes a semiconductor stack and a passivation layer. The semiconductor stack includes a top surface, a bottom surface, and a plurality of sidewalls located between the opposite top and bottom surfaces. The passivation layer conformally covers the top surface and the sidewalls of the semiconductor stack. When viewed from the bottom surface, the top view profile of the semiconductor stack includes a plurality of edges and a plurality of corners, each corner being defined by two adjacent edges. The top view profile of the passivation layer surrounds the top view profile of the semiconductor stack, and the top view profile of the passivation layer includes a protrusion adjacent to one of the corners and protruding outward from the top view profile of the passivation layer.

[0005] In some embodiments of the present disclosure, the protrusion of the passivation layer has a fracture surface.

[0006] In some embodiments of the present disclosure, the bottom surface includes an uneven structure.

[0007] In some embodiments of the present disclosure, the semiconductor wafer is a light-emitting diode wafer, and the semiconductor wafer further includes a first electrode located on the passivation layer. The semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and the first electrode penetrates the passivation layer to electrically connect to the first semiconductor layer.

[0008] In some embodiments of the present disclosure, the semiconductor wafer further includes a second electrode located on the passivation layer and penetrating the passivation layer to electrically connect to the second semiconductor layer, wherein the first electrode and the second electrode are located on the same side of the semiconductor stack.

[0009] In some embodiments of the present disclosure, the semiconductor wafer further includes a second electrode located on the bottom surface of the semiconductor stack and electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

[0010] In some embodiments of the present disclosure, the semiconductor wafer is an integrated circuit wafer, and the semiconductor wafer further includes a first electrode located on the semiconductor stack and electrically connected to the semiconductor stack.

[0011] In some embodiments of the present disclosure, the light-emitting device includes a carrier substrate, light-emitting units, and a control unit. The light-emitting units are located on the carrier substrate. The light-emitting units respectively emit red light, green light, or blue light, and there is a light-blocking structure between any two adjacent light units. Among them, at least one of the light-emitting units includes a semiconductor wafer. The control unit is located on the carrier substrate, wherein the control unit is electrically connected to at least one of the light-emitting units.

[0012] In some embodiments of the present disclosure, the semiconductor wafer includes a semiconductor stack and a passivation layer. The semiconductor stack includes a top surface, a bottom surface, and a plurality of sidewalls located between the opposite top and bottom surfaces. The passivation layer conformally covers the top surface and the sidewalls of the semiconductor stack. Wherein, when viewed from the bottom surface direction, the top view profile of the semiconductor wafer is a closed shape including a plurality of edges and a plurality of corners, each corner is defined by two adjacent edges, and at least one of the plurality of corners has a fracture surface.

[0013] In the top view profile range of the semiconductor wafer, the connecting lines of any two non-adjacent corners among the plurality of corners are not of equal length.

[0014] In some embodiments of the present disclosure, the semiconductor wafer is a light-emitting diode wafer, and the semiconductor wafer further includes a first electrode located on the passivation layer. Wherein, the semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and the first electrode penetrates the passivation layer to be electrically connected to the first semiconductor layer.

[0015] In some embodiments of the present disclosure, the semiconductor wafer further includes a second electrode located on the passivation layer and penetrating the passivation layer to be electrically connected to the second semiconductor layer. Wherein, the first electrode and the second electrode are located on the same side of the semiconductor stack.

[0016] In some embodiments of the present disclosure, the semiconductor wafer further includes a second electrode located on the bottom surface of the semiconductor stack and electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

[0017] In some embodiments of the present disclosure, the semiconductor wafer is an integrated circuit wafer, and the semiconductor wafer further includes a first electrode located on the semiconductor stack and electrically connected to the semiconductor stack.

[0018] In some embodiments of the present disclosure, the light-emitting device includes a carrier substrate, a plurality of light-emitting units, and a control unit. The light-emitting units are located on the carrier substrate. Each of the light-emitting units emits red light, green light, or blue light, and there is a light-blocking structure between any two adjacent light-emitting units. At least one of the light-emitting units includes a semiconductor wafer. The control unit is located on the carrier substrate, and the control unit is electrically connected to at least one of the light-emitting units.

[0019] In some embodiments of the present disclosure, the top view profile of the semiconductor wafer is a closed quadrilateral including four edges and four corners.

[0020] In some embodiments of the present disclosure, the light-emitting device is characterized by including a carrier substrate and a plurality of light-emitting diode wafers. The plurality of light-emitting diode wafers are located on the carrier substrate and are arranged at least along a first direction. Each of the light-emitting diode wafers includes a semiconductor stack and a passivation layer. The semiconductor stack includes a top surface, a bottom surface, and at least one sidewall located between the opposite top and bottom surfaces. The semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The passivation layer conformally covers the top surface and the sidewall of the semiconductor stack, and the passivation layer includes a protrusion. The extending direction of the protrusion and the first direction together define a first angle, and the first angle is an acute angle.

[0021] In some embodiments of the present disclosure, the protrusion of the passivation layer has a fracture surface.

[0022] In some embodiments of the present disclosure, at least one of the light-emitting diode wafers further includes a first electrode and a second electrode, and the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

[0023] In some embodiments of the present disclosure, the light-emitting device further includes an integrated circuit wafer located on the carrier substrate, and the integrated circuit wafer is electrically connected to at least one of the light-emitting diode wafers.

[0024] In some embodiments of the present disclosure, the position of the bracket of the semiconductor wafer is changed and the area of the bracket is minimized, so that more wafers can be produced on each wafer. In addition, since the area of the bracket of the wafer has been minimized, the area of the remaining bracket on the transferred wafer becomes smaller, and the influence of the remaining bracket on the light emission pattern of the component can be effectively reduced. Accordingly, the light-emitting effect of the semiconductor wafer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings disclose one or more embodiments of the present disclosure and are used together with the descriptions in the specification to explain the principles of the present disclosure. Whenever possible, the same reference numerals are used throughout the drawings to represent the same or similar elements in the embodiments. These drawings include:

[0026] Figures 1 to 9 Cross-sectional view showing an intermediate process step of a semiconductor wafer for fabricating some embodiments of the present disclosure;

[0027] Figure 10A and Figure 10B Cross-sectional view showing a semiconductor wafer of some embodiments of the present disclosure;

[0028] Figures 11A to 11D Top view of a semiconductor wafer of some embodiments of the present disclosure from the bottom surface;

[0029] Figure 12 Cross-sectional view showing a semiconductor wafer fabricated using a process similar to Figures 1 to 9 ;

[0030] Figure 13A and Figure 13B Cross-sectional view showing a light-emitting device using a light-emitting unit and a control unit of some embodiments of the present disclosure;

[0031] Figure 13C Showing Figure 13A and Figure 13B top view;

[0032] Figures 14 to 21 Cross-sectional view showing an intermediate process step of a semiconductor wafer for fabricating other embodiments of the present disclosure;

[0033] Figure 22 Cross-sectional view showing a semiconductor wafer of some embodiments of the present disclosure;

[0034] Figure 23A Top schematic view showing an intermediate process step before transferring a semiconductor wafer of some embodiments of the present disclosure;

[0035] Figures 23B to 23C Light-emitting device using a semiconductor wafer according to some embodiments of the present disclosure.

[0036]

Symbol Description

[0037] 100: Semiconductor wafer

[0038] 110: First substrate

[0039] 120: Semiconductor stack

[0040] 121: First semiconductor stack

[0041] 122: Second semiconductor stack

[0042] 123: Third semiconductor stack

[0043] 124: Active layer

[0044] 125: Conductive glass layer

[0045] 126: Bracket

[0046] 127: Semiconductor stack

[0047] 127a: Bottom surface

[0048] 127b: Top surface

[0049] 128: Side wall

[0050] 129: Top view contour

[0051] 130: Edge

[0052] 131: Corner

[0053] 134: Groove

[0054] 135: Groove

[0055] 140: Passivation layer

[0056] 142: First electrode hole

[0057] 144: Second electrode hole

[0058] 145: Top view contour

[0059] 146: Edge

[0060] 147: Corner

[0061] 152: First electrode

[0062] 154: Second electrode

[0063] 160: Sacrificial layer

[0064] 172: Semiconductor layer

[0065] 174: Connection layer

[0066] 176: Second substrate

[0067] 182: Protrusion

[0068] 184: Fracture surface

[0069] 186: Protrusion structure

[0070] 200: Semiconductor wafer

[0071] 227: Semiconductor stack

[0072] 240: Passivation layer

[0073] 250: Electrode

[0074] 282: Protrusion

[0075] 284: Fracture surface

[0076] 300: Light-emitting device

[0077] 310: Carrier board

[0078] 320: Light-emitting unit

[0079] 320R: Light-emitting unit

[0080] 320G: Light-emitting unit

[0081] 320B: Light-emitting unit

[0082] 322: Light-emitting diode wafer

[0083] 324R: Conversion layer

[0084] 324R: Red light conversion layer

[0085] 324G: Green light conversion layer

[0086] 326: Conversion layer

[0087] 326R: Red light conversion layer

[0088] 326G: Green light conversion layer

[0089] 330: Control unit

[0090] 340: Adhesive

[0091] 400: Semiconductor wafer

[0092] 410: First substrate

[0093] 420: Semiconductor stack

[0094] 421: First semiconductor stack

[0095] 422: Second semiconductor stack

[0096] 423: Third semiconductor stack

[0097] 424: Active layer

[0098] 425: Conductive glass layer

[0099] 426: Bracket

[0100] 427: Semiconductor stack

[0101] 427a: Bottom surface

[0102] 427b: Top surface

[0103] 428: Side wall

[0104] 434: Groove

[0105] 435: Groove

[0106] 440: Passivation layer

[0107] 442: First electrode hole

[0108] 448: Connection part

[0109] 452: First electrode

[0110] 460: Sacrificial layer

[0111] 472: Semiconductor layer

[0112] 474: Connection layer

[0113] 476: Second substrate

[0114] 480: Second electrode

[0115] 482: Protrusion

[0116] 484: Fracture surface

[0117] 500: Light-emitting device

[0118] 510: Carrier board

[0119] A - A’: Line

[0120] a1: First angle

[0121] a2: First angle

[0122] D1: First extension direction

[0123] D2: First extension direction

[0124] L1: Connecting line

[0125] L2: Connecting line

[0126] X: First direction Detailed implementation manners

[0127] In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of the present disclosure; however, this is not the only form of implementing or applying the specific embodiments of the present disclosure. The following disclosed embodiments can be combined or replaced with each other under beneficial circumstances, or other embodiments can be added to one embodiment without further recording or explanation.

[0128] It is understood that although terms such as "first", "second", and "third" may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of the present invention.

[0129] In the following description, numerous specific details will be set forth in order to provide a thorough understanding of the following embodiments. However, the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in the drawings for simplicity.

[0130] Some embodiments of the present disclosure can increase the number of wafers that can be produced per wafer. Specifically, the position of the wafer support can be changed, and the wafer support can be placed at the corner of the wafer. This can reduce the distance between wafers, enabling more wafers to be produced per wafer. In addition, this can also reduce the area of the support remaining on the transferred wafer and improve the light-emitting effect of the wafer.

[0131] Figures 1 to 9 A cross-sectional schematic diagram showing an intermediate process step of manufacturing a semiconductor wafer according to some embodiments of the present disclosure. In Figure 1 , a first substrate 110 is provided. The first substrate 110 can be any suitable material. In some embodiments, the first substrate 110 is a sapphire substrate. Next. A semiconductor stack 120 can be deposited on the first substrate 110. The semiconductor stack 120 can include n-type / p-type semiconductor layers made of different materials, or the same material doped with n-type / p-type impurities. For example, as Figure 1 shown, a first semiconductor layer 121, a second semiconductor layer 122, and an optionally formed third semiconductor layer 123. In some embodiments, the semiconductor stack 120 also includes an active layer 124 between the first semiconductor layer 121 and the second semiconductor layer 122. In some embodiments, a transparent conductive layer 125 can be deposited on the semiconductor stack 120.

[0132] In some embodiments, the first semiconductor layer 121 is an N-type doped gallium nitride (GaN), and the second semiconductor layer 122 is a P-type doped gallium nitride, or vice versa. Additionally, the third semiconductor layer 123 may be undoped gallium nitride and is used as a buffer layer between the first semiconductor layer 121 and the first substrate 110. The active layer 124 may be gallium nitride incorporated with quantum well structures and / or quantum dot structures. Thus, when current passes through the active layer 124, the active layer 124 can emit light of a specific wavelength. The transparent conductive layer 125 may be made of indium tin oxide or other suitable materials.

[0133] As Figure 2 shown, trenches 134 and 135 are formed in the transparent conductive layer 125 and the semiconductor stack 120. In some embodiments, an etching process, such as a dry etching process, may be used to form trenches 134 and 135. For example, a first etching step may be performed first to form shallower and wider trenches 134 in the transparent conductive layer 125 and the semiconductor stack 120, and then a second etching step may be performed to form deeper and narrower trenches 135 in the first semiconductor layer 121 and the third semiconductor layer 123. In this etching process, trenches 134 and 135 partially divide the semiconductor stack 120 into a support 126 and a patterned semiconductor stack 127 (i.e., the bottoms of trenches 134 and 135 are at a distance from the first substrate 110), where trench 135 defines the sidewalls 128 of the patterned semiconductor stack 127 (such as Figures 11A to 11D the top-down contour 129). The sidewalls 128 may define the shape of the semiconductor wafer 100 in subsequent processes. The position of the support 126 is also determined in this step, which will be Figures 11A to 11D introduced in detail. In some embodiments, the boundaries of trenches 134 and 135 have a distance for forming electrode holes and electrodes in subsequent processes.

[0134] As Figure 3 shown, a passivation layer 140 is conformally deposited on the semiconductor stack 120 and the transparent conductive layer 125. Thus, the outer contour of the passivation layer 140 (such as the top-down contour 145 shown in Figures 11A to 11D below) is only slightly larger than the outer contour of the semiconductor wafer 100 (i.e., the range defined by the sidewalls 128). The passivation layer 140 can be used to protect the exposed surface of the semiconductor stack 120 from foreign objects or moisture intrusion from the outside, and can also ensure that the first semiconductor layer 121 and the second semiconductor layer 122 are not electrically connected to the subsequently formed conductive layer except through the electrode holes. In some embodiments, the passivation layer 140 may be an insulating layer.

[0135] Next, a first electrode hole 142 and a second electrode hole 144 are formed in the passivation layer 140. The first electrode hole 142 and the second electrode hole 144 are used to expose the second semiconductor layer 122 (or the transparent conductive layer 125 electrically connected to the second semiconductor layer 122) and the first semiconductor layer 121, respectively.

[0136] Next, as Figure 4 shown, a first electrode 152 and a second electrode 154 are formed in the first electrode hole 142 and the second electrode hole 144, respectively. The first electrode 152 and the second electrode 154 are both located on the same side of the semiconductor stack 120. The first electrode 152 and the second electrode 154 are in contact with the second semiconductor layer 122 (or the transparent conductive layer 125 electrically connected to the second semiconductor layer 122) and the first semiconductor layer 121, respectively, to provide an electrical connection between the semiconductor wafer 100 and the circuit board of the display device in subsequent applications.

[0137] As Figure 5 shown, a sacrificial layer 160 is formed on the passivation layer 140, the first electrode 152, and the second electrode 154. After the sacrificial layer 160 is formed, a groove 162 located on the bracket 126 is formed by an etching process or other suitable means. And, the bottom of the groove 162 exposes a part of the passivation layer 140 located on the bracket 126.

[0138] As Figure 6 shown, a support structure layer 172, a connection layer 174, and a second substrate 176 are sequentially deposited on the sacrificial layer 160, and the support structure layer 172 is in contact with a part of the passivation layer 140 located on the bracket 126 through the groove 162 (as Figure 5 shown). In some embodiments, the support structure layer 172 is made of silicon dioxide and can be used to support the bracket 126 and the patterned semiconductor stack 127 in subsequent processes of transferring elements. The connection layer 174 is a metal layer connecting the semiconductor layer and the second substrate 176, and the second substrate 176 can be a substrate similar to the first substrate 110.

[0139] As Figure 7 shown, flip the structure as Figure 6 shown and remove the first substrate 110. In some embodiments, an etching process, a Laser-Lift-Off process can be used to remove the first substrate 110. In some embodiments, after the first substrate 110 is removed, the exposed surface of the third semiconductor layer 123 is a rough surface.

[0140] As Figure 8As shown, the semiconductor stack 120 of the removed portion is removed until the surface of the partial passivation layer 140 located between the semiconductor stack 127 and the bracket 126 is exposed, and the bottom surface 127a of the patterned semiconductor stack 127 is exposed. The bottom surface 127a can be maintained as a rough surface or a flat surface. Here, the bottom surface 127a is the side of the semiconductor stack 127 that is farther from the light-emitting layer 124. In other words, in this step, the passivation layer 140 is not removed. Any suitable method can be used to remove the partial semiconductor stack 120, such as chemical mechanical polishing, etching process, etc. After removing the partial semiconductor stack 120, the manufacturing process of the semiconductor wafer 100 (as Figure 9 shown) is completed. In some embodiments, the semiconductor wafer 100 can be used as a light-emitting diode wafer in subsequent manufacturing processes.

[0141] As Figure 9 shown, the sacrificial layer 160 is removed. Any suitable method can be used, such as chemical etching, to remove the sacrificial layer 160. Therefore, the sacrificial layer 160 can be removed without damaging the semiconductor wafer 100. After removing the sacrificial layer 160, the semiconductor wafer 100 is connected to the bracket 126 through the passivation layer 140. Then, the semiconductor wafer 100 is transferred using a transfer technique. The semiconductor wafer 100 (as Figure 10A shown) includes the semiconductor stack 127, the passivation layer 140, the first electrode 152, and the second electrode 154 as described above. During the transfer of the semiconductor wafer 100, a transfer device (e.g., a stamp) contacts the semiconductor wafer 100 from the bottom surface 127a and then lifts the semiconductor wafer 100. At the same time, the bracket 126 remains fixed on the support structure layer 172. Therefore, the lifting action will separate the semiconductor wafer 100 from the bracket 126, and the separated semiconductor wafer 100 can be transferred to a device for subsequent applications, such as a circuit board (as Figure 13A the carrier plate 310).

[0142] Figure 10A The cross-sectional view of the semiconductor wafer 100 according to some embodiments of the present disclosure is shown. The semiconductor stack 127 of the semiconductor wafer 100 has a bottom surface 127a and a top surface 127b, and there is a sidewall 128 between the bottom surface 127a and the top surface 127b. The top surface 127b is closer to the light-emitting layer 124 than the bottom surface 127a. Since the semiconductor wafer 100 is directly removed from the bracket 126 by the transfer device, the passivation layer 140 breaks at the connection between the semiconductor stack 127 and the bracket 126 and forms a protrusion 182 with a fracture surface 184. The protrusion 182 is substantially coplanar with the bottom surface 127a. In other embodiments, a concavo-convex structure 186 can be formed on the bottom surface 127a, as Figure 10BAs shown, when the bottom surface 127a has the concavo-convex structure 186, total internal reflection of light can be reduced and the light extraction rate can be increased.

[0143] Figures 11A to 11D FIG. shows a top view of the semiconductor wafer 100 according to some embodiments of the present disclosure as viewed from the bottom surface 127a. In Figure 11A , the semiconductor stack 127 of the semiconductor wafer 100 has a top view profile 129, and the top view profile 129 has a plurality of edges 130. If the top view profile 129 is a quadrilateral, the top view profile 129 has a total of four edges 130. However, in other embodiments, the top view profile 129 can be a triangle or a polygon with more than four sides. Two adjacent edges 130 together define a corner 131. In Figures 11A to 11D , the top view profile 129 has four corners 131.

[0144] The passivation layer 140 of the semiconductor wafer 100 also has a top view profile 145. The shape of the top view profile 145 can be substantially the same as that of the top view profile 129. For example, in Figures 11A to 11D , if the top view profile 129 is a quadrilateral, the top view profile 145 is also a quadrilateral. The top view profile 145 has a plurality of edges 146. Two adjacent edges 146 together define a corner 147. The corner 131 of the top view profile 129 is substantially aligned with the corner 147 of the top view profile 145. At the adjacent corners 131 (i.e., at the corners 147), there are the protruding portions 182 as described above, and the protruding portions 182 protrude outward from the top view profile 145 of the passivation layer 140.

[0145] As described above, during the transfer process after the process in Figure 9 , the passivation layer 140 will break at the connection between the semiconductor wafer 100 and the bracket 126, and the broken passivation layer 140 becomes the protruding portion 182. Therefore, the broken portion of the protruding portion 182 has a fracture surface 184. This fracture surface 184 is a random section formed by fracture and is related to the pulling force and angle of extraction. Therefore, each protruding portion 182 can have a fracture surface 184 with a different shape, and each protruding portion 182 can also have a different extension length. For example, in Figure 11A , two protruding portions 182 located diagonally can have fracture surfaces 184 with different shapes, and / or the two protruding portions 182 have different extension lengths. Similarly, in Figure 11C and Figure 11D , the fracture surface 184 of each protruding portion 182 can have a different shape, and / or each protruding portion 182 can have a different extension length.

[0146] In addition, in Figure 11A , it can be seen that the bracket 126 (such as Figure 9As shown, it was originally placed at the corner 147 of the semiconductor wafer 100. Since the bracket 126 is located at the corner 147 and occupies little wafer space, when manufacturing the semiconductor wafer 100, adjacent semiconductor wafers 100 can be closely arranged. In this way, the number of semiconductor wafers 100 that can be manufactured on a single wafer can be increased. Furthermore, the residual bracket area (i.e., the protruding portion 182) of the transferred semiconductor wafer 100 can be reduced, which can effectively reduce the influence of the residual bracket on the light emission pattern of the component and improve the light emission effect of the semiconductor wafer 100.

[0147] In some embodiments, the semiconductor wafer 100 has a length and a width, and the width of the protruding portion 182 does not exceed 1 / 3 of the width of the semiconductor wafer 100. The width of the protruding portion 182 is basically determined by the material of the passivation layer 140. However, if the width of the protruding portion 182 is too wide, it is not conducive to the separation between the semiconductor wafer 100 and the bracket 126; if the width of the protruding portion 182 is too narrow, after removing the sacrificial layer 160, the passivation layer 140 may not be able to support the semiconductor wafer 100.

[0148] Although Figure 11A the illustration shows that the semiconductor wafer 100 has two protruding portions 182, the number of protruding portions 182 is not limited to two. As Figures 11B to 11D shown, Figure 11B 、 Figure 11C 、 Figure 11D respectively illustrate that the semiconductor wafer 100 has 1, 3, and 4 protruding portions 182. In addition, each non-adjacent corner 147 can form a diagonal line, such as the diagonal connecting lines L1 and L2 shown in Figures 11A to 11D . The ends of the diagonal connecting lines can be the midpoints of the boundaries of the corners 147 without protruding portions 182 or the midpoints of the boundaries of the protruding portions 182. For example, the diagonal connecting line can be the midpoint connecting line of two fracture surfaces 184, as shown by the connecting line L1 in Figure 11A . The diagonal connecting line can be the midpoint connecting line of two corners 147, as shown by the connecting line L2 in Figure 11A . The diagonal connecting line can be the midpoint connecting line of a corner 147 and a fracture surface 184, as shown by the connecting line L1 in Figure 11B . Due to the presence of the protruding portions 182, in each semiconductor wafer 100, the diagonal connecting lines L1 and L2 are not of equal length. This is because when removing the semiconductor wafer 100 from the bracket 126 (as shown in Figure 9 ), the parts connected to the bracket 126 are subjected to different forces, resulting in different lengths of the formed protruding portions 182.

[0149] The semiconductor wafer disclosed in this disclosure is not limited to the above-mentioned light-emitting diode wafer. Figure 12 The cross-sectional schematic diagram of the semiconductor wafer 200 in some embodiments is shown. In Figure 12In [the figure], the semiconductor wafer 200 can be an integrated circuit wafer and includes a semiconductor stack 227, a passivation layer 240, and a first electrode 250. The passivation layer 240 conformally covers the semiconductor stack 227, and the first electrode 250 penetrates the semiconductor stack and is electrically connected to the semiconductor stack 227. In addition, the passivation layer 240 includes a protrusion 282 having a fracture surface 284. The difference between the semiconductor wafer 200 and the semiconductor wafer 100 is the composition of the semiconductor stack. In some embodiments, the semiconductor stack 227 of the semiconductor wafer 200 may include a silicon layer, etc., and suitable structures such as a metal layer, an interconnect structure, and components (such as transistors, resistors, capacitors, etc.) may be formed in the semiconductor stack 227, and the first electrode 250 may be electrically connected to the components in the semiconductor stack 227.

[0150] Figure 13A A cross-sectional schematic diagram of a light-emitting device 300 using some embodiments of the present disclosure is shown. The light-emitting device 300 includes a carrier substrate 310, a light-emitting unit 320, and a control unit 330. The light-emitting unit 320 and the control unit 330 are arranged on the carrier substrate 310. The carrier substrate 310 can be a circuit board to provide power for operating the light-emitting unit 320 and the control unit 330.

[0151] The light-emitting unit 320 includes a light-emitting diode wafer 322. The light-emitting diode wafer 322 can be the semiconductor wafer 100 as described above. In the Figure 13A embodiment shown, the light-emitting diode wafer 322 is a blue light-emitting diode wafer. In some embodiments, the light-emitting unit 320 is a light-emitting unit 320B that can emit blue light.

[0152] In some other embodiments, the light-emitting unit 320 includes a light-emitting unit 320R that emits red light and a light-emitting unit 320G that emits green light. The light-emitting units 320R and 320G may further include a conversion layer and a filter respectively. In each of the light-emitting units 320R and 320G, a conversion layer 324 having quantum dots or fluorescent materials is disposed on the corresponding light-emitting diode 322 to convert the light emitted by the light-emitting diode wafer 322 into light of different wavelengths, such as red light or green light. Filters 326 for different colors are disposed on the corresponding conversion layers to filter light of specific wavelengths. For example, a red light conversion layer 324R can convert the blue light emitted by the light-emitting diode wafer 322 into red light and emit the red light through a red light filter 326R. A green light conversion layer 324G can convert the blue light emitted by the light-emitting diode wafer 322 into green light and emit the green light through a green light filter 326G. In addition to the blue light-emitting diode wafer, the light-emitting diode wafers in the light-emitting units 320R and 320G can also be other suitable wafers, such as ultraviolet light-emitting diode wafers. Each light-emitting unit 320 may have a light-blocking structure 328 to ensure that the light emitted by the light-emitting unit 320 is emitted in the desired direction and prevent crosstalk between adjacent light-emitting units 320. The red light, green light, and blue light respectively emitted by the light-emitting units 320R, 320G, and 320B can be mixed into white light and can be used in subsequent applications.

[0153] The control unit 330 includes an integrated circuit chip 332 and is electrically connected to the light-emitting unit 320. The integrated circuit chip 332 can be the semiconductor chip 200 as described above. The control unit 330 can be used to control the light-emitting unit 320, such as the brightness, on / off, etc. of the light-emitting unit 320.

[0154] In some embodiments, a glue material 340 can be filled above the light-emitting diode wafer 322 and the integrated circuit chip 332. The glue material 340 is a light-transmitting glue and can be used to prevent the light-emitting diode wafer 322, the integrated circuit chip 332, and the carrier board 310 from being damaged (such as by moisture or oxygen).

[0155] The light-emitting unit 320 and the control unit 330 can be arranged in any suitable manner. In some embodiments, the arrangement of the light-emitting unit 320 (such as the light-emitting units 320R, 320G, and 320B) and the control unit 330 is as Figure 13C shown. However, it should be noted that the arrangement of the light-emitting unit 320 and the control unit 330 is not limited to the form as Figure 13C shown. For example, the light-emitting units 320R, 320G, 320B and the control unit 330 can be arranged in sequence on the same column, as Figure 13A shown.

[0156] In some other embodiments, the light-emitting device 300 is asFigure 13B The aspect shown. In Figure 13B , the light-emitting diode wafers 322 in the light-emitting units 320R and 320G are a red light-emitting diode wafer and a green light-emitting diode wafer, respectively. Therefore, the light-emitting units 320R and 320G may not include the conversion layers 324G and 324B, respectively, and can emit red light or green light.

[0157] Figures 14 to 21 A cross-sectional schematic diagram of an intermediate manufacturing process step of a semiconductor wafer showing some other embodiments of the present disclosure, where Figures 14 to 21 is a cross-sectional view along line A-A' in Figure 23A . In Figure 14 , a first substrate 410 is provided, and a semiconductor stack 420, an active layer 424, and a transparent conductive layer 425 are deposited on the first substrate 410. The relevant details of the first substrate 410, the semiconductor stack 420, the active layer 424, and the transparent conductive layer 425 are similar to or the same as those described in Figure 1 , so the description of this aspect will not be repeated.

[0158] As Figure 15 shown, trenches 434 and 435 are formed in the semiconductor stack 420 to define the positions of the brackets 426 and the patterned semiconductor stack 427, and to define the shape of the patterned semiconductor stack 427, such as circular (as Figure 23A shown) or quadrilateral. Relative to the trenches 134 and 135 in Figure 2 , the distance between the boundaries of the trenches 434 and 435 can be shortened. Figure 15 Other relevant details of the process of Figure 2 are similar to or the same as those described in

[0159] As Figure 16 shown, a passivation layer 440 is conformally deposited on the semiconductor stack 420 and the transparent conductive layer 425. The relevant details of the passivation layer 440 are similar to or the same as those described in Figure 3 , so the description of this aspect will not be repeated. Then, a first electrode hole 442 is formed in the passivation layer 440 to expose the semiconductor stack 420 (or the transparent conductive layer 425). After forming the first electrode hole 442, a first electrode 452 is formed in the first electrode hole 442.

[0160] As Figures 17 to 19 shown, a sacrificial layer 460, a support structure layer 472, a connection layer 474, and a second substrate 476 are formed on the passivation layer 440 and the first electrode 452. Then, flip as Figure 18For the structure shown, the first substrate 410 and a portion of the semiconductor stack 420 are removed, and a bottom surface 427a is formed. The sacrificial layer 460, semiconductor layer 472, connection layer 474, second substrate 476, and related details of the process are similar or the same as those described in Figures 5 to 8 and thus the description of this aspect will not be repeated.

[0161] In some embodiments, as shown in Figure 20 , a second electrode 480 is formed on the bottom surface 427a of the semiconductor stack 427. The second electrode 480 and the first electrode 452 are respectively located on opposite sides of the semiconductor stack 420. In other embodiments, the second electrode 480 may not be formed in the semiconductor stack 420. In this step, the complete structure of the semiconductor wafer 400 is formed.

[0162] As shown in Figure 21 , the sacrificial layer 460 is removed, and the semiconductor wafer 400 is transferred to a device for subsequent applications. Figure 21 The related details of the process of Figures 5 to 9 are similar or the same as those described in

[0163] The transferred semiconductor wafer 400 is as shown in Figure 22 . The semiconductor stack 427 of the semiconductor wafer 400 has a bottom surface 427a and a top surface 427b, and there are sidewalls 428 between the bottom surface 427a and the top surface 427b. Moreover, the passivation layer 440 of the semiconductor wafer 400 includes a protrusion 482 having a fracture surface 484. The difference between the semiconductor wafer 400 and Figure 10A (or Figure 10B ) the semiconductor wafer 100 is that the first electrode 452 and the second electrode 480 of the semiconductor wafer 400 are respectively located on opposite sides of the semiconductor stack 427, while the first electrode 152 and the second electrode 154 of the semiconductor wafer 100 are located on the same side of the semiconductor stack 127. Other related details of the semiconductor wafer 400 are similar or the same as those described in Figure 10A and thus the description of this aspect will not be repeated.

[0164] Figure 23A FIG. shows a top view schematic diagram of an intermediate process step when the semiconductor wafer 400 has not been transferred in some embodiments of the present disclosure. In Figure 23AIn [description], the bracket 426 on the support structure layer 472 provides support for the semiconductor wafer 400. The passivation layer 440 of the semiconductor wafer 400 has a circular top view profile and is connected to the bracket 426 through the connecting portion 448. The semiconductor wafer 400 is arranged on the semiconductor layer 472 along the first direction X, and the first extension direction D1 of the connecting portion 448 and the first direction X jointly define an acute first angle a1. In some embodiments, the first angle a1 can be about 10 degrees to about 80 degrees, such as about 45 degrees.

[0165] Figure 23B The upper view of the light-emitting device 500 using some embodiments according to the present disclosure is shown. The semiconductor wafer 400 is transferred to the carrier plate 510, as Figure 23B shown. During the transfer process, the transfer device does not change (such as rotate) the direction of the semiconductor wafer 400. Therefore, after being transferred onto the carrier plate 510, the semiconductor wafer 400 still arranges along the first direction X. The protruding portion 482 formed after the transfer still faces the first extension direction D1, and the angle between it and the first direction X is also the first angle a1. Before or after transferring the semiconductor wafer 400, the semiconductor wafer 200 as Figure 12 shown can be transferred, and the semiconductor wafer 200 arranges along the first direction X and is electrically connected to the semiconductor wafer 400. The extension direction of the protruding portion 282 of the semiconductor wafer 200 is the second extension direction D2, and the second extension direction D2 and the first direction X jointly define an acute second angle a2. In some embodiments, the second angle a2 can be about 10 degrees to about 80 degrees, such as about 45 degrees. After the transfer of the semiconductor wafers 400 and 200 is completed, other structures similar to Figures 13A to 13B can be further formed, such as a conversion layer, a filter, a light-transmitting adhesive, and an opaque structure, etc., to manufacture a display device.

[0166] Although Figure 23B the transferred semiconductor wafer 400 is shown to have 2 protruding portions 482, the number of the protruding portions 482 is not limited thereto. In some embodiments, the number of the connecting portions of each semiconductor wafer 400 in Figure 21 can be adjusted so that the number of the protruding portions 482 of the semiconductor wafer 400 can be changed, as Figure 23C shown. In addition, in some embodiments, some of the semiconductor wafers 400 and 200 on the carrier plate 510 can be different from the state as Figure 23B shown. For example, the protruding portions of some of the semiconductor wafers 400 and 200 can be parallel to the first direction X.

[0167] In summary, some embodiments of the present disclosure change the position of the carrier of the semiconductor wafer and minimize the area of the carrier, thus producing more wafers on each wafer. In addition, since the area of the carrier of the wafer is minimized, the remaining carrier area on the transferred wafer becomes smaller. Accordingly, the light-emitting effect of the semiconductor wafer can be improved.

[0168] Although the present invention has been disclosed as above in embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor wafer, characterized in that, Comprising: A semiconductor stack including a top surface, a bottom surface, and a plurality of sidewalls located between the opposite top and bottom surfaces; and A passivation layer conformally covering the top surface and the plurality of sidewalls of the semiconductor stack; Wherein, when viewed from above the bottom surface, the top view profile of the semiconductor stack includes a plurality of edges and a plurality of corners, each of the corners being defined by two adjacent ones of the edges, the top view profile of the passivation layer surrounds the top view profile of the semiconductor stack, and the top view profile of the passivation layer includes a plurality of protrusions, the plurality of protrusions being respectively adjacent to one of the plurality of corners and protruding outward from the top view profile of the passivation layer, and the plurality of protrusions having different extension lengths.

2. The semiconductor wafer according to claim 1, wherein, The plurality of protrusions of the passivation layer respectively have a fracture surface.

3. The semiconductor wafer according to claim 1, wherein The bottom surface includes an uneven structure.

4. The semiconductor wafer according to claim 1, wherein, The semiconductor wafer is a light-emitting diode wafer, and the semiconductor wafer further includes a first electrode located on the passivation layer; wherein, the semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and the first electrode penetrates the passivation layer to be electrically connected to the first semiconductor layer.

5. The semiconductor wafer according to claim 4, wherein Further comprising a second electrode located on the passivation layer and penetrating the passivation layer to be electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are located on the same side of the semiconductor stack.

6. The semiconductor wafer according to claim 4, wherein Further comprising a second electrode located on the bottom surface of the semiconductor stack and electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

7. The semiconductor wafer according to claim 1, characterized in that, The semiconductor wafer is an integrated circuit wafer, and the semiconductor wafer further includes a first electrode located on the semiconductor stack and electrically connected to the semiconductor stack.

8. A light-emitting device, characterized in that, Comprising: A carrier plate; A plurality of light-emitting units located on the carrier plate, each of the plurality of light-emitting units emitting red light, green light, or blue light, and having a light-blocking structure between any two adjacent ones of the light-emitting units, wherein at least one of the light-emitting units includes a semiconductor wafer as described in any one of claims 1 to 6; and A control unit located on the carrier plate, wherein the control unit is electrically connected to at least one of the plurality of light-emitting units.

9. A semiconductor wafer, characterized in that, Comprising: A semiconductor stack including a top surface, a bottom surface, and a plurality of sidewalls located between the opposite top and bottom surfaces; and A passivation layer conformally covering the top surface and the plurality of sidewalls of the semiconductor stack; Wherein, when viewed from above in the direction of the bottom surface, the top view profile of the semiconductor wafer is a closed shape including a plurality of edges and a plurality of corners, each of the corners being defined by two adjacent ones of the edges, and at least two of the plurality of corners respectively have a fracture surface, and the plurality of fracture surfaces have different shapes.

10. The semiconductor wafer according to claim 9, wherein, Within the range of the top view profile of the semiconductor wafer, the connecting lines of any two non-adjacent corners among the plurality of corners are not of equal length.

11. The semiconductor wafer according to claim 9, wherein The semiconductor wafer is a light-emitting diode wafer, and the semiconductor wafer further includes a first electrode located on the passivation layer; wherein, the semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and the first electrode penetrates through the passivation layer to be electrically connected to the first semiconductor layer.

12. The semiconductor wafer according to claim 11, wherein, It further includes a second electrode located on the passivation layer and penetrating through the passivation layer to be electrically connected to the second semiconductor layer; wherein, the first electrode and the second electrode are located on the same side of the semiconductor stack.

13. The semiconductor wafer according to claim 11, wherein It further includes a second electrode located on the bottom surface of the semiconductor stack and electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

14. The semiconductor wafer according to claim 9, wherein The semiconductor wafer is an integrated circuit wafer, and the semiconductor wafer further includes a first electrode located on the semiconductor stack and electrically connected to the semiconductor stack.

15. A light-emitting device, characterized in that, Comprising: A carrier board; A plurality of light-emitting units located on the carrier board, each of the plurality of light-emitting units emitting red light, green light, or blue light, and there is a light-blocking structure between any two adjacent light-emitting units, wherein at least one of the light-emitting units includes a semiconductor wafer as described in any one of claims 9 to 13; and A control unit located on the carrier board, wherein the control unit is electrically connected to at least one of the plurality of light-emitting units.

16. The semiconductor wafer according to claim 9, wherein, The top view profile of the semiconductor wafer is a closed quadrilateral including four edges and four corners.

17. A light-emitting device, characterized in that, Comprising: A carrier board; and A plurality of light-emitting diode wafers located on the carrier board and arranged at least along a first direction, wherein at least one of the plurality of light-emitting diode wafers includes: A semiconductor stack including a top surface, a bottom surface, and at least one sidewall located between the opposite top surface and bottom surface, wherein the semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; and A passivation layer conformally covering the top surface and the sidewall of the semiconductor stack, and the passivation layer includes a protrusion, an extending direction of the protrusion and the first direction jointly define a first angle, and the first angle is an acute angle, and when viewed from the bottom surface direction, the passivation layer has a circular top view profile.

18. The light-emitting device according to claim 17, characterized in that, The protrusion of the passivation layer has a fracture surface.

19. The light-emitting device according to claim 17, wherein Each of the plurality of light-emitting diode wafers further includes a first electrode and a second electrode, and the first electrode and the second electrode are respectively located on opposite sides of the semiconductor stack.

20. The light-emitting device according to claim 17, wherein It further includes an integrated circuit wafer located on the carrier board, wherein the integrated circuit wafer is electrically connected to at least one of the plurality of light-emitting diode wafers.

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