Magnetoresistive random access memory structure and method of making same

Abstract

A magnetoresistive random access memory structure and a method of fabricating the same are disclosed. The magnetoresistive random access memory structure includes a plurality of magnetoresistive random access memory cells. An atomic layer deposition dielectric layer is disposed outside and between the magnetoresistive random access memory cells. A material of an upper electrode layer of the magnetoresistive random access memory cells is titanium nitride. A nitrogen composition ratio in the titanium nitride is greater than a titanium composition ratio and greater than an oxygen composition ratio. The nitrogen composition ratio increases from a top surface of the upper electrode layer to an inside of the upper electrode layer until reaching a depth, and then decreases to a first level and remains unchanged. The titanium composition ratio decreases from the top surface of the upper electrode layer to the inside of the upper electrode layer until reaching the depth, and then increases to a second level and remains unchanged.

Description

TECHNICAL FIELD

[0001] The present invention relates to a magnetoresistive random access memory, and more particularly, to a magnetoresistive random access memory structure with a special material ratio distribution in the upper electrode layer and a related fabrication process. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with the application of a magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, which represents the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetoresistive random access memory (MRAM) can be made, which has the advantage of being able to continuously retain stored data without power.

[0003] Magnetoresistive random access memory (MRAM) has received much attention in recent years as a new type of memory that integrates the advantages of various types of memory, such as comparable access speed to static random access memory (SRAM), non-volatility and low power consumption to flash memory, high density and durability to dynamic random access memory (DRAM), and can be fabricated with the current semiconductor back-end fabrication process, thus having the potential to become the main memory used in semiconductor chips.

[0004] Magnetoresistive random access memory includes a memory stack structure disposed between upper and lower interconnect structures, which contains a magnetic tunneling junction (MTJ). Unlike conventional memory, which stores data by storing electric charge, the operation of magnetoresistive random access memory is to control the magnetization direction of the MTJ by applying an external magnetic field to the MTJ to obtain different tunneling magnetoresistive (TMR) to store digital data. SUMMARY

[0005] The present invention proposes a method for fabricating a magnetoresistive random access memory, characterized in that a back-etching fabrication process and a wet-etching fabrication process are used in the fabrication process to form an atomic layer deposition dielectric layer around the magnetoresistive random access memory, and the composition ratio of the upper electrode of the magnetoresistive random access memory is changed as a result.

[0006] One aspect of the present application is to provide a magnetoresistive random access memory structure, comprising a plurality of magnetoresistive random access memory cells, wherein each of the magnetoresistive random access memory cells comprises a lower electrode layer, a magnetic tunnel junction stack layer above the lower electrode layer, and an upper electrode layer above the magnetic tunnel junction stack layer, an atomic layer deposition dielectric layer outside and between the magnetoresistive random access memory cells, wherein the upper electrode layer is made of titanium nitride, the nitrogen content in the titanium nitride is greater than the titanium content, and the nitrogen content is greater than the oxygen content, the nitrogen content increases from the top surface of the upper electrode layer to a depth and then decreases to a first level and remains constant, and the titanium content decreases from the top surface of the upper electrode layer to the depth and then increases to a second level and remains constant.

[0007] Another aspect of the present application is to provide a method for manufacturing a magnetoresistive random access memory, comprising the steps of providing a substrate, sequentially forming a lower electrode layer, a magnetic tunnel junction stack layer, and an upper electrode layer above the substrate, patterning the lower electrode layer, the magnetic tunnel junction stack layer, and the upper electrode layer into a plurality of magnetoresistive random access memory cells, blanket coating an atomic layer deposition dielectric layer on the magnetoresistive random access memory cells and the substrate, removing the atomic layer deposition dielectric layer on the upper electrode layer and the substrate by a back-etching manufacturing process, leaving the atomic layer deposition dielectric layer between and outside the magnetoresistive random access memory cells, and performing a wet cleaning manufacturing process on the magnetoresistive random access memory cells after the back-etching manufacturing process, wherein the upper electrode layer is made of titanium nitride, the nitrogen content in the titanium nitride is greater than the titanium content, and the nitrogen content is greater than the oxygen content, the back-etching manufacturing process and the wet cleaning manufacturing process cause the nitrogen content in the upper electrode layer to increase from the top surface of the upper electrode layer to a depth and then decrease to a first level and remain constant, and the nitrogen content to decrease from the top surface of the upper electrode layer to the depth and then increase to a second level and remain constant.

[0008] These and other objects of the present application will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are shown in a variety of contexts. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present application. These drawings, together with the description, explain the principles of the application. In the drawings:

[0010] Figures 1 to 7A cross-sectional schematic diagram of a manufacturing process of a magnetoresistive random access memory according to an embodiment of the present application; and

[0011] Figure 8 A graph of the depth of the upper electrode layer versus the composition ratio thereof of a magnetoresistive random access memory according to an embodiment of the present application.

[0012] It is to be noted that all drawings in the present specification are schematic in nature and for purposes of clarity with respect to understanding the concepts presented therein. Although the drawings can be very detailed, it is to be noted that the various drawings can not be to scale and the dimensions of the various features can have been exaggerated or minimized for the sake of clarity. It is also to be noted that like reference numerals are intended to refer to like and corresponding features throughout the various drawings.

[0013] Main element symbol explanation

[0014] 100 inter-metal dielectric layer

[0015] 100a memory area

[0016] 100b logic area

[0017] 102 stop layer

[0018] 104 dielectric layer

[0019] 104a surface

[0020] 106 metal interconnect layer

[0021] 108 via

[0022] 110 lower electrode layer

[0023] 112 magnetic tunnel junction stack

[0024] 114 upper electrode layer

[0025] 116 magnetoresistive random access memory cell

[0026] 118 liner

[0027] 118a spacer

[0028] 120 atomic layer deposition dielectric layer

[0029] 120a recess

[0030] 122 inter-metal dielectric layer

[0031] 123 dual damascene recess

[0032] 124 stop layer

[0033] 126 inter-metal dielectric layer

[0034] 128 stop layer

[0035] d1 depth

[0036] L1 first level

[0037] L2 second level

[0038] M3, M4 metal interconnect layer

[0039] V2, V3 via DETAILED DESCRIPTION

[0040] Embodiments of the present application will now be described in detail with reference to the drawings, where:

[0041] It should be readily understood that the terms "on", "above", and "upper" are used in their broadest sense and mean that one element can be directly on another element or can be indirectly on another element with intervening elements present. It should also be readily understood that the term "over" is used in its broadest sense and means that one element can be directly over another element or can be indirectly over another element with no intervening elements present (i.e., directly on another element).

[0042] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0043] Reference will now be made to Figures 1 to 7 , Figures 1 to 7 FIG. 1 is a cross-sectional view of a method of fabricating a magnetic random access memory (MRAM) according to an embodiment of the present application. As shown in FIG. 1, a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. The substrate 100 can also be a glass substrate, a ceramic substrate, a metal substrate, or other suitable substrate. The substrate 100 can be a single crystal substrate or a polycrystalline substrate. The substrate 100 can also be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate. Figure 1As shown, a substrate (not shown), such as one made of semiconductor material, is first provided, which can be selected from a group consisting of silicon, germanium, silicon-germanium compound, silicon-carbon compound, gallium arsenide, and the like. The substrate is preferably defined with a memory region 100a and a logic region 100b, which are used to set up a memory array and logic circuitry (e.g., word lines or peripheral circuitry), respectively. It is noted that the focus of the present application is on the structure of magnetoresistive random access memory cells and related fabrication processes on the memory region 100a.

[0044] Referring again to Figure 1 , an inter-metal dielectric layer (IMD) 100, a stop layer 102, and a dielectric layer 104 are sequentially formed on the substrate, which can be formed by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) process. In the embodiment of the present application, the inter-metal dielectric layer 100 can be an inter-metal dielectric layer in a lower interconnect level (e.g., second metal layer M2), which is preferably made of ultra low-k (ULK) material, such as porous silicon oxide-carbon (SiOC). A metal interconnect layer 106, such as second metal layer M2, can be formed in the inter-metal dielectric layer 100. The material of the stop layer 102 is preferably silicon carbon nitride (SiCN), nitrogen doped carbide (NDC), or silicon nitride, which can be used as an etch stop layer when fabricating an upper contact hole. The material of the dielectric layer 104 is preferably tetraethoxysilane (TEOS), but is not limited thereto, in which a via 108 is formed through the underlying stop layer 102 to electrically connect with the metal interconnect layer 106 in the memory region 100a. The material of the metal interconnect layer 106 and the via 108 can be selected from a group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but is not limited thereto.

[0045] Referring again to Figure 1, a lower electrode layer 110, a magnetic tunnel junction (MTJ) stack 112, and an upper electrode layer 114 are sequentially formed on the dielectric layer 104. The lower electrode layer 110, the MTJ stack 112, and the upper electrode layer 114 can be formed in-situ in the same chamber using physical vapor deposition (PVD). In an embodiment of the present application, the material of the lower electrode layer 110 preferably comprises a conductive material, such as tantalum nitride (TaN), but is not limited thereto. According to other embodiments of the present application, the lower electrode layer 110 can also comprise tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. The MTJ stack 112 is a multi-layer structure, which can comprise a seed layer, a pinned layer, a reference layer, a tunnel barrier layer, a free layer, and a metal spacer layer, etc. In general, the pinned layer can be composed of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to pin or limit the direction of the magnetic moment of the adjacent layer. The tunnel barrier layer can be composed of an insulating material including an oxide, such as aluminum oxide (AlO X ) or magnesium oxide (MgO), but is not limited thereto. The free layer can be composed of a ferromagnetic material, such as iron, cobalt, nickel, or an alloy thereof, such as cobalt-iron-boron (CoFeB), but is not limited thereto. The magnetization direction of the free layer is "free" to change under an external magnetic field. Since the structure of the MTJ stack 112 is not the focus of the present application, the MTJ stack 112 is used to generally represent the above-mentioned multi-layer structure in the figure. The material of the upper electrode layer 114 is titanium nitride (TiN).

[0046] Next, as shown in FIG. 1C, a first photoresist layer 116 is formed on the upper electrode layer 114. The first photoresist layer 116 can be formed by spin coating, and can be composed of a photoresist material, such as polymethyl methacrylate (PMMA), polyhydroxystyrene (PHS), or a combination thereof, but is not limited thereto. The first photoresist layer 116 can be patterned by photolithography, and can be used as a mask to etch the upper electrode layer 114, the MTJ stack 112, and the lower electrode layer 110. Figure 2As shown, the upper electrode layer 114, the magnetic tunneling junction stack 112, and the lower electrode layer 110 are patterned using photolithography and etching processes to define individual magnetoresistive random access memory (RAM) cells 116. Specifically, the upper electrode layer 114 can be patterned first using reactive ion etching (RIE) in conjunction with a silicon oxide hard mask layer, resulting in fewer sidewall byproducts. Next, the magnetic tunneling junction stack 112 and the lower electrode layer 110 are patterned using ion beam etching (IBE) to define the RAM cells 116. Due to the characteristics of the ion beam etching process, the surface 104a of the remaining dielectric layer 104 after etching is preferably slightly lower than the upper surface of the via 108, and the surface 104a of the dielectric layer 104 preferably has an arc or curved shape. Following the patterning process, a conformal substrate 118 is formed on the surfaces of the magnetoresistive random access memory (RAM) cells 116 and the dielectric layer 104. The substrate 118 is preferably made of silicon nitride, but other dielectric materials, such as silicon oxide, silicon oxynitride, or silicon carbide, can be selected depending on the fabrication requirements. The substrate 118 has a uniform thickness and covers the RAM cells 116 and the dielectric layer 104. It should be noted that although only two RAM cells 116 are shown in the figures, those skilled in the art will understand that a memory region or memory array can contain a large number of memory cells.

[0047] Then as Figure 3 As shown, an etching process, such as an anisotropic etching process, is performed to remove a certain thickness of the substrate 118, leaving only the substrate 118 located on the side of the magnetoresistive random access memory cell 116, forming a spacer 118a. The spacer 118a covers the magnetic tunneling junction stack 112 and the lower electrode layer 110 of the magnetoresistive random access memory cell 116 to provide protection and isolation. Other areas outside the magnetoresistive random access memory cell 116 are not covered by the substrate 118 or the spacer 118a. The upper electrode layer 110 of the magnetoresistive random access memory cell 116 is exposed through the spacer 118a.

[0048] Then as Figure 4As shown, an atomic layer deposition dielectric layer 120 is blanketed on the magnetoresistive random access memory cell 116 and the dielectric layer 104. The material of this dielectric layer may include, but is not limited to, tetraethylorthosilicate (TEOS), silicon oxide, silicon nitride, or combinations thereof. Compared to the prior art method of directly using ultra-low dielectric constant (ULK) materials to cover the magnetoresistive random access memory cell 116, this embodiment uses an atomic layer deposition (ALD) process to form an additional dielectric layer, which effectively avoids voids between the magnetoresistive random access memory cells 116, achieving higher surface coverage. The surface of the atomic layer deposition dielectric layer 120 follows the surface undulations of the substrate, especially exhibiting higher surface protrusions at the location of the magnetoresistive random access memory cell 116.

[0049] Then as Figure 5 As shown, an etch-back process, such as an anisotropic dry etching process, is performed on the atomic layer deposited dielectric layer 120 to remove the atomic layer deposited dielectric layer 120 located outside the memory region 100a and above the magnetoresistive random access memory cell 116 and the spacer 118a. This ensures that the logic region 100b is not covered by the atomic layer deposited dielectric layer 120, and the upper electrode layer 114 and the spacer 118a of the magnetoresistive random access memory cell 116 can be exposed from the atomic layer deposited dielectric layer 120. Due to the etch-back process, the surface of the atomic layer deposited dielectric layer 120 located around the magnetoresistive random access memory cell 116 will be curved and recessed to the boundary between the memory region 100a and the logic region 100b. The etch-back atomic layer deposited dielectric layer 120 will still fill the gaps between the magnetoresistive random access memory cells 116, and a recess 120a will exist at that location.

[0050] In this embodiment of the invention, a wet cleaning process is performed after the above-mentioned etch-back fabrication process, for example, using DuPont's... A 580 solution is used to remove metal oxides or residual polymers formed on the surface of the magnetoresistive random access memory cell 116. The alkaline hydrogen peroxide component in the 580 solution oxidizes part of the exposed titanium nitride upper electrode layer 114, producing titanium oxide products (TiO2). 2+ The titanium dioxide product combines with water and dissolves in water. Its chemical formula is shown in the following formulas (1) and (2):

[0051] TiN + 3H₂O + H₂O₂ → TiO₂ 2+ +3OH - +NH4OH…(1)

[0052] TiO2+ + H2O [OH-] → TiO 2+ · H2O … (2)

[0053] On the other hand, the hydrogen peroxide component can also react with the polymer (e.g. hydrofluorocarbon C x H y F z ) produced in the aforementioned etch-back fabrication process to produce a water-soluble hydrofluorocarbon oxide C x H y F z O a product, while the dilute hydrogen fluoride component in the solution can react with the metal oxide component (e.g. undissolved titanium oxide) remaining on the surface after the fabrication process to produce a water-soluble metal oxyfluoride, as shown in the following formulas (3) and (4):

[0054] C x H y F z + H2O2→ C x H y F z O a … (3)

[0055] MO x + HF→ MO y F z - … (4)

[0056] The aforementioned water-soluble reaction products can all be removed in the wet cleaning process, achieving the cleaning effect.

[0057] Since in the embodiments of the present application, the etch-back fabrication process is used to remove part of the atomic layer deposition dielectric layer 120, and the wet cleaning fabrication process is used to clean the surface after the fabrication process, the composition of the exposed titanium nitride material upper electrode layer 114 will be affected and changed by these fabrication processes, as shown in the following formula (5): Figure 8 Figure 8 ​Fig. 6 is a graph showing the depth profile of the composition ratio of the upper electrode layer 114. The x-axis represents the depth from the surface of the upper electrode layer 114, and the y-axis represents the ratio of the composition of nitrogen (N), titanium (Ti), oxygen (O), etc. in the upper electrode layer 114 at the depth. As shown in Fig. 6, in the embodiment of the present application, the ratio of nitrogen and titanium at the surface of the upper electrode layer 114 is approximately the same. The ratio of nitrogen composition increases from the top surface of the upper electrode layer 114 to the depth dl, and then decreases to the first level LI and remains constant. The ratio of titanium composition decreases from the top surface of the upper electrode layer 114 to the depth dl, and then increases to the second level L2 and remains constant. The second level L2 is less than the first level LI. In the embodiment of the present application, there is a small amount of oxygen composition in the upper electrode layer 114, and the ratio of the oxygen composition decreases from the top surface of the upper electrode layer 114 to 0%. Basically, the ratio of nitrogen composition is greater than the ratio of titanium composition, and the ratio of titanium composition is greater than the ratio of oxygen composition.

[0058] In the embodiment of the present application, the reason for the composition ratio profile of the upper electrode layer 114 is due to the aforementioned etching back process and the wet cleaning process. Due to the bombardment effect of the plasma ions and the chemical reaction of nitrogen gas in the etching back process, the ratio of nitrogen composition in the upper electrode layer 114 increases from the surface to the depth dl, and then decreases to the first level LI and remains constant. The ratio of titanium composition in the upper electrode layer 114 changes in the opposite direction, and decreases from the surface to the depth dl, and then increases to the second level L2 and remains constant. The ratio of oxygen composition in the upper electrode layer 114 is due to the hydrogen peroxide in the wet cleaning process. Since the wet cleaning process does not apply ion bombardment, the ratio of the oxygen composition decreases from the top surface of the upper electrode layer 114 to 0%.

[0059] Next, as shown in Fig. 7, the upper electrode layer 114 is formed on the substrate 110. The upper electrode layer 114 is formed by the etching back process and the wet cleaning process. The etching back process is performed by using a mixture of argon (Ar) and nitrogen (N2) as the plasma gas. The wet cleaning process is performed by using hydrogen peroxide (H2O2) as the cleaning agent. Figure 6As shown, another intermetal dielectric layer 122 is formed on the atomic layer deposition dielectric layer 120 to fill up the area outside the memory region 100a, such as the logic region. The intermetal dielectric layer 122 is planarized by a planarization process, such as chemical mechanical polishing (CMP), to have an upper surface slightly higher than the upper electrode layer 114 of the magnetoresistive random access memory cell 116, so as to provide a planar surface for subsequent fabrication processes. The recesses 120a of the atomic layer deposition dielectric layer 120 between the magnetoresistive random access memory cells 116 are also filled up by the intermetal dielectric layer 122. In an embodiment of the present application, the material of the intermetal dielectric layer 122 is preferably an ultra low k (ULK) material. It is noted that the dielectric constant of the atomic layer deposition dielectric layer 120 is different from that of the intermetal dielectric layer 122.

[0060] Next, as shown in Figure 7 An dual damascene recess 123 is formed in the intermetal dielectric layer 122, which includes a via and a metal interconnect layer. The dual damascene recess 123 can be formed by a dual damascene fabrication process, which is connected to the metal interconnect layer 106, such as the second metal layer M2, in the underlying logic region 100b. Then, a desired metal material is filled in the dual damascene recess 123, such as a barrier layer including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like, and a low resistance metal layer selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, or a combination thereof. Then, a planarization fabrication process is performed, such as a chemical mechanical polishing fabrication process, to remove part of the metal material to form a dual damascene structure including a via V2 and a metal interconnect layer M3, the via V2 being electrically connected to the metal interconnect layer 106 in the underlying logic region 100b.

[0061] Referring again to Figure 7After the via V2 and the metal interconnect layer M3 are formed, another stop layer 124 and an intermetal dielectric layer 126 are formed on the surface of the intermetal dielectric layer 122 and the metal interconnect layer M3. The stop layer 124 can be made of the same material as the stop layer 102, such as silicon carbon nitride (SiCN), nitrogen doped carbide (NDC), or silicon nitride. The intermetal dielectric layer 126 can be made of the same material as the intermetal dielectric layer 122, such as an ultra low k (ULK) material. After the stop layer 124 and the intermetal dielectric layer 126 are formed, the dual damascene process described above is performed again to form an upper via V3 and a metal interconnect layer M4. The via V3 above the memory region 100a is electrically connected to the upper electrode layer 114 of the MRAM cell 116, and the via V3 above the logic region 100b is electrically connected to the lower metal interconnect layer M3. After the via V3 and the metal interconnect layer M4 are formed, another stop layer 128 can be formed on the surface of the intermetal dielectric layer 126, and the steps of forming the via and the metal interconnect layer can be repeated again.

[0062] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the present application.

Claims

1. A magnetoresistive random access memory structure, characterized in that, include: A plurality of magnetoresistive random access memory (RAM) cells, wherein each of the magnetoresistive RAM cells includes: The lower electrode layer is located above the substrate; A magnetic tunneling stack is located above the lower electrode layer; and The upper electrode layer is located above the magnetic tunneling stack; An atomic layer is deposited dielectric layer located outside the magnetoresistive random access memory cells and between the magnetoresistive random access memory cells. The material of the upper electrode layer is titanium nitride. The proportion of nitrogen in the titanium nitride is greater than the proportion of titanium and then greater than the proportion of oxygen. The proportion of nitrogen increases from the top surface of the upper electrode layer inward until it reaches a certain depth, then decreases to a first level and then remains flat. The proportion of titanium decreases from the top surface of the upper electrode layer inward to that depth, then increases to a second level and then remains flat.

2. The magnetoresistive random access memory structure according to claim 1, wherein the oxygen content decreases to 0% from the top surface of the upper electrode layer toward the interior.

3. The magnetoresistive random access memory structure according to claim 1, wherein the nitrogen content in the titanium nitride is between greater than 0% and less than 50%.

4. The magnetoresistive random access memory structure according to claim 1, wherein the magnetic tunneling junction stack comprises a seed layer, a fixed layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator.

5. The magnetoresistive random access memory structure according to claim 1 further includes a spacer wall between the magnetoresistive random access memory cell and the atomic layer deposited dielectric layer.

6. The magnetoresistive random access memory structure according to claim 1 further includes an intermetallic dielectric layer covering the magnetoresistive random access memory cells and the atomic layer deposited dielectric layer.

7. The magnetoresistive random access memory structure according to claim 1, wherein the lower electrode layer and the lower electrode layer are electrically connected to the metal interconnect layers in the lower and upper layers respectively through vias.

8. A method for manufacturing a magnetoresistive random access memory, comprising: Provide a base; A lower electrode layer, a magnetic tunneling stack, and an upper electrode layer are sequentially formed on the substrate. The lower electrode layer, the magnetic tunneling junction stack, and the upper electrode layer are patterned into multiple magnetoresistive random access memory cells. A dielectric layer is blanketed on the substrate between the magnetoresistive random access memory cells and the substrate, wherein the atomic layer deposited dielectric layer fills the gaps between the magnetoresistive random access memory cells. The atomic layer deposited dielectric layer is removed by an etch-back process, leaving only the atomic layer deposited dielectric layer located between and on the outside of the magnetoresistive random access memory cells. as well as After the etching process, the magnetoresistive random access memory cells are subjected to a wet cleaning process. The material of the upper electrode layer is titanium nitride, in which the nitrogen content is greater than the titanium content and also greater than the oxygen content. The bombardment effect of plasma ions and the chemical reaction of nitrogen gas in the back etching process, along with the wet cleaning process, cause the nitrogen content in the upper electrode layer to increase from the top surface of the upper electrode layer inwards until a certain depth, then decrease to a first level and remain flat. The nitrogen content then increases from the top surface of the upper electrode layer inwards to that depth and then increases to a second level and remains flat.

9. The method for manufacturing a magnetoresistive random access memory according to claim 8, wherein the hydrogen peroxide in the etch-back process and the wet cleaning process causes the oxygen content in the upper electrode layer to decrease to 0% from the top surface of the upper electrode layer downwards.

10. The method for manufacturing a magnetoresistive random access memory according to claim 8, wherein the wet cleaning manufacturing process uses... 580 solution.

11. The method for manufacturing a magnetoresistive random access memory according to claim 8, wherein the nitrogen content in the titanium nitride is between greater than 0% and less than 50%.

12. The method for manufacturing a magnetoresistive random access memory according to claim 8, wherein the magnetic tunneling junction stack comprises a seed layer, a fixed layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator.

13. The method for manufacturing a magnetoresistive random access memory according to claim 8 further comprises: Before forming the atomic layer deposited dielectric layer, a liner is formed on the magnetoresistive random access memory cells and the substrate; and Another etching process is performed to remove part of the substrate, leaving only the substrate located on the sides of the magnetoresistive random access memory cells, thus forming a spacer between the magnetoresistive random access memory cells and the atomic layer deposited dielectric layer.

14. The method for manufacturing a magnetoresistive random access memory according to claim 8 further comprises forming an intermetallic dielectric layer on the magnetoresistive random access memory cells and the atomic layer deposition dielectric layer.

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