Phase-shifted full-bridge soft switching circuit and driving method and device thereof

Abstract

The application provides a phase-shift full-bridge soft switching circuit and a driving method and device thereof. The circuit comprises a full-bridge circuit, a synchronous rectification circuit, a control module and a magnetic device. The full-bridge circuit and the synchronous rectification circuit are both composed of switching tubes. The control module generates driving signals for driving the switching tubes according to the collected load voltage and load current. The phase-shift full-bridge soft switching circuit provided by the application has better versatility, stronger anti-interference and portability, and can greatly shorten the development cycle and reduce the cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of phase-shifted full-bridge soft switching, and in particular to a phase-shifted full-bridge soft switching circuit and a driving method and device thereof. BACKGROUND

[0002] In the field of switching power supply, the phase-shifted full-bridge soft switching direct current to direct current (DC / DC) converter technology is increasingly mature, and gradually becomes the first topology structure of medium and high power direct current converter. Influenced by the complexity of the scheme and the cost and other factors, the secondary winding of the transformer in the traditional phase-shifted full-bridge soft switching DC / DC converter is mostly in a diode uncontrolled rectification mode. However, in the application of low-voltage and large-current output, the conduction loss caused by the diode uncontrolled rectification mode is larger than that of the metal oxide semiconductor field effect transistor (MOSFET) switch tube, so the diode uncontrolled rectification mode is gradually replaced by the synchronous rectification mode.

[0003] At present, one application of the synchronous rectification mode is an analog control chip integrated with a phase-shifted full-bridge and a synchronous rectification drive. The analog control chip can realize the generation of the phase-shifted full-bridge and the synchronous rectification drive. However, the driving timing of the analog control chip is greatly affected by the peripheral matching circuit, is easily disturbed and has poor portability. Moreover, once the peripheral matching circuit is formed, the subsequent new requirements will have a large amount of changes, and often need to be upgraded or revised to meet the requirements, which has a long development cycle and high cost. SUMMARY

[0004] The present application provides a phase-shifted full-bridge soft switching circuit and a driving method and device thereof to solve the defects in the generation of the phase-shifted full-bridge and the synchronous rectification drive by the analog control chip.

[0005] In a first aspect, the present application provides a phase-shifted full-bridge soft switching circuit, comprising a full-bridge circuit, a synchronous rectification circuit, a control module and a magnetic device, the full-bridge circuit and the synchronous rectification circuit are both composed of switch tubes; the control module is used for generating a driving signal for driving each switch tube according to the collected load voltage and load current.

[0006] Optionally, a first input end of the full-bridge circuit is connected with a direct current input bus voltage, and a second input end of the full-bridge circuit is connected with the ground;

[0007] One end of a primary winding of the magnetic device is connected with a lagging bridge arm output end of the full-bridge circuit through a first inductor, and the other end of the primary winding of the magnetic device is connected with a leading bridge arm output end of the full-bridge circuit through a first capacitor;

[0008] The first input end of the synchronous rectification circuit is connected with a first end of the secondary winding of the magnetic device, the second input end of the synchronous rectification circuit is connected with a second end of the secondary winding of the magnetic device, and the output end of the synchronous rectification circuit is connected with the load.

[0009] The intermediate tap of the secondary winding of the magnetic device is grounded.

[0010] Optionally, the switch tube includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the lagging bridge arm includes the first switch tube and the second switch tube, and the leading bridge arm includes the third switch tube and the fourth switch tube.

[0011] The drain of the first switch tube is connected with the drain of the third switch tube, and the connection end serves as the first input end of the full-bridge circuit.

[0012] The source of the second switch tube is connected with the source of the fourth switch tube, and the connection end serves as the second input end of the full-bridge circuit.

[0013] The source of the first switch tube is connected with the drain of the second switch tube, and the connection end serves as the lagging bridge arm output end of the full-bridge circuit.

[0014] The source of the third switch tube is connected with the drain of the fourth switch tube, and the connection end serves as the leading bridge arm output end of the full-bridge circuit.

[0015] The gates of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are respectively connected with different output ends of the control module, for inputting respective corresponding driving signals.

[0016] Optionally, the switch tube includes a fifth switch tube and a sixth switch tube, and the synchronous rectification circuit includes the fifth switch tube and the sixth switch tube.

[0017] The source of the fifth switch tube serves as the first input end of the synchronous rectification circuit.

[0018] The source of the sixth switch tube serves as the second input end of the synchronous rectification circuit.

[0019] The drain of the fifth switch tube is connected with the drain of the sixth switch tube, and the connection end serves as the output end of the synchronous rectification circuit.

[0020] The gates of the fifth switch tube and the sixth switch tube are respectively connected with different output ends of the control module, for inputting respective corresponding driving signals.

[0021] Optionally, the phase-shifted full-bridge soft switching circuit further includes a second capacitor and a second inductor, the output end of the synchronous rectification circuit is connected with the load through the second inductor, and the second capacitor is connected in parallel with the load.

[0022] Optionally, the control module comprises a first pulse width modulation unit, a second pulse width modulation unit, a third pulse width modulation unit, a fourth pulse width modulation unit and a processing unit; wherein:

[0023] the processing unit is configured to determine a phase shift amount according to the load voltage and the load current, and transmit the phase shift amount to the second pulse width modulation unit; and determine a first dead time, a second dead time and a third dead time according to the load current, the first dead time being a dead time of driving signals of different switching tubes contained in a lagging bridge arm in the full-bridge circuit, the second dead time being a dead time of driving signals of different switching tubes contained in a leading bridge arm in the full-bridge circuit, and the third dead time being a dead time of a driving signal of a switching tube in the synchronous rectification circuit and a driving signal of a switching tube contained in the lagging bridge arm;

[0024] the first pulse width modulation unit is configured to generate the driving signals for driving the different switching tubes contained in the lagging bridge arm according to the first dead time;

[0025] the second pulse width modulation unit is configured to generate the driving signals for driving the different switching tubes contained in the leading bridge arm according to the second dead time and the phase shift amount;

[0026] the third pulse width modulation unit is configured to generate the driving signal for driving the switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount;

[0027] the fourth pulse width modulation unit is configured to generate the driving signal for driving another switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount.

[0028] Optionally, when determining the phase shift amount according to the load voltage and the load current, the processing unit is specifically configured to:

[0029] compare the load voltage with a preset voltage to obtain a first difference value;

[0030] perform proportional integral (PI) control on the first difference value to obtain a target current;

[0031] compare the target current with the load current to obtain a second difference value;

[0032] perform PI control on the second difference value to obtain the phase shift amount.

[0033] Optionally, the first pulse width modulation unit is further configured to generate a synchronization signal and output the synchronization signal to the second pulse width modulation unit;

[0034] The second pulse width modulation unit is also configured to output the synchronization signal to a third pulse width modulation unit.

[0035] The third pulse width modulation unit is also configured to output the synchronization signal to a fourth pulse width modulation unit.

[0036] In a second aspect, the present application provides a driving method of a phase-shifted full-bridge soft switching circuit, which is applied to the phase-shifted full-bridge soft switching circuit of the first aspect of the present application, and the driving method of the phase-shifted full-bridge soft switching circuit comprises the following steps.

[0037] determining a phase-shifted amount according to the load voltage and the load current;

[0038] determining a first dead time, a second dead time and a third dead time according to the load current, the first dead time being a dead time of a driving signal of different switching tubes contained in a lagging bridge arm in the full-bridge circuit, the second dead time being a dead time of a driving signal of different switching tubes contained in a leading bridge arm in the full-bridge circuit, and the third dead time being a dead time of a driving signal of a switching tube in the synchronous rectification circuit and a driving signal of a switching tube contained in the lagging bridge arm;

[0039] generating the driving signal for driving the different switching tubes contained in the lagging bridge arm according to the first dead time;

[0040] generating the driving signal for driving the different switching tubes contained in the leading bridge arm according to the second dead time and the phase-shifted amount;

[0041] generating the driving signal for driving the switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase-shifted amount;

[0042] generating the driving signal for driving another switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase-shifted amount.

[0043] Optionally, the determination of the phase-shifted amount according to the load voltage and the load current comprises the following steps.

[0044] comparing the load voltage with a preset voltage to obtain a first difference value;

[0045] performing PI control on the first difference value to obtain a target current;

[0046] comparing the target current with the load current to obtain a second difference value;

[0047] performing PI control on the second difference value to obtain the phase-shifted amount.

[0048] In a third aspect, the present application provides a driving device of a phase-shifted full-bridge soft switching circuit, which is applied to the phase-shifted full-bridge soft switching circuit of the first aspect of the present application, and the driving device of the phase-shifted full-bridge soft switching circuit comprises:

[0049] A first determining module is configured to determine a phase-shifted amount according to the load voltage and the load current;

[0050] A second determining module is configured to determine a first dead time, a second dead time and a third dead time according to the load current, the first dead time being a dead time of a driving signal of different switching tubes contained in a lagging bridge arm in the full-bridge circuit, the second dead time being a dead time of a driving signal of different switching tubes contained in a leading bridge arm in the full-bridge circuit, and the third dead time being a dead time of a driving signal of a switching tube in the synchronous rectification circuit and a driving signal of a switching tube contained in the lagging bridge arm;

[0051] A first generating module is configured to generate a driving signal for driving different switching tubes contained in the lagging bridge arm according to the first dead time;

[0052] A second generating module is configured to generate a driving signal for driving different switching tubes contained in the leading bridge arm according to the second dead time and the phase-shifted amount;

[0053] A third generating module is configured to generate a driving signal for driving a switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase-shifted amount;

[0054] A fourth generating module is configured to generate a driving signal for driving another switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase-shifted amount.

[0055] Optionally, the first determining module is specifically configured to:

[0056] compare the load voltage with a preset voltage to obtain a first difference value;

[0057] perform PI control on the first difference value to obtain a target current;

[0058] compare the target current with the load current to obtain a second difference value;

[0059] perform PI control on the second difference value to obtain the phase-shifted amount.

[0060] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer program instructions, and the computer program instructions are executed to implement the driving method of the phase-shifted full-bridge soft switching circuit according to the second aspect of the present application.

[0061] In a fifth aspect, the present application provides a computer program product, comprising a computer program which, when executed by a processor, implements the driving method of the phase-shifted full-bridge soft switching circuit according to the second aspect of the present application.

[0062] The phase-shifted full-bridge soft switching circuit and the driving method and device thereof provided by the present application have better versatility, stronger anti-interference and portability, because the full-bridge circuit and the synchronous rectification circuit in the phase-shifted full-bridge soft switching circuit are composed of switching tubes, compared with the full-bridge circuit and the synchronous rectification circuit composed of diodes. Moreover, the generation of the driving of the phase-shifted full-bridge and the synchronous rectification can be realized by software through the control module, so that the development cycle can be greatly shortened and the cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0064] Figure 1 The schematic diagram of the phase-shifted full-bridge soft switching circuit provided by an embodiment of the present application is shown in FIG. 1.

[0065] Figure 2 The schematic diagram of the phase-shifted full-bridge soft switching circuit provided by another embodiment of the present application is shown in FIG. 2.

[0066] Figure 3 The schematic diagram of the phase-shifted full-bridge soft switching circuit provided by another embodiment of the present application is shown in FIG. 3.

[0067] Figure 4 The schematic diagram of the phase-shifted full-bridge soft switching circuit provided by another embodiment of the present application is shown in FIG. 4.

[0068] Figure 5 The schematic diagram of the phase-shifted full-bridge soft switching circuit provided by another embodiment of the present application is shown in FIG. 5.

[0069] Figure 6 The schematic diagram of the two-way driving time sequence generation of the first pulse width modulation unit EPWM1 provided by an embodiment of the present application is shown in FIG. 6.

[0070] Figure 7 The flowchart of the driving signal generation of the third pulse width modulation unit EPWM3 provided by an embodiment of the present application is shown in FIG. 7.

[0071] Figure 8 The flowchart of the driving signal generation of the fourth pulse width modulation unit EPWM4 provided by an embodiment of the present application is shown in FIG. 8.

[0072] Figure 9 A schematic diagram of the connection relationship among four pulse width modulation units provided for an embodiment of the present application is shown in FIG. 1;

[0073] Figure 10 A schematic diagram of six driving signals provided for an embodiment of the present application is shown in FIG. 2;

[0074] Figure 11 A flow chart of a driving method of a phase-shift full-bridge soft switching circuit provided for an embodiment of the present application is shown in FIG. 3;

[0075] Figure 12 A structural schematic diagram of a driving device of a phase-shift full-bridge soft switching circuit provided for an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0076] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0077] Based on the problems in generating a phase-shift full-bridge and a synchronous rectification drive by using an analog control chip, the present application provides a phase-shift full-bridge soft switching circuit and a driving method and device thereof, which replace the original diode with a switching tube and control the driving of the switching tube by software, so as to provide a phase-shift full-bridge soft switching circuit with better versatility, stronger anti-interference and portability, greatly shorten the development cycle and reduce the cost.

[0078] Exemplarily, the switching tube is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Based on the generation logic algorithm of the driving signals of the six MOSFETs of the full-digital switching power supply phase-shift full-bridge and synchronous rectification topology of the C2000 Digital Signal Processor (DSP) platform, the dead time of the full-bridge circuit in the same bridge arm can be dynamically adjusted with the load change, and then the Zero Voltage Switch (ZVS) of the MOSFET in the full-bridge circuit in the full load range can be realized; the dead time between the driving signal of the MOSFET in the transformer secondary side (i.e. the secondary winding side) synchronous rectification circuit and the driving signal of the MOSFET in the transformer primary side (i.e. the primary winding side) full-bridge circuit corresponding thereto can also be dynamically adjusted, so as to reduce the conduction time of the body diode of the MOSFET in the synchronous rectification circuit, and then improve the overall efficiency of the switching power supply.

[0079] Figure 1 This is a schematic diagram of a phase-shifted full-bridge soft-switching circuit provided in an embodiment of this application. Figure 1 As shown, the phase-shifted full-bridge soft-switching circuit 100 of this application embodiment includes: a full-bridge circuit 110, a synchronous rectification circuit 120, a control module 130, and a magnetic device 140. Both the full-bridge circuit 110 and the synchronous rectification circuit 120 are composed of switching transistors 150; the control module 130 is used to generate drive signals for driving each switching transistor 150 based on the collected load voltage and load current.

[0080] In this embodiment of the application, for example, if the switching transistor 150 is a MOSFET, then both the full-bridge circuit 110 and the synchronous rectification circuit 120 are composed of MOSFETs, but this application is not limited thereto.

[0081] For example, the magnetic device 140 is a multi-winding transformer; the control module 130 can specifically be a DSP. The DSP collects the load voltage and load current output from the full-bridge circuit 110 and the synchronous rectifier circuit 120, and then generates drive signals for driving each switch 150 based on the collected load voltage and load current. For example, the DSP determines whether the load is heavy or light based on the collected load voltage and load current, and then generates corresponding drive signals for driving each switch 150. It should be noted that the drive generation logic is fully programmable. Therefore, the control module 130 can also be a programmable controller such as a microcontroller unit (MCU) or an advanced RISC machine (ARM), and this application is not limited thereto.

[0082] The phase-shifted full-bridge soft-switching circuit provided in this application embodiment has better versatility, stronger anti-interference ability, and stronger portability compared to the full-bridge circuit and synchronous rectification circuit composed of diodes, since the full-bridge circuit and synchronous rectification circuit in the phase-shifted full-bridge soft-switching circuit are composed of switching transistors. Moreover, the generation of phase-shifted full-bridge and synchronous rectification drive can be realized by software through the control module, which can greatly shorten the development cycle and reduce costs.

[0083] Figure 2 This is a schematic diagram of a phase-shifted full-bridge soft-switching circuit according to another embodiment of this application. Based on the above embodiments, this application further describes the phase-shifted full-bridge soft-switching circuit 100. For example... Figure 2As shown, in the phase-shifted full-bridge soft switching circuit 100 of the embodiment of the present application, the first input end of the full-bridge circuit is connected to the DC input bus voltage Vdc, and the second input end of the full-bridge circuit is connected to the ground G1; one end of the primary winding of the magnetic device T is connected to the lagging bridge arm output end of the full-bridge circuit through the first inductor Lr, and the other end of the primary winding of the magnetic device T is connected to the leading bridge arm output end of the full-bridge circuit through the first capacitor C1. The first input end of the synchronous rectification circuit is connected to the first end of the secondary winding of the magnetic device T, the second input end of the synchronous rectification circuit is connected to the second end of the secondary winding of the magnetic device T, and the output end of the synchronous rectification circuit is connected to the load Ro. The middle tap of the secondary winding of the magnetic device T is connected to the ground G2. The load voltage Vo is output from the output end of the synchronous rectification circuit.

[0084] In the embodiment of the present application, the full-bridge circuit includes a lagging bridge arm and a leading bridge arm, and both the lagging bridge arm and the leading bridge arm are composed of switching tubes. Exemplarily, the switching tube is a MOSFET, the first inductor Lr is a resonant inductor or a transformer leakage inductance, and the first inductor Lr is used to resonate with the parasitic capacitance between the drain (D) and the source (S) of the MOSFET of the full-bridge circuit (or a capacitor connected in parallel between the D and S) to provide the possibility of soft switching for the full-bridge MOSFET. Exemplarily, the magnetic device T is a multi-winding transformer, the first capacitor C1 is an isolation capacitor, and the isolation DC component is used to prevent the magnetic device T from being magnetically biased due to the DC component. Exemplarily, the load Ro is a load resistor output by the synchronous rectification circuit.

[0085] On the basis of the above-mentioned embodiment, with reference to Figure 2 , the switching tubes of the full-bridge circuit in the phase-shifted full-bridge soft switching circuit 100 of the embodiment of the present application are further described. As shown, Figure 2 In the phase-shifted full-bridge soft switching circuit 100 of the embodiment of the present application, the switching tubes include a first switching tube QA, a second switching tube QB, a third switching tube QC and a fourth switching tube QD, the lagging bridge arm includes the first switching tube QA and the second switching tube QB, and the leading bridge arm includes the third switching tube QC and the fourth switching tube QD; wherein:

[0086] The drain D of the first switching tube QA is connected to the drain D of the third switching tube QC, and the connection end serves as the first input end of the full-bridge circuit; the source S of the second switching tube QB is connected to the source S of the fourth switching tube QD, and the connection end serves as the second input end of the full-bridge circuit; the source S of the first switching tube QA is connected to the drain D of the second switching tube QB, and the connection end serves as the lagging bridge arm output end of the full-bridge circuit; the source S of the third switching tube QC is connected to the drain D of the fourth switching tube QD, and the connection end serves as the leading bridge arm output end of the full-bridge circuit; the gate G of the first switching tube QA, the gate G of the second switching tube QB, the gate G of the third switching tube QC and the gate G of the fourth switching tube QD are respectively connected to different output ends of the control module for inputting respective corresponding driving signals.

[0087] In the embodiment, the first switch tube QA, the second switch tube QB, the third switch tube QC and the fourth switch tube QD constitute a full-bridge circuit, wherein the first switch tube QA and the second switch tube QB constitute a lagging bridge arm of the full-bridge circuit, and the third switch tube QC and the fourth switch tube QD constitute a leading bridge arm of the full-bridge circuit 110. Each switch tube includes a drain D, a source S and a gate G. The drain D and the source S of each switch tube are used for circuit connection of the full-bridge circuit, and the gate G of each switch tube is used for connecting different output terminals of the control module to input respective corresponding drive signals.

[0088] Based on the above embodiment, referring to Figure 2 , the embodiment further describes the switch tubes of the synchronous rectification circuit in the phase-shifted full-bridge soft switching circuit 100. As shown in Figure 2 , in the phase-shifted full-bridge soft switching circuit 100 of the embodiment, the switch tubes include a fifth switch tube QF and a sixth switch tube QE, and the synchronous rectification circuit includes the fifth switch tube QF and the sixth switch tube QE; wherein:

[0089] The source S of the fifth switch tube QF is used as a first input terminal of the synchronous rectification circuit; the source S of the sixth switch tube QE is used as a second input terminal of the synchronous rectification circuit; the drain D of the fifth switch tube QF is connected with the drain D of the sixth switch tube QE, and the connection end is used as an output terminal of the synchronous rectification circuit; the gate G of the fifth switch tube QF and the gate G of the sixth switch tube QE are respectively connected with different output terminals of the control module to input respective corresponding drive signals.

[0090] In the embodiment, the fifth switch tube QF and the sixth switch tube QE constitute the synchronous rectification circuit, each switch tube includes a drain D, a source S and a gate G, the drain D and the source S of each switch tube are used for circuit connection of the synchronous rectification circuit, and the gate G of each switch tube is used for connecting different output terminals of the control module to input respective corresponding drive signals.

[0091] Based on the above embodiment, referring to Figure 2 , the embodiment further describes the phase-shifted full-bridge soft switching circuit 100. As shown in Figure 3 , the phase-shifted full-bridge soft switching circuit 100 of the embodiment further includes a second capacitor Co and a second inductor Lo, the output terminal of the synchronous rectification circuit is connected with a load Ro through the second inductor Lo, and the second capacitor Co is connected with the load Ro in parallel.

[0092] Exemplarily, the second inductor Lo is an output filter inductor, the second capacitor Co is an output filter capacitor, the second inductor Lo and the second capacitor Co constitute an inductor-capacitor (LC) low-pass filter circuit, which is used for ensuring that the output voltage is a smooth direct current voltage.

[0093] Based on the above embodiments, the main power transmission process of the phase-shifted full-bridge soft-switching circuit 100 is divided into two steps: (1) Figure 3 A schematic diagram of a phase-shifted full-bridge soft-switching circuit provided in another embodiment of this application is shown below. Figure 4 As shown, when the first switch QA and the fourth switch QD of the full-bridge circuit are turned on, the voltage of the magnetic device T is positive at the top and negative at the bottom. At this time, the secondary energy comes out from the secondary winding of the magnetic device T, passes through the fifth switch QF of the synchronous rectifier circuit, the second inductor Lo, the second capacitor Co and the load Ro, and then returns to the middle tap of the secondary winding of the magnetic device T; (2) Figure 4 A schematic diagram of a phase-shifted full-bridge soft-switching circuit provided in another embodiment of this application is shown below. Figure 5 As shown, when the third switch QC and the second switch QB of the full-bridge circuit are turned on, the voltage of the magnetic device T is negative at the top and positive at the bottom. At this time, the secondary energy comes out from the secondary winding of the magnetic device T, passes through the sixth switch QE of the synchronous rectifier circuit, the second inductor Lo, the second capacitor Co and the load Ro, and then returns to the middle tap of the secondary winding of the magnetic device T.

[0094] Figure 5 This is a schematic diagram of a phase-shifted full-bridge soft-switching circuit provided in another embodiment of this application. Based on the above embodiments, this application further describes the control module of the phase-shifted full-bridge soft-switching circuit 100. For example... Figure 5 As shown, exemplarily, the control module is a DSP, which includes a first pulse width modulation unit EPWM1, a second pulse width modulation unit EPWM2, a third pulse width modulation unit EPWM3, a fourth pulse width modulation unit EPWM4, and a processing unit. Wherein:

[0095] The processing unit is configured to determine a phase shift amount according to the load voltage and the load current, and transmit the phase shift amount to the second pulse width modulation unit EPWM2; and determine a first dead time, a second dead time and a third dead time according to the load current, the first dead time being a dead time of driving signals of different switching tubes contained in a lagging bridge arm in the full-bridge circuit, the second dead time being a dead time of driving signals of different switching tubes contained in a leading bridge arm in the full-bridge circuit, and the third dead time being a dead time of a driving signal of a switching tube in the synchronous rectification circuit and a driving signal of a switching tube contained in the lagging bridge arm; the first pulse width modulation unit EPWM1 is configured to generate the driving signals for driving the different switching tubes contained in the lagging bridge arm according to the first dead time; the second pulse width modulation unit EPWM2 is configured to generate the driving signals for driving the different switching tubes contained in the leading bridge arm according to the second dead time and the phase shift amount; the third pulse width modulation unit EPWM3 is configured to generate a driving signal for driving a switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount; and the fourth pulse width modulation unit EPWM4 is configured to generate a driving signal for driving another switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount.

[0096] In the embodiment, the processing unit samples the load voltage and the load current at the output end of the synchronous rectification circuit, determines the phase shift amount according to the sampled load voltage and load current, and transmits the phase shift amount to the second pulse width modulation unit EPWM2. In a possible implementation, the processing unit adopts an average current control mode, the output of the voltage outer loop is used as a current reference signal of the current inner loop, the output inductance current feedback signal is compared to obtain an error signal, and the required phase shift amount (i.e. effective duty cycle) is obtained through the current loop controller. The value of the corresponding register (such as Epwm2Regs.TBPHS.half.TBPHS) of the second pulse width modulation unit EPWM2 is adjusted in proportion to the obtained required phase shift amount, so as to realize the phase shift control of the second pulse width modulation unit EPWM2.

[0097] Further, when determining the phase shift amount according to the load voltage and the load current, the processing unit is specifically configured to:

[0098] compare the load voltage with a preset voltage to obtain a first difference; perform proportional-integral (PI) control on the first difference to obtain a target current; compare the target current with the load current to obtain a second difference; and perform PI control on the second difference to obtain the phase shift amount.

[0099] For example, as shown in FIG. 2, the processing unit is configured to determine the phase shift amount according to the load voltage and the load current, and transmit the phase shift amount to the second pulse width modulation unit EPWM2. Figure 5As shown, the control module is a DSP, which collects the load voltage and the load current at the output end of the synchronous rectification circuit through an Analog-to-Digital Converter (ADC); the load voltage is compared with a given voltage (i.e., a preset voltage) as a voltage feedback to obtain an error signal (i.e., a first difference), which is subjected to PI control by a Proportional Integral Differential (PID) controller to obtain a target current, which belongs to a voltage outer loop structure, and the output of the voltage outer loop is the target current as a given current signal of a current inner loop; the load current is compared with the target current as a current feedback to obtain a second difference, which is subjected to PI control by a PID controller to obtain a phase shift amount.

[0100] After determining the phase shift amount according to the load voltage and the load current, the processing unit also determines a first dead time, a second dead time and a third dead time according to the load current. Exemplarily, reference is made to FIG. 4. Figure 5, the first switch tube QA, the second switch tube QB, the third switch tube QC, the fourth switch tube QD, the fifth switch tube QF and the sixth switch tube QE are MOSFETs, the first dead time is a dead time of a driving signal of the first switch tube QA and the second switch tube QB contained in a lagging bridge arm in the full-bridge circuit, and the first dead time can be used to avoid a circuit short circuit problem caused by simultaneous conduction of the first switch tube QA and the second switch tube QB; the second dead time is a dead time of a driving signal of the third switch tube QC and the fourth switch tube QD contained in a leading bridge arm in the full-bridge circuit, and the second dead time can be used to avoid a circuit short circuit problem caused by simultaneous conduction of the third switch tube QC and the fourth switch tube QD; the third dead time is a dead time of a driving signal of the fifth switch tube QF in the synchronous rectification circuit and a driving signal of the first switch tube QA contained in the lagging bridge arm, or a dead time of a driving signal of the sixth switch tube QE in the synchronous rectification circuit and a driving signal of the second switch tube QB contained in the lagging bridge arm, and the third dead time can be used to reduce a body diode conduction time of a MOSFET in the synchronous rectification circuit. A possible implementation manner for determining the first dead time, the second dead time and the third dead time is as follows: for example, the first dead time is denoted by DB1, the second dead time is denoted by DB2, further, the dead times DB1 and DB2 are denoted by y1, and an output current (i.e., a load current) is denoted by x1, then a relationship between y1 and x1 is y1=a1-b1*x1, and it can be seen from the relationship that the greater the output current, the smaller the dead times DB1 and DB2, and a minimum dead time needs to be limited to prevent bridge arm shoot-through; for example, the third dead time is denoted by DB3, further, the dead time DB3 is denoted by y2, and the output current is denoted by x2, then a relationship between y2 and x3 is y2=a2+b2*x2, and it can be seen from the relationship that the greater the output current, the greater the dead time DB3, and therefore, a suitable DB3 value can reduce a body diode conduction time of a synchronous rectification MOSFET, reduce loss and improve overall efficiency. Values of the coefficients a1, b1, a2 and b2 are closely related to hardware parameters (such as a model of a used MOSFET, a driving rise time and a driving fall time), and a value of the dead time directly affects, for example, a soft switching effect of a MOSFET, and needs to be repeatedly adjusted and optimized in an actual debugging process to obtain an optimal value.

[0101] In the embodiments of the application, after the phase shift amount, the first dead time, the second dead time and the third dead time are determined by the processing unit, the first pulse width modulation unit EPWM1, the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3 and the fourth pulse width modulation unit EPWM4 in the control module generate corresponding driving signals according to relevant information in the information, respectively. For example, with reference to Figure 6, the output EPWM1A and EPWM1B of the first pulse width modulation unit EPWM1 correspond to the driving signals of the first switch tube QA and the second switch tube QB respectively; the output EPWM2A and EPWM2B of the second pulse width modulation unit EPWM2 correspond to the driving signals of the third switch tube QC and the fourth switch tube QD respectively; the output EPWM3A of the third pulse width modulation unit EPWM3 corresponds to the driving signal of the fifth switch tube QF; the output EPWM4A of the fourth pulse width modulation unit EPWM4 corresponds to the driving signal of the sixth switch tube QE.

[0102] Specifically, for the first pulse width modulation unit EPWM1, first, the duty cycle of the first pulse width modulation unit EPWM1 is set to, for example, 50%, and then the initialization setting of the first pulse width modulation unit EPWM1 related register is performed, including the following seven steps:

[0103] The first step is to set the time base control register, and set the counting mode to the increment-decrement counting mode (convenient for collecting the average value of the output inductor current for average current control);

[0104] The second step is to set the time base period register, and set the switching frequency (also called switching period) to 100KHz;

[0105] The third step is to disable the phase loading, that is, the phase of the first pulse width modulation unit EPWM1 is fixed and unchanged;

[0106] The fourth step is to set the output synchronization signal when the time base counter counts to 0;

[0107] The fifth step is to set the value of the comparator A to be half of the upper limit of the time base count value, for example, if the maximum count value of the time base count value is 300, the value of the comparator A is 150;

[0108] The sixth step is to set the action limiter output a register to: when the count value of the time base counter is equal to the set value CMPA of the comparator A (CMPA) and is incrementing, the EPWM1A output is forced to be pulled low (i.e. output low); when the count value of the time base counter is equal to the set value CMPA of the comparator A and is decrementing, the EPWM1A output is forced to be pulled high (i.e. output high);

[0109] The seventh step is to enable the dead zone module, and set the two-way output of EPWM1A and EPWM1B to be high level effective complementary mode.

[0110] After the first pulse width modulation unit EPWM1 completes the initialization setting, the driving signals EPWM1A and EPWM1B for driving the first switch tube QA and the second switch tube QB contained in the lagging bridge arm are generated according to the first dead time.Figure 6 The schematic diagram of two-way drive generation timing provided by the first pulse width modulation unit EPWM1 of an embodiment of the present application is shown. As shown, the dead time includes the rising edge dead time and the falling edge dead time, the original waveform of EPWM1A is the original drive signal corresponding to the first switch tube QA without the first dead time, EPWM1A is the drive signal corresponding to the first switch tube QA with the first dead time (such as the rising edge dead time), EPWM1B is the drive signal corresponding to the second switch tube QB with the first dead time (such as the falling edge dead time), the time base counter count value from 0 to 300 and then to 0 is one switching cycle, in each switching cycle, EPWM1A and EPWM1B are two-way high level complementary output. Figure 5

[0111] Specifically, for the second pulse width modulation unit EPWM2, first, the duty cycle of the second pulse width modulation unit EPWM2 is set to, for example, 50%, and then the initialization setting of the second pulse width modulation unit EPWM2 related registers is performed, including the following seven steps:

[0112] The first step is to set the time base control register, and set the count mode to the increment and decrement count mode;

[0113] The second step is to set the time base period register, and set the switching frequency to 100KHz;

[0114] The third step is to enable phase loading for phase shift amount control;

[0115] The fourth step is to allow synchronization with the synchronization signal output by the first pulse width modulation unit EPWM1;

[0116] The fifth step is to set the value of the comparator A to be half of the upper limit of the time base counter value;

[0117] The sixth step is to set the action limiter output a register to: when the count value of the time base counter is equal to the set value CMPA of the comparator A and is incrementing, the EPWM1A output is forced to be pulled low; when the count value of the time base counter is equal to the set value CMPA of the comparator A and is decrementing, the EPWM1A output is forced to be pulled high;

[0118] The seventh step is to enable the dead time module and set the two-way output to the high level effective complementary mode.

[0119] After the second pulse width modulation unit EPWM2 completes the initialization setting, the drive signals EPWM2A for driving the third switch tube QC included in the leading leg and the drive signals EPWM2B for driving the fourth switch tube QD are generated according to the second dead time and the phase shift amount, in each switching cycle, EPWM2A and EPWM2B are two-way high level complementary output. ​

[0120] Referring to Figure 7 , the relationship between the drive signal of the MOSFET of the secondary synchronous rectification circuit and the drive signal of the corresponding primary full-bridge circuit diagonal switching tube (the first switching tube QA and the fourth switching tube QD form a pair of diagonal tubes, and the second switching tube QB and the third switching tube QC form a pair of diagonal tubes) is as follows:

[0121] Driver_QE = Driver_QB | Driver_QC

[0122] Driver_QF = Driver_QA | Driver_QD

[0123] That is, if any one of the drive signals of the second switching tube QB and the third switching tube QC is high at a certain moment, the drive signal of the sixth switching tube QE is high; if any one of the drive signals of the first switching tube QA and the fourth switching tube QD is high at a certain moment, the drive signal of the fifth switching tube QF is high.

[0124] On the basis of the above embodiment, the third pulse width modulation unit EPWM3 generates a drive signal for driving the fifth switching tube QF contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time, and the phase shift amount. Exemplarily, Figure 7 The flow chart of the third pulse width modulation unit EPWM3 provided by an embodiment of the present application for generating a drive signal is shown in Figure 7 , where d represents the duty cycle of a single drive signal, d is set to 50%, for example, PRD represents the maximum count value of the time base count value, PRD is 300, for example, DB1 is the first dead time of EPWM1A and EPWM1B, DB2 is the second dead time of EPWM2A and EPWM2B, DB3 is the dead time of EPWM1A and EPWM3A or the third dead time of EPWM1B and EPWM4A, and the phase shift amount is represented by P. It should be noted that the quantities such as the duty cycle d, the phase shift amount P, the dead times DB1, DB2, and DB3 need to be under the same calibration to be able to be added or subtracted. Referring to Figure 8 , the step of generating a drive signal by the third pulse width modulation unit EPWM3 can include:

[0125] S701, initializing each register of the third pulse width modulation unit EPWM3;

[0126] The method comprises the following steps: setting a time base control register, and setting a counting mode as an increment or decrement counting mode; setting a time base period register, and setting a switching frequency as 100 KHz, and setting a maximum time base counting value as 300; enabling phase loading; allowing synchronization with a synchronization signal output by a first pulse width modulation unit EPWM1; setting an action limiter output a register as: when a time base counter counting value is equal to a set value CMPA of a comparator A and the counting is in increment, forcibly pulling up an EPWM3A output; when the time base counter counting value is equal to a set value CMPB of a comparator B (Compare B, CMPB) and the counting is in decrement, forcibly pulling down the EPWM3A output.

[0127] S702, determining a phase shift amount P according to the load voltage and the load current;

[0128] S703, determining a first dead time DB1, a second dead time DB2 and a third dead time DB3 according to the load current;

[0129] In the embodiments of the present application, the specific implementation process of S702 and S703 can refer to the related description of the above embodiments, which will not be repeated here.

[0130] S704, setting the set value CMPB of the comparator B as equal to "a counting value corresponding to the duty ratio d + a counting value corresponding to the DB3";

[0131] S705, judging whether "a counting value corresponding to the duty ratio d - a counting value corresponding to the current phase shift amount P - a counting value corresponding to the DB2" is greater than 0;

[0132] Specifically, if greater than 0, step S706 is executed, and if not greater than 0, step S710 is executed;

[0133] S706, judging whether "a counting value corresponding to the current phase shift amount P" is greater than "a counting value corresponding to the DB1";

[0134] S707, setting the set value CMPA of the comparator A as equal to "a counting value corresponding to the duty ratio d + a counting value corresponding to the current phase shift amount P + a counting value corresponding to the DB2";

[0135] S708, configuring the EPWM3A output to be pulled up when the time base counter counts to CMPA and the counting is in increment, and to be pulled down when the time base counter counts to CMPB and the counting is in increment;

[0136] S709, setting the set value CMPA of the comparator A and the set value CMPB of the comparator B as 0, and forcibly pulling down the EPWM3A output;

[0137] S710, determining whether the count value corresponding to the current phase shift amount P is greater than the maximum count value of the time base counter minus the count value corresponding to DB2 plus the minimum of the count value corresponding to DB1 and the count value corresponding to DB2;

[0138] S711, setting the set value CMPA of the comparator A equal to the count value corresponding to the duty cycle d minus the count value corresponding to DB1;

[0139] S712, setting the set value CMPA of the comparator A equal to the maximum count value of the time base counter plus the count value corresponding to the duty cycle d minus the count value corresponding to DB2 minus the count value corresponding to the current phase shift amount P;

[0140] S713, configuring the EPWM3A output to be pulled high when the time base counter counts to CMPA and counts down, and to be pulled low when it counts to CMPB and counts up.

[0141] Through the above steps, the third pulse width modulation unit EPWM3 generates a driving signal EPWM3A.

[0142] On the basis of the above embodiment, the fourth pulse width modulation unit EPWM4 generates a driving signal for driving the sixth switch tube QE contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount. Illustratively, Figure 8 The flow chart of the fourth pulse width modulation unit EPWM4 generating a driving signal provided by an embodiment of the present application is described with reference to Figure 9 , the steps of the fourth pulse width modulation unit EPWM4 generating a driving signal can include:

[0143] S801, initializing each register of the fourth pulse width modulation unit EPWM4;

[0144] Among them, including setting the time base control register, setting the count mode to the up-down count mode; setting the time base period register, setting the switching frequency to, for example, 100KHz, setting the maximum count value of the time base counter to, for example, 300; enabling phase loading; allowing synchronization with the synchronization signal output by the first pulse width modulation unit EPWM1; setting the action limiter output a register to: when the count value of the time base counter is equal to the set value CMPA of the comparator A and is up-counting, the EPWM4A output is forced to be pulled high; when the count value of the time base counter is equal to the set value CMPB of the comparator B and is down-counting, the EPWM4A output is forced to be pulled low;

[0145] S802, determining the phase shift amount P according to the load voltage and the load current;

[0146] S803, determining the first dead time DB1, the second dead time DB2 and the third dead time DB3 according to the load current;

[0147] In the embodiments of the present application, the specific implementation process of S802 and S803 can refer to the related description of the above embodiments, which will not be repeated here.

[0148] S804, setting the setting value CMPB of the comparator B equal to "the count value corresponding to the duty cycle d - the count value corresponding to DB3";

[0149] S805, judging whether "the count value corresponding to the duty cycle d - the count value corresponding to the current phase shift P - the count value corresponding to DB2" is greater than 0;

[0150] Specifically, if greater than 0, step S806 is executed, and if not greater than 0, step S810 is executed;

[0151] S806, judging whether "the count value corresponding to the current phase shift P" is greater than "the count value corresponding to DB1";

[0152] S807, setting the setting value CMPA of the comparator A equal to "the count value corresponding to the duty cycle d - the count value corresponding to the current phase shift P - the count value corresponding to DB2";

[0153] S808, configuring the EPWM4A to be pulled high when the time base counter counts to CMPA and counts down, and to be pulled low when the time base counter counts to CMPB and counts down;

[0154] S809, setting the setting value CMPA of the comparator A and the setting value CMPB of the comparator B both to 0, and forcibly pulling down the EPWM4A output;

[0155] S810, judging whether "the count value corresponding to the current phase shift P" is greater than "the maximum count value of the time base counter - the count value corresponding to DB2 + the count value corresponding to DB1 and the count value corresponding to DB2, whichever is smaller";

[0156] S811, setting the setting value CMPA of the comparator A equal to "the count value corresponding to the duty cycle d + the count value corresponding to DB1";

[0157] S812, setting the setting value CMPA of the comparator A equal to "the count value corresponding to the duty cycle d + the count value corresponding to DB2 + the count value corresponding to the current phase shift P - the maximum count value of the time base counter";

[0158] S813, configuring the EPWM4A to be pulled high when the time base counter counts to CMPA and counts up, and to be pulled low when it counts to CMPB and counts down.

[0159] The fourth pulse width modulation unit EPWM4 generates a driving signal EPWM4A through the above steps.

[0160] Further based on the above embodiment, the first pulse width modulation unit EPWM1 is further configured to generate a synchronization signal and output the synchronization signal to the second pulse width modulation unit EPWM2.

[0161] The second pulse width modulation unit EPWM2 is further configured to output the synchronization signal to the third pulse width modulation unit EPWM3.

[0162] The third pulse width modulation unit EPWM3 is further configured to output the synchronization signal to the fourth pulse width modulation unit EPWM4.

[0163] In the embodiments of the present application, to ensure the timing consistency of the driving signals generated by the first pulse width modulation unit EPWM1, the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3 and the fourth pulse width modulation unit EPWM4, it is necessary to ensure that the above four pulse width modulation units are kept high-frequency synchronization. For example, Figure 9 The schematic diagram of the connection relationship between the four pulse width modulation units provided by an embodiment of the present application is shown in FIG. 1. Figure 10 As shown in FIG. 1, according to the resource condition of the DSP, each pulse width modulation unit has a synchronization signal input end (SyncIn) and a synchronization signal output end (SyncOut). The enable end (EN) of each pulse width modulation unit is used to control whether to allow being synchronized by an external signal. When the EN is opened, it means that the pulse width modulation unit is not allowed to be synchronized by an external signal. When the EN is closed, it means that the pulse width modulation unit is allowed to be synchronized by an external signal. The counter register (CTR) is a time base counter. The counting value is from 0 to 300 and then to 0 for one switching period. The switching period of the first pulse width modulation unit EPWM1 is 100 KHz. The first pulse width modulation unit EPWM1 is set to an increment-decrement counting mode. The synchronization signal is generated once every 10us (i.e., 1 / 100 KHz) in each switching period. The synchronization signal is, for example, a square wave or an electric pulse. The first pulse width modulation unit EPWM1 is a master unit and is prohibited to be synchronized by an external signal. The synchronization signal is output when the time base counter counts to 0, which is used to synchronize the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3 and the fourth pulse width modulation unit EPWM4. The switching periods of the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3 and the fourth pulse width modulation unit EPWM4 are also set to 100 KHz. All of them are set to be allowed to be synchronized by the input synchronization signal.

[0164] Further based on the above embodiment, for example,Figure 10 The schematic diagram of six driving signals provided for an embodiment of the present application is shown in FIG. 1, which shows six driving signals: the driving signal EPWM1A of the first switch tube QA, the driving signal EPWM1B of the second switch tube QB, the driving signal EPWM2A of the third switch tube QC, the driving signal EPWM2B of the fourth switch tube QD, the driving signal EPWM3A of the fifth switch tube QF, and the driving signal EPWM4A of the sixth switch tube QE, and the first dead time DB1 of EPWM1A and EPWM1B, the second dead time DB2 of EPWM2A and EPWM2B, and the third dead time DB3 of EPWM1A and EPWM3A or EPWM1B and EPWM4A. The overall process of generating the six driving signals can include: Figure 11 (1) initializing and setting the first pulse width modulation unit EPWM1, the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3, and the fourth pulse width modulation unit EPWM4, wherein the first pulse width modulation unit EPWM1, the second pulse width modulation unit EPWM2, the third pulse width modulation unit EPWM3, and the fourth pulse width modulation unit EPWM4 are high-frequency synchronized, the driving signals EPWM1A and EPWM1B are set to high-level complementary outputs with a certain dead time, and the driving signals EPWM2A and EPWM2B are set to high-level complementary outputs with a certain dead time;

[0165] (2) when the count value of the time base counter of the first pulse width modulation unit EPWM1 is 0, triggering the ADC to sample the load voltage and the load current;

[0166] (3) entering the main interrupt program, obtaining the instantaneous values of the load voltage and the load current, and obtaining the target current through the PI control of the voltage outer ring according to the load voltage value, as the current given signal of the current inner ring, and obtaining the phase shift amount through the PI control of the current inner ring according to the given current signal and the load current value;

[0167] (4) if the phase shift amount is greater than the preset minimum duty cycle, obtaining the first dead time DB1, the second dead time DB2, and the third dead time DB3 according to the load current, respectively;

[0168]

[0169] ​(5) if the load current is greater than a preset current threshold required for starting the synchronous rectification, the phase-shifted full-bridge synchronous rectification mode is entered, the first dead time DB1 of the EPWM1A and the EPWM1B, the second dead time DB2 of the EPWM2A and the EPWM2B, the third dead time DB3 of the EPWM1A and the EPWM3A or the EPWM1B and the EPWM4A are updated, and the phase-shift amount of the second pulse width modulation unit EPWM2 is updated, and the duty cycles of the EPWM3A and the EPWM4A are updated respectively; if the load current is less than or equal to the preset current threshold required for starting the synchronous rectification, the synchronous rectification driving signal is turned off.

[0170] The phase-shifted full-bridge soft switching circuit provided by the embodiment of the application determines the phase-shift amount, the first dead time, the second dead time and the third dead time through the processing unit, and the first pulse width modulation unit, the second pulse width modulation unit, the third pulse width modulation unit and the fourth pulse width modulation unit in the control module generate corresponding driving signals according to the related information in the phase-shift amount, the first dead time, the second dead time and the third dead time respectively, so that the dead time of the full-bridge circuit in the same bridge arm can be dynamically adjusted according to the load, and the zero voltage switching of the MOSFET of the full-bridge circuit in the full load range can be realized; the dead time between the driving signal of the synchronous rectification circuit MOSFET and the driving signal of the full-bridge circuit MOSFET corresponding thereto can also be dynamically adjusted, so as to reduce the conduction time of the body diode of the synchronous rectification circuit MOSFET, reduce the conduction loss of the synchronous rectification circuit MOSFET, and make the overall efficiency of the switching power supply reach more than 95%.

[0171] On the basis of the above-mentioned embodiment of the phase-shifted full-bridge soft switching circuit, Figure 1 The flow chart of the driving method of the phase-shifted full-bridge soft switching circuit provided by the embodiment of the application can be applied to the phase-shifted full-bridge soft switching circuit as shown in Figure 11 As shown in Figure 12 The method of the embodiment of the application comprises:

[0172] S1101, determining the phase-shift amount according to the load voltage and the load current;

[0173] As a possible implementation, the step can further comprise: comparing the load voltage with a preset voltage to obtain a first difference; performing proportional-integral PI control on the first difference to obtain a target current; comparing the target current with the load current to obtain a second difference; and performing proportional-integral PI control on the second difference to obtain the phase-shift amount.

[0174] S1102, determining the first dead time, the second dead time and the third dead time according to the load current.

[0175] The first dead time is a dead time of a driving signal of different switch tubes contained in a lagging bridge arm in the full-bridge circuit, the second dead time is a dead time of a driving signal of different switch tubes contained in a leading bridge arm in the full-bridge circuit, and the third dead time is a dead time of a driving signal of a switch tube in the synchronous rectification circuit and a driving signal of a switch tube contained in the lagging bridge arm.

[0176] S1103, generating a driving signal for driving different switch tubes contained in the lagging bridge arm according to the first dead time.

[0177] S1104, generating a driving signal for driving different switch tubes contained in the leading bridge arm according to the second dead time and the phase shift amount.

[0178] S1105, generating a driving signal for driving a switch tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount.

[0179] S1106, generating a driving signal for driving another switch tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time and the phase shift amount.

[0180] On the basis of any of the above-mentioned embodiments, the phase shift amount is determined according to the load voltage and the load current, comprising:

[0181] Comparing the load voltage with a preset voltage to obtain a first difference value;

[0182] Performing proportional integral (PI) control on the first difference value to obtain a target current;

[0183] Comparing the target current with the load current to obtain a second difference value;

[0184] Performing proportional integral (PI) control on the second difference value to obtain the phase shift amount.

[0185] The driving method of the above-mentioned phase-shifted full-bridge soft switching circuit is executed by a control module, and the control module generates driving signals of each switch tube in the full-bridge circuit and the synchronous rectification circuit through the driving method of the phase-shifted full-bridge soft switching circuit.

[0186] The method of the embodiment of the application can be used to execute the technical solutions of any of the above-mentioned phase-shifted full-bridge soft switching circuit embodiments, and the implementation principles and technical effects are similar, which will not be described here.

[0187] The following is a device embodiment of the application, which can be used to execute the method embodiments of the application. For details not disclosed in the device embodiments of the application, please refer to the method embodiments of the application.

[0188] Figure 12A structural schematic diagram of a driving device of a phase-shift full-bridge soft switching circuit is provided in an embodiment of the present application. As shown in ​ The driving device 1200 of the phase-shift full-bridge soft switching circuit in the embodiment of the present application includes a first determining module 1201, a second determining module 1202, a first generating module 1203, a second generating module 1204, a third generating module 1205, and a fourth generating module 1206. Wherein:

[0189] The first determining module 1201 is configured to determine a phase-shift amount according to a load voltage and a load current.

[0190] The second determining module 1202 is configured to determine a first dead time, a second dead time, and a third dead time according to the load current. The first dead time is a dead time of a driving signal of different switching tubes contained in a lagging bridge arm in the full-bridge circuit. The second dead time is a dead time of a driving signal of different switching tubes contained in an advancing bridge arm in the full-bridge circuit. The third dead time is a dead time of a driving signal of a switching tube in the synchronous rectification circuit and a driving signal of a switching tube contained in the lagging bridge arm.

[0191] The first generating module 1203 is configured to generate a driving signal for driving different switching tubes contained in the lagging bridge arm according to the first dead time.

[0192] The second generating module 1204 is configured to generate a driving signal for driving different switching tubes contained in the advancing bridge arm according to the second dead time and the phase-shift amount.

[0193] The third generating module 1205 is configured to generate a driving signal for driving a switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time, and the phase-shift amount.

[0194] The fourth generating module 1206 is configured to generate a driving signal for driving another switching tube contained in the synchronous rectification circuit according to the first dead time, the second dead time, the third dead time, and the phase-shift amount.

[0195] In the above embodiment, the first determining module 1201 is specifically configured to:

[0196] compare the load voltage with a preset voltage to obtain a first difference value; perform proportional integral (PI) control on the first difference value to obtain a target current; compare the target current with the load current to obtain a second difference value; and perform proportional integral (PI) control on the second difference value to obtain the phase-shift amount.

[0197] The device of the embodiment of the present application can be used to execute the technical solutions of any of the above-mentioned method embodiments, and has similar principles and technical effects, which will not be described here again.

[0198] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores computer execution instructions, and when a processor executes the computer execution instructions, the scheme of the driving method of the phase-shifted full-bridge soft switching circuit is realized.

[0199] The embodiment of the present application further provides a computer program product, and the computer program product contains computer execution instructions, and when a processor executes the computer execution instructions, the scheme of the driving method of the phase-shifted full-bridge soft switching circuit is realized.

[0200] The computer readable storage medium described above can be realized by any type of volatile or nonvolatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0201] An exemplary readable storage medium is coupled to the processor, so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in the driving device of the phase-shifted full-bridge soft switching circuit.

[0202] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The foregoing program can be stored in a computer readable storage medium. The program executes to perform the steps of the above-mentioned method embodiments; and the foregoing storage medium includes ROM, RAM, magnetic disk or optical disk and various storage medium that can store program codes.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A phase-shifted full-bridge soft-switching circuit, applied to a phase-shifted full-bridge synchronous rectification system, comprising a full-bridge circuit, a synchronous rectification circuit, a control module, and magnetic components, characterized in that, The control module is used to generate drive signals for driving each switching transistor based on the acquired load voltage and load current; the control module includes a first pulse width modulation unit, a second pulse width modulation unit, a third pulse width modulation unit, a fourth pulse width modulation unit, and a processing unit; wherein: The processing unit is configured to determine a phase shift amount based on the load voltage and the load current, and transmit the phase shift amount to the second pulse width modulation unit; and to determine a first dead time, a second dead time, and a third dead time based on the load current, wherein the first dead time and the second dead time are the dead times of the drive signals of different switching transistors contained in the lagging bridge arm and the leading bridge arm in the full-bridge circuit, respectively, and the third dead time is the dead time of the drive signal of the switching transistor in the synchronous rectification circuit and the drive signal of the switching transistor contained in the lagging bridge arm; The first pulse width modulation unit is used to generate a drive signal for driving the different switching transistors contained in the hysteresis bridge arm according to the first dead time. The second pulse width modulation unit is used to generate a drive signal for driving the different switching transistors contained in the lead bridge arm, based on the second dead time and the phase shift amount. The third pulse width modulation unit and the fourth pulse width modulation unit are respectively used to generate a drive signal for driving one switch and another switch included in the synchronous rectification circuit based on the first dead time, the second dead time, the third dead time and the phase shift. The logic for generating the drive signal by the third pulse width modulation unit is as follows: when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the sum of the count value corresponding to the duty cycle, the count value corresponding to the current phase shift, and the count value corresponding to the second dead time, and the output is configured to go high when the time base counter counts to the value of comparator A and is incrementing, and go low when it counts to the value of comparator B and is incrementing; wherein, the value of comparator B is the sum of the count value corresponding to the duty cycle and the count value corresponding to the third dead time; The logic for generating the drive signal by the fourth pulse width modulation unit is as follows: when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time, and the output is configured to go high when the time base counter counts to the value of comparator A and is decrementing, and go low when it counts to the value of comparator B and is decrementing; wherein, the value of comparator B is the count value corresponding to the duty cycle minus the count value corresponding to the third dead time.

2. The phase-shifted full-bridge soft-switching circuit according to claim 1, characterized in that, The first input terminal of the full-bridge circuit is connected to the DC input bus voltage, and the second input terminal of the full-bridge circuit is grounded. One end of the primary winding of the magnetic device is connected to the output terminal of the lagging bridge arm of the full-bridge circuit via a first inductor, and the other end of the primary winding of the magnetic device is connected to the output terminal of the leading bridge arm of the full-bridge circuit via a first capacitor. The first input terminal of the synchronous rectifier circuit is connected to the first terminal of the secondary winding of the magnetic device, the second input terminal of the synchronous rectifier circuit is connected to the second terminal of the secondary winding of the magnetic device, and the output terminal of the synchronous rectifier circuit is connected to the load. The middle tap of the secondary winding of the magnetic device is grounded.

3. The phase-shifted full-bridge soft-switching circuit according to claim 2, characterized in that, The switching transistors include a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; the lagging bridge arm includes the first switching transistor and the second switching transistor; the leading bridge arm includes the third switching transistor and the fourth switching transistor; wherein: The drain of the first switching transistor is connected to the drain of the third switching transistor, and the connection terminal serves as the first input terminal of the full-bridge circuit. The source of the second switch is connected to the source of the fourth switch, and the connection terminal serves as the second input terminal of the full-bridge circuit. The source of the first switching transistor is connected to the drain of the second switching transistor, and the connection terminal serves as the output terminal of the hysteresis arm of the full-bridge circuit. The source of the third switch is connected to the drain of the fourth switch, and the connection terminal serves as the output terminal of the leading bridge arm of the full-bridge circuit. The gates of the first switch, the second switch, the third switch, and the fourth switch are respectively connected to different output terminals of the control module for inputting their respective drive signals.

4. The phase-shifted full-bridge soft-switching circuit according to claim 2, characterized in that, The switching transistors include a fifth switching transistor and a sixth switching transistor, and the synchronous rectification circuit includes the fifth switching transistor and the sixth switching transistor; wherein: The source of the fifth switch serves as the first input terminal of the synchronous rectifier circuit; The source of the sixth switch serves as the second input terminal of the synchronous rectifier circuit; The drain of the fifth switch is connected to the drain of the sixth switch, and the connection terminal serves as the output terminal of the synchronous rectification circuit. The gates of the fifth and sixth switching transistors are respectively connected to different output terminals of the control module, and are used to input their respective driving signals.

5. The phase-shifted full-bridge soft-switching circuit according to claim 2, characterized in that, It also includes a second capacitor and a second inductor. The output terminal of the synchronous rectifier circuit is connected to the load via the second inductor, and the second capacitor is connected in parallel with the load.

6. The phase-shifted full-bridge soft-switching circuit according to claim 1, characterized in that, The first pulse width modulation unit is further configured to generate a synchronization signal and output the synchronization signal to the second pulse width modulation unit; The second pulse width modulation unit is also used to output the synchronization signal to the third pulse width modulation unit; The third pulse width modulation unit is also used to output the synchronization signal to the fourth pulse width modulation unit.

7. A driving method for a phase-shifted full-bridge soft-switching circuit, characterized in that, The phase-shifted full-bridge soft-switching circuit, as described in any one of claims 1 to 6, is further described by the driving method of the phase-shifted full-bridge soft-switching circuit comprising: The phase shift amount is determined based on the load voltage and the load current; Based on the load current, a first dead time, a second dead time, and a third dead time are determined. The first dead time and the second dead time are the dead times of the drive signals of different switching transistors contained in the lagging bridge arm and the leading bridge arm in the full-bridge circuit, respectively. The third dead time is the dead time of the drive signal of the switching transistor in the synchronous rectifier circuit and the drive signal of the switching transistor contained in the lagging bridge arm. Based on the first dead time, a drive signal is generated to drive the different switching transistors contained in the hysteresis bridge arm; Based on the second dead time and the phase shift, drive signals are generated to drive the different switching transistors contained in the advanced bridge arm; Based on the first dead time, the second dead time, the third dead time, and the phase shift, a drive signal is generated to drive a switching transistor included in the synchronous rectification circuit. Specifically, when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the sum of the count value corresponding to the duty cycle, the count value corresponding to the current phase shift, and the count value corresponding to the second dead time. The output is configured to go high when the time base counter counts to the value of comparator A and is incrementing, and go low when it counts to the value of comparator B and is incrementing. The value of comparator B is the sum of the count value corresponding to the duty cycle and the count value corresponding to the third dead time. Based on the first dead time, the second dead time, the third dead time, and the phase shift, a drive signal is generated to drive another switch included in the synchronous rectification circuit. Specifically, when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time. The output is configured to go high when the time base counter counts to the value of comparator A and is decrementing, and go low when it counts to the value of comparator B and is decrementing. The value of comparator B is the count value corresponding to the duty cycle minus the count value corresponding to the third dead time.

8. A driving device for a phase-shifted full-bridge soft-switching circuit, characterized in that, The phase-shifted full-bridge soft-switching circuit as described in any one of claims 1 to 6, wherein the driving device for the phase-shifted full-bridge soft-switching circuit comprises: The first determining module is used to determine the phase shift amount based on the load voltage and the load current; The second determining module is used to determine a first dead time, a second dead time, and a third dead time based on the load current. The first dead time and the second dead time are the dead times of the drive signals of different switching transistors contained in the lagging bridge arm and the leading bridge arm in the full-bridge circuit, respectively. The third dead time is the dead time of the drive signal of the switching transistor in the synchronous rectification circuit and the drive signal of the switching transistor contained in the lagging bridge arm. The first generation module is used to generate drive signals for driving the different switching transistors contained in the hysteresis bridge arm based on the first dead time. The second generation module is used to generate drive signals for driving the different switching transistors contained in the advanced bridge arm based on the second dead time and the phase shift amount. The third generation module is used to generate a drive signal for driving a switching transistor included in the synchronous rectification circuit based on the first dead time, the second dead time, the third dead time, and the phase shift. Specifically, when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the sum of the count value corresponding to the duty cycle, the count value corresponding to the current phase shift, and the count value corresponding to the second dead time. The output is configured to go high when the time base counter counts to the value of comparator A and is incrementing, and go low when it counts to the value of comparator B and is incrementing. The value of comparator B is the sum of the count value corresponding to the duty cycle and the count value corresponding to the third dead time. The fourth generation module is used to generate a drive signal for driving another switch included in the synchronous rectification circuit based on the first dead time, the second dead time, the third dead time, and the phase shift. Specifically, when the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time is greater than zero, and the count value corresponding to the current phase shift is greater than the count value corresponding to the first dead time, the value of comparator A is set to the count value corresponding to the duty cycle minus the count value corresponding to the current phase shift minus the count value corresponding to the second dead time. The output is configured to go high when the time base counter counts to the value of comparator A and is decrementing, and go low when it counts to the value of comparator B and is decrementing. The value of comparator B is the count value corresponding to the duty cycle minus the count value corresponding to the third dead time.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed, implement the driving method of the phase-shifted full-bridge soft-switching circuit as described in claim 7.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the driving method for the phase-shifted full-bridge soft-switching circuit as described in claim 7.

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