A peak detector and a peak detection method

Abstract

The application discloses a peak detector, which comprises a signal input end, a signal output end, a first triode, a sampling capacitor and a bias current control circuit; the base of the first triode is connected with the signal input end; the collector of the first triode is connected with a power supply voltage; the emitter of the first triode is connected with the bias current control circuit, the sampling capacitor and the signal output end respectively; the terminal of the sampling capacitor, which is not connected with the emitter of the first triode, is grounded; the bias current control circuit is connected with a first bias circuit; when the input signal is in a peak value detection period, the bias current control circuit is connected with the first bias circuit, the bias current is connected with the emitter of the first triode, and the signal output end outputs a detection signal; when the input signal is in a non-peak value detection period, the bias current control circuit is disconnected with the first bias circuit and the first triode simultaneously. The peak detector has higher detection precision in high-speed detection.

Description

Technical Field

[0001] This invention belongs to the field of peak detector technology, specifically relating to a peak detector and a peak detection method. Background Technology

[0002] High-performance peak detectors are widely used as sub-circuit units in various communication systems. In communication systems, peak detectors can assist in determining whether a communication channel is functioning correctly. For example, if the peak detector detects a signal amplitude below a certain set level, it is considered that the signal is interrupted or the user has lost connection. High-speed, high-precision peak detectors can significantly reduce the diagnostic time for the presence or absence of signals in communication systems, thereby improving network efficiency.

[0003] Figure 1(a) shows the circuit diagram of a traditional detector. In a traditional detector, monitoring speed and accuracy are mutually constrained. When the input signal rises or is at its peak, the peak detector Q1 quickly charges the output capacitor Cpk to its peak value. When the input signal is in a non-peak period, the sampling capacitor Cpk maintains the detected peak voltage, but due to the discharge effect of the bias current IB, the detected voltage on the sampling capacitor Cpk continues to decrease until the next peak value arrives. The working principle of a traditional detector inevitably results in ripple on the detector output voltage Vout. To improve the operating speed, the bias current IB needs to be appropriately increased, but increasing IB leads to a larger output ripple. Summary of the Invention

[0004] Technical problem solved: Based on the aforementioned technical problem, this invention discloses a peak detector and a peak detection method, which have higher detection accuracy in high-speed detection.

[0005] Technical solution:

[0006] A peak detector includes a signal input terminal, a signal output terminal, a first transistor (Q1), a sampling capacitor (Cpk), and a bias current control circuit (block1).

[0007] The base of the first transistor (Q1) is connected to the signal input terminal to receive the input signal (Vin); the collector of the first transistor (Q1) is connected to the power supply voltage; the emitter of the first transistor (Q1) is connected to the bias current control circuit (block1), the sampling capacitor (Cpk), and the signal output terminal, respectively; the terminal of the sampling capacitor (Cpk) that is not connected to the emitter of the first transistor (Q1) is grounded; the bias current control circuit (block1) is connected to the first bias circuit.

[0008] Specifically, when the input signal (Vin) is in the peak period to be measured, the bias current control circuit (block1) connects to the first bias circuit, and connects the bias current (IB) to the emitter of the first transistor (Q1), and outputs the detector signal (Vout) at the signal output terminal; when the input signal (Vin) is not in the peak period to be measured, the bias current control circuit (block1) simultaneously disconnects the first bias circuit and the first transistor (Q1).

[0009] Furthermore, the bias current control circuit (block 1) includes a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), and a second bias circuit;

[0010] The base of the second transistor (Q2) is connected to the signal input terminal, the emitter of the second transistor (Q2) is connected to the base of the second bias circuit and the third transistor (Q3) respectively, and the collector of the second transistor (Q2) is connected to the power supply voltage.

[0011] The collector of the third transistor (Q3) and the base of the fourth transistor (Q4) are both connected to the emitter of the first transistor (Q1). The emitters of the third transistor (Q3) and the fourth transistor (Q4) are both connected to the first bias circuit. The collector of the fourth transistor (Q4) is connected to the power supply voltage.

[0012] When the input signal (Vin) is at the peak value to be measured, the third transistor (Q3) and the fourth transistor (Q4) are turned on, and the sampling capacitor (Cpk) is charged by the first transistor (Q1). When the input signal (Vin) is not at the peak value to be measured, the first transistor (Q1) and the third transistor (Q3) are turned off, the fourth transistor (Q4) is turned on, and the voltage of the sampling capacitor (Cpk) remains constant.

[0013] Furthermore, the bias current control circuit (block1) includes a resistor, a filter capacitor, a third transistor (Q3), a fourth transistor (Q4), and a second bias circuit;

[0014] The two ends of the filter capacitor are connected to the signal input terminal and the base of the third transistor (Q3) respectively; one end of the resistor is connected to the base of the third transistor (Q3), and the other end is connected to the bias voltage.

[0015] The collector of the third transistor (Q3) and the base of the fourth transistor (Q4) are both connected to the emitter of the first transistor (Q1). The emitters of the third transistor (Q3) and the fourth transistor (Q4) are both connected to the first bias circuit. The collector of the fourth transistor (Q4) is connected to the power supply voltage.

[0016] When the input signal (Vin) is at the peak value to be measured, the third transistor (Q3) and the fourth transistor (Q4) are turned on, and the sampling capacitor (Cpk) is charged by the first transistor (Q1). When the input signal (Vin) is not at the peak value to be measured, the first transistor (Q1) and the third transistor (Q3) are turned off, the fourth transistor (Q4) is turned on, and the voltage of the sampling capacitor (Cpk) remains constant.

[0017] Furthermore, the transistor used in the peak detector is one of the following: NPN transistor, PNP transistor, PMOS transistor, NMOS transistor, or insulated gate bipolar transistor.

[0018] A differential peak detector, the differential peak detector comprising two peak detectors symmetrically arranged;

[0019] The peak detector is the same as described above, and the two peak detectors share the same sampling capacitor (Cpk).

[0020] A peak detection method based on the aforementioned peak detector, the peak detection method comprising the following steps:

[0021] When the input signal (Vin) is in the peak detection period, the bias current control circuit (block1) connects to the first bias circuit, and the bias current (IB) is connected to the emitter of the first transistor (Q1). The signal output terminal outputs the detection signal (Vout), and the sampling capacitor (Cpk) is charged at the same time. When the input signal (Vin) is in the non-peak detection period, the bias current control circuit (block1) disconnects the first bias circuit and the first transistor (Q1) at the same time. The sampling capacitor (Cpk) maintains the detection voltage of the previous peak value until the next peak detection period.

[0022] Beneficial effects:

[0023] First, the peak detector of the present invention introduces a bias current control circuit block1 on the basis of a traditional detector. During the no-signal and peak detection stages, the bias current of the detection circuit Q1 remains unchanged, thereby achieving high-speed detection. During the non-signal valley or negative peak stages, the bias current is turned off, and there is no discharge current on the sampling capacitor Cpk, thereby keeping the detection signal unchanged. The introduction of the bias current control circuit block1 greatly improves the detection accuracy of the high-speed detector.

[0024] Secondly, the peak detector of the present invention can solve the conflict between high-speed detection and high precision in traditional detectors. The detector technology of the present invention can achieve high-speed detection while maintaining high precision.

[0025] Third, the peak detector of the present invention has a wide range of applications. For example, it can be used in PON systems to monitor whether burst user data packets are valid; it can also be used in high-speed AGC (automatic gain control) loops to detect signal amplitude, etc. Attached Figure Description

[0026] Figure 1(a) is a schematic diagram of the structure of a traditional peak detector;

[0027] Figure 1(b) is a schematic diagram of the peak detector in this embodiment;

[0028] Figure 2 This is a schematic diagram of one type of bias current control circuit.

[0029] Figure 3 A schematic diagram comparing the simulation results of a traditional detector and the detector in this embodiment;

[0030] Figures 4(a) to 4(d) Figure 4(a) is a schematic diagram of a differential positive peak detector based on an NPN transistor; Figure 4(b) is a schematic diagram of a differential positive peak detector based on an NMOS transistor; Figure 4(c) is a schematic diagram of a single-ended positive peak detector based on an AC-coupled NPN transistor; Figure 4(d) is a schematic diagram of a single-ended positive peak detector based on an AC-coupled NMOS transistor. Detailed Implementation

[0031] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0032] Figure 1(b) is a schematic diagram of the peak detector in this embodiment. Referring to Figure 1(b), the peak detector includes a signal input terminal, a signal output terminal, a first transistor Q1, a sampling capacitor Cpk, and a bias current control circuit block1.

[0033] The base of the first transistor Q1 is connected to the signal input terminal to receive the input signal Vin; the collector of the first transistor Q1 is connected to the power supply voltage; the emitter of the first transistor Q1 is connected to the bias current control circuit block1, the sampling capacitor Cpk, and the signal output terminal respectively; the terminal of the sampling capacitor Cpk that is not connected to the emitter of the first transistor Q1 is grounded; and the bias current control circuit block1 is connected to the first bias circuit.

[0034] Specifically, when the input signal Vin is in the peak period to be measured, the bias current control circuit block1 connects to the first bias circuit, and connects the bias current IB to the emitter of the first transistor Q1, and outputs the detection signal Vout at the signal output terminal; when the input signal Vin is not in the peak period to be measured, the bias current control circuit block1 disconnects the first bias circuit and the first transistor Q1 at the same time.

[0035] In this embodiment, the basic functions of the bias current control circuit block1 include: 1) when the signal Vin is at the peak value to be measured, the bias current IB is connected to the emitter of the first transistor Q1 to improve the detector's operating speed, and the voltage on the sampling capacitor Cpk is the same as the input signal Vin; 2) when the signal Vin is not at the peak value to be measured, the bias current IB is disconnected from or bypassed by the first transistor Q1, and the sampling capacitor has no discharge path to accurately maintain the sampling peak value. Therefore, after introducing the block1 functional module, the peak detector in this embodiment can achieve high-speed detection while maintaining high detection accuracy.

[0036] Figure 2 This is a schematic diagram of one type of bias current control circuit. The base of the second transistor Q2 is connected to the input signal Vin, and its emitter is connected to the base of the third transistor Q3 and the second bias circuit. The second bias circuit provides a bias current IB2 for the second transistor Q2. The collector of the third transistor Q3 is connected to the signal output terminal, and its emitter is connected to the emitter of the third transistor Q3. The base of the fourth transistor Q4 is connected to the signal output terminal Vout, and its collector is connected to the power supply voltage VCC or other voltages.

[0037] Based on this structure, the peak detector works as follows: 1) When the input signal Vin is at its peak value, transistors Q3 and Q4 are simultaneously turned on. Half of the bias current IB flows through transistor Q1, which operates in a high standby state. Simultaneously, transistor Q1 charges the sampling capacitor Cpk, and the peak detector output signal Vout quickly follows the rise of the input signal Vin. 2) When the input signal Vin is in a non-peak value period, transistors Q1 and Q3 are turned off, and transistor Q4 is turned on, bypassing the bias current IB. The peak detector output voltage Vout is maintained by the sampling capacitor Cpk.

[0038] Figure 3 The following is a simulation comparison of the detection characteristics of a conventional peak detector and the peak detector of this embodiment under the same input conditions: Figure 3 The black square wave represents the input signal Vin, the light gray waveform represents the output of a conventional peak detector, and the dark gray waveform represents the output of the peak detector in this embodiment. Figure 3 It is easy to see that the peak detector in this embodiment has higher detection accuracy during high-speed detection.

[0039] Figure 2 This is merely one implementation of the peak detector in this embodiment. Figures 4(a) to 4(b) Several other typical implementation schemes for peak detectors are further presented.

[0040] It should be understood that the implementation scheme of the peak detector in this embodiment includes, but is not limited to, those described above. Figure 2 , Figures 4(a) to 4(b) The listed types of positive peak detectors. Due to the substitutability and complementarity of the components, Figure 2 , Figures 4(a) to 4(b) The peak detector implementation scheme can be simply replaced with PNP or PMOS devices to replace the corresponding negative peak detector and differential detector. When using PNP transistors or PMOS devices, the connection methods of the ground terminal and power supply voltage terminal are changed. For example, in the negative peak detector corresponding to Figure 4(c), the collectors of the first transistor Q1 and the fourth transistor Q4 are grounded, the terminal of the first bias circuit away from the third transistor Q3, and the terminal of the sampling capacitor away from the signal output terminal are connected to the power supply voltage. The peak detector of this embodiment can be further optimized into corresponding positive peak detectors, negative peak detectors, and peak-to-peak detectors constructed therefrom (positive peak minus negative peak), etc.

[0041] Based on the aforementioned peak detector, this embodiment mentions a peak detection method, which includes the following steps:

[0042] When the input signal Vin is in the peak detection period, the bias current control circuit block1 connects to the first bias circuit, and the bias current IB is connected to the emitter of the first transistor Q1. The signal output terminal outputs the detection signal Vout, and the sampling capacitor Cpk is charged at the same time. When the input signal Vin is in the non-peak detection period, the bias current control circuit block1 disconnects the first bias circuit and the first transistor Q1 at the same time. The sampling capacitor Cpk maintains the detection voltage of the previous peak value until the next peak detection period.

Claims

1. A peak detector, characterized in that, The peak detector includes a signal input terminal, a signal output terminal, a first transistor (Q1), a sampling capacitor (Cpk), and a bias current control circuit (block1). The base of the first transistor (Q1) is connected to the signal input terminal to receive the input signal (Vin); the collector of the first transistor (Q1) is connected to the power supply voltage; the emitter of the first transistor (Q1) is connected to the bias current control circuit (block1), the sampling capacitor (Cpk), and the signal output terminal, respectively; the terminal of the sampling capacitor (Cpk) that is not connected to the emitter of the first transistor (Q1) is grounded; the bias current control circuit (block1) is connected to the first bias circuit. Specifically, when the input signal (Vin) is in the peak period to be measured, the bias current control circuit (block1) connects to the first bias circuit, and connects the bias current (IB) to the emitter of the first transistor (Q1), and outputs the detector signal (Vout) at the signal output terminal; when the input signal (Vin) is not in the peak period to be measured, the bias current control circuit (block1) simultaneously disconnects the first bias circuit and the first transistor (Q1).

2. The peak detector according to claim 1, characterized in that, The bias current control circuit (block 1) includes a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), and a second bias circuit; the base of the second transistor (Q2) is connected to the signal input terminal, the emitter of the second transistor (Q2) is connected to the second bias circuit and the base of the third transistor (Q3) respectively, and the collector of the second transistor (Q2) is connected to the power supply voltage; The collector of the third transistor (Q3) and the base of the fourth transistor (Q4) are both connected to the emitter of the first transistor (Q1). The emitters of the third transistor (Q3) and the fourth transistor (Q4) are both connected to the first bias circuit. The collector of the fourth transistor (Q4) is connected to the power supply voltage. When the input signal (Vin) is in the peak period to be measured, the third transistor (Q3) and the fourth transistor (Q4) are in the turned-on state, and the sampling capacitor (Cpk) is charged by the first transistor (Q1); when the input signal (Vin) is not in the peak period to be measured, the first transistor (Q1) and the third transistor (Q3) are in the turned-off state, the fourth transistor (Q4) is in the turned-on state, and the voltage of the sampling capacitor (Cpk) remains unchanged.

3. The peak detector according to claim 1, characterized in that, The bias current control circuit (block1) includes a resistor, a filter capacitor, a third transistor (Q3), a fourth transistor (Q4), and a second bias circuit; the two ends of the filter capacitor are connected to the signal input terminal and the base of the third transistor (Q3) respectively; one end of the resistor is connected to the base of the third transistor (Q3), and the other end is connected to the bias voltage. The collector of the third transistor (Q3) and the base of the fourth transistor (Q4) are both connected to the emitter of the first transistor (Q1). The emitters of the third transistor (Q3) and the fourth transistor (Q4) are both connected to the first bias circuit. The collector of the fourth transistor (Q4) is connected to the power supply voltage. When the input signal (Vin) is in the peak period to be measured, the third transistor (Q3) and the fourth transistor (Q4) are in the turned-on state, and the sampling capacitor (Cpk) is charged by the first transistor (Q1); when the input signal (Vin) is not in the peak period to be measured, the first transistor (Q1) and the third transistor (Q3) are in the turned-off state, the fourth transistor (Q4) is in the turned-on state, and the voltage of the sampling capacitor (Cpk) remains unchanged.

4. The peak detector according to any one of claims 1 to 3, characterized in that, The transistor used in the peak detector is one of the following: NPN transistor, PNP transistor, PMOS transistor, NMOS transistor, or insulated gate bipolar transistor.

5. A differential peak detector, characterized in that, The differential peak detector includes two peak detectors arranged symmetrically. The peak detector is the peak detector as described in any one of claims 1-3, and the two peak detectors share the same sampling capacitor (Cpk).

6. A peak detection method based on the peak detector according to any one of claims 1-3, characterized in that, The peak detection method includes the following steps: When the input signal (Vin) is in the peak detection period, the bias current control circuit (block1) connects to the first bias circuit, and the bias current (IB) is connected to the emitter of the first transistor (Q1). The signal output terminal outputs the detection signal (Vout), and the sampling capacitor (Cpk) is charged at the same time. When the input signal (Vin) is in the non-peak detection period, the bias current control circuit (block1) disconnects the first bias circuit and the first transistor (Q1) at the same time. The sampling capacitor (Cpk) maintains the detection voltage of the previous peak value until the next peak detection period.

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