Electrostatic discharge circuit, driver integrated circuit and display device

Abstract

The present invention provides an electrostatic discharge circuit, a driving integrated circuit and a display device. The electrostatic discharge circuit includes a first protection circuit and a second protection circuit; the first protection circuit includes at least two first protection transistors connected in series, and the second protection circuit includes at least two second protection transistors connected in series; the first protection circuit is used to control the generation of a first discharge current from the input-output interface to the power supply end when the voltage value of the voltage signal connected to the input-output interface is greater than the first voltage value threshold, and to generate a second discharge current from the input-output interface to the first voltage end when the voltage value of the voltage signal connected to the input-output interface is less than the second voltage value threshold. The present invention is compatible with the electrostatic discharge of the 1.2V / 1.8V dual-voltage input-output interface.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an electrostatic discharge circuit, a driving integrated circuit and a display device. Background Art

[0002] In the related art, under the 7nm process, the communication voltage between the AP (Application Processor) end and the DDIC (display driver integrated circuit) is 1.8V. With the improvement of process technology, the 5nm process technology is becoming more and more mature. When the AP-end device uses the 5nm process, the communication voltage between the AP end and the DDIC drops to 1.2V. Under the 7nm process, the power supply voltage of the logic circuit in the DDIC is greater than or equal to 1.65V and less than or equal to 1.95V, typically 1.8V. Under the 5nm process on the AP end, the communication voltage between the AP end and the DDIC is 1.2V. In order for the DDIC to better adapt to the communication requirements of the AP end under the 5nm process, a DDIC I / O (input and output) interface function compatible with 1.2V / 1.8V dual voltage is designed. The existing electrostatic discharge circuit is difficult to be compatible with the electrostatic discharge of the input and output interface. Summary of the invention

[0003] The main purpose of the present invention is to provide an electrostatic discharge circuit, a driving integrated circuit and a display device to solve the problem that the existing electrostatic discharge circuit is not compatible with the electrostatic discharge of the 1.2V / 1.8V dual voltage input and output interface.

[0004] In one aspect, an embodiment of the present invention provides an electrostatic discharge circuit, which is applied to a driving integrated circuit, wherein the electrostatic discharge circuit includes a first protection circuit and a second protection circuit;

[0005] The first protection circuit includes at least two first protection transistors connected in series, and the second protection circuit includes at least two second protection transistors connected in series;

[0006] A first end of the first protection circuit is electrically connected to an input / output interface of the driver integrated circuit, and a second end of the first protection circuit is electrically connected to a power supply end of the driver integrated circuit;

[0007] A first end of the second protection circuit is electrically connected to the input / output interface of the driving integrated circuit, and a second end of the second protection circuit is electrically connected to the first voltage end;

[0008] The first protection circuit is used to control the generation of a first discharge current from the input-output interface to the power supply end when the voltage value of the voltage signal connected to the input-output interface is greater than a first voltage value threshold, and to generate a second discharge current from the input-output interface to the first voltage end when the voltage value of the voltage signal connected to the input-output interface is less than a second voltage value threshold.

[0009] Optionally, the first protection circuit includes a first first protection transistor and a second first protection transistor;

[0010] The control electrode of the first first protection transistor is electrically connected to the first control voltage terminal, the first electrode of the first first protection transistor is electrically connected to the power supply terminal, and the second electrode of the first first protection transistor is electrically connected to the first electrode of the second first protection transistor;

[0011] The control electrode of the second first protection transistor is electrically connected to the second control voltage terminal, and the second electrode of the second first protection transistor is electrically connected to the input-output interface.

[0012] Optionally, the first first protection transistor and the second first protection transistor are both p-type transistors.

[0013] Optionally, the absolute value of the second control voltage is smaller than the absolute value of the first control voltage.

[0014] Optionally, the first protection circuit further includes a first protection resistor;

[0015] The second electrode of the second first protection transistor is electrically connected to the input-output interface through the first protection resistor.

[0016] Optionally, the first protection circuit further includes a third first protection transistor; the second electrode of the second first protection transistor is electrically connected to the input-output interface through the third first protection transistor;

[0017] The control electrode of the third first protection transistor is electrically connected to the third control voltage terminal, the first electrode of the third first protection transistor is electrically connected to the second electrode of the second first protection transistor, and the second electrode of the third first protection transistor is electrically connected to the input-output interface;

[0018] The third first protection transistor is a p-type transistor.

[0019] Optionally, the second protection circuit includes a first second protection transistor and a second second protection transistor;

[0020] The control electrode of the first second protection transistor is electrically connected to the fourth control voltage terminal, the first electrode of the first second protection transistor is electrically connected to the first voltage terminal, and the second electrode of the first second protection transistor is electrically connected to the first electrode of the second second protection transistor;

[0021] The control electrode of the second second protection transistor is electrically connected to the fifth control voltage terminal, and the second electrode of the second second protection transistor is electrically connected to the input-output interface.

[0022] Optionally, the first second protection transistor and the second second protection transistor are both n-type transistors.

[0023] Optionally, an absolute value of a fifth control voltage provided by the fifth control voltage terminal is smaller than an absolute value of a fourth control voltage provided by the fourth control voltage terminal.

[0024] Optionally, the second protection circuit further includes a second protection resistor;

[0025] The second electrode of the second second protection transistor is electrically connected to the input-output interface through the second protection resistor.

[0026] Optionally, the second protection circuit further includes a third second protection transistor;

[0027] The second electrode of the second second protection transistor is electrically connected to the input-output interface through the third second protection transistor;

[0028] The control electrode of the third second protection transistor is electrically connected to the sixth control voltage terminal, the first electrode of the third second protection transistor is electrically connected to the second electrode of the second second protection transistor, and the second electrode of the third second protection transistor is electrically connected to the input-output interface;

[0029] The third second protection transistor is an n-type transistor.

[0030] Optionally, the electrostatic discharge circuit described in at least one embodiment of the present invention further includes a first diode and a second diode;

[0031] The anode of the first diode is electrically connected to the input / output interface, and the cathode of the first diode is electrically connected to the power supply terminal;

[0032] An anode of the second diode is electrically connected to the first voltage terminal, and a cathode of the second diode is electrically connected to the input / output interface.

[0033] Optionally, the electrostatic discharge circuit described in at least one embodiment of the present invention further includes a voltage clamping circuit;

[0034] The voltage clamping circuit is electrically connected to the power supply end and is used for clamping the power supply voltage provided by the power supply end.

[0035] In a second aspect, an embodiment of the present invention provides a driver integrated circuit, comprising the above-mentioned electrostatic discharge circuit.

[0036] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned driver integrated circuit.

[0037] The electrostatic discharge circuit, the driving integrated circuit and the display device of the present invention are compatible with the electrostatic discharge of the 1.2V / 1.8V dual voltage input and output interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a structural diagram of an electrostatic discharge circuit according to an embodiment of the present invention;

[0039] Figure 2 is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present invention;

[0040] Figure 3 is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present invention;

[0041] Figure 4 is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present invention;

[0042] Figure 5 is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0045] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0046] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0047] The electrostatic discharge circuit described in the embodiment of the present invention is applied to a driving integrated circuit, and the electrostatic discharge circuit includes a first protection circuit and a second protection circuit;

[0048] The first protection circuit includes at least two first protection transistors connected in series, and the second protection circuit includes at least two second protection transistors connected in series;

[0049] A first end of the first protection circuit is electrically connected to an input / output interface of the driver integrated circuit, and a second end of the first protection circuit is electrically connected to a power supply end of the driver integrated circuit;

[0050] A first end of the second protection circuit is electrically connected to the input / output interface of the driving integrated circuit, and a second end of the second protection circuit is electrically connected to the first voltage end;

[0051] The first protection circuit is used to control the generation of a first discharge current from the input-output interface to the power supply end when the voltage value of the voltage signal connected to the input-output interface is greater than a first voltage value threshold, and to generate a second discharge current from the input-output interface to the first voltage end when the voltage value of the voltage signal connected to the input-output interface is less than a second voltage value threshold.

[0052] When the electrostatic release circuit described in the embodiment of the present invention is working, the first protection circuit generates a first discharge current from the input-output interface to the power supply end when the voltage value of the voltage signal connected to the input-output interface is greater than the first voltage value threshold, so as to provide a conduction path for the instantaneous large current to perform electrostatic release; when the voltage value of the voltage signal connected to the input-output interface is less than the second voltage value threshold, the second protection circuit generates a second discharge current from the input-output interface to the first voltage end, so as to provide a conduction path for the instantaneous large current to perform electrostatic release.

[0053] In at least one embodiment of the present invention, the first voltage terminal may be a ground terminal, but is not limited thereto.

[0054] In at least one embodiment of the present invention, the first voltage value threshold may be a positive value, the second voltage value threshold may be a negative value, and the values ​​of the first voltage value threshold and the second voltage value threshold may be selected according to actual conditions. For example, the first voltage value threshold may be 800V, and the second voltage value threshold may be -800V, but the present invention is not limited thereto.

[0055] In a specific implementation, a single 1.8V output buffer is constructed by an MV (medium voltage) device, and the corresponding electrostatic discharge circuit includes an MV ESD (electrostatic discharge) MOS (metal-oxide-semiconductor) transistor with a self-protection function. When the power supply terminal of the driver integrated circuit provides a 1.2V voltage signal, the gate-source voltage of the MV device in the output buffer is too low to obtain sufficient driving force. Therefore, a LV (low voltage) device can be used to obtain sufficient driving force when the voltage value of the power supply voltage provided by the power supply terminal decreases. However, the absolute value of the BVdss (drain-source breakdown voltage) of the LV MOS transistor is small. In order to improve the reliability of the electrostatic discharge circuit, in an embodiment of the present invention, the protection circuit in the electrostatic discharge circuit may include at least two protection transistors connected in series.

[0056] like Figure 1 As shown, the electrostatic discharge circuit according to the embodiment of the present invention is applied to a driving integrated circuit, and the electrostatic discharge circuit includes a first protection circuit 11 and a second protection circuit 12;

[0057] The first protection circuit 11 includes at least two first protection transistors connected in series, and the second protection circuit 12 includes at least two second protection transistors connected in series;

[0058] The first end of the first protection circuit 11 is electrically connected to the input / output interface IO1 of the driving integrated circuit, and the second end of the first protection circuit 11 is electrically connected to the power supply terminal P1 of the driving integrated circuit;

[0059] A first end of the second protection circuit 12 is electrically connected to the input / output interface IO1 of the driving integrated circuit, and a second end of the second protection circuit 12 is electrically connected to the first voltage terminal V1;

[0060] The first protection circuit 11 is used to control the generation of a first discharge current from the input-output interface IO1 to the power supply terminal P1 when the voltage value of the voltage signal connected to the input-output interface IO1 is greater than a first voltage value threshold, and to generate a second discharge current from the input-output interface IO1 to the first voltage terminal V1 when the voltage value of the voltage signal connected to the input-output interface IO1 is less than a second voltage value threshold.

[0061] Optionally, the first protection circuit includes a first first protection transistor and a second first protection transistor;

[0062] The control electrode of the first first protection transistor is electrically connected to the first control voltage terminal, the first electrode of the first first protection transistor is electrically connected to the power supply terminal, and the second electrode of the first first protection transistor is electrically connected to the first electrode of the second first protection transistor;

[0063] The control electrode of the second first protection transistor is electrically connected to the second control voltage terminal, and the second electrode of the second first protection transistor is electrically connected to the input-output interface.

[0064] In a specific implementation, the first protection circuit may include a first first protection transistor and a second first protection transistor connected in series, the first first protection transistor is electrically connected to the power supply terminal, and the second first protection transistor is electrically connected to the input-output interface.

[0065] In at least one embodiment of the present invention, the first first protection transistor and the second first protection transistor are both p-type transistors.

[0066] In a specific implementation, the absolute value of the second control voltage may be smaller than the absolute value of the first control voltage.

[0067] Optionally, the first protection circuit further includes a first protection resistor;

[0068] The second electrode of the second first protection transistor is electrically connected to the input-output interface through the first protection resistor.

[0069] In a specific implementation, since the LV MOS transistor has no self-protected ESD (electrostatic discharge) rule, the first protection circuit may further include a first protection resistor.

[0070] like Figure 2 As shown, Figure 1 Based on the embodiment of the electrostatic discharge circuit shown, in at least one embodiment of the present invention, the first protection circuit 11 includes a first first protection transistor M11, a second first protection transistor M11 and a first protection resistor R1;

[0071] The gate of the first first protection transistor M11 is electrically connected to the first control voltage terminal VC1, the source of the first first protection transistor M11 is electrically connected to the power supply terminal P1, and the drain of the first first protection transistor M11 is electrically connected to the source of the second first protection transistor M21;

[0072] The gate of the second first protection transistor M21 is electrically connected to the second control voltage terminal VC2, and the drain of the second first protection transistor M21 is electrically connected to the first end of the first protection resistor R1;

[0073] The second end of the first protection resistor R1 is electrically connected to the input-output interface IO1.

[0074] exist Figure 2 In at least one embodiment of the electrostatic discharge circuit shown, both M11 and M21 are p-type transistors, and the first control voltage provided by VC1 and the second control voltage provided by VC2 may be negative voltages.

[0075] exist Figure 2 In at least one embodiment of the electrostatic release circuit shown, when P1 provides a 1.8V voltage signal, VC1 can provide a -1.8V voltage signal, and VC2 can provide a -0.9V voltage signal; when P1 provides a 1.2V voltage signal, VC1 can provide a -1.2V voltage signal, and VC2 can provide a -0.6V voltage signal, but not limited to this.

[0076] exist Figure 2 In at least one embodiment of the electrostatic discharge circuit shown, the gate-source voltage of M11 is greater than the threshold voltage of M11, and the gate-source voltage of M21 is greater than the threshold voltage of M21.

[0077] The present invention Figure 2 When at least one embodiment of the electrostatic discharge circuit shown is in operation, when the voltage value of the voltage signal connected to IO1 is greater than the first voltage value threshold, so that M11 and M21 are broken down, a discharge path from IO1 to P1 is formed to perform electrostatic discharge.

[0078] exist Figure 2 In at least one embodiment of the electrostatic discharge circuit shown, the absolute value of the second control voltage is smaller than the absolute value of the first control voltage.

[0079] In at least one embodiment of the present invention, the first protection circuit further includes a third first protection transistor; the second electrode of the second first protection transistor is electrically connected to the input-output interface through the third first protection transistor;

[0080] The control electrode of the third first protection transistor is electrically connected to the third control voltage terminal, the first electrode of the third first protection transistor is electrically connected to the second electrode of the second first protection transistor, and the second electrode of the third first protection transistor is electrically connected to the input-output interface;

[0081] The third first protection transistor is a p-type transistor.

[0082] In a specific implementation, the first protection circuit may further include a third first protection transistor, which is arranged between the second first protection transistor and the input / output interface.

[0083] Optionally, the second protection circuit includes a first second protection transistor and a second second protection transistor;

[0084] The control electrode of the first second protection transistor is electrically connected to the fourth control voltage terminal, the first electrode of the first second protection transistor is electrically connected to the first voltage terminal, and the second electrode of the first second protection transistor is electrically connected to the first electrode of the second second protection transistor;

[0085] The control electrode of the second second protection transistor is electrically connected to the fifth control voltage terminal, and the second electrode of the second second protection transistor is electrically connected to the input-output interface.

[0086] In a specific implementation, the second protection circuit may include a first second protection transistor and a second second protection transistor connected in series, the first second protection transistor is electrically connected to the first voltage terminal, and the second second protection transistor is electrically connected to the input-output interface.

[0087] In a specific implementation, the first second protection transistor and the second second protection transistor may both be n-type transistors.

[0088] In at least one embodiment of the present invention, an absolute value of a fifth control voltage provided by the fifth control voltage terminal is smaller than an absolute value of a fourth control voltage provided by the fourth control voltage terminal.

[0089] Optionally, the second protection circuit further includes a second protection resistor;

[0090] The second electrode of the second second protection transistor is electrically connected to the input-output interface through the second protection resistor.

[0091] In a specific implementation, since the LV MOS transistor has no self-protected ESD (electrostatic discharge) rule, the second protection circuit may further include a second protection resistor.

[0092] like Figure 3 As shown, Figure 2 Based on at least one embodiment of the electrostatic discharge circuit shown, in at least one embodiment of the present invention, the second protection circuit includes a first second protection transistor M12, a second second protection transistor M22 and a second protection resistor R2;

[0093] The gate of the first second protection transistor M12 is electrically connected to the fourth control voltage terminal VC4, the source of the first second protection transistor M12 is electrically connected to the ground terminal GND, and the drain of the first second protection transistor M12 is electrically connected to the source of the second second protection transistor M22;

[0094] The gate of the second second protection transistor M22 is electrically connected to the fifth control voltage terminal VC5, and the drain of the second second protection transistor M22 is electrically connected to the first end of the second protection resistor R2;

[0095] The second end of the second protection resistor R2 is electrically connected to the input-output interface IO1.

[0096] exist Figure 3 In at least one embodiment of the electrostatic discharge circuit shown, both M12 and M22 are n-type transistors, and the fourth control voltage provided by VC4 and the fifth control voltage provided by VC5 can be positive voltages.

[0097] exist Figure 3 In at least one embodiment of the electrostatic release circuit shown, when P1 provides a 1.8V voltage signal, VC4 can provide a 1.8V voltage signal, and VC5 can provide a 0.9V voltage signal; when P1 provides a 1.2V voltage signal, VC4 can provide a 1.2V voltage signal, and VC5 can provide a 0.6V voltage signal, but not limited to this.

[0098] exist Figure 3 In at least one embodiment of the electrostatic discharge circuit shown, the gate-source voltage of M12 is less than the threshold voltage of M12, and the gate-source voltage of M22 is less than the threshold voltage of M22.

[0099] The present invention Figure 3 When at least one embodiment of the electrostatic discharge circuit shown is in operation, when the voltage value of the voltage signal connected to IO1 is less than the second voltage value threshold, so that M12 and M22 are broken down, a discharge path from IO1 to GND is formed to perform electrostatic discharge.

[0100] exist Figure 3 In at least one embodiment of the electrostatic discharge circuit shown, the absolute value of the fifth control voltage is smaller than the absolute value of the fourth control voltage.

[0101] In at least one embodiment of the present invention, the second protection circuit may further include a third second protection transistor;

[0102] The second electrode of the second second protection transistor is electrically connected to the input-output interface through the third second protection transistor;

[0103] The control electrode of the third second protection transistor is electrically connected to the sixth control voltage terminal, the first electrode of the third second protection transistor is electrically connected to the second electrode of the second second protection transistor, and the second electrode of the third second protection transistor is electrically connected to the input-output interface;

[0104] The third second protection transistor is an n-type transistor.

[0105] In a specific implementation, the second protection circuit may further include a third second protection transistor, and the third second protection transistor is arranged between the second protection transistor and the input-output interface.

[0106] The electrostatic discharge circuit described in at least one embodiment of the present invention may further include a first diode and a second diode to perform voltage clamping;

[0107] The anode of the first diode is electrically connected to the input / output interface, and the cathode of the first diode is electrically connected to the power supply terminal;

[0108] An anode of the second diode is electrically connected to the first voltage terminal, and a cathode of the second diode is electrically connected to the input / output interface.

[0109] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the electrostatic discharge circuit shown, the electrostatic discharge circuit according to at least one embodiment of the present invention may further include a first diode D1 and a second diode D2;

[0110] An anode of the first diode D1 is electrically connected to the input / output interface IO1, and a cathode of the first diode D1 is electrically connected to the power supply terminal P1;

[0111] An anode of the second diode D2 is electrically connected to the ground terminal GND, and a cathode of the second diode D2 is electrically connected to the input / output interface IO1.

[0112] The present invention Figure 4 When at least one embodiment of the electrostatic discharge circuit shown is in operation, when the power supply terminal P1 provides a 1.2V voltage signal, the forward conduction voltage drop Vf of D1 is 0.1V, and IO1 provides a 1.5V voltage signal, D1 is turned on to clamp the voltage of IO1 at 1.3V;

[0113] When the forward conduction voltage drop Vf of D2 is 0.1V, when IO1 provides a -0.5V voltage signal, D2 is turned on to clamp the potential of IO1 at -0.1V.

[0114] exist Figure 3 , Figure 4 In at least one embodiment of the electrostatic discharge circuit shown, M11 and M21 are stacked, and M21 and M22 are stacked, so as to limit the voltage by twice the BVdss (drain-source breakdown voltage) of the low-voltage MOS transistor, thereby improving the reliability of the ESD circuit.

[0115] In at least one embodiment of the present invention, the power supply terminal is used to provide a first power supply voltage or a second power supply voltage; for example, the first power supply voltage may be a 1.8V voltage signal, and the second power supply voltage may be a 1.2V voltage signal, but not limited thereto;

[0116] The protection transistor included in the first protection circuit and the protection transistor included in the second protection circuit may both be low voltage process transistors.

[0117] Optionally, the electrostatic discharge circuit described in at least one embodiment of the present invention further includes a voltage clamping circuit;

[0118] The voltage clamping circuit is electrically connected to the power supply end and is used for clamping the power supply voltage provided by the power supply end.

[0119] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the electrostatic discharge circuit shown in the figure, the electrostatic discharge circuit according to at least one embodiment of the present invention further includes a voltage clamping circuit 50;

[0120] The voltage clamping circuit 50 is electrically connected to the power supply terminal P1 and is used to clamp the power supply voltage provided by the power supply terminal P1.

[0121] The present invention Figure 5 When at least one embodiment of the electrostatic discharge circuit shown is in operation, when the power supply terminal P1 provides a 1.8V voltage signal, the voltage clamping circuit 50 is used to clamp the power supply voltage to 1.8V;

[0122] When the power supply terminal P1 provides a 1.2V voltage signal, the voltage clamping circuit 50 is used to clamp the power supply voltage to 1.2V.

[0123] The driving integrated circuit described in the embodiment of the present invention includes the above-mentioned electrostatic discharge circuit.

[0124] The display device described in the embodiment of the present invention includes the above-mentioned driver integrated circuit.

[0125] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0126] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An electrostatic discharge circuit, applied to a driver integrated circuit, characterized in that: The electrostatic discharge circuit includes a first protection circuit and a second protection circuit; The first protection circuit includes at least two first protection transistors connected in series, and the second protection circuit includes at least two second protection transistors connected in series; A first end of the first protection circuit is electrically connected to an input / output interface of the driver integrated circuit, and a second end of the first protection circuit is electrically connected to a power supply end of the driver integrated circuit; A first end of the second protection circuit is electrically connected to the input / output interface of the driving integrated circuit, and a second end of the second protection circuit is electrically connected to the first voltage end; The first protection circuit is used to control the generation of a first discharge current from the input-output interface to the power supply terminal when the voltage value of the voltage signal connected to the input-output interface is greater than a first voltage value threshold, and to generate a second discharge current from the input-output interface to the first voltage terminal when the voltage value of the voltage signal connected to the input-output interface is less than a second voltage value threshold; The first protection circuit includes a first first protection transistor and a second first protection transistor; The control electrode of the first first protection transistor is electrically connected to the first control voltage terminal, the first electrode of the first first protection transistor is electrically connected to the power supply terminal, and the second electrode of the first first protection transistor is electrically connected to the first electrode of the second first protection transistor; The control electrode of the second first protection transistor is electrically connected to the second control voltage terminal, and the second electrode of the second first protection transistor is electrically connected to the input-output interface; The second protection circuit includes a first second protection transistor and a second second protection transistor; The control electrode of the first second protection transistor is electrically connected to the fourth control voltage terminal, the first electrode of the first second protection transistor is electrically connected to the first voltage terminal, and the second electrode of the first second protection transistor is electrically connected to the first electrode of the second second protection transistor; The control electrode of the second second protection transistor is electrically connected to the fifth control voltage terminal, and the second electrode of the second second protection transistor is electrically connected to the input-output interface; The first first protection transistor and the second first protection transistor are both p-type transistors; the first second protection transistor and the second second protection transistor are both n-type transistors; The first voltage value threshold is greater than the second voltage value threshold.

2. The electrostatic discharge circuit according to claim 1, wherein: An absolute value of the second control voltage is smaller than an absolute value of the first control voltage.

3. The electrostatic discharge circuit according to claim 1, wherein: The first protection circuit also includes a first protection resistor; The second electrode of the second first protection transistor is electrically connected to the input-output interface through the first protection resistor.

4. The electrostatic discharge circuit according to claim 1, wherein: The first protection circuit further includes a third first protection transistor; the second electrode of the second first protection transistor is electrically connected to the input-output interface through the third first protection transistor; The control electrode of the third first protection transistor is electrically connected to the third control voltage terminal, the first electrode of the third first protection transistor is electrically connected to the second electrode of the second first protection transistor, and the second electrode of the third first protection transistor is electrically connected to the input-output interface; The third first protection transistor is a p-type transistor.

5. The electrostatic discharge circuit according to claim 1, wherein: An absolute value of a fifth control voltage provided by the fifth control voltage terminal is smaller than an absolute value of a fourth control voltage provided by the fourth control voltage terminal.

6. The electrostatic discharge circuit according to claim 1, wherein: The second protection circuit also includes a second protection resistor; The second electrode of the second second protection transistor is electrically connected to the input-output interface through the second protection resistor.

7. The electrostatic discharge circuit according to claim 1, wherein: The second protection circuit further includes a third second protection transistor; The second electrode of the second second protection transistor is electrically connected to the input-output interface through the third second protection transistor; The control electrode of the third second protection transistor is electrically connected to the sixth control voltage terminal, the first electrode of the third second protection transistor is electrically connected to the second electrode of the second second protection transistor, and the second electrode of the third second protection transistor is electrically connected to the input-output interface; The third second protection transistor is an n-type transistor.

8. The electrostatic discharge circuit according to any one of claims 1 to 7, characterized in that: Also including a first diode and a second diode; An anode of the first diode is electrically connected to the input / output interface, and a cathode of the first diode is electrically connected to the power supply terminal; An anode of the second diode is electrically connected to the first voltage terminal, and a cathode of the second diode is electrically connected to the input / output interface.

9. The electrostatic discharge circuit according to any one of claims 1 to 7, characterized in that: Also included is a voltage clamping circuit; The voltage clamping circuit is electrically connected to the power supply end and is used for clamping the power supply voltage provided by the power supply end.

10. A driver integrated circuit, characterized in that: The method comprises an electrostatic discharge circuit as claimed in any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the driver integrated circuit as claimed in claim 10.

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