Methods and apparatus for detecting defects on wafer surfaces

Abstract

This invention provides a method and apparatus for detecting surface defects on a wafer. The method includes: receiving scanning information of a wafer, wherein the scanning information includes multiple scanning parameters; determining at least one reference point of the scanning information, and generating path information based on the at least one reference point and a reference value; obtaining multiple first scanning parameters corresponding to the path information from the scanning parameters to generate a curve; and determining whether the wafer has defects and the defect type based on the curve.

Description

Technical Field

[0001] This invention relates to a defect detection technology for semiconductor wafers, and more particularly to a wafer surface defect detection method and a wafer surface defect detection device. Background Technology

[0002] Before electronic components leave the factory, they are typically inspected visually by experienced visual inspectors to check for defects or flatness. For example, when determining the flatness of a silicon carbide (SiC) wafer, an automated optical inspection (AOI) device is used to obtain a haze image of the wafer, which is then manually interpreted by the human eye.

[0003] However, there is no consistent standard for interpreting visual inspections by visual inspectors, which often leads to misjudgments due to the subjective interpretation of each inspector. Therefore, how to avoid the problem of overly subjective test results caused by relying on visual inspection is a matter of concern to those skilled in the art. Summary of the Invention

[0004] This invention provides a wafer surface defect detection method and a wafer surface defect detection device, which can automatically identify the scanning information of the wafer and improve the integrity and accuracy of defect detection.

[0005] An embodiment of the present invention provides a method for detecting defects on a wafer surface, applicable to an electronic device including a processor. The method includes: receiving scanning information of a wafer, wherein the scanning information includes a plurality of scanning parameters; determining at least one reference point of the scanning information, and generating path information based on the at least one reference point and a reference value; obtaining a plurality of first scanning parameters corresponding to the path information from the scanning parameters to generate a graph; and determining whether the wafer has defects and the type of the defects based on the graph.

[0006] In an exemplary embodiment of the present invention, the reference value includes at least one radius. The steps of determining the at least one reference point of the scan information and generating the path information based on the at least one reference point and the reference value include: calculating the center of the wafer corresponding to the scan information as the at least one reference point; and determining at least one circular path based on the at least one reference point and the at least one radius.

[0007] In an exemplary embodiment of the present invention, the step of obtaining the scanning parameters of the scanning information based on the path information to generate the curve includes: obtaining the first scanning parameters from the pixels corresponding to the at least one circular path in the scanning information along the direction of the at least one circular path; and generating the curve according to the first scanning parameters and the order in which the first scanning parameters were obtained.

[0008] In an exemplary embodiment of the present invention, the aforementioned reference value includes a slicing angle. The steps of determining the at least one reference point of the scan information and generating the path information based on the at least one reference point and the reference value include: calculating the facet position of the scan information and the center of the wafer corresponding to the scan information; calculating the midpoint of the facet position as a first reference point and the center of the wafer as a second reference point; determining a reference path based on the first reference point and the second reference point; and determining a through-path based on the reference path and the slicing angle.

[0009] In an exemplary embodiment of the present invention, the step of determining the through-path based on the reference path and the slice angle includes: calculating a rotation angle based on the slice angle; and rotating the reference path based on the rotation angle to generate the through-path.

[0010] In an exemplary embodiment of the present invention, the step of obtaining the first scanning parameter corresponding to the path information in the scanning parameters according to the path information to generate the curve includes: obtaining the first scanning parameter from the pixel corresponding to the path in the scanning information along the direction of the through-path; and generating the curve according to the first scanning parameter and the order in which the first scanning parameter was obtained.

[0011] In an exemplary embodiment of the present invention, the steps of determining whether the wafer has a defect and determining the type of the defect based on the curve graph include: calculating the distance between each adjacent peak or each adjacent trough in the curve graph; if the difference between each distance is less than a first threshold value and at least one of the first scanning parameters is greater than a second threshold value, determining that the wafer has the defect; if the difference between each distance is not less than the first threshold value and at least one of the first scanning parameters is greater than the second threshold value, determining that the wafer has the defect; and if none of the first scanning parameters are greater than the second threshold value, determining that the wafer does not have the defect.

[0012] In one exemplary embodiment of the present invention, the above-mentioned defect types include at least one of sunburst pattern, zebra stripe pattern, and cloud pattern.

[0013] In an exemplary embodiment of the present invention, the scanning parameters are generated by scanning the wafer using a scanning device, and the scanning parameters include at least one of haze value, surface roughness value, and image parameters.

[0014] In an exemplary embodiment of the present invention, the above-mentioned image parameters include at least one of grayscale value, brightness value, contrast value, RGB hue value, saturation value, color temperature value, and Gamma value.

[0015] This invention provides a wafer surface defect detection device, including a connection device, a storage device, and a processor. The connection device is used to connect to a scanning device to receive scanning information generated by the scanning device scanning the wafer. The storage device stores one or more instructions. The processor is coupled to the connection device and the storage device and configured to execute the instructions to: receive the scanning information, wherein the scanning information includes multiple scanning parameters; determine at least one reference point of the scanning information, and generate path information based on the at least one reference point and a reference value; obtain multiple first scanning parameters corresponding to the path information from the scanning parameters to generate a curve; and determine whether the wafer has defects and determine the defect type based on the curve.

[0016] In an exemplary embodiment of the present invention, the reference value includes at least one radius. The operation of determining the at least one reference point of the scan information and generating the path information based on the at least one reference point and the reference value includes: calculating the center of the wafer corresponding to the scan information as the at least one reference point; and determining at least one circular path based on the at least one reference point and the at least one radius.

[0017] In an exemplary embodiment of the present invention, the operation of obtaining the scanning parameters of the scanning information based on the path information to generate the graph includes: obtaining the first scanning parameters from the pixels corresponding to the at least one circular path in the scanning information along the direction of the at least one circular path; and generating the graph according to the first scanning parameters and the order in which the first scanning parameters were obtained.

[0018] In an exemplary embodiment of the present invention, the aforementioned reference value includes a slicing angle. The operation of determining the at least one reference point of the scan information and generating the path information based on the at least one reference point and the reference value includes: calculating the facet position of the scan information and the center of the wafer corresponding to the scan information; calculating the midpoint of the facet position as a first reference point and the center of the wafer as a second reference point; determining a reference path based on the first reference point and the second reference point; and determining a through-path based on the reference path and the slicing angle.

[0019] In an exemplary embodiment of the present invention, the operation of determining the through-path based on the reference path and the slice angle includes: calculating a rotation angle based on the slice angle; and rotating the reference path based on the rotation angle to generate the through-path.

[0020] In an exemplary embodiment of the present invention, the operation of obtaining the first scanning parameter corresponding to the path information from the scanning parameters to generate the curve includes: obtaining the first scanning parameter from the pixel corresponding to the path in the scanning information along the direction of the through-path; and generating the curve according to the first scanning parameter and the order in which the first scanning parameter was obtained.

[0021] In an exemplary embodiment of the present invention, the operation of determining whether the wafer has a defect and determining the type of the defect based on the curve graph includes: calculating the distance between each adjacent peak or each adjacent trough in the curve graph; if the difference between each distance is less than a first threshold value and at least one of the first scanning parameters is greater than a second threshold value, determining that the wafer has the defect; if the difference between each distance is not less than the first threshold value and at least one of the first scanning parameters is greater than the second threshold value, determining that the wafer has the defect; and if the difference between each distance is not less than the first threshold value and all of the first scanning parameters are not greater than the second threshold value, determining that the wafer does not have the defect.

[0022] In one exemplary embodiment of the present invention, the above-mentioned defect types include at least one of sunburst pattern, zebra stripe pattern, and cloud pattern.

[0023] In an exemplary embodiment of the present invention, the scanning parameters are generated by the scanning device scanning the wafer, and the scanning parameters include at least one of haze value, surface roughness value and image parameters.

[0024] In an exemplary embodiment of the present invention, the above-mentioned image parameters include at least one of grayscale value, brightness value, contrast value, RGB hue value, saturation value, color temperature value, and Gamma value.

[0025] Based on the above, the wafer surface defect detection method and wafer surface defect detection device proposed in this invention can improve the accuracy of identification by extracting parameters from the wafer scanning information according to the path information and analyzing the extracted parameters.

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a wafer scanning system according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a wafer surface defect detection device according to an embodiment of the present invention;

[0029] Figures 3 to 4 This is an example of the texture content of a wafer as shown in an embodiment of the present invention;

[0030] Figure 5 This is a flowchart illustrating a wafer surface defect detection method according to an embodiment of the present invention;

[0031] Figure 6 This is an example of path information shown in an embodiment of the present invention;

[0032] Figure 7 This is an example of path information shown in an embodiment of the present invention;

[0033] Figure 8A This is a schematic diagram illustrating the generation process of the through-path according to an embodiment of the present invention;

[0034] Figure 8B This is a schematic diagram illustrating the generation process of the through-path according to another embodiment of the present invention;

[0035] Figure 9 This is an example of a graph shown according to an embodiment of the present invention. Detailed Implementation

[0036] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0037] Figure 1 This is a schematic diagram of a wafer scanning system according to an embodiment of the present invention. Please refer to... Figure 1 The wafer scanning system 100 can be applied to automated optical inspection equipment to scan semiconductor chips, wafers, circuit boards, panels, and other objects under test. In other words, the wafer scanning system 100 can be used to scan the surface of the object under test to obtain scanning information about the surface.

[0038] The wafer scanning system 100 may include a scanning device 110, a transfer device 120, and a light source device 130. The scanning device 110 has an optical lens 111. In one embodiment, the scanning device 110 may transmit control signals wired or wirelessly to control at least one of the optical lens 111, the transfer device 120, and the light source device 130. The optical lens 111 may be an area scan camera and / or a line scan camera. Line scan cameras are often used in conjunction with dynamic scanning inspection to capture images while the object under test 101 is moving. This ensures the continuity of the inspection process. The transfer device 120 is used to achieve fully automated inspection. For example, the transfer device 120 can transfer the object under test 101 to the inspection area and scan it via the optical lens 111 located on one side of the inspection area to obtain information about the object under test 101 for subsequent analysis.

[0039] In different embodiments, the wafer scanning system 100 may employ various wafer scanning systems, such as optical microscope systems, scanning electron microscope (SEM) systems, focused ion beam microscope (FIB) systems, laser microscope systems, transmission electron microscope (TEM) systems, scanning probe microscope (SPM) systems, or other suitable optical imaging systems. Accordingly, when employing different wafer scanning systems, the scanning information that the wafer scanning system 100 can obtain by scanning the surface of the object under test includes scanning parameters such as haze value, surface roughness (Ra), and image parameters. For example, image parameters include grayscale values, brightness values, contrast values, RGB hue values, saturation values, color temperature values, and gamma values, etc., which are not limited in this respect.

[0040] The light source device 130 provides a light source to assist in illuminating the object under test 101. The type of light source device 130 may be, for example, a parallel light fixture, a diffused light fixture, or a dome light, and this invention is not limited thereto. The light source device 130 can emit various types of light, such as white light, red light, green light, blue light, ultraviolet light, and infrared light. Furthermore, the type of light source device 130 can be changed to suit different types of objects under test 101. It should be noted that this invention does not limit the number of scanning devices 110, transfer devices 120, and light source devices 130.

[0041] Figure 2 This is a schematic diagram of a wafer surface defect detection device according to an embodiment of the present invention. Please refer to... Figure 2The wafer surface defect detection device 200 includes, but is not limited to, a connection device 210, a storage device 220, and a processor 230. The wafer surface defect detection device 200 can be any electronic device with computing capabilities, such as a personal computer, laptop computer, or server; this invention is not limited thereto. The connection device 210 is used to connect to the scanning device 110 via wired or wireless connection to receive scanning information generated by the scanning device 110 scanning the wafer.

[0042] Storage device 220 may include volatile storage media and / or non-volatile storage media and may be used to store data. For example, the volatile storage media may be random access memory (RAM), and the non-volatile storage media may be read-only memory (ROM), solid-state drive (SSD), or conventional hard disk drive (HDD) or other similar devices or combinations thereof, for storing one or more instructions executable by processor 230.

[0043] Processor 230 is coupled to connection device 210 and storage device 220, and can access and execute instructions recorded in storage device 220 to implement the wafer surface defect detection method of the present invention. In different embodiments, processor 230 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination thereof, and the present invention is not limited thereto.

[0044] In wafer fabrication, after silicon carbide is grown into silicon carbide ingots, it undergoes several processing steps. These steps include slicing, edge rounding, grinding, etching, heat treatment, and defect removal. During slicing and grinding, defects such as saw marks or grinding lines may be left on the wafer surface, resulting in an uneven surface. Under such processes, wafers are prone to zebra stripes, sunburst patterns, and wavy lines. Therefore, the sliced ​​wafers need to undergo further grinding processes of varying degrees to form a flat surface.

[0045] Figures 3 to 4This is an example of wafer texture content shown in an embodiment of the present invention. In wafer inspection, if a wafer image displays zebra stripes, sunburst patterns, cloud-like patterns, or other textures, it can be determined that the wafer surface corresponding to this image is not flat. For example, Figure 3 The image IMG_1 shows that its corresponding wafer has a sunburst pattern. Figure 4 Image IMG_2 shows that the corresponding wafer has zebra stripes. However, visual inspectors may interpret the flatness judgment criteria according to their own subjective understanding, leading to misjudgments. In view of this, the wafer surface defect detection method provided in this embodiment of the invention can solve the above problems.

[0046] Figure 5 This is a flowchart illustrating a wafer surface defect detection method according to an embodiment of the present invention. Please also refer to... Figure 2 and Figure 5 The method of this embodiment is applicable to the wafer surface defect detection device 200 described above, and will be used in conjunction with it below. Figure 2 and Figure 5 The components of the wafer surface defect detection device 200 are described, and the detailed process of the method in this embodiment is explained.

[0047] It should be noted that, Figure 5 Each step can be implemented as multiple codes or circuits, and this invention is not limited thereto. Furthermore, Figure 5 The methods described herein can be used in conjunction with the following exemplary embodiments, or they can be used alone; this invention does not impose any limitations.

[0048] In step S502, the processor 230 receives scan information of the wafer, wherein the scan information includes multiple scan parameters. Specifically, the scan information can be formatted as a pixel array, where each pixel in the pixel array represents a specific location on the corresponding wafer and contains a scan parameter. The number of pixels in the array can be varied depending on the resolution capability of the scanning device.

[0049] In step S504, the processor 230 determines at least one reference point of the scan information and generates path information based on the at least one reference point and a reference value. In this embodiment, the reference point corresponds to a specific coordinate of the wafer. For example, the reference point may include the center of the wafer or other coordinate points. Furthermore, the reference value may be any reference information such as wafer size parameters or wafer processing parameters. For example, wafer size parameters may include the wafer's dimensions, radius, etc., and wafer processing parameters may include the slicing angle, etc., which are not limited in this invention. The slicing angle is the angle between the wafer's flat edge (flat side) position and the dovetail groove, based on the dovetail groove used to fix the wafer during slicing. It should be noted that the reference value can be a value input by the operator. For example, the slicing angle is the angle input by the operator after confirming the wafer's flat edge (flat side) position.

[0050] The following section further details the implementation of generating path information.

[0051] Figure 6 This is an example of path information shown in an embodiment of the present invention. This embodiment is illustrated using the generation of a circular path as an example. In this embodiment, the reference value includes the radius of the wafer. In this embodiment, the processor 230 calculates the center of the wafer corresponding to the scan information as a reference point. Then, the processor 230 determines the circular path based on the radius and the reference point.

[0052] Please refer to Figure 6 , Figure 6 Image 601 is included, which is a graphical representation of scan information corresponding to a wafer. For ease of explanation, it is assumed here that the reference value includes the wafer radius R. Specifically, the processor 230 may, for example, calculate the midpoint between the pixel corresponding to coordinate point M1 and the pixel corresponding to coordinate point M2 in the pixel array of the scan information as a reference point (i.e., Figure 6 The center point O is defined in the image. Coordinate point M1 corresponds to the pixel in the pixel array of the scanned information that corresponds to the wafer (see the gray area of ​​image 601) with the maximum Y-axis coordinate Ymax. Coordinate point M2 corresponds to the pixel in the pixel array of the scanned information that corresponds to the wafer with the minimum Y-axis coordinate Ymin. Then, the processor 230 generates a circular path P1 with radius R, centered at O. It should be noted that this invention does not limit the method of calculating the center point; those skilled in the art can design their own method for calculating the center point based on the above exemplary embodiments. In other embodiments, the processor 230 can also generate multiple circular paths based on different radii. For example, the processor 230 can scale the radius R or the circular path P1 according to a preset scaling ratio (e.g., 2 / 5, 3 / 5, 4 / 5) to generate multiple circular paths.

[0053] Figure 7 This is an example of path information according to an embodiment of the present invention. This embodiment is described using the generation of a through-path as an example. In this embodiment, the reference value includes the wafer slicing angle. First, the processor 230 calculates the facet position of the scan information and the center of the wafer corresponding to the scan information. Next, the processor 230 calculates the midpoint of the facet position as a reference point (also called the first reference point), and the center of the wafer as another reference point (also called the second reference point). Then, the processor 230 determines the reference path based on the first reference point and the second reference point.

[0054] After determining the reference path, processor 230 determines the through-path based on the reference path and the slice angle. For example, processor 230 can calculate the rotation angle based on the slice angle. Then, processor 230 rotates the reference path according to the rotation angle to generate the through-path.

[0055] Please refer to Figure 7 , Figure 7 Image 701 is included, which is a graphical schematic diagram of the scan information corresponding to a wafer. For ease of explanation, it is assumed here that the reference value includes the wafer slicing angle α. Figure 7 The diagram shows a through-path P2 with coordinate points a and b as its two endpoints and passing through the center O of a circle. Please refer to the subsequent explanation for how the through-path is generated.

[0056] Figure 8A This is a schematic diagram illustrating the generation process of the through-path according to an embodiment of the present invention. Figure 8B This is a schematic diagram illustrating the generation process of the through-path according to another embodiment of the present invention. Figure 8A and Figure 8B The dovetail groove 80 shown is only for illustrating the relationship between the position of the dovetail groove 80 used to fix the wafer during wafer slicing and the slicing angle. Please refer to... Figure 8A and Figure 8B With the dovetail groove 80 as the reference, the angle between the vertical line of the wafer face position 71 of wafer 70 and the clockwise direction of the vertical line of the dovetail groove 80 is the slicing angle α. Figure 8A In this embodiment, the processor 230 calculates the facet position 71 of the wafer 70 in the scan information and the center O of the wafer corresponding to the scan information. Next, the processor 230 calculates the midpoint c of the facet position 71 as a first reference point and the center O as a second reference point. Then, the processor 230 determines a reference path R1 based on the midpoint c and the center O. After determining the reference path R1, the processor 230 calculates a rotation angle β based on the slicing angle α. Next, the processor 230 rotates the reference path R1 counterclockwise according to the rotation angle β, generating a through-path P3.

[0057] The calculation method for the rotation angle β differs depending on the slice angle α. Figure 8A For example, if the slicing angle α is greater than 180°, then the rotation angle β is equal to the slicing angle α minus 180°. Furthermore, taking... Figure 8B For example, if the slicing angle α is less than 180°, then the rotation angle β is equal to the slicing angle α plus 180°. Figure 8BIn this embodiment, the processor 230 rotates the reference path R2 counterclockwise according to the rotation angle β, and generates the through-path P4. It should be noted that although the aforementioned embodiment uses the vertical line of the dovetail groove as a reference, the angle between the vertical line of the wafer facet position and the vertical line of the dovetail groove in a clockwise direction is the slicing angle. However, those skilled in the art should understand that the slicing angle can also be taken as a counterclockwise angle, and the rotation direction of the reference path can be designed to generate the through-path based on different angle directions; this invention is not limited in this respect.

[0058] Please refer to again Figure 5 In step S506, the processor 230 obtains multiple first scan parameters corresponding to the path information from the scan parameters to generate a graph. Specifically, after generating the path information, the processor 230 obtains scan parameters (also called first scan parameters) from the pixels corresponding to the path information in the scan information along one direction of the path information. Then, the processor 230 generates a graph according to the first scan parameters and the order in which the first scan parameters were obtained.

[0059] Continued Figure 6 In one embodiment, the processor 230 can start from any point on the circular path P1 (e.g., coordinate point a) and obtain the first scanning parameters from the pixels corresponding to the circular path P1 in the scanning information in a clockwise or counterclockwise direction along the circular path P1. (Continued) Figure 7 In one embodiment, the processor 230 can obtain the first scanning parameters from the pixels corresponding to the through-path P2 in the scanning information along the direction from coordinate point a to coordinate point b or from coordinate point b to coordinate point a. As for obtaining the scanning parameters from the pixels corresponding to the path information in the scanning information based on the path information, this is a well-known technique and will not be described further here.

[0060] Figure 9 This is an example of a graph shown according to an embodiment of the present invention. Figure 9 This indicates the relationship between the first scan parameters and the order in which they are acquired. Graph 901 includes curve W1, where the vertical axis represents the first scan parameters and the horizontal axis represents the order in which they are acquired. Processor 230 can generate curve W1 based on the first scan parameters and the order in which they are acquired. The starting point 91 of curve W1 can correspond to... Figure 6 The coordinates of point a or Figure 7 The coordinates of points a and b. In this embodiment, curve W1 presents a waveform; however, curve W1 may present different shapes depending on the condition of different wafers.

[0061] In step S508, the processor 230 determines whether the wafer has defects based on the curve graph. When the wafer is uneven, the curve graph generated through the aforementioned steps will exhibit specific patterns. Therefore, the processor 230 can analyze the curve graph to determine whether the wafer has defects (unevenness). Furthermore, the processor 230 can further determine the defect type of the wafer based on the curve graph. For example, a curve graph generated based on a circular path can be used to determine patterns such as sunburst and cloud patterns, and a curve graph generated based on a through-path can be used to determine patterns such as zebra stripes and cloud patterns.

[0062] Specifically, the processor 230 can determine whether the wafer corresponding to the curve graph has defects and the type of defect based on conditions such as whether the curve in the graph contains a regular sine wave and / or whether the value contained in the curve exceeds a threshold value. For example, the processor 230 can calculate the distance between each adjacent peak or trough in the curve graph and determine whether the curve contains a regular sine wave based on the difference between each distance. For example, if the difference between the distances between each adjacent peak or trough is less than the threshold value, the processor 230 determines that the curve contains a regular sine wave. If at least one of the differences between the distances between each adjacent peak or trough is not less than the threshold value, the processor 230 determines that the curve does not contain a regular sine wave. It should be noted that the present invention is not limited to the above-described method of determining whether a regular sine wave is present. Those skilled in the art should understand that there are other implementation methods for determining whether a curve graph contains a regular sine wave, which will not be elaborated here.

[0063] In this embodiment, if the curve contains a regular sine wave (e.g., the difference between the distances of adjacent peaks or troughs is less than a threshold value (also called the first threshold value)), and at least one of the first scanning parameters corresponding to the curve is greater than the threshold value (also called the second threshold value), the processor 230 can determine that the wafer corresponding to the curve has a defect. Furthermore, if the curve used to determine the defect is generated based on a circular path, then based on this condition, it can be determined that the wafer has a sunburst pattern, and the processor 230 can instruct a polishing machine to perform fine polishing on the chip. On the other hand, if the curve used to determine the defect is generated based on a through-path pattern, then based on this condition, it can be determined that the wafer has a zebra stripe pattern, and the processor 230 can instruct a polishing machine to perform coarse polishing on the chip.

[0064] Furthermore, if the curve does not contain a regular sine wave (e.g., at least one of the differences between distances is not less than a first threshold value), and at least one of the first scanning parameters is greater than a second threshold value, the processor 230 can also determine that the wafer has a defect. In this embodiment, if the curve used to determine defects is generated based on a circular path or a through-path, then based on this condition, it can be determined that the wafer has a cloud-like pattern, and the processor 230 can instruct the polishing machine to perform fine polishing on the chip. Finally, regardless of whether the curve contains a regular sine wave, if none of the first scanning parameters are greater than the second threshold value, the processor 230 can determine that the wafer has no defects. In this case, the chip can be determined as a qualified chip and does not need to be polished.

[0065] Continued Figure 9 In this embodiment, curve W1 in graph 901 includes peaks 92, 93, and 94, where the difference between peak 92 and peak 93 is distance λ1, and the difference between peak 93 and peak 94 is distance λ2. In this embodiment, the difference between distance λ1 and distance λ2 is less than a first threshold value, and at least the first scan parameters SP1, SP2, and SP3 corresponding to peaks 92, 93, and 94 are greater than a second threshold value TH2. Therefore, processor 230 determines that the wafer corresponding to graph 901 has a defect.

[0066] Table 1 lists the defect types and their judgment conditions in this embodiment. Referring to Table 1, if the curve contains a regular sine wave and at least one of the first scanning parameters is greater than the second threshold value, the processor 230 can determine the defect type as a sunburst or zebra stripe pattern based on the difference between the curve being based on a circular path or a through-path. If the curve does not contain a regular sine wave and at least one of the first scanning parameters is greater than the second threshold value, the processor 230 can determine the defect type as a cloud pattern. If none of the first scanning parameters are greater than the second threshold value, regardless of whether the curve contains a regular sine wave, the processor 230 can determine that the wafer does not have a defect. It should be noted that this invention does not limit the method of defect type judgment. Those skilled in the art can design their own conditions for judging different defect types based on the inspiration from the above exemplary embodiments.

[0067] Table 1

[0068]

[0069] In summary, embodiments of the present invention provide a wafer surface defect detection method and device. These methods can extract parameters from the wafer's scanning information based on path information to analyze whether the wafer has defects, thereby improving the completeness of defect detection. Furthermore, one embodiment of the present invention, when generating path information, also considers the different characteristics of different wafer textures, thus generating path information of different shapes to extract parameters from the scanning information, thereby improving the accuracy of identification. Based on this, embodiments of the present invention can effectively extract parameters from the scanning information used for defect analysis through path analysis, facilitating rapid determination of defect types. Accordingly, a unified defect judgment standard can be established, reducing the probability of false defect judgments.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer surface defect detection method, applicable to an electronic device comprising a processor, the method comprising: receiving scan information of a wafer, wherein the scan information comprises a plurality of scan parameters; deciding at least one reference point of the scan information, and generating path information according to the at least one reference point and a reference value; obtaining a plurality of first scan parameters of the scan parameters corresponding to the path information according to the path information, to generate a graph, comprising obtaining the plurality of first scan parameters from pixels corresponding to the path information in the scan information along a direction of the path information, and generating the graph according to an order of obtaining the plurality of first scan parameters; and judging whether the wafer has a defect and judging a defect type of the defect according to the graph, comprising: calculating distances between each adjacent peak or each adjacent valley in the graph and whether the distances exceed a threshold value; wherein if differences between the distances are all less than a first threshold value, and at least one of the first scan parameters is greater than a second threshold value, judging that the wafer has the defect; if at least one of the differences between the distances is not less than the first threshold value, and at least one of the first scan parameters is greater than the second threshold value, judging that the wafer has the defect; and if the first scan parameters are all not greater than the second threshold value, judging that the wafer does not have the defect.

2. The wafer surface defect detection method of claim 1, wherein the reference value comprises at least one radius, and the step of deciding the at least one reference point of the scan information, and generating the path information according to the at least one reference point and the reference value comprises: calculating a center of the wafer corresponding to the scan information as the at least one reference point; and deciding at least one circular path according to the at least one radius based on the at least one reference point.

3. The wafer surface defect detection method of claim 2, wherein the step of obtaining the scan parameters of the scan information according to the path information to generate the graph comprises: obtaining the first scan parameters from pixels corresponding to the at least one circular path in the scan information along a direction of the at least one circular path; and generating the graph according to the first scan parameters and an order of obtaining the first scan parameters.

4. The wafer surface defect detection method of claim 1, wherein the reference value comprises a slice angle, and the step of deciding the at least one reference point of the scan information, and generating the path information according to the at least one reference point and the reference value comprises: calculating a flat position of the scan information and a center of the wafer corresponding to the scan information; calculating a midpoint of the flat position as a first reference point, and the center as a second reference point; deciding a reference path according to the first reference point and the second reference point; and deciding a through path according to the reference path and the slice angle.

5. The wafer surface defect detection method of claim 4, wherein the step of deciding the through path according to the reference path and the slice angle comprises: ​ ​ ​ calculating a rotation angle according to the slice angle; and rotating the reference path according to the rotation angle to generate the through-path.

6. The wafer surface defect detection method of claim 4, wherein the step of obtaining the first scan parameters corresponding to the path information from the scan parameters according to the path information to generate the graph comprises: obtaining the first scan parameters from the scan information corresponding to the pixels of the through-path along the direction of the through-path; and and generating the graph according to the first scan parameters and the order of obtaining the first scan parameters.

7. The wafer surface defect detection method of claim 1, wherein the defect type includes at least one of striae, zebra, and clouding.

8. The wafer surface defect detection method of claim 1, wherein the scan parameters are generated by a scanning device scanning the wafer, and the scan parameters include at least one of haze value, surface roughness value, and image parameter.

9. The wafer surface defect detection method of claim 8, wherein the image parameter includes at least one of gray scale value, brightness value, contrast value, RGB hue value, saturation value, color temperature value, and Gamma value.

10. A wafer surface defect detection device, comprising: a connecting device configured to connect a scanning device to receive scan information generated by the scanning device scanning a wafer; a storage device storing one or more instructions; and a processor coupled to the connecting device and the storage device and configured to execute the instructions to: receive the scan information, wherein the scan information includes a plurality of scan parameters; determine at least one reference point of the scan information and generate path information according to the at least one reference point and a reference value; obtain a plurality of first scan parameters corresponding to the path information from the scan parameters according to the path information to generate a graph, including obtaining the plurality of first scan parameters from the scan information corresponding to the pixels of the path information along the direction of the path information, and generating the graph according to the order of obtaining the plurality of first scan parameters; and determine whether the wafer has a defect and determine a defect type of the defect according to the graph, including: calculating distances between each adjacent peak or each adjacent trough in the graph and whether the distances exceed a threshold value; wherein if the differences between each of the distances are less than a first threshold value and at least one of the first scan parameters is greater than a second threshold value, determining that the wafer has the defect; if at least one of the differences between each of the distances is not less than the first threshold value and at least one of the first scan parameters is greater than the second threshold value, determining that the wafer has the defect; and if none of the first scan parameters is greater than the second threshold value, determining that the wafer does not have the defect.

11. The wafer surface defect detection device of claim 10, wherein the reference value includes at least one radius, and the operation of determining the at least one reference point of the scan information and generating the path information according to the at least one reference point and the reference value comprises: calculating a center of the wafer corresponding to the scan information as the at least one reference point; and determining at least one circular path according to the at least one radius based on the at least one reference point.

12. The wafer surface defect inspection device of claim 11, wherein the operation of obtaining the scan parameters of the scan information according to the path information to generate the graph comprises: obtaining the first scan parameters from the pixels corresponding to the at least one circular path in the scan information along the direction of the at least one circular path; and generating the graph according to the first scan parameters and the order of obtaining the first scan parameters.

13. The wafer surface defect inspection device of claim 10, wherein the reference value comprises a slice angle, and the operation of determining the at least one reference point of the scan information and generating the path information according to the at least one reference point and the reference value comprises: calculating a flat position of the scan information and a center of the wafer corresponding to the scan information; calculating a midpoint of the flat position as a first reference point and the center as a second reference point; determining a reference path according to the first reference point and the second reference point; and determining a through path according to the reference path and the slice angle.

14. The wafer surface defect inspection device of claim 13, wherein the operation of determining the through path according to the reference path and the slice angle comprises: calculating a rotation angle according to the slice angle; and rotating the reference path according to the rotation angle to generate the through path.

15. The wafer surface defect inspection device of claim 13, wherein the operation of obtaining the first scan parameters of the scan parameters corresponding to the path information according to the path information to generate the graph comprises: obtaining the first scan parameters from the pixels corresponding to the through path in the scan information along the direction of the through path; and generating the graph according to the first scan parameters and the order of obtaining the first scan parameters.

16. The wafer surface defect inspection device of claim 10, wherein the defect type comprises at least one of a sunburst, a zebra, and a cloud.

17. The wafer surface defect inspection device of claim 10, wherein the scan parameters are generated by the scanning device scanning the wafer, and the scan parameters comprise at least one of a haze value, a surface roughness value, and an image parameter.

18. The wafer surface defect inspection device of claim 17, wherein the image parameter comprises at least one of a gray scale value, a brightness value, a contrast value, an RGB hue value, a saturation value, a color temperature value, and a Gamma value. ​ ​ ​

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