Transmission circuit, method, storage device, and storage medium

Abstract

The application relates to a transmission circuit, a method, a storage device and a storage medium. The transmission circuit comprises a comparison module and a data conversion module. The comparison module is used for receiving first data on a first data line and second data on a second data line, and comparing the first data and the second data to output a comparison result of whether the number of bits of the first data and the second data that are different exceeds a preset threshold value. The first data and the second data have the same preset bit width. The data conversion module is electrically connected with the first data line, the comparison module and the second data line. In the case that the comparison result exceeds the preset threshold value, the data conversion module is used for transmitting the first data to the second data line after the first data is inverted. In the case that the comparison result does not exceed the preset threshold value, the data conversion module is used for transmitting the first data to the second data line. The application reduces the number of data inversion and the power consumption in the data transmission process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor storage, in particular to a transmission circuit, a method, a storage device and a storage medium. BACKGROUND

[0002] The semiconductor storage device usually comprises a storage array area and a peripheral circuit area, wherein the storage array area is provided with a storage unit array composed of a plurality of storage units. The peripheral circuit area is provided with a control circuit for controlling reading and writing.

[0003] With the rapid development of semiconductor technology, the market has higher and higher requirements for the storage capacity and power saving performance of the semiconductor storage device, which puts forward higher requirements for the power saving performance of the peripheral circuit area and the storage array area in the semiconductor storage device.

[0004] However, the increase in the density and number of storage units in the storage unit array leads to an increase in the length of the data transmission path in the storage array area, resulting in a larger proportion of the power consumption of the data transmission path in the power consumption of the semiconductor storage device. How to effectively reduce the power consumption of the data transmission path in the storage array area has become one of the technical problems to be solved in the process of further improving the storage capacity and power saving performance of the semiconductor storage device. SUMMARY

[0005] Therefore, a transmission circuit, a method, a storage device and a storage medium are provided to effectively reduce the power consumption of the data transmission path in the storage array area.

[0006] To achieve the above-mentioned and other purposes, the first aspect of the present application provides a transmission circuit, comprising a comparison module and a data conversion module, the comparison module is used for receiving first data on a first data line and second data on a second data line, and comparing the first data and the second data to output a comparison result of whether the number of bits different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; the data conversion module is electrically connected with the first data line, the comparison module and the second data line, and is used for transmitting the first data to the second data line after inverting the first data when the comparison result exceeds the preset threshold; and is also used for transmitting the first data to the second data line when the comparison result does not exceed the preset threshold.

[0007] In the transmission circuit in the above embodiment, the comparison module receives first data on the first data line and second data on the second data line, and compares the first data and the second data to output a comparison result of whether the number of bits different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width, so that the data conversion module transmits the first data to the second data line after inverting the first data in the case that the comparison result exceeds the preset threshold, and transmits the first data to the second data line in the case that the comparison result does not exceed the preset threshold, thereby reducing the number of data inversion under the premise of ensuring data transmission accuracy, and effectively reducing the power consumption in the data transmission process. Thus, the power consumption of the data transmission path in the storage array area can be effectively reduced under the premise of ensuring the density and quantity of the storage cells in the storage cell array.

[0008] In one of the embodiments, the comparison module comprises:

[0009] The comparison unit is configured to compare the first data and the second data bit by bit, and output comparison state data of each bit.

[0010] The state recognition unit is electrically connected to the comparison unit, configured to count the comparison state data of each bit, and output the comparison result according to the counting result.

[0011] In one of the embodiments, the data conversion module comprises:

[0012] The first transmission unit is electrically connected to the first data line, the second data line, and the output end of the state recognition unit through the first inverting unit, configured to transmit the first data to the second data line in the case that the comparison result does not exceed the preset threshold, wherein the preset threshold is half of the preset bit width.

[0013] The second transmission unit is electrically connected to the second data line, the output end of the state recognition unit, and the first data line through the second inverting unit, configured to transmit the first data to the second data line after inverting the first data in the case that the comparison result exceeds the preset threshold.

[0014] In one of the embodiments, the data conversion module is electrically connected to the second data line through a data bus buffer module; the data bus buffer module comprises a write unit configured to transmit the first data or the first data after inversion to the second data line.

[0015] In one of the embodiments, the data bus buffer module is further electrically connected to the state identification unit, for generating a data polarity identification signal according to the comparison result.

[0016] In one of the embodiments, the transmission circuit further comprises a read-write conversion circuit, which generates third data according to the data polarity identification signal and the data on the second data line, and transmits the third data to the third data line.

[0017] In one of the embodiments, the second data line comprises a global data line and a complementary global data line, and the global data line and the complementary global data line transmit signals that are opposite to each other; and the transmitting the inverted first data to the second data line comprises:

[0018] transmitting the inverted first data to the global data line;

[0019] The transmitting the first data to the second data line comprises:

[0020] transmitting the first data to the global data line.

[0021] In one of the embodiments, the read-write conversion circuit comprises:

[0022] a write enable module, which generates a write enable signal and a write enable inverse signal according to the data polarity identification signal and an initial write enable signal;

[0023] a write drive circuit, which generates the third data according to the write enable signal, the write enable inverse signal and the data on the second data line.

[0024] In one of the embodiments, the write enable module comprises:

[0025] a first inverter, which is configured to have an input end electrically connected to an initial write enable signal and an output end outputting a first write enable inverse signal;

[0026] a first NOR gate, which is configured to have an input end electrically connected to the data polarity identification signal and the output end of the first inverter, and an output end outputting a write enable signal;

[0027] a second inverter, which is configured to have an input end electrically connected to the data polarity identification signal and an output end outputting a data polarity identification inverse signal;

[0028] a second NOR gate, which is configured to have an input end electrically connected to the output end of the second inverter and the output end of the first inverter, and an output end outputting a write enable inverse signal.

[0029] In one of the embodiments, the third data line comprises a local data line and a complementary local data line.

[0030] In one of the embodiments, the write driving circuit comprises:

[0031] a first switch unit, electrically connecting the local data line and the global data line according to the write enable signal;

[0032] a second switch unit, electrically connecting the local data line and the complementary global data line according to the write enable inverse signal;

[0033] a third switch unit, electrically connecting the complementary local data line and the global data line according to the write enable inverse signal;

[0034] a fourth switch unit, electrically connecting the complementary local data line and the complementary global data line according to the write enable signal.

[0035] In one of the embodiments, the read-write conversion circuit further comprises a read driving circuit, and the read driving circuit comprises:

[0036] a fifth switch unit, having a control terminal electrically connected to the local data line, and electrically connecting the complementary global data line and a first node according to a control terminal signal;

[0037] a sixth switch unit, electrically connecting the first node and a ground terminal according to a read enable signal;

[0038] a seventh switch unit, having a control terminal electrically connected to the complementary local data line, and electrically connecting the global data line and a second node according to a control terminal signal;

[0039] an eighth switch unit, electrically connecting the second node and the ground terminal according to the read enable signal.

[0040] In one of the embodiments, the data conversion module is further configured to transmit the second data to the first data line after taking inversion of the second data when the comparison result exceeds the preset threshold, and is further configured to transmit the second data to the first data line when the comparison result does not exceed the preset threshold.

[0041] In one of the embodiments, the data conversion module further comprises:

[0042] a third transmission unit, electrically connected to the first data line, the second data line, and an output terminal of the state identification unit through a third inverting unit, and configured to transmit the second data to the first data line when the comparison result does not exceed the preset threshold;

[0043] a fourth transmission unit electrically connected with the first data line, the output end of the state identification unit, and the second data line through a fourth inverting unit, configured to transmit the second data to the first data line after inverting the second data in a case that the comparison result exceeds the preset threshold.

[0044] In one of the embodiments, the data bus buffer module further comprises a reading unit configured to transmit the second data to a third transmission unit or transmit the second data to a fourth transmission unit after inverting the second data through a fourth inverting unit.

[0045] The second aspect of the present application provides a storage device comprising the transmission circuit described in any of the embodiments of the present application, configured to store and transmit data of a read operation or a write operation.

[0046] The third aspect of the present application provides a transmission method, comprising:

[0047] receiving first data on a first data line and second data on a second data line;

[0048] comparing the first data and the second data, and outputting a comparison result of whether a number of bits different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width;

[0049] if the comparison result exceeds the preset threshold, transmitting the first data to the second data line after inverting the first data; otherwise, transmitting the first data to the second data line.

[0050] In one of the embodiments, the second data line comprises a global data line and a complementary global data line, wherein the global data line and the complementary global data line transmit signals that are inverses of each other;

[0051] the transmitting the first data to the second data line after inverting the first data comprises:

[0052] transmitting the first data to the global data line after inverting the first data;

[0053] the transmitting the first data to the second data line comprises:

[0054] transmitting the first data to the global data line.

[0055] In one of the embodiments, the preset threshold is half of the preset bit width, and the method further comprises:

[0056] If the comparison result is that the preset threshold is exceeded, the second data is transmitted to the first data line after being inverted; otherwise, the second data is transmitted to the first data line.

[0057] A fourth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the transmission method in any embodiment of the present application.

[0058] In the storage device and the computer readable storage medium in the above embodiments, the received first data on the first data line and the second data on the second data line are compared, and a comparison result of whether the number of bits in which the first data and the second data are different exceeds a preset threshold is output, wherein the first data and the second data have the same preset bit width; in the case that the comparison result is that the preset threshold is exceeded, the first data is inverted and then transmitted to the second data line; otherwise, the first data is transmitted to the second data line. Since the transmitted data generally includes a data string composed of 0 and 1, by applying the power saving algorithm in the data transmission process, the number of data flips is reduced under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption in the data transmission process. Thus, the power consumption of the data transmission path in the storage array area is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0060] Figure 1 A circuit principle schematic diagram of a transmission circuit provided in the first embodiment of the present application;

[0061] Figure 2 A circuit principle schematic diagram of a transmission circuit provided in the second embodiment of the present application;

[0062] Figure 3a A circuit principle schematic diagram of a transmission circuit provided in the third embodiment of the present application;

[0063] Figure 3b An embodiment schematic diagram of Figure 3a ;

[0064] Figure 4 A circuit principle schematic diagram of a transmission circuit provided in the fourth embodiment of the present application;

[0065] Figure 5 This is a schematic diagram of the circuit principle of a transmission circuit provided in the fifth embodiment of this application;

[0066] Figure 6 This is a schematic diagram of the circuit principle of a transmission circuit provided in the sixth embodiment of this application;

[0067] Figure 7 This is a schematic diagram of the circuit principle of a transmission circuit provided in the seventh embodiment of this application;

[0068] Figure 8 This is a circuit diagram of a write enable module in a transmission circuit provided in one embodiment of this application;

[0069] Figure 9 This is a circuit diagram of a write drive circuit in a transmission circuit provided in one embodiment of this application;

[0070] Figure 10a This is a schematic diagram of the circuit principle of a transmission circuit provided in the eighth embodiment of this application;

[0071] Figure 10b for Figure 10a A schematic diagram of one implementation method;

[0072] Figure 11 This is a schematic diagram of the circuit principle of a transmission circuit provided in the ninth embodiment of this application;

[0073] Figure 12 This is a structural block diagram of a storage device provided in one embodiment of this application;

[0074] Figure 13 This is a flowchart illustrating a transmission method provided in one embodiment of this application;

[0075] Figure 14 This is a flowchart illustrating a transmission method provided in another embodiment of this application.

[0076] Explanation of reference numerals in the attached figures:

[0077] 100, transmission circuit; 10, comparison module; 20, data conversion module; 30, first data line; 40, second data line; 11, comparison unit; 12, state recognition unit; 21, first transmission unit; 22, first inversion unit; 23, second transmission unit; 24, second inversion unit; 25, third transmission unit; 26, third inversion unit; 27, fourth transmission unit; 28, fourth inversion unit; 50, data bus buffer module; 51, write unit; 52, read unit; 70, read-write conversion circuit; 71, write enable module; 72, write drive circuit; 73, read drive circuit; 721, first switch unit; 722, second switch unit; 723, third switch unit; 724, fourth switch unit; 731, fifth switch unit; 732, sixth switch unit; 733, seventh switch unit; 734, eighth switch unit; 80, third data line; 200, storage device. DETAILED DESCRIPTION

[0078] For the purposes of this application, a more complete understanding of the application can be obtained by reference to the following description and the associated drawings. The application is illustrated by and described with reference to preferred embodiments. However, it is to be understood that the application can be carried out in many different constructions and that the application is not limited to the specific embodiments described. Rather, the specific embodiments are provided as exemplary of the application so as to enable anyone skilled in the art, having the benefit of the true disclosure herein, to make and use the application.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Additionally, some terms are used throughout the description and the claims that follow are intended to refer to particular embodiments of the present application. Those skilled in the art will recognize that manufacturers can use different names to refer to the same element. The present document does not intend to distinguish between names as long as the function of the element remains the same. In the following description and examples, the terms "comprising" and "including" are open-ended terms that are intended to refer to the inclusion of elements that are not necessarily limited to a specific number of elements. Also, the term "connected" is intended to mean either an indirect or direct electrical connection.

[0080] It should be understood that although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present application.

[0081] Reference is made to Figure 1In one embodiment of the present application, a transmission circuit 100 is provided, comprising a comparison module 10 and a data conversion module 20. The comparison module 10 is configured to receive first data on a first data line 30 and second data on a second data line 40, and compare the first data and the second data to output a comparison result indicating whether the number of bits in which the first data and the second data are different exceeds a preset threshold, wherein the first data and the second data have the same preset bit width. The data conversion module 20 is electrically connected to the first data line 30, the comparison module 10, and the second data line 40, and is configured to transmit the first data to the second data line 40 after inverting the first data when the comparison result indicates that the preset threshold is exceeded, and transmit the first data to the second data line 40 when the comparison result indicates that the preset threshold is not exceeded. For example, the preset threshold can be set as half of the preset bit width. The data conversion module 20 is configured to transmit the first data to the second data line 40 after inverting the first data when the comparison result indicates that the preset threshold is exceeded, and transmit the first data to the second data line 40 when the comparison result indicates that the preset threshold is not exceeded, thereby reducing the number of data flips while ensuring data transmission accuracy, and effectively reducing power consumption during data transmission. Thus, the power consumption of the data transmission path in the storage array region can be effectively reduced while ensuring the density and number of storage units in the storage unit array.

[0082] Further, refer to Figure 2 In one embodiment of the present application, the comparison module 10 comprises a comparison unit 11 and a state recognition unit 12. The comparison unit 11 is configured to compare the first data and the second data bit by bit, and output comparison state data of each bit. The state recognition unit 12 is electrically connected to the comparison unit 11, and is configured to count the comparison state data of each bit, and output a comparison result according to the counting result. The data conversion module 20 is configured to transmit the first data to the second data line 40 after inverting the first data when the comparison result indicates that the preset threshold is exceeded, and transmit the first data to the second data line 40 when the comparison result indicates that the preset threshold is not exceeded, thereby reducing the number of data flips while ensuring data transmission accuracy, and effectively reducing power consumption during data transmission.

[0083] Further, refer to Figure 3a and Figure 3bIn an embodiment of the present application, the data conversion module 20 comprises a first transmission unit 21, a first inversion unit 22, a second transmission unit 23 and a second inversion unit 24. The first transmission unit 21 is electrically connected to the first data line 30, the second data line 40, and the output terminal of the state identification unit 12 through the first inversion unit 22. When the comparison result output by the comparison unit 11 does not exceed the preset threshold, the first transmission unit 21 transmits the first data to the second data line 40. The preset threshold can be set as half of the preset bit width. The second transmission unit 23 is electrically connected to the second data line 40, the output terminal of the state identification unit 12, and the first data line 30 through the second inversion unit 24. When the comparison result output by the comparison unit 11 exceeds the preset threshold, the second transmission unit 23 transmits the first data after inversion to the second data line 40. The embodiment reduces the number of data inversions under the premise of ensuring the accuracy of data transmission, thereby effectively reducing the power consumption in the data transmission process.

[0084] Further, referring to Figure 4 In an embodiment of the present application, the data conversion module 20 is electrically connected to the second data line 40 through the data bus buffer module 50. The data bus buffer module 50 comprises a write unit 51 for transmitting the first data or the first data after inversion to the second data line 40.

[0085] By way of example, continuing to refer to Figure 4 The first data line 30 can be set as a data bus, the second data line 40 can be set as a global data line YIO, and the write unit 51 can be set in the data bus buffer module 50. The write unit 51 transmits the first data or the first data after inversion on the data bus to the global data line YIO, thereby reducing the number of data inversions under the premise of ensuring the accuracy of data transmission, and effectively reducing the power consumption in the process of writing data from the data bus to the global data line YIO.

[0086] Further, referring to Figure 5 In an embodiment of the present application, the data bus buffer module 50 is further electrically connected to the state identification unit 12, and is used to generate a data polarity identification signal pl according to the output signal of the state identification unit 12, so as to restore the inverted data according to the data polarity identification signal pl in the subsequent process, thereby ensuring the accuracy of data transmission.

[0087] Further, referring to Figure 6In an embodiment of the present application, the transmission circuit 100 further comprises a read-write conversion circuit 70, and the second data line 40 transmits data with the third data line 80 through the read-write conversion circuit 70, so as to realize transmission of read data or transmission of write data through the read-write conversion circuit 70.

[0088] As an example, please refer to Figure 7 In an embodiment of the present application, the second data line 40 comprises a global data line YIO and a complementary global data line YIO_, and the global data line YIO and the complementary global data line YIO_ transmit signals that are mutually inverted; the third data line 80 can be set to comprise a local data line LIO and a complementary local data line LIO_, and the local data line LIO and the complementary local data line LIO_ transmit signals that are mutually inverted, and the transmission of the first data to the second data line 40 after being inverted comprises:

[0089] transmitting the first data to the global data line YIO after being inverted;

[0090] transmitting the first data to the second data line 40 comprises:

[0091] transmitting the first data to the global data line YIO.

[0092] As an example, please refer to Figure 7 By setting the second data line 40 to comprise a global data line YIO and a complementary global data line YIO_, and the global data line YIO and the complementary global data line YIO_ transmit signals that are mutually inverted, in the case that the comparison result output by the comparison module 10 exceeds a preset threshold, the second transmission unit 23 transmits the first data to the global data line YIO after being inverted; and in the case that the comparison result output by the comparison module 10 does not exceed the preset threshold, the first transmission unit 21 transmits the first data to the global data line YIO. The embodiment reduces the number of data flips under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption of data in the process of being transmitted through the data bus, the global data line YIO or the complementary global data line YIO_, and being written into the local data line LIO or the complementary local data line LIO_.

[0093] Further, please refer to Figure 7 In an embodiment of the present application, the read-write conversion circuit 70 comprises a write enable module 71 and a write driving circuit 72, the write enable module 71 is used for generating a write enable signal WrEn and a write enable inverse signal WrEn_ according to a data polarity identification signal pl and an initial write enable signal we; the write driving circuit 72 is used for generating a third data according to the write enable signal WrEn, the write enable inverse signal WrEn_ and the data on the second data line, and transmitting the third data to the third data line 80, so as to ensure the accuracy of data transmission.

[0094] As an example, refer to Figure 8 In an embodiment of the present application, the write enable module 71 includes a first inverter Inv1, a first NOR gate Nor1, a second inverter Inv2, and a second NOR gate Nor2, an input terminal of the first inverter Inv1 is electrically connected to an initial write enable signal we, an output terminal of the first inverter Inv1 outputs a first write enable inverse signal We1_, an input terminal of the first NOR gate Nor1 is electrically connected to a data polarity identification signal pl and an output terminal of the first inverter Inv1, an output terminal of the first NOR gate Nor1 outputs a write enable signal WrEn, an input terminal of the second inverter Inv2 is electrically connected to the data polarity identification signal pl, an output terminal of the second inverter Inv2 outputs a data polarity identification inverse signal Pl_, an input terminal of the second NOR gate Nor2 is electrically connected to an output terminal of the second inverter Inv2 and an output terminal of the first inverter Inv1, and an output terminal of the second NOR gate Nor2 outputs a write enable inverse signal WrEn_. In this way, the write drive circuit 72 generates third data according to data on the second data line 40 according to the write enable signal WrEn and the write enable inverse signal WrEn_, and transmits the third data to the third data line 80, for example, a local data line LIO or a complementary local data line LIO_, to ensure the accuracy of data transmission.

[0095] As an example, refer to Figure 9 In an embodiment of the present application, the write drive circuit 72 includes a first switch unit 721, a second switch unit 722, a third switch unit 723, and a fourth switch unit 724, the first switch unit 721 is used to electrically connect the local data line LIO and the global data line YIO according to the write enable signal WrEn, the second switch unit 722 is used to electrically connect the local data line LIO and the complementary global data line YIO_ according to the write enable inverse signal WrEn_, the third switch unit 723 is used to electrically connect the complementary local data line LIO_ and the global data line YIO according to the write enable inverse signal WrEn_, and the fourth switch unit 724 is used to electrically connect the complementary local data line LIO_ and the complementary global data line YIO_ according to the write enable signal WrEn. In this way, the recovery of transmitted data is realized, and the accuracy of data transmission is ensured.

[0096] As an example, refer to Figure 9In one embodiment of the present application, the read-write conversion circuit 70 further comprises a read driving circuit 73, which includes a fifth switch unit 731, a sixth switch unit 732, a seventh switch unit 733 and an eighth switch unit 734. The control terminal of the fifth switch unit 731 is electrically connected to the local data line LIO, for electrically connecting the complementary global data line YIO_ and the first node a according to the control terminal signal; the sixth switch unit 732 is for electrically connecting the first node a and the ground terminal according to the read enable signal; the control terminal of the seventh switch unit 733 is electrically connected to the complementary local data line LIO_, for electrically connecting the global data line YIO and the second node b according to the control terminal signal; the eighth switch unit 734 is for electrically connecting the second node b and the ground terminal according to the read enable signal. This embodiment effectively reduces the power consumption of data in the process of being transmitted via the data bus Data bus, the global data line YIO or the complementary global data line YIO_, and being written into the local data line LIO or the complementary local data line LIO_ by reducing the number of times of flipping in the process of transmitting the write data.

[0097] Further, please refer to Figure 10a and 10b In one embodiment of the present application, the data conversion module 20 is further configured to transmit the second data to the first data line 30 after inverting the second data when the comparison result output by the comparison unit 11 exceeds a preset threshold, for example, half of the preset bit width, and is further configured to transmit the second data to the first data line 30 when the comparison result does not exceed the preset threshold. For example, the first data line 30 can be set as the data bus Data bus, and the second data line 40 can be set as the global data line YIO or the complementary global data line YIO_. In the process of reading data, when the comparison result output by the comparison unit 11 exceeds a preset threshold, for example, half of the preset bit width, the data conversion module 20 inverts the second data provided by the global data line YIO or the complementary global data line YIO_ and then transmits the inverted second data to the data bus Data bus, and when the comparison result output by the comparison unit 11 does not exceed the preset threshold, the data conversion module 20 transmits the second data provided by the global data line YIO or the complementary global data line YIO_ to the data bus Data bus. This effectively reduces the power consumption of the read data in the process of being transmitted via the global data line YIO or the complementary global data line YIO_ to the data bus Data bus.

[0098] As an example, please continue to refer to FIG. 10, in one embodiment of the present application, the data conversion module 20 further comprises a third transmission unit 25, a third inverting unit 26, a fourth transmission unit 27 and a fourth inverting unit 28, the third transmission unit 25 is electrically connected with the first data line 30, the second data line 40, and is electrically connected with the output terminal of the state recognition unit 12 through the third inverting unit 26. In the case that the comparison result outputted by the comparison module 10 does not exceed the preset threshold value, the third transmission unit 25 transmits the second data to the first data line 30. The fourth transmission unit 27 is electrically connected with the first data line 30, the output terminal of the state recognition unit 12, and is electrically connected with the second data line 40 through the fourth inverting unit 28. In the case that the comparison result exceeds the preset threshold value, the fourth transmission unit 27 transmits the second data after being inverted to the first data line 30.

[0099] Further, please refer to Figure 11 In one embodiment of the present application, the data bus buffer module 50 further comprises a reading unit 52, which is used to transmit the second data to the third transmission unit 25, or transmit the second data after being inverted to the fourth transmission unit 27 through the fourth inverting unit 28. For example, the first data line 30 can be set as a data bus Data bus, and the second data line 40 can be set as a global data line YIO or a complementary global data line YIO_. In the process of reading data, in the case that the comparison result outputted by the comparison unit 11 exceeds the preset threshold value, for example, half of the preset bit width, the fourth transmission unit 27 transmits the second data provided by the global data line YIO or the complementary global data line YIO_ after being inverted to the data bus Data bus, and in the case that the comparison result outputted by the comparison unit 11 does not exceed the preset threshold value, the third transmission unit 25 transmits the second data provided by the global data line YIO or the complementary global data line YIO_ to the data bus Data bus. Thus, the power consumption of the reading data in the process of being transmitted from the global data line YIO or the complementary global data line YIO_ to the data bus Data bus can be effectively reduced.

[0100] Further, please refer to Figure 12 In one embodiment of the present application, a storage device 200 is provided, which comprises the transmission circuit 100 described in any embodiment of the present application, and is used to store and transmit data of reading operation or writing operation.

[0101] The specific limitation of the storage device 200 in the above-mentioned embodiments can refer to the specific limitation of the transmission circuit 100 described above, which will not be described here again.

[0102] Further, please refer to Figure 13 In one embodiment of the present application, a transmission method is provided, which comprises:

[0103] Step 102, receiving first data on a first data line and second data on a second data line;

[0104] Step 104, comparing the first data and the second data, and outputting a comparison result of whether a number of bits different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width;

[0105] Step 106, if the comparison result exceeds the preset threshold, transmitting the first data after being inverted to the second data line; otherwise, transmitting the first data to the second data line.

[0106] Specifically, please continue to refer to Figure 13 , by comparing the first data on a first data line and the second data on a second data line, and outputting a comparison result of whether a number of bits different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width; in the case that the comparison result exceeds the preset threshold, transmitting the first data after being inverted to the second data line; otherwise, transmitting the first data to the second data line. Since the transmitted data generally includes a data string composed of 0 and 1, by applying the power saving algorithm in the data transmission process, the number of data flips is reduced under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption in the data transmission process. Thus, the power consumption of the data transmission path in the storage array area can be effectively reduced under the premise of ensuring the density and quantity of the storage cells in the storage cell array.

[0107] As an example, in an embodiment of the present application, the second data line includes a global data line and a complementary global data line, wherein the global data line and the complementary global data line transmit signals that are inversely related to each other;

[0108] The transmitting the first data after being inverted to the second data line includes:

[0109] Transmitting the first data after being inverted to the global data line YIO;

[0110] The transmitting the first data to the second data line includes:

[0111] Transmitting the first data to the global data line YIO.

[0112] Further, please refer to Figure 14 , in an embodiment of the present application, the method includes:

[0113] Step 102, receiving first data on a first data line and second data on a second data line;

[0114] Step 104, comparing the first data and the second data, and outputting a comparison result of whether the number of bits that are not the same between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width;

[0115] Step 1061, if the comparison result exceeds the preset threshold, transmitting the first data after being inverted to the second data line; otherwise, transmitting the first data to the second data line, and the preset threshold is half of the preset bit width;

[0116] Step 108, if the comparison result exceeds the preset threshold, transmitting the second data after being inverted to the first data line; otherwise, transmitting the second data to the first data line, and the preset threshold is half of the preset bit width.

[0117] As an example, please continue to refer to Figure 11 and Figure 14 The first data line 30 can be set as a data bus Data bus, and the second data line 40 includes a global data line YIO and a complementary global data line YIO_. In the process of writing data, the second transmission unit 23 transmits the first data after being inverted to the global data line YIO when the comparison result output by the comparison module 10 exceeds a preset threshold, for example, half of the preset bit width; and the first transmission unit 21 transmits the first data to the global data line YIO when the comparison result output by the comparison module 10 does not exceed the preset threshold. In this way, the power consumption of the writing data in the process of being transmitted from the data bus Data bus to the global data line YIO can be effectively reduced. In the process of reading data, the fourth transmission unit 27 transmits the second data provided by the complementary global data line YIO_ after being inverted to the data bus Data bus when the comparison result output by the comparison unit 11 exceeds the preset threshold, and the third transmission unit 25 transmits the second data provided by the complementary global data line YIO_ to the data bus Data bus when the comparison result output by the comparison unit 11 does not exceed the preset threshold. In this way, the power consumption of the reading data in the process of being transmitted from the complementary global data line YIO_ to the data bus Data bus can be effectively reduced.

[0118] In an embodiment of the present application, a computer readable storage medium is provided, and a computer program is stored on the computer readable storage medium. The computer program is executed by a processor to implement the transmission method described in any embodiment of the present application.

[0119] In the computer readable storage medium in the above embodiment, the received first data on the first data line and the second data on the second data line are compared, and a comparison result of whether the number of bits in which the first data is different from the second data exceeds a preset threshold is output, wherein the first data and the second data have the same preset bit width; in the case that the comparison result exceeds the preset threshold, the first data is inverted and then transmitted to the second data line; otherwise, the first data is transmitted to the second data line. Since the transmitted data generally includes a data string composed of 0 and 1, by applying the power saving algorithm in the data transmission process, the number of data flips is reduced under the premise of ensuring the accuracy of data transmission, so as to effectively reduce the power consumption in the data transmission process. Thus, the power consumption of the data transmission path in the storage array area can be effectively reduced under the premise of ensuring the density and quantity of the storage units in the storage unit array.

[0120] It should be understood that, although Figure 13 , Each step in the flowchart of Figure 14 is shown in sequence according to the arrow, but these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 13 , At least part of the steps in Figure 14 may include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0121] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0122] Please note that the above embodiments are only for illustrative purposes and do not mean to limit the present application.

[0123] The technical features of the above-mentioned embodiments can be combined in any way. In order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0124] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A transmission circuit, characterized by, include: The comparison module is used to receive first data on a first data line and second data on a second data line, and compare the first data and the second data to output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; The data conversion module is electrically connected to the first data line, the comparison module, and the second data line. It is used to invert the first data and transmit it to the second data line when the comparison result exceeds a preset threshold; and it is also used to transmit the first data to the second data line when the comparison result does not exceed the preset threshold. The comparison module includes: The comparison unit is used to compare the first data and the second data bit by bit and output the comparison status data of each bit. A status recognition unit, electrically connected to the comparison unit, is used to statistically analyze the comparison status data of each bit and output the comparison result based on the statistical results. The data conversion module is electrically connected to the second data line through the data bus buffer module; The data bus buffer module includes a write unit, which is used to transmit the first data or the inverted first data to the second data line. The data bus buffer module is also electrically connected to the status identification unit, and is used to generate a data polarity identification signal based on the comparison result. It also includes a read-write conversion circuit, which generates third data based on the data polarity identification signal and the data on the second data line, and transmits the third data to the third data line; The second data line includes a global data line and a complementary global data line, wherein the global data line and the complementary global data line transmit signals that are in opposite phases. The step of inverting the first data and transmitting it to the second data line includes: The first data is inverted and then transmitted to the global data line; The step of transmitting the first data to the second data line includes: The first data is transmitted to the global data line; The read / write conversion circuit includes: A write enable module generates a write enable signal and a write enable inverse signal based on the data polarity identifier signal and the initial write enable signal; A write driver circuit is used to generate the third data based on the write enable signal, the write enable inverse signal, and the data on the second data line.

2. The transmission circuit according to claim 1, characterized in that, The data conversion module includes: The first transmission unit is electrically connected to the first data line, the second data line, and electrically connected to the output terminal of the state recognition unit through the first inverting unit. It is used to transmit the first data to the second data line when the comparison result is not exceeded by the preset threshold, wherein the preset threshold is half of the preset bit width. The second transmission unit is electrically connected to the second data line, the output terminal of the state recognition unit, and electrically connected to the first data line through the second inverting unit. It is used to invert the first data and transmit it to the second data line when the comparison result exceeds the preset threshold.

3. The transmission circuit of claim 1, wherein The write enable module comprises: a first inverter configured to have an input end electrically connected to an initial write enable signal and an output end outputting a first write enable inverse signal; a first NOR gate configured to have an input end electrically connected to the data polarity identification signal and the output end of the first inverter and an output end outputting a write enable signal; a second inverter configured to have an input end electrically connected to the data polarity identification signal and an output end outputting a data polarity identification inverse signal; a second NOR gate configured to have an input end electrically connected to the output end of the second inverter and the output end of the first inverter and an output end outputting a write enable inverse signal.

4. The transmission circuit according to claim 3, characterized in that, The third data line comprises a local data line and a complementary local data line.

5. The transmission circuit of claim 4, wherein, The write drive circuit comprises: a first switch unit for electrically connecting the local data line and the global data line according to the write enable signal; a second switch unit for electrically connecting the local data line and the complementary global data line according to the write enable inverse signal; a third switch unit for electrically connecting the complementary local data line and the global data line according to the write enable inverse signal; a fourth switch unit for electrically connecting the complementary local data line and the complementary global data line according to the write enable signal.

6. The transmission circuit of claim 5, wherein, The read-write conversion circuit further comprises a read drive circuit, and the read drive circuit comprises: a fifth switch unit having a control end electrically connected to the local data line and being configured to electrically connect the complementary global data line and a first node according to a control end signal; a sixth switch unit configured to electrically connect the first node and a ground end according to a read enable signal; a seventh switch unit having a control end electrically connected to the complementary local data line and being configured to electrically connect the global data line and a second node according to a control end signal; an eighth switch unit configured to electrically connect the second node and the ground end according to the read enable signal.

7. The transmission circuit of claim 1, wherein, The data conversion module is further configured to, in a case where the comparison result exceeds the preset threshold value, transmit the second data after being inverted to the first data line, and is further configured to in a case where the comparison result does not exceed the preset threshold value, transmit the second data to the first data line.

8. The transmission circuit of claim 7, wherein, The data conversion module further comprises: a third transmission unit electrically connected to the first data line, the second data line, and the output end of the state identification unit through a third inverting unit, and configured to, in a case where the comparison result does not exceed the preset threshold value, transmit the second data to the first data line; a fourth transmission unit electrically connected to the first data line, the output end of the state identification unit, and the second data line through a fourth inverting unit, and configured to, in a case where the comparison result exceeds the preset threshold value, transmit the second data after being inverted to the first data line.

9. The transmission circuit of claim 8, wherein, The data bus buffer module further comprises: a read unit configured to transmit the second data to the third transmission unit or transmit the second data after being inverted through the fourth inverting unit to the fourth transmission unit.

10. A memory device, comprising: comprises: The transmission circuit according to any one of claims 1-9, configured to store and transmit data of a read operation or a write operation.

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