A semiconductor memory and a control method thereof, and a memory system

Abstract

The embodiment of the present disclosure provides a semiconductor memory, comprising: an input module configured to receive an address / command input signal; a plurality of redundancy modules, the plurality of redundancy modules being divided into N sets, N being an integer greater than 1; the redundancy module is configured to receive the address / command input signal and output a first enable signal; N buses corresponding to the N sets, each bus being directly electrically connected to the output end of the plurality of redundancy modules in the corresponding set; a control module configured to obtain a second enable signal according to the signals output by the N buses; the first enable signal and the second enable signal are used to indicate redundancy decoding or normal decoding. Since the output ends of the plurality of redundancy modules are directly electrically connected to the corresponding buses, the plurality of first enable signals are combined, the number of signal transmission stages is greatly reduced, and the use performance of the memory is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and relates to, but is not limited to, a semiconductor memory and a control method thereof, and a memory system. BACKGROUND

[0002] A semiconductor memory chip is an important component for storing data in various electronic devices, and with the development of integrated circuit technology, the precision and complexity of semiconductor memory chips are increasingly improved. Due to the limitations of production processes and production conditions, the semiconductor memory chips produced are not perfect, and therefore higher and higher requirements are put forward for fault diagnosis and redundancy repair of the memory. For the memory with storage failure in the actual use process, how to improve the processing speed of the redundancy repair operation thereof becomes a problem to be solved. SUMMARY

[0003] Therefore, the main purpose of the present disclosure is to provide a semiconductor memory and a control method thereof, and a memory system.

[0004] To achieve the above purpose, the technical scheme of the present disclosure is as follows:

[0005] The present disclosure provides a semiconductor memory, comprising:

[0006] An input module configured to receive an address / command input signal;

[0007] A plurality of redundancy modules, the plurality of redundancy modules are divided into N sets, N is an integer greater than 1; the redundancy module is configured to receive the address / command input signal and output a first enable signal;

[0008] N buses corresponding to the N sets, each bus is directly electrically connected to the output end of the plurality of redundancy modules in the corresponding set;

[0009] A control module configured to obtain a second enable signal according to the signals output by the N buses; the first enable signal and the second enable signal are configured to indicate redundancy decoding or normal decoding.

[0010] In the above scheme, the control module comprises a logic unit;

[0011] Each bus is connected to the logic unit;

[0012] The logic unit is configured to obtain the second enable signal by performing logical operation on the signals output by the N buses.

[0013] In the scheme, the logic unit comprises a logic NAND gate and an inverter, the input ends of the logic NAND gate are connected with the buses respectively, and the output end of the logic NAND gate is connected with the input end of the inverter.

[0014] In the scheme, the control module further comprises N reset units and N holding units; each bus is connected with a reset unit and a holding unit;

[0015] The reset unit is configured to reset the signal of the bus at power-on.

[0016] The holding unit is configured to hold the signal of the corresponding bus.

[0017] In the scheme, the holding unit comprises an inverter and a first transistor; the input end of the inverter is connected with the bus, and the output end of the inverter is connected with the gate of the first transistor.

[0018] The reset unit comprises a second transistor, the gate of the second transistor is connected with an external power supply, one pole of the second transistor is connected with a power supply voltage, and the other pole of the second transistor is connected with the bus.

[0019] In the scheme, the holding unit is configured to hold the signal of the bus at weak logic 1 after the reset unit is reset, and pull down the signal of the bus from weak logic 1 to logic 0 when at least one of the first enable signals output by the plurality of redundant modules in the set indicates to perform redundant decoding.

[0020] In the scheme, further comprising: a storage array, the storage array comprises a plurality of storage parts;

[0021] The plurality of redundant modules are connected with the plurality of storage parts one by one.

[0022] In the scheme, further comprising: a decoding module, the output end of the control module is coupled to the input end of the decoding module, and the decoding module is configured to perform redundant decoding or normal decoding on the address / command input signal based on the second enable signal.

[0023] In the scheme, the redundant module comprises an address comparison unit, the address comparison unit is configured to compare address information in the address / command input signal with redundant address information, and output a first enable signal according to a comparison result.

[0024] The embodiments of the present disclosure further provide a control method of a semiconductor memory, the semiconductor memory comprising a plurality of storage parts, the method comprising:

[0025] receive address / command input signals and output a plurality of first enable signals corresponding to the plurality of storage portions;

[0026] For each of the sets, output the plurality of first enable signals directly to a corresponding one of the buses;

[0027] obtain a second enable signal from signals output by the N buses; the first enable signals and the second enable signal are used to indicate whether to perform redundant decoding or normal decoding.

[0028] In the above solution, the method further includes: performing redundant decoding or normal decoding on the address / command input signals according to the second enable signal.

[0029] In the above solution, the method further includes: resetting the signals of the buses at power-on.

[0030] In the above solution, the method further includes: after the resetting, maintaining the signals of the buses at a weak logic 1, and when at least one of the first enable signals in the set indicates that redundant decoding is to be performed, pulling down the signals of the buses from the weak logic 1 to a logic 0.

[0031] In the above solution, the receiving address / command input signals and outputting a plurality of first enable signals corresponding to the plurality of storage portions includes:

[0032] comparing address information in the address / command input signals with redundant address information, and outputting a plurality of first enable signals corresponding to the plurality of storage portions according to a comparison result.

[0033] The embodiments of the present disclosure further provide a memory system, including: at least one semiconductor memory as described above; and

[0034] a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory.

[0035] The technical solution provided in this disclosure includes a semiconductor memory comprising: an input module for receiving address / command input signals; multiple redundant modules divided into N sets, where N is an integer greater than 1; each redundant module receiving the address / command input signals and outputting a first enable signal; N buses corresponding one-to-one with the N sets, each bus being directly electrically connected to the output terminals of the multiple redundant modules in its corresponding set; and a control module for obtaining a second enable signal based on the signals output by the N buses. The first and second enable signals are used to indicate whether to perform redundancy decoding or normal decoding. By directly connecting the output terminals of multiple redundant modules to their corresponding buses, the multiple first enable signals are combined, significantly reducing the number of signal transmission stages and enabling faster receipt of the second enable signal indicating whether to perform redundancy decoding or normal decoding. This improves the processing speed of redundancy repair operations and enhances the memory's performance in practical applications. Simultaneously, it simplifies the circuit structure and reduces the area occupied by the circuit. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a redundant signal generation circuit provided in related technologies;

[0037] Figure 2 A schematic diagram of a redundant signal generation circuit provided in an embodiment of this disclosure;

[0038] Figure 3 A schematic diagram of a semiconductor memory provided for an embodiment of this disclosure;

[0039] Figure 4 A schematic diagram of the circuit of the control module provided in an embodiment of this disclosure;

[0040] Figure 5 A schematic diagram of a decoding module provided in an embodiment of this disclosure;

[0041] Figure 6 A schematic diagram illustrating the implementation flow of a semiconductor memory control method provided in this embodiment of the disclosure;

[0042] Figure 7 This is a schematic diagram of a memory system provided in an embodiment of the present disclosure. Detailed Implementation

[0043] The technical solutions of the present disclosure will be described in further detail below in conjunction with the accompanying drawings and examples. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to convey the full scope of the present disclosure to those skilled in the art.

[0044] The present disclosure will be described in further detail below with reference to the accompanying drawings and examples. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to convey the full scope of the present disclosure to those skilled in the art.

[0045] It should be understood that spatially relative terms, such as "under", "below", "lower", "on", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, then a dependent element described as "below" or "beneath" or "under" another element or feature would then be oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0048] Figure 1 A schematic diagram of a generation circuit of an overall redundancy signal HITTOR in a semiconductor memory is shown. As Figure 1As shown, taking the storage array of the semiconductor memory including 64 storage parts as an example, each storage part is provided with a redundant unit, and the redundant unit of each storage part generates a local redundancy signal HITT. The 64 HITT signals HITT<0:63> are subjected to serial logic operation (for example, logic OR operation) to obtain an overall redundancy signal HITTOR. Specifically, a first OR gate O1 is used to receive two local redundancy signals HITT<0:1> among the first to sixty-four local redundancy signals HITT<0:63> and output a first logic signal. A second OR gate O2 is used to receive the first logic signal and the local redundancy signal HITT<2> and output a second logic signal. In this way, a sixty-third OR gate O63 is used to receive the logic signal output by a sixty-second OR gate O62 and the local redundancy signal HITT<63> and output the overall redundancy signal HITTOR. When there is at least one logic 1 in the 64 local redundancy signals HITT<0:63>, the output overall redundancy signal HITTOR is logic 1, which is used to indicate that the redundancy repair operation is performed. The serial logic operation has too many logic gates used in the circuit structure, and needs to perform 64-level signal step-by-step transmission, so that the signal delay is prone to occur, and the delay does not improve the processing speed of the redundancy repair operation.

[0049] The embodiment of the present disclosure provides a schematic diagram of a generation circuit of an overall redundancy signal HITTOR in a semiconductor memory. Please refer to Figure 2 As shown, taking the storage array of the semiconductor memory including 32 storage parts as an example, the redundant unit of each storage part generates a local redundancy signal HITT. The 32 HITT signals HITT<0:31> are subjected to binary logic operation, specifically, Figure 2The schematic diagram of the generation circuit of the overall redundancy signal HITTOR includes first to thirty-second AND gates A1 to A32, wherein each of the first to sixteenth AND gates A1 to A16 is configured to output a first to sixteenth logic signal in response to two partial repair signals in the first to thirty-second partial redundancy signals HITT<0:31>, respectively. The seventeenth to twenty-fourth AND gates A17 to A24 are configured to receive the first to sixteenth logic signals output from the first to sixteenth AND gates A1 to A16, wherein each of the A17 to A24 receives two logic signals in the first to sixteenth logic signals. The twenty-fifth to twenty-eighth AND gates A25 to A28 are configured to receive output signals of the seventeenth to twenty-fourth AND gates A17 to A24, wherein each of the A25 to A28 receives two logic signals in the output signals of the A17 to A24. The twenty-ninth to thirtieth AND gates A29 to A30 are configured to receive output signals of the twenty-fifth to twenty-eighth AND gates A25 to A28, wherein each of the A29 to A30 receives two logic signals in the output signals of the A25 to A28. The thirty-first AND gate A31 is configured to generate the overall redundancy signal HITTOR by receiving the output signals of the AND gates A29 and A30, and the output overall redundancy signal HITTOR is logic 0 when there is at least one logic 0 in the thirty-two partial redundancy signals HITT<0:31>, which is configured to indicate that the redundancy repair operation is performed. The above-mentioned binary-decision logic operation reduces the transmission level of the thirty-two partial redundancy signals HITT<0:31> to five levels, which reduces the delay in the signal transmission process. However, the above-mentioned binary-decision circuit structure includes thirty-one AND gates, which occupies a large area and has complex wiring between the logic gates at each level, which is not conducive to improving the performance of the semiconductor memory, and thus further improvement is needed.

[0050] Based on this, the present disclosure proposes the following embodiments.

[0051] Figure 3 A schematic diagram of an exemplary semiconductor memory 30 according to the present disclosure is shown. In one example, the semiconductor memory can include a dynamic random access memory (DRAM). As shown in FIG. 1, the semiconductor memory 30 includes a memory array 31, a row decoder 32, a column decoder 33, a sense amplifier 34, a data register 35, a data buffer 36, a command decoder 37, a control logic 38, and a redundancy repair circuit 39. Figure 3As shown, the semiconductor memory 30 comprises: an input module 310, configured to receive address / command input signals; a plurality of redundancy modules 320, the plurality of redundancy modules 320 being divided into N sets, N being an integer greater than 1; the redundancy modules 320 are configured to receive the address / command input signals and output first enable signals; N buses 330 corresponding to the N sets respectively, each bus 330 being directly electrically connected to the output ends of the plurality of redundancy modules 320 in the corresponding set; a control module 340, configured to obtain a second enable signal according to the signals output by the N buses 330; the first enable signal and the second enable signal are used to indicate to perform redundancy decoding or normal decoding. It should be noted that, Figure 3 An example in which N is equal to 2 is described.

[0052] By directly electrically connecting each bus 330 to the output ends of the plurality of redundancy modules 320 in the corresponding set, the merging of the first enable signals output by the plurality of redundancy modules 320 is realized without using logic gates, the number of signal transmission stages is greatly reduced, the signal transmission time is shortened, the second enable signal indicating to perform redundancy decoding or normal decoding can be obtained faster, thereby improving the processing speed of the redundancy repair operation, and the circuit structure is simplified and the occupied area of the circuit structure is reduced.

[0053] In the embodiment of the present disclosure, the control module 340 comprises a logic unit 341; each bus 330 is connected to the logic unit 341; and the logic unit 341 is configured to perform a logic operation on the signals output by the N buses 330 to obtain the second enable signal.

[0054] Figure 4 A circuit schematic diagram of the control module provided in the embodiment of the present disclosure is shown in Figure 4 As shown, the logic unit 341 comprises a logic NAND gate 3411 and an inverter 3412, the input ends of the logic NAND gate 3411 are connected to the buses 330 respectively, and the output end of the logic NAND gate 3411 is connected to the input end of the inverter 3412. In a specific example, the logic NAND gate 3411 receives the signals from the buses and outputs the signals output by the buses to the inverter 3412 after performing a logic operation on the signals, and outputs the second enable signal through the inverter 3412. When there is at least one signal of logic 0 in the bus signals input to the logic unit 341, the second enable signal obtained after the logic operation via the logic unit 341 is also of logic 0, and at this time the second enable signal indicates to perform redundancy decoding.

[0055] In the embodiment of the present disclosure, the control module further comprises N reset units and N holding units; each bus is connected to a reset unit 342 and a holding unit 343; the reset unit 342 is configured to reset the signal of the corresponding bus when powered on; and the holding unit 343 is configured to hold the signal of the corresponding bus.

[0056] In the embodiments of the present disclosure, the holding unit 343 comprises an inverter 3431 and a first transistor 3432; an input end of the inverter 3431 is connected with the bus, and an output end of the inverter 3431 is connected with a gate of the first transistor 3432; the reset unit 342 comprises a second transistor 3421, a gate of the second transistor 3421 is connected with the external power supply PWRB, one of source-drain electrodes of the second transistor 3421 is connected with the power supply voltage VDD, and the other is connected with the bus 330.

[0057] In some embodiments, a source of the second transistor 3421 is connected with the power supply voltage VDD, when the external power supply PWRB connected with the gate of the second transistor 3421 of the reset unit 342 provides a logic low voltage (for example, ground or 0V), the second transistor 3421 will be turned on, and the signal of the bus 330 is reset to logic 1.

[0058] In some embodiments, in order to maintain the signal state of the bus 330, the holding unit 343 is set, when the signal of the bus 330 is reset to logic 1, the inverter 3431 outputs logic 0 to the gate of the first transistor 3432, and because the source of the first transistor 3432 is connected with the power supply voltage VDD, the first transistor 3432 is turned on, so that the signal of the bus 330 is maintained or kept as logic 1. In the preferred embodiments, the first transistor 3432 is a P-type metal oxide semiconductor (PMOS) transistor, and the ratio of the width to the length of the channel of the PMOS transistor is set to be small, so that the driving capability of the PMOS transistor is weak, and the current is small after the PMOS transistor is turned on. When the first transistor 3432 is set as the PMOS transistor in the holding unit 343, the signal of the bus 330 is maintained as weak logic 1. It should be noted that, in the above embodiments, the logic 1 corresponds to the case that the output voltage of the PMOS transistor is high voltage, and the weak logic 1 corresponds to the case that the output voltage of the PMOS transistor is weak high voltage, and here, the weak high voltage is less than the high voltage and greater than half of the high voltage. For example, when the output voltage of the PMOS transistor is 1V, it is in the logic 1 state. When the output voltage of the PMOS transistor is 0.7V, it is in the weak logic 1 state.

[0059] In the embodiment of the present disclosure, the holding unit 343 is configured to hold the signal of the bus at weak logic 1 after the resetting of the resetting unit 342, and pull down the signal of the bus from weak logic 1 to logic 0 when at least one of the first enable signals output by the plurality of redundant modules 320 in the set indicates that the redundant decoding is performed. In the embodiment of the present disclosure, by setting the holding unit, the signal of the bus can be pulled down from weak logic 1 to logic 0 directly and quickly when the first enable signal indicating that the redundant decoding is performed is received, so as to further reduce the delay time and improve the processing speed of the redundant repair operation.

[0060] In the embodiment of the present disclosure, the redundant module 320 comprises an address comparison unit configured to compare the address information in the address / command input signal with the redundant address information, and output the first enable signal according to the comparison result. Specifically, when the address information in the address / command input signal matches the redundant address information, the first enable signal is 0, indicating that the redundant decoding is performed. When at least one of the first enable signals output to the plurality of buses 330 indicates that the redundant decoding is performed, the signal of the bus 330 will be pulled down from weak logic 1 to logic 0 quickly, and then at least one of the signals input to the logic unit 341 is logic 0, regardless of whether the signals on the other buses are logic 1 or logic 0, the obtained second enable signal is 0, indicating that the redundant decoding is performed. When the address information in the address / command input signal does not match the redundant address information, the first enable signal is 1, indicating that the normal decoding is performed, and the signal of the bus is always maintained at weak logic 1, so that the signals input to the logic unit 341 are all logic 1, and the obtained second enable signal is 1, indicating that the normal decoding is performed.

[0061] It can be understood that when there is at least one first enable signal being 0 among the plurality of first enable signals input to the corresponding bus, the signal of the corresponding bus will be pulled down from weak logic 1 to logic 0 rapidly and output to the logic unit 341. Since the logic unit 341 performs logical AND operation on the received bus signals, once a signal logic 0 transmitted by a bus is received, the logic unit 341 can directly output the second enable signal indicating the redundant decoding regardless of the state of other bus signals. Therefore, the time for the logic unit 341 to output the second enable signal indicating the redundant decoding will not be affected by the signals of other buses, and the overall output speed of the signal can be improved and the delay can be reduced, thereby improving the processing speed of the redundant repair operation. In a specific example, the address comparison unit can include an array rupture electrical fuse (ARE), which can store information about addresses that have failed, i.e., redundancy address information. The redundancy address information collected during the semiconductor memory test can be temporarily stored in a storage device of the semiconductor memory tester and then applied to the semiconductor memory to cause the electrical fuse corresponding to the address to rupture, so as to permanently store the redundancy address information in the semiconductor memory.

[0062] In the embodiments of the present disclosure, the semiconductor memory further includes a decoding module 350, an output end of the control module is coupled to an input end of the decoding module 350, and the decoding module 350 is configured to perform redundant decoding or normal decoding on the address / command input signal based on the second enable signal.

[0063] Figure 5 A schematic diagram of the decoding module 350 is shown as follows. Figure 5 As shown in the figure, the decoding module 350 includes a redundant decoding unit 351 and a normal decoding unit 352. When the second enable signal is 1, the second enable signal indicates to perform normal decoding, and thus the normal decoding unit 352 is enabled to perform normal decoding on the address information in the address / command input signal to obtain the address of the normal storage unit. When the second enable signal is 0, the second enable signal indicates to perform redundant decoding, and thus the redundant decoding unit 351 is enabled to perform redundant decoding on the address information in the address / command input signal to obtain the address of the redundant storage unit replacing the defective address. The redundant decoding unit 351 and the normal decoding unit 352 each include two decoding parts, i.e., a row decoding part for performing row address decoding and a column decoding part for performing column address decoding.

[0064] In the embodiments of the present disclosure, the semiconductor memory further includes a storage array 360 including a plurality of storage portions; and the plurality of redundancy modules 320 are connected to the plurality of storage portions one by one. The storage portion can be a storage bank or a memory array tile (Mat), and each storage bank or each memory array tile can include a plurality of storage units.

[0065] The embodiments of the present disclosure further provide a control method of a semiconductor memory including a plurality of storage portions, Figure 6 The specific implementation flowchart of the control method of the semiconductor memory provided by the embodiments of the present disclosure is shown in Figure 6 The control method specifically includes the following steps:

[0066] Step S610: receiving an address / command input signal and outputting a plurality of first enable signals corresponding to a plurality of storage portions; dividing the plurality of first enable signals into N sets, N being an integer greater than 1.

[0067] In the above step S610, the address / command input signal is received, and a plurality of first enable signals corresponding to a plurality of storage portions are outputted, including: comparing address information in the address / command input signal with redundancy address information, and outputting a plurality of first enable signals corresponding to a plurality of storage portions according to the comparison result. Specifically, when the address information in the address / command input signal matches the redundancy address information, the first enable signal is 0, indicating that redundancy decoding is performed; when the address information in the address / command input signal does not match the redundancy address information, the first enable signal is 1, indicating that normal decoding is performed.

[0068] Step S620: for each set, directly outputting the plurality of first enable signals to a corresponding bus.

[0069] In the above step S620, the method further includes resetting the signal of the bus at power-on. Specifically, the source of the second transistor 3421 is connected to the power supply voltage VDD, and when the external power supply PWRB connected to the gate of the second transistor 3421 in the reset unit 342 provides a logic low voltage (for example, ground or 0V), the second transistor 3421 will be turned on, and the signal of the bus 330 is reset to logic 1.

[0070] After the reset, the signal of the bus 330 is kept at weak logic 1, and when at least one of the plurality of first enable signals in the set indicates that the redundant decoding is performed, the signal of the bus is pulled down from weak logic 1 to logic 0. In a specific example, when the address information in the address / command input signal matches the redundant address information, the first enable signal is 0, indicating that the redundant decoding is performed, and when at least one of the plurality of first enable signals output to the corresponding bus is 0, the signal of the bus will be pulled down from weak logic 1 to logic 0; when the address information in the address / command input signal does not match the redundant address information, the first enable signal is 1, indicating that the normal decoding is performed, and the signal of the bus is always maintained at weak logic 1.

[0071] Step S630: obtaining a second enable signal according to the signals output by the N buses; the first enable signal and the second enable signal are used to indicate that the redundant decoding or the normal decoding is performed.

[0072] In a specific example, the logic operation on the signals output by the N buses is implemented by the logic unit 341, the logic NAND gate 3411 receives the signals output by the N buses and outputs to the inverter 3412, and the second enable signal is output via the inverter 3412. When there is at least one signal of the bus being logic 0 among the bus signals input to the logic unit 341, the second enable signal obtained after the logic operation via the logic unit 341 is also logic 0, and at this time the second enable signal indicates that the redundant decoding is performed.

[0073] In some embodiments, when the address information in the address / command input signal matches the redundant address information, the first enable signal is 0, indicating that the redundant decoding is performed, at least one of the plurality of first enable signals output to the corresponding bus is logic 0, and the signal of the bus will be quickly pulled down from weak logic 1 to logic 0, so that there is at least one signal being logic 0 input to the logic unit 341, regardless of whether the signals on other buses are logic 1 or logic 0, the obtained second enable signal is 0, and at this time the second enable signal indicates that the redundant decoding is performed; when the address information in the address / command input signal does not match the redundant address information, the first enable signal is 1, indicating that the normal decoding is performed, and the signal of the bus is always maintained at weak logic 1, so that the signals of the buses input to the logic unit 341 are all logic 1, the obtained second enable signal is 1, and at this time the second enable signal indicates that the normal decoding is performed.

[0074] According to the second enable signal, the address / command input signal is redundantly decoded or normally decoded. When the second enable signal is 1, it indicates to perform normal decoding, and the address information in the address / command input signal is normally decoded to obtain the address of a normal storage unit. When the second enable signal is 0, it indicates to perform redundant decoding, and the address information in the address / command input signal is redundantly decoded to obtain the address of a redundant storage unit that replaces a defective address.

[0075] Figure 7 A schematic diagram of a memory system according to an exemplary embodiment is shown. Based on the semiconductor memory structure described above, embodiments of the present disclosure provide a memory system, as shown in Figure 7 The memory system includes at least one semiconductor memory as described above; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory.

[0076] The memory system 700 includes a mobile phone, a smart phone, a desktop computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a digital TV, a set-top box, a portable game console, a navigation system, a wearable electronic device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a semiconductor memory therein.

[0077] As shown in Figure 7 The memory system 700 can include a host 708 and a memory sub-system 702 having one or more semiconductor memories 704, as shown in

[0078] According to some embodiments, the memory controller 706 is also coupled to the host 708. The memory controller 706 can provide an interface to the semiconductor memory 704 to manage data stored in the semiconductor memory 704, and can communicate with the host 708 through at least one of various interface protocols (e.g., USB, MMC, PCIe, Serial ATA, Parallel ATA, SCSI). The memory controller 706 can be implemented as a standalone chip, or can be integrated with the semiconductor memory 704. The memory controller 706 can be implemented on a motherboard, and can be implemented as an integrated memory controller (IMC) included in a microprocessor.

[0079] In some embodiments, the memory controller 706 can transmit and receive command / address signals C / A, clock signals CLK, control signals CTRL, data DQ, and / or data strobe signals DQS to and from the semiconductor memory 704. The memory controller 706 can be configured to control operations of the semiconductor memory 704, such as read and write operations.

[0080] It can be understood that the memory controller 706 can perform a control method as provided by any of the embodiments of the present disclosure.

[0081] The embodiments of the present disclosure provide a semiconductor memory that directly electrically connects outputs of a plurality of redundancy modules to corresponding buses, reduces the number of signal transmission stages, can obtain a second enable signal indicating to perform redundancy decoding or normal decoding more quickly, and can improve the processing speed of a redundancy repair operation, thereby improving the use performance of the memory in the actual use of the semiconductor memory.

[0082] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above-mentioned embodiments of the present disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0083] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor memory, characterized by comprising: The semiconductor memory comprises: an input module configured to receive an address / command input signal; a plurality of redundancy modules, the plurality of redundancy modules being divided into N sets, N being an integer greater than 1; the redundancy modules being configured to receive the address / command input signal and output a first enable signal; N buses corresponding to the N sets respectively, each bus being directly electrically connected to the output terminals of the plurality of redundancy modules in the corresponding set; a control module configured to obtain a second enable signal according to the signals output by the N buses; the first enable signal and the second enable signal being used to indicate whether to perform redundancy decoding or normal decoding; the control module comprises a logic unit; each bus is connected to the logic unit; the logic unit is configured to perform a logic operation on the signals output by the N buses to obtain the second enable signal; the control module further comprises N reset units and N holding units; each bus is connected to a reset unit and a holding unit; the reset unit is configured to reset the signals of the bus when power is turned on; the holding unit is configured to hold the signals of the corresponding bus.

2. The semiconductor memory according to claim 1, wherein the logic unit comprises a logic NAND gate and an inverter, the input terminals of the logic NAND gate being connected to the buses respectively, and the output terminal of the logic NAND gate being connected to the input terminal of the inverter.

3. The semiconductor memory according to claim 1, wherein the holding unit comprises an inverter and a first transistor; the input terminal of the inverter is connected to the bus, and the output terminal of the inverter is connected to the gate of the first transistor; the reset unit comprises a second transistor, the gate of the second transistor being connected to an external power supply, one of the source and drain of the second transistor being connected to a power supply voltage, and the other being connected to the bus.

4. The semiconductor memory according to claim 1, wherein the holding unit is configured to hold the signals of the bus at a weak logic 1 after the reset unit is reset, and to pull down the signals of the bus from the weak logic 1 to a logic 0 when at least one of the first enable signals output by the plurality of redundancy modules in the set indicates that redundancy decoding is to be performed.

5. The semiconductor memory according to claim 1, wherein The semiconductor memory further comprises: a memory array comprising a plurality of memory portions; the plurality of redundancy modules are connected to the plurality of memory portions one by one.

6. The semiconductor memory according to claim 1, wherein The semiconductor memory further comprises: a decoding module, the output terminal of the control module being coupled to the input terminal of the decoding module, the decoding module being configured to perform redundancy decoding or normal decoding on the address / command input signal based on the second enable signal.

7. The semiconductor memory according to claim 1, wherein the redundancy module comprises an address comparison unit, the address comparison unit being configured to compare address information in the address / command input signal with redundancy address information, and output a first enable signal according to the comparison result.

8. A control method of a semiconductor memory, characterized by, The semiconductor memory comprises a plurality of memory portions, and the method comprises: receive address / command input signals and output a plurality of first enable signals corresponding to the plurality of storage portions; for each of the sets, output the plurality of first enable signals directly to a corresponding one of N buses, N being an integer greater than 1; obtain a second enable signal from signals output by the N buses; the first enable signals and the second enable signal are used to indicate whether to perform redundant decoding or normal decoding; the method further comprises: perform redundant decoding or normal decoding on the address / command input signals according to the second enable signal; reset the signals of the buses at power-up; after the reset, maintain the signals of the buses at a weak logic 1, and when at least one of the first enable signals in the set indicates that redundant decoding is to be performed, pull down the signals of the buses from the weak logic 1 to a logic 0.

9. The control method according to claim 8, characterized by, the receiving address / command input signals and outputting a plurality of first enable signals corresponding to the plurality of storage portions comprises: comparing address information in the address / command input signals with redundant address information, and outputting a plurality of first enable signals corresponding to the plurality of storage portions according to a comparison result.

10. A memory system, characterized by, comprises: at least one semiconductor memory as claimed in any of claims 1 to 7; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory. ​

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