Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and fabrication processes are provided. A semiconductor according to the present invention includes a first region having a first fin, a second fin, and a third fin extending along a first direction, and a second region adjoining the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin, and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region. Embodiments of the present application also relate to methods for forming semiconductor structures.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming them. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (the number of interconnects per chip area) has generally increased, while its geometry (the smallest element (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down generally benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices in which the gate structure or a portion thereof is positioned above multiple sides of the channel region. FinFETs are examples of multi-gate devices, and these devices have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel surrounded by gates on more than one side (e.g., the gates surround the top and sidewalls of a "fin" of semiconductor material extending from the substrate).

[0004] As the name suggests, the active region of a FinFET resembles a fin and is formed from a semiconductor substrate or a semiconductor layer formed on the substrate. During fin formation, some fins may be removed or cut to fit various design needs. Although existing active formation processes are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this application provide a semiconductor structure including: a first non-rectangular device region including: a first region including a first fin, a second fin and a third fin extending along a first direction; and a second region adjacent to the first region, the second region including a fourth fin and a fifth fin extending along the first direction, wherein the first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin, wherein the third fin terminates at the interface between the first region and the second region.

[0006] Other embodiments of this application provide a semiconductor structure including: a semiconductor substrate; a first dual-fin device region located above the semiconductor substrate, the first dual-fin device region including: a first fin; and a second fin spaced apart from the first fin; and a second dual-fin device region located above the semiconductor substrate, the second dual-fin device region including: a third fin spaced apart from the second fin by at least four times the space; and a fourth fin spaced apart from the third fin, wherein a portion of the semiconductor substrate between the second fin and the third fin is substantially flat.

[0007] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: depositing a first hard mask layer over a substrate; depositing a second hard mask layer over the first hard mask layer; forming a plurality of spacers over the second hard mask layer; depositing an underlayer over the plurality of spacers and the second hard mask layer; depositing a third hard mask layer over the underlayer; patterning the third hard mask layer to form a patterned third hard mask layer disposed directly over a first portion of the plurality of spacers but not directly over a second portion of the plurality of spacers; forming a patterned photoresist layer over the patterned third hard mask; using the patterned third hard mask layer and the patterned photoresist layer as an etch mask to pattern the underlayer such that the patterned underlayer covers the first portion of the plurality of spacers, and removing the second portion of the plurality of spacers; removing the underlayer to expose the first portion of the plurality of spacers; and after removing the underlayer, using the first portion of the plurality of spacers as an etch mask to pattern the substrate to form a plurality of fin elements. Attached Figure Description

[0008] Aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A flowchart illustrating a method for forming a semiconductor structure having a plurality of semiconductor fins according to one or more aspects of the present invention is shown.

[0010] Figures 2 to 22 According to one or more aspects of the invention Figure 1 A partial cross-sectional view or top view of the workpiece during the manufacturing process of the method. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] Furthermore, as those skilled in the art will understand, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with a manufactured component, the component has characteristics associated with a numerical value, and the numerical value or range encompasses a reasonable range including the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer with a thickness of "about 5 nm" may cover a size range of 4.25 nm to 5.75 nm, where a manufacturing tolerance associated with the deposited material layer is known to those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or characters may be repeated in various embodiments of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, exemplary embodiments are described herein with reference to schematic and / or idealized partial cross-sectional or top views. Thus, variations in the illustrated shapes are expected due to manufacturing tolerances. Unless expressly specified herein, the shapes in the illustrations may not be intended to represent actual shapes and should not limit the scope of the invention. Moreover, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain.

[0015] FinFETs can include one or more fins to accommodate different design needs. For example, the number of fins in a FinFET can determine its drive current, speed, and leakage current. Generally, a FinFET with a larger number of fins has a larger drive current, faster speed, and larger leakage current. Conversely, a FinFET with a smaller number of fins has a smaller drive current, slower speed, and smaller leakage current. In some existing technologies, adjacent fin groups can accommodate a lateral cut and a longitudinal cut after their formation. The former reduces the length of the fins, while the latter reduces the number of fins. The lateral cut can also be referred to as a fine cut, and the longitudinal cut can also be referred to as a coarse cut. The lateral and longitudinal cuts are typically unidirectionally elongated. Because the lateral and longitudinal cuts are perpendicular to each other and elongate, they result in a rectangular multi-fin device region that includes the same number of fins along its entire length, such as two, three, or four fins. In some instances, device regions with different numbers of fins can even be placed on two different wafers. In these prior art technologies, when circuit design requires low-leakage transistors with fewer fins and high-speed transistors with more fins, these two types of transistors must be formed in different active regions that are far apart from each other, thereby reducing design flexibility or increasing wiring.

[0016] This invention provides a method for forming a non-rectangular active region having more than one sub-region, which includes different numbers of fin elements. For example, the non-rectangular active region may include one sub-region with three fin elements and another sub-region with two fin elements. The non-rectangular active region allows for greater design flexibility because high-speed / high-drive-current 3-fin transistors can be placed near low-power / low-leakage dual-fin transistors. Unlike prior art, the method of this invention uses a patterned hard mask and a patterned photoresist layer as an etching mask when forming the active region. Forming the patterned photoresist layer includes using a bidirectional exposure pattern.

[0017] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after these methods, and some steps described may be replaced, eliminated, or moved for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 22 Description method 100, Figures 2 to 22These are partial cross-sectional or top views of the workpiece 200 at different manufacturing stages of method 100. Because the workpiece 200 will be manufactured into a semiconductor device or semiconductor structure at the end of the manufacturing process, the workpiece 200 may also be referred to as semiconductor device 200 or semiconductor structure 200 as the context requires. Furthermore, throughout this application, unless otherwise stated, the same reference numerals denote the same parts. Moreover, although the semiconductor structure shown in the figures may have two to three fins, the invention is not limited thereto and is applicable to semiconductor devices having transistors with more than three fins or transistors with fewer than two fins.

[0018] refer to Figure 1 , Figure 2 and Figure 3 Method 100 includes a frame 102 that provides workpiece 200. Figure 2 Includes a partial cross-sectional view of workpiece 200, and Figure 3 A partial top view of workpiece 200 is shown. (For example...) Figure 2 As shown, workpiece 200 includes a substrate 202, a first hard mask 204, a second hard mask 206, a third hard mask 208, and a plurality of spacer members 210. The substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Exemplary group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. The first hard mask 204 may include silicon oxide and may be formed using a thermal oxidation process. The second hard mask 206 may include a dielectric material different from that of the first hard mask 204. In some embodiments, the second hard mask 206 may include silicon nitride. The second hard mask 206 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The third hard mask 208 may include silicon oxide and may be formed using ALD or CVD. In some instances, the thickness of the first hard mask 204 may be between about 15 Å and 35 Å; the thickness of the second hard mask 206 may be between about 200 Å and about 300 Å; and the thickness of the third hard mask 208 may be between about 300 Å and about 700 Å.

[0019] like Figure 2As shown, workpiece 200 may also include a plurality of spacer members 210. The plurality of spacer members 210 may be intermediate structures formed during a dual-patterning or multi-patterning process. Typically, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns, for example, with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process to form a sacrificial mandrel. A spacer material layer is then conformally deposited over the sacrificial mandrel. After the deposited spacer mandrel layer is etched back, the spacer material layer remains along the sidewalls of the sacrificial mandrel. The sacrificial mandrel is then removed, leaving the plurality of spacer members 210. In some embodiments, the plurality of spacer members 210 may comprise silicon nitride.

[0020] Now for reference Figure 2 and Figure 3 The plurality of spacer components 210 includes two sets of spacer components. The first set includes a first spacer component 210-1, a second spacer component 210-2, and a third spacer component 210-3. The second set includes a fourth spacer component 210-4, a fifth spacer component 210-5, and a sixth spacer component 210-6. The first and second sets are characterized by the same spacing P and interval S. However, the first and second sets are spaced apart from each other by a distance D equal to at least four times the interval S. It should be noted that although the first and second sets each include three spacer components, they are merely examples. The invention can be applied to workpieces comprising sets of spacer components, each comprising more than three spacer components.

[0021] refer to Figure 1 , Figure 4 and Figure 5 Method 100 includes a frame 104 in which a first underlayer 211, a fourth hard mask 212, a fifth hard mask 214, and a second underlayer 216 are deposited over a workpiece 200. Figure 4 Includes a partial top view of workpiece 200, and Figure 5A partial cross-sectional view of workpiece 200 along the Y direction is shown. In some embodiments, the first underlayer 211 may be a carbon-containing layer and may include silicon carbide (SiC), silicon carbide oxide (SiOC), or spin-coated carbon (SOC). In some other embodiments, the first underlayer 211 may be a base antireflective coating (BARC) and may include a silicon-containing polymer, such as a polysilazane resin. The second underlayer 216 may be different from the first underlayer 211. In some implementations, the second underlayer 216 may include silicon carbide (SiC), silicon carbide oxide (SiOC), or spin-coated carbon (SOC). The fourth hard mask 212 may include silicon oxide or silicon carbonitride. The fifth hard mask 214 may include silicon or silicon nitride. In an example process, flowable CVD (FCVD), CVD, or spin coating is used to deposit the first underlayer 211 over workpiece 200. The fourth hard mask 212 is then deposited on the first underlayer 211 by CVD. The fifth hard mask 214 is deposited on the fourth hard mask 212 by CVD. Subsequently, flowable CVD (FCVD) or spin coating is used to deposit a second base layer 216 over the fifth hard mask 214.

[0022] refer to Figure 1 and Figures 4 to 6 Method 100 includes a frame 106 in which a fifth hard mask 214 is patterned to form a patterned fifth hard mask 214 disposed directly above a first portion I of a plurality of spacers 210 but not directly above a second portion II of the plurality of spacers 210. Operation of frame 106 may include forming a patterned first photoresist layer 218 over a second bottom layer 216. Figure 4 and Figure 5 As shown), and the patterned first photoresist layer 218 is used as an etching mask ( Figure 6 (As shown) to etch the fifth hard mask 214. At frame 106, the fifth hard mask 214 can be patterned using photolithography and etching processes. In the example process, a first photoresist layer 218 is deposited on the second bottom layer 216. The first photoresist layer 218 is exposed to unidirectional patterning radiation (along the X direction) reflected or transmitted through the photomask, developed in a developer, and baked in a baking process to form the patterned first photoresist layer 218. For ease of reference, the first photoresist layer is identified by reference numeral 218 before and after patterning. Figure 4 and Figure 5As shown, a patterned first photoresist layer 218 extends along the length direction (X direction) of the spacers and is positioned directly above the first portion I of the plurality of spacers 210, rather than directly above the second portion II of the plurality of spacers 210. In the depicted implementation, each of the first portions I includes two spacers. To ensure sufficient coverage of the spacers in the first portion, the long edge of the patterned first photoresist layer 218 overhangs by a margin M above the outermost spacer to be covered. The margin M can be... Figure 3 The interval shown is approximately half of S (0.5), such as between approximately 0.4 times and approximately 0.6 times S. Now refer to... Figure 6 The patterned first photoresist layer 218 can then be used as an etching mask in a dry etching process to pattern a fifth hard mask 214, thereby forming a patterned fifth hard mask 214. The patterned fifth hard mask 214 may have substantially the same vertical coverage as the patterned first photoresist layer 218. That is, the patterned fifth hard mask 214 may also be suspended above the outermost spacer by a margin M. The exemplary dry etching process at block 106 may be a reactive ion etching (RIE) process that uses oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Figure 6 As shown, the patterned fifth hard mask 214 is also positioned directly above the first portion I of the plurality of spacers 210, rather than directly above the second portion II of the plurality of spacers 210.

[0023] refer to Figure 1 and Figures 7 to 9 Method 100 includes a frame 108 in which a patterned second photoresist layer 220 is formed over a patterned fifth hard mask 214 to expose the vertical projection area of ​​a third portion III of a plurality of spacers 210. Figure 7 A partial top view of the workpiece 200 after the patterned second photoresist layer 220 has been formed. Figure 8 The cross-sectional view of workpiece 200 along line A-A' is shown. Figure 9 The diagram shows a cross-sectional view of workpiece 200 along line B-B'. Figure 7 and Figure 8As shown, the patterned second photoresist layer 220 extends longitudinally along the Y direction to intersect with the patterned fifth hard mask 214, thereby defining a third portion III of the plurality of spacer members 210. It should be noted that the third portion III falls within the second portion II, whose X-direction span is truncated by the patterned second photoresist layer 220. Figure 7 and Figure 8 As shown, the third part III is basically rectangular in shape and is located directly above a portion of the third spacer 210-3 and a portion of the fourth spacer 210-4.

[0024] It should be noted that the patterned fifth hard mask 214 and the patterned second photoresist layer 220 together define the third portion III. Specifically, the Y-direction boundary of the third portion III is defined by the patterned fifth hard mask 214, and the X-direction boundary of the third portion III is defined by the patterned second photoresist layer 220. Method 100 includes patterning the second photoresist layer 220 using an exposure pattern 222, which represents the area of ​​the second photoresist layer 220 exposed in the exposure step of the photolithography process. Unlike existing photolithography patterning practices, the exposure pattern 222 is bidirectional, meaning that the exposure pattern 222 includes a component extending along the X-direction and a component extending along the Y-direction. Although this bidirectional exposure pattern 222 tends to result in defects around corners C, those corners C do not define the third portion III in any way. Thus, method 100 obtains the benefits of the bidirectional exposure pattern 222 without suffering any negative consequences.

[0025] refer to Figure 1 and Figures 10 to 11 Method 100 includes a frame 110 in which the third portion III of a plurality of spacer members 210 is removed. Figure 8 (As shown), while the remaining portions of multiple spacer members 210 are embedded in the first bottom layer 211. At frame 110, a patterned fifth hard mask 214 and a patterned second photoresist layer 220 are applied as etching masks to etch the first bottom layer 211 and the spacer members 210. As a result, portions of the first bottom layer 211, as well as the portions of the third spacer members 210-3 and the fourth spacer members 210-4 not covered by the patterned fifth hard mask 214 and the patterned second photoresist layer 220, are etched away at frame 110. Reference Figure 10 Because the spacers in the third portion III of the multiple spacer members 210 are removed, the workpiece 200 includes two dual-fin active regions along line A-A'. (Reference) Figure 11Since the multiple spacer members 210 are protected by a patterned fifth hard mask 214 and a patterned second photoresist layer 220 along the B-B' line, the workpiece 200 includes two tri-fin active regions along the line B-B'. The portion of the spacer members 210 that is not removed at frame 110 is embedded in a patterned first bottom layer 211.

[0026] refer to Figure 1 , Figure 12 and Figure 13 Method 100 includes block 112, in which a first underlayer 211 is removed. At block 112, a selective wet cleaning process or a selective dry etching process can be used to selectively remove the first underlayer 211. An exemplary selective wet cleaning process may include the use of sulfuric acid, hydrogen peroxide, or a combination thereof. An exemplary selective dry etching process may include the use of oxygen (O2) and sulfur dioxide (SO2). Figure 12 A cross-sectional view along line A-A' is shown, while Figure 13 A cross-sectional view along line B-B' is shown after the first underlayer 211 has been removed. Because the etching process of frame 112 is selective for the first underlayer 211, the third hard mask 208 and spacer 210 are substantially intact after the first underlayer 211 has been removed.

[0027] refer to Figure 1 and Figures 14 to 16 Method 100 includes a frame 114 in which the remainder of a plurality of spacer members 210 are used as an etching mask to pattern the substrate 202. Figure 14 A partial top view of workpiece 200 after the operation at box 114 is shown. Figure 15 Including along Figure 14 The diagram shows a partial cross-section of line A-A'. Figure 16 Including along Figure 14A partial cross-sectional view of line B-B' is shown. At box 114, the substrate 202 is patterned to form fin elements 240. In the depicted embodiment, the fin elements 240 include a first fin element 240-1, a second fin element 240-2, a third fin element 240-3, a fourth fin element 240-4, a fifth fin element 240-5, and a sixth fin element 240-6. The first fin element 240-1 corresponds to a first spacer 210-1, the second fin element 240-2 corresponds to a second spacer 210-2, the third fin element 240-3 corresponds to a third spacer 210-3, the fourth fin element 240-4 corresponds to a fourth spacer 210-4, the fifth fin element 240-5 corresponds to a fifth spacer 210-5, and the sixth fin element 240-6 corresponds to a sixth spacer 210-6. In this respect, the spacer may be referred to as the precursor of the corresponding fin element. At frame 114, an anisotropic etching process can be used to pattern the substrate 202. In some embodiments, anisotropic etching can be performed using a RIE process that uses oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof.

[0028] refer to Figure 14 Due to the patterned fifth hard mask 214 and the patterned second photoresist layer 220, frame 114 forms a first non-rectangular device region 300 and a second non-rectangular device region 302. Each of the first non-rectangular device region 300 and the second non-rectangular device region 302 includes two tri-fin active regions 1000 sandwiching a dual-fin active region 2000. Due to the above-described forming process, the first non-rectangular device region 300 is a mirror image of the second non-rectangular device region 302 with respect to the center line between the first and second non-rectangular device regions 300 and 302. Figure 14 As shown, the third fin element 240-3 and the fourth fin element 240-4 do not extend the entire length along the X direction. Due to the lack of a corresponding spacer 210, the middle portion of the third fin element 240-3 and the fourth fin element 240-4 is not formed at all. Figure 15 Show along Figure 14 The cross-sectional view of workpiece 200 along line A-A'. Because line A-A' passes through the double-fin active region 2000, therefore... Figure 14Two fin element groups are shown—one comprising a first fin element 240-1 and a second fin element 240-2, and the other comprising a fifth fin element 240-5 and a sixth fin element 240-6. The two fin element groups are divided by a field region 245. Because the field region 245 is not formed by etching away already formed fin elements, the field region 245 is substantially flat without any fin residue (i.e., residue of removed fins). Figure 16 Show along Figure 14 The cross-sectional view of workpiece 200 with line B-B' in the diagram. Because line B-B' passes through the three-fin active region 1000, therefore... Figure 16 Two sets of three-fin elements are shown—one includes a first fin element 240-1, a second fin element 240-2, and a third fin element 240-3, and the other includes a fourth fin element 240-4, a fifth fin element 240-5, and a sixth fin element 240-6.

[0029] refer to Figure 1 , Figure 17 and Figure 18 Method 100 includes block 116, in which an optional fin cutting process is performed. In some embodiments, a portion of the fin element is removed to cut the formed fin element into more than one segment. Figure 17 A partial top view of workpiece 200 is shown. At box 116, a fin notch 400 is formed using photolithography and etching processes. The fin notch 400 is a lateral notch spanning several fin elements and is performed after the fin elements 240 are formed. In the example process, a substrate similar to a first substrate 211 is deposited over the fin elements 240, and a patterned photoresist layer is formed over the substrate to expose the area of ​​the fin notch 400. Reference Figure 18 Because the fin cut 400 is performed after the fin element 240 is formed and the etching process is selective for the fin element 240, fin residue 250 may remain after the fin cut 400 is formed. No similar fin residue 250 was observed in field area 245 because no formed fin element was removed there.

[0030] refer to Figure 1 , Figure 19 and Figure 20 Method 100 includes block 118 for performing an additional process. This additional process may include forming an isolation portion between fin elements 240, forming a gate dicing portion 266 over the isolation portion, forming a dummy gate, forming source / drain portions (including a first source / drain portion 262 and a second source / drain portion 272), removing the dummy gate stack, and forming a gate structure (including a plurality of first gate structures 264 and a plurality of second gate structures 274).

[0031] Isolation components are formed over substrate 202 to isolate fin elements 240 from each other. In the depicted embodiment, the isolation components surround the bottom of fin elements 240. The isolation components may be referred to as shallow trench isolation (STI) components. In the example process, a dielectric layer is first deposited over substrate 202 while simultaneously filling trenches with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, fluorinated silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited via CVD processes, subatmospheric pressure CVD (SACVD) processes, FCVD processes, spin coating processes, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by dry etching processes, wet etching processes, and / or combinations thereof to form the isolation components.

[0032] Still referencing Figure 19 A gate dicing member 266 may be formed over an isolation member to separate gate structure segments. The gate dicing member 266 may comprise a single layer or multiple layers. In some embodiments, the gate dicing member 266 layer may comprise silicon nitride, silicon carbonitride, silicon carbonitride oxide, aluminum oxide, zinc oxide, titanium oxide, zirconium oxide, hafnium oxide, or other suitable metal oxides. The gate dicing member 266 may be used to segment the gate structure. Subsequently, a dummy gate stack is deposited over workpiece 200, including over fin element 240, isolation member, and gate dicing member 266. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack serves as a placeholder to undergo various processes and is removed and replaced by a functional gate structure. Although not explicitly shown, the dummy gate stack may include a dummy gate dielectric layer and a dummy gate electrode over the dummy gate dielectric layer. In some instances, the dummy gate dielectric layer may include silicon oxide. The dummy electrode layer may include polysilicon. Although not explicitly shown in the figures, one or more gate spacers may be deposited over the sidewalls of the dummy gate stack. After forming one or more gate spacers, the source / drain regions are recessed to form recessed source / drain regions. Source components 262 and drain components 272 can then be formed over the recessed source / drain regions. Source components 262 / drain components 272 may comprise silicon (Si) doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)) or silicon germanium (SiGe) doped with a p-type dopant (e.g., boron (B) or boron difluoride (BF2)). After forming the source / drain components, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer may be sequentially deposited over workpiece 200.

[0033] Still referencing Figure 19After forming the ILD layer, the dummy gate stack can be removed to expose the fin elements 240 in the gate trench defined by the gate spacers. Gate structures 264 and 274 are then formed in the gate trench. Each of gate structures 264 and 274 may include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include an interface layer and a high-k dielectric layer. The interface layer may include silicon oxide, hafnium silicate, or silicon oxynitride. The high-k dielectric layer may include hafnium oxide. Optionally, the high-k dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. Figure 20 The semiconductor structure 200 is similar to Figure 19 The semiconductor structure in 200, but Figure 20 The semiconductor structure also includes a fin-cut dielectric component 402 formed above the fin cutout 400 during the operation of block 116. The fin-cut dielectric component 402 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or a combination thereof.

[0034] Refer again Figure 19Following the operation of block 118, a three-fin transistor is formed above the three-fin active region 1000 and a two-fin transistor is formed above the two-fin active region 2000. The two-fin active region 2000 is sandwiched between the two three-fin active regions 1000. In other words, the two three-fin active regions 1000 are adjacent to the two-fin active regions 2000 from both sides. A plurality of first gate structures 264 are disposed and surround the fin elements in the two three-fin active regions 1000. A plurality of second gate structures 274 are disposed and surround the fin elements in the two-fin active regions 2000. Each of the plurality of first gate structures 264 terminates at a gate cleaving member 266, which extends along the X direction between the first non-rectangular device region 300 and the second non-rectangular device region 302. Each of the plurality of second gate structures 274 extends from the fin element in the first non-rectangular device region 300 to the fin element in the second non-rectangular device region 302. More specifically, each of the plurality of second gate structures 274 is disposed above the first fin element 240-1 and the second fin element 240-2 in the first non-rectangular device region 300, and the fifth fin element 240-5 and the sixth fin element 240-6 in the second non-rectangular device region 302. For example... Figure 19 As shown, each of the first non-rectangular device area 300 and the second non-rectangular device area 302 is a telephone handset shape including a rectangular shape and a rectangular cutout. In some embodiments, Figure 19 The semiconductor structure 200 shown may be a ring oscillator. In these embodiments, the first non-rectangular device region 300 may include an n-type multi-fin transistor, and the second non-rectangular device region 302 may include a p-type multi-fin transistor. A plurality of second gate structures 274 may be used to interconnect the n-type multi-fin transistor and the p-type multi-fin transistor.

[0035] In some alternative embodiments, the non-rectangular device area may take other shapes based on the pattern of the patterned second photoresist layer formed in frame 108. Referring now to... Figure 21 In an optional embodiment, an optional patterned photoresist layer 220' is formed at frame 108. The optional patterned photoresist layer 220' intersects with a patterned fifth hard mask 214 to jointly define two fourth portions IV of the plurality of spacers 210. Forming the patterned photoresist layer 220' includes using a bidirectional exposure pattern. When this optional patterned photoresist layer 220' is formed at frame 108, the plurality of spacers 210 and the substrate 202 are correspondingly patterned at frames 110 and 114, thereby producing Figure 22 The third non-rectangular device region 300' and the fourth non-rectangular device region 302' are shown. Figure 22 This includes three trifined active regions 1000 that intersect with the two bifined active regions 2000. For simplicity, details regarding... Figure 22 A detailed description of the additional processes for the workpiece 200 shown.

[0036] Embodiments of the present invention offer advantages. For example, the method of the present invention forms a non-rectangular device region comprising an active region having a different number of fins. This arrangement allows different types of transistors to be placed close to each other. In an exemplary embodiment, a three-fin active region for a high-speed or high-drive-current transistor is adjacent to a two-fin active region for a low-power transistor.

[0037] In one exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a first non-rectangular device region. The first non-rectangular device region includes: a first region including a first fin, a second fin, and a third fin extending along a first direction; and a second region adjacent to the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin, and the second fin is aligned with the fifth fin. The third fin terminates at the interface between the first region and the second region.

[0038] In some embodiments, the semiconductor structure further includes a second non-rectangular device region. In some implementations, the second non-rectangular device region is a mirror image of the first non-rectangular device region. In some instances, the first region further includes a first plurality of gate structures extending over the first fin, the second fin, and the third fin along a second direction perpendicular to the first direction, and the second region further includes a second plurality of gate structures extending over the fourth fin and the fifth fin along the second direction. In some embodiments, each of the first plurality of gate structures is shorter than each of the second plurality of gate structures. In some instances, the second non-rectangular device region further includes a third region having a sixth fin, a seventh fin, and an eighth fin extending along the first direction; and a fourth region adjacent to the third region. The fourth region includes a ninth fin and a tenth fin extending along the first direction. In some implementations, the second region further includes a second plurality of gate structures extending over the fourth fin and the fifth fin along a second direction perpendicular to the first direction, and the second plurality of gate structures extending over the ninth fin and the tenth fin. In some instances, the semiconductor structure may further include a gate dicing member disposed between the first region and the third region, and the third region is a mirror image of the first region relative to the gate dicing member. In some instances, the first region further includes a plurality of first gate structures extending over the first fin, the second fin, and the third fin along a second direction perpendicular to the first direction. The plurality of gate structures terminate at the gate dicing member.

[0039] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a semiconductor substrate; a first dual-fin device region located above the semiconductor substrate; and a second dual-fin device region located above the semiconductor substrate. The first dual-fin device region includes: a first fin; and a second fin spaced apart from the first fin by a distance. The second dual-fin device region includes: a third fin spaced apart from the second fin by at least four times the distance; and a fourth fin spaced apart from the third fin by the distance. The portion of the semiconductor substrate located between the second fin and the third fin is substantially flat.

[0040] In some embodiments, the portion of the semiconductor substrate does not include fin residue. In some embodiments, the semiconductor structure may further include: a plurality of gate structures extending over and surrounding the first, second, third, and fourth fins. In some implementations, the semiconductor structure may further include: a first 3-fin device region adjacent to the first dual-fin device region. The first 3-fin device region includes: a fifth fin disposed over the semiconductor substrate and aligned with the first fin; a sixth fin disposed over the semiconductor substrate and aligned with the second fin; and a seventh fin disposed over the semiconductor substrate and spaced apart from the sixth fin. In some implementations, the semiconductor structure may further include: a second 3-fin device region adjacent to the second dual-fin device region. The second 3-fin device region includes: an eighth fin disposed over the semiconductor substrate and aligned with the third fin; a ninth fin disposed over the semiconductor substrate and aligned with the fourth fin; and a tenth fin disposed over the semiconductor substrate and spaced apart from the ninth fin. In some instances, the semiconductor structure may further include: a gate dicing member disposed between the first 3-fin device region and the second 3-fin device region. In some embodiments, the gate dicing component does not extend between the first dual-fin device region and the second dual-fin device region.

[0041] In another exemplary aspect, the present invention relates to a method. The method includes: depositing a first hard mask layer over a substrate; depositing a second hard mask layer over the first hard mask layer; forming a plurality of spacers over the second hard mask layer; depositing an underlayer over the plurality of spacers and the second hard mask layer; depositing a third hard mask layer over the underlayer; patterning the third hard mask layer to form a patterned third hard mask layer disposed directly over a first portion of the plurality of spacers but not directly over a second portion of the plurality of spacers; forming a patterned photoresist layer over the patterned third hard mask; using the patterned third hard mask layer and the patterned photoresist layer as an etch mask to pattern the underlayer such that the patterned underlayer covers the first portion of the plurality of spacers, and removing the second portion of the plurality of spacers; removing the underlayer to expose the first portion of the plurality of spacers; and after removing the underlayer, using the first portion of the plurality of spacers as an etch mask to pattern the substrate to form a plurality of fin elements.

[0042] In some embodiments, the underlying layer completely covers the first portion of the plurality of spacers. In some implementations, removing the underlying layer includes a wet cleaning process. In some instances, the method may further include selectively removing portions of the plurality of fin elements after the patterning of the substrate.

[0043] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: A first non-rectangular device region includes: a first region including a first fin, a second fin, and a third fin extending along a first direction; and a second region adjacent to the first region, the second region including a fourth fin and a fifth fin extending along the first direction, wherein the first region further includes a first plurality of gate structures extending above the first fin, the second fin, and the third fin along a second direction perpendicular to the first direction. The semiconductor structure further includes a second non-rectangular device region, which in turn includes: a third region comprising a sixth, seventh, and eighth fin extending along the first direction; and a fourth region adjacent to the third region, the fourth region comprising a ninth and tenth fin extending along the first direction; and a second plurality of gate structures extending along the second direction above the sixth, seventh, and eighth fins. Wherein, the first fin is aligned with the fourth fin, and the second fin is aligned with the fifth fin. The third fin terminates at the interface between the first region and the second region. Each of the first plurality of gate structures and each of the second plurality of gate structures extends along the second direction and terminates at a gate dicing member and is connected to the gate dicing member, wherein the gate dicing member is located between the first region and the third region.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure is a ring oscillator.

3. The semiconductor structure of claim 2, wherein, The second non-rectangular device area is a mirror image of the first non-rectangular device area.

4. The semiconductor structure of claim 1, wherein, The second region also includes a third plurality of gate structures extending over the fourth and fifth fins along the second direction.

5. The semiconductor structure of claim 4, wherein, Each of the first plurality of gate structures is shorter than each of the third plurality of gate structures.

6. The semiconductor structure of claim 4, wherein, The third plurality of gate structures extend above the ninth and tenth fins in the fourth region.

7. The semiconductor structure according to claim 6, wherein The gate dicing component may be a single layer or multiple layers.

8. The semiconductor structure according to claim 6, wherein, The gate cutting component is disposed between the first region and the third region. The third region is a mirror image of the first region relative to the gate dicing component.

9. The semiconductor structure according to claim 8, wherein The gate dicing component includes silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, zinc oxide, titanium oxide, zirconium oxide, and hafnium oxide.

10. A semiconductor structure, comprising: Semiconductor substrate; A first dual-fin device region is located above the semiconductor substrate, and the first dual-fin device region includes: a first fin; and a second fin spaced apart from the first fin; and... A second dual-fin device region is located above the semiconductor substrate, the second dual-fin device region comprising: a third fin spaced at least four times the distance from the second fin; and a fourth fin spaced from the third fin; The source / drain components extend continuously above the first fin, the second fin, the third fin, and the fourth fin. The portion of the semiconductor substrate located between the second fin and the third fin is flat.

11. The semiconductor structure of claim 10, wherein, The portion of the semiconductor substrate does not include fin residue.

12. The semiconductor structure according to claim 10, further comprising: Multiple gate structures extend above and surround the first fin, the second fin, the third fin, and the fourth fin.

13. The semiconductor structure according to claim 10, further comprising: The first three-fin device region is adjacent to the first dual-fin device region, and the first three-fin device region includes: The fifth fin is disposed above the semiconductor substrate and aligned with the first fin. The sixth fin is disposed above the semiconductor substrate and aligned with the second fin, and The seventh fin is disposed above the semiconductor substrate and spaced apart from the sixth fin by the interval.

14. The semiconductor structure according to claim 13, further comprising: The second 3-fin device region is adjacent to the second dual-fin device region, and the second 3-fin device region includes: The eighth fin is disposed above the semiconductor substrate and aligned with the third fin. A ninth fin is disposed above the semiconductor substrate and aligned with the fourth fin; and The tenth fin is disposed above the semiconductor substrate and spaced apart from the ninth fin by the interval.

15. The semiconductor structure according to claim 14, further comprising: A gate dicing component is disposed between the first 3-fin device region and the second 3-fin device region.

16. The semiconductor structure of claim 15, wherein, The gate dicing component does not extend between the first dual-fin device region and the second dual-fin device region.

17. A method for forming a semiconductor structure, comprising: A first hard mask layer is deposited over the substrate; A second hard mask layer is deposited over the first hard mask layer; Multiple spacers are formed above the second hard mask layer; An underlayer is deposited over the plurality of spacers and the second hard mask layer; A third hard mask layer is deposited on top of the underlying layer; The third hard mask layer is patterned to form a patterned third hard mask layer disposed directly above the first portion of the plurality of spacers, rather than the second portion of the plurality of spacers; A patterned photoresist layer is formed over the patterned third hard mask; The patterned third hard mask layer and the patterned photoresist layer are used as etching masks to pattern the bottom layer, such that the patterned bottom layer covers the first portion of the plurality of spacers and removes the second portion of the plurality of spacers; Remove the underlying layer to expose the first portion of the plurality of spacers; as well as After removing the underlying layer, the first portion of the plurality of spacers is used as an etching mask to pattern the substrate to form a plurality of fin elements.

18. The method of claim 17, wherein, The bottom layer completely covers the first portion of the plurality of spacers.

19. The method of claim 17, wherein, Removing the underlying layer includes a wet cleaning process.

20. The method of claim 17, further comprising: After the substrate is patterned, portions of the plurality of fin elements are selectively removed.

Images