A pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof

Abstract

The present invention relates to a pad impedance optimization structure in an FCBGA substrate, comprising: one or more layers of cavities located directly above or below a BGA pad, wherein the cavity is a blank area containing no metal in one or more metal wiring layers directly opposite the BGA pad; and a plurality of metal strips extending from the metal wiring layer to the cavity.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof. Background Art

[0002] With the increasing demand for high-density, high-speed SiP (System in Package) integration, high-speed signals face numerous impedance discontinuities within the SiP, further highlighting the issue of impedance matching within microsystems. For example, the ball pads, vias, and via-pads of FCBGA (Flip Chip Ball Grid Array) substrates create impedance discontinuities in high-speed pathways. These impedance discontinuities can lead to poor transmission performance. Therefore, when designing high-speed, high-density system-level packages, it is important to utilize appropriate structures to minimize the impact of impedance discontinuities on transmission performance, improve high-speed signal transmission performance, and ensure stable system functionality.

[0003] Currently, the primary approach to improving high-speed, high-density SiP impedance discontinuities is to reduce the impedance variation at the discontinuity. For example, for vias, common methods for reducing via impedance discontinuities include adopting a padless process, selecting a routing method, and optimizing the anti-pad diameter. For pads, which are impedance discontinuities, current approaches primarily involve adjusting dielectric thickness and hollowing out the ground plane directly above and below the pad. These methods can reduce the distributed capacitance of the pad. However, within the limited range of dielectric thickness adjustment, this type of pad impedance discontinuity requires hollowing out the multiple layers of power / ground planes directly above and below the pad. Figure 1 FIG. 1 shows an impedance optimization structure with a hollowed-out top portion of a pad in the prior art. Figure 1 As shown, the multi-layer power / ground plane 40 directly above / below the pad 30 is hollowed out.

[0004] Although the hollowing process can optimize the electrical performance of the transmission structure, for the optimized structure that requires hollowing out multiple layers of power / ground planes directly above / below the large pad structure, its optimized structure of continuous multi-layer large-area hollowing will have more serious preparation problems for the preparation process of the FCBGA substrate, affecting the reliability of the final product. Summary of the Invention

[0005] The task of the present invention is to provide a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof. The pad impedance optimization structure can optimize the impedance at the BGA pad while playing a supporting role, preventing the inconsistent dielectric pressing thickness during the pressing of the ABF thin composite material and the presence of gaps between multiple layers of ABF thin composite materials.

[0006] In a first aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a pad impedance optimization structure in an FCBGA substrate, comprising:

[0007] One or more layers of voids located directly above or below a BGA pad, where a void is a blank area containing no metal in one or more metal wiring layers directly opposite the BGA pad; and

[0008] Multiple metal strips extend from the metal wiring layer to the cavity.

[0009] Furthermore, the multiple metal strips located in the same layer are connected to each other or not connected to each other.

[0010] Furthermore, the diameter of the cavity is 600 μm-1000 μm.

[0011] Furthermore, the length of the metal strip is 300 μm-1000 μm, and the width is 30 μm-70 μm.

[0012] Furthermore, the pad impedance optimization structure and the metal wiring layer are formed simultaneously.

[0013] In a second aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a method for manufacturing a pad impedance optimization structure in an FCBGA substrate, comprising:

[0014] The second metal plate, the ABF thin composite material, the first substrate, the ABF thin composite material, and the second metal plate are sequentially stacked from top to bottom and pressed together;

[0015] removing the second metal plate;

[0016] Making a blind hole penetrating the ABF thin composite material, and filling the blind hole with metal to form a second conductive through-hole, while forming a first metal layer on the surface of the ABF thin composite material; and

[0017] The first metal layer is etched to form a second metal wiring layer, and at the same time, a pad impedance optimization structure is formed in an area facing the pad, wherein the pad impedance optimization structure is a cavity with a metal strip.

[0018] Furthermore, the ABF thin composite material pressing step is repeated multiple times until the pad impedance optimization structure step is formed, thereby obtaining multiple layers of cavities with metal strips.

[0019] Furthermore, the plurality of metal strips located on the same layer are connected to each other or are not connected to each other; and / or

[0020] The metal strip has a length of 300 μm-1000 μm and a width of 30 μm-70 μm.

[0021] Furthermore, the area of the cavity is 1-1.67 times the area of the BGA pad.

[0022] The present invention has at least the following beneficial effects: the present invention discloses a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof, wherein the pad impedance optimization structure can optimize the impedance at the BGA pad while playing a supporting role, thereby preventing inconsistent dielectric pressing thickness and the presence of gaps between multiple layers of ABF thin composite materials during the pressing of the ABF thin composite material; the pad impedance optimization structure can avoid board explosion during the manufacture of the FCBGA substrate; the pad impedance optimization structure is formed simultaneously with the metal rewiring on the surface of the ABF thin composite material, without adding additional process steps, and is simple to operate and highly feasible. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0024] Figure 1 The figure shows an impedance optimization structure with a hollowed-out portion above a pad in the prior art;

[0025] Figure 2 A cross-sectional schematic diagram of a BGA pad upper structure according to the prior art is shown;

[0026] Figure 3 A schematic diagram of the structure of a BGA pad according to the prior art when the impedance is not optimized is shown;

[0027] Figure 4 The figure shows a TDR impedance simulation diagram of a BGA pad after small-area hollowing and impedance optimization according to the prior art;

[0028] Figure 5 A schematic diagram showing the optimization of BGA pad impedance by hollowing out a large area according to the prior art is shown;

[0029] Figure 6 The figure shows a TDR impedance simulation diagram of a BGA pad after large-area hollowing to optimize impedance according to the prior art;

[0030] Figure 7 A cross-sectional schematic diagram of a manufacturing process of an FCBGA substrate according to an embodiment of the present invention is shown;

[0031] Figure 8 A schematic diagram showing separation of an optimized structure of a BGA pad according to an embodiment of the present invention is shown;

[0032] Figure 9 A schematic diagram showing an optimized structure of a BGA pad according to an embodiment of the present invention; and

[0033] Figure 10 A TDR impedance simulation diagram of a BGA pad after structural optimization according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0035] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0036] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0037] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0038] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0039] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0041] Conventional technology for optimizing BGA pad impedance involves hollowing out the metal directly above and below the BGA pad during fabrication of the FCBGA substrate. Fabricating a multi-layer FCBGA substrate requires multiple laminations of thin ABF composite material and the creation of metal wiring layers on the surface of the ABF composite material. Conventional BGA pad impedance optimization methods result in inconsistent dielectric thickness during these multiple laminations, making it impossible to ensure uniformity in the thickness of the electroplated metal on the ABF composite material. Gaps between multiple layers of ABF composite material can also cause cracking during subsequent heating.

[0042] Figure 2 A cross-sectional schematic diagram of a BGA pad upper structure according to the prior art is shown;

[0043] Figure 3 A schematic diagram showing the structure of a BGA pad according to the prior art when the impedance is not optimized; and

[0044] Figure 4 The figure shows a TDR impedance simulation diagram of a BGA pad after impedance optimization by hollowing out a small area according to the prior art.

[0045] like Figure 2 and Figure 3 As shown, above the BGA pad 101 are the second ABF thin composite material 102, the third metal wiring layer 103, the first ABF thin composite material 104, and the second metal wiring layer 105. The metal planes of the third metal wiring layer 103 and the second metal wiring layer 105 have a significant impact on the impedance of the BGA pad 101. Figure 4 As shown in FIG. 1 , if the metal planes of the third metal wiring layer 103 and the second metal wiring layer 105 above the BGA pad 101 are hollowed out with a diameter of 200 μm, the TDR (time domain reflectometer) impedance value of the BGA pad 101 is at a relatively low level. High-speed signals are easily reflected at the impedance mismatch point, and the transmission performance of the BGA pad cannot be guaranteed. The simulation results show that the impedance value at the BGA pad is only 39.27Ω, which is -21.4% away from the standard 50Ω impedance.

[0046] Figure 5 A schematic diagram showing the optimization of BGA pad impedance by hollowing out a large area according to the prior art is shown; Figure 6 The figure shows a TDR impedance simulation diagram of a BGA pad after large-area hollowing to optimize impedance according to the prior art.

[0047] like Figure 5 and Figure 6As shown, if the metal plane of the third metal wiring layer 103 and the second metal wiring layer 105 above the BGA pad 101 is hollowed out with a diameter of 800μm, the TDR impedance value of the BGA pad 101 can be maintained at around 50Ω, which is a good improvement for the impedance mismatch that is prone to occur at this location for high-speed signals, and its transmission performance is guaranteed. Simulation results show that the impedance value at the BGA pad can reach 48.68Ω, with an error of only -2.6% from the standard 50Ω impedance. However, this large-area hollowing process will cause serious process problems in the ABF thin composite material lamination step during the FCBGA substrate manufacturing process. Because there are large areas of metal layer missing continuously, the dielectric has uneven lamination thickness during lamination, which leads to uneven metal layer in the subsequent electroplating process. It is even possible that the large area of metal layer missing will cause voids to form between the ABF thin composite materials during lamination, and may even cause board explosion.

[0048] Therefore, it is necessary to improve this impedance optimization structure with serious preparation problems and propose an optimized structure that is both manufacturable and can guarantee the transmission performance of the BGA substrate to a certain extent.

[0049] Figure 7 A cross-sectional schematic diagram of a manufacturing process of an FCBGA substrate according to an embodiment of the present invention is shown; Figure 8 A schematic diagram showing separation of an optimized structure of a BGA pad according to an embodiment of the present invention is shown; Figure 9 A schematic diagram showing an optimized structure of a BGA pad according to an embodiment of the present invention is shown; Figure 10 A TDR impedance simulation diagram of a BGA pad after structural optimization according to an embodiment of the present invention is shown.

[0050] like Figure 7 As shown, a method for manufacturing an FCBGA substrate includes:

[0051] In step 1 , first metal plates 202 are covered on the front and back surfaces of a first substrate 201 .

[0052] In step 2, a first through hole 203 penetrating the first substrate 201 and the first metal plate 202 is formed by etching.

[0053] In step 3, metal is filled into the first through hole 203 by electroplating, chemical plating, deposition, etc. to form the first conductive through hole 204.

[0054] In step 4, the first metal plate 202 is etched to form a first wiring layer 205 on the front and back surfaces of the first substrate 201. The first metal wiring layer 205 is electrically connected to the first conductive via 204.

[0055] In step 5, the second metal plate 206, the ABF thin composite material 207, the first substrate 201, the ABF thin composite material 207, and the second metal plate 206 are stacked in order from top to bottom and pressed together, for example, by using a vacuum pressing process.

[0056] In step 6, the second metal plate 206 is removed by a subtractive copper process.

[0057] In step 7 , a blind hole 208 is formed through the ABF thin composite material 207 to expose a portion of the first metal wiring layer 205 .

[0058] In step 8 , metal is filled in the blind hole 208 by electroplating, chemical plating, deposition, etc. to form a second conductive via 209 , and a first metal layer 210 is formed on the surface of the first ABF thin composite material 207 .

[0059] In step 9 , the first metal layer 210 is etched to form a second metal wiring layer 211 . The second metal wiring layer 211 is electrically connected to the first metal wiring layer 205 through the second conductive via 209 .

[0060] In step 10, a solder resist layer 212 covering the second metal wiring layer 211 is formed by coating, deposition, or the like.

[0061] In step 11, a portion of the solder resist layer on the second metal wiring layer 211 is removed to expose a portion of the second metal wiring layer 211 as a BGA pad, and a protective layer is applied to the exposed surface of the second metal wiring layer 211, such as gold plating, nickel-palladium gold plating, or organic solder paste (OSP).

[0062] Repeat steps 5 to 9 to perform multiple ABF thin composite material lamination, blind hole production, and metal wiring layer production, so that multiple ABF thin composite materials are stacked and interconnected second metal wiring layers to Nth metal wiring layers are obtained.

[0063] Existing methods for optimizing BGA pad impedance hollow out the metal plane of the metal wiring layer directly above the BGA pad. This continuous, large area of missing metal leads to uneven thickness during lamination of the thin ABF composite material. This can cause uneven metal layers during the subsequent electroplating process and even lead to voids during the lamination of the thin ABF composite materials. The present invention proposes a BGA impedance optimization structure that optimizes BGA impedance while also preventing uneven thickness and voids during lamination of the thin ABF composite materials.

[0064] like Figure 8 and Figure 9As shown, when fabricating the second metal wiring layer corresponding to one or more ABF thin composite materials, a BGA pad impedance optimization structure with metal strips is fabricated directly above / below the subsequent BGA pad 101. This BGA pad impedance optimization structure includes a cavity with a diameter of 600μm-1000μm directly opposite the BGA pad 101. Multiple metal strips 106 extend from the third metal wiring layer 103 and the second metal wiring layer 105 into the cavity. The dimensions of the BGA pad 101 are 500μm-800μm. In other words, the cavity area is 1-1.67 times the size of the BGA pad 101. The cavity is filled with a dielectric. Multiple metal strips 106 on the same layer are symmetrically distributed and may or may not be connected to each other. Preferably, the number of metal strips 106 is an even number. The length of the metal strips 106 is 300μm-1000μm, and the width is 30μm-70μm. When multiple metal wiring layers are present above and below the BGA pad 101, a BGA pad impedance optimization structure with metal strips is provided at corresponding locations on each second metal wiring layer. The metal strips of each BGA pad impedance optimization structure are positioned at different angles. This BGA pad impedance optimization structure with metal strips is formed simultaneously with the fabrication of the metal wiring layers, without adding any additional process steps.

[0065] like Figure 10 As shown, a BGA pad impedance optimization structure with metal strips is set up. For example, there are two layers of ABF thin composite material and two layers of second metal wiring above the BGA pad. The cavity diameter is selected to be 800μm, and the four metal strips are selected. The TDR impedance value of the BGA pad with a diameter of 600μm can be maintained at around 50Ω. The impedance mismatch that is prone to occur at this location for high-speed signals is greatly improved, and its transmission performance is guaranteed. The simulation results show that the impedance value at the BGA pad can reach 46.42Ω, with an error of only -7.2% from the standard 50Ω impedance. In addition, this optimized structure improves the problems existing in the ABF thin composite material pressing process in the FCBGA substrate preparation process of the conventional optimized structure, which can effectively avoid the occurrence of board explosion, better control the consistency of the dielectric pressing thickness, and ensure the uniformity of the electroplated metal thickness.

[0066] The present invention has at least the following beneficial effects: the present invention discloses a pad impedance optimization structure in an FCBGA substrate and a manufacturing method thereof, wherein the pad impedance optimization structure can optimize the impedance at the BGA pad while playing a supporting role, thereby preventing inconsistent dielectric pressing thickness and the presence of gaps between multiple layers of ABF thin composite materials during the pressing of the ABF thin composite material; the pad impedance optimization structure can avoid board explosion during the manufacture of the FCBGA substrate; the pad impedance optimization structure is formed simultaneously with the metal rewiring on the surface of the ABF thin composite material, without adding additional process steps, and is simple to operate and highly feasible.

[0067] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A method for manufacturing a pad impedance optimization structure in an FCBGA substrate, comprising: The second metal plate, the ABF thin composite material, the first substrate, the ABF thin composite material, and the second metal plate are sequentially stacked from top to bottom and pressed together; removing the second metal plate; Making a blind hole through the ABF thin composite material, and filling the blind hole with metal to form a second conductive through-hole, while forming a first metal layer on the surface of the ABF thin composite material; as well as The first metal layer is etched to form a second metal wiring layer, and at the same time, a pad impedance optimization structure is formed in an area facing the pad, wherein the pad impedance optimization structure is a cavity with a metal strip.

2. The method for manufacturing a pad impedance optimization structure in an FCBGA substrate according to claim 1, wherein: The ABF thin composite material pressing step is repeated multiple times until the pad impedance optimization structure step is formed, thereby obtaining multiple layers of cavities with metal strips.

3. The method for manufacturing a pad impedance optimization structure in an FCBGA substrate according to claim 1, wherein: Multiple metal strips on the same layer may or may not be connected to each other; and / or The metal strip has a length of 300 μm-1000 μm and a width of 30 μm-70 μm.

4. The method for manufacturing a pad impedance optimization structure in an FCBGA substrate according to claim 1, wherein: The area of the cavity is 1-1.67 times the area of the BGA pad.

5. A pad impedance optimization structure in an FCBGA substrate formed by the method for manufacturing a pad impedance optimization structure in an FCBGA substrate according to any one of claims 1 to 4, comprising: One or more layers of voids located directly above or below a BGA pad, where a void is a blank area containing no metal in one or more metal wiring layers directly opposite the BGA pad; as well as Multiple metal strips extend from the metal wiring layer to the cavity.

6. The pad impedance optimization structure in the FCBGA substrate according to claim 5, characterized in that: The plurality of metal strips located in the same layer are connected to each other or are not connected to each other.

7. The pad impedance optimization structure in the FCBGA substrate according to claim 5, characterized in that: The diameter of the cavity is 600 μm-1000 μm.

8. The pad impedance optimization structure in the FCBGA substrate according to claim 5, characterized in that: The metal strip has a length of 300 μm-1000 μm and a width of 30 μm-70 μm.

9. The pad impedance optimization structure in the FCBGA substrate according to claim 5, characterized in that: The pad impedance optimization structure is formed simultaneously with the metal wiring layer.

10. The pad impedance optimization structure in the FCBGA substrate according to claim 5, characterized in that: The area of the cavity is 1-1.67 times the area of the BGA pad.

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