Semiconductor device including through-hole structures

Abstract

A semiconductor device can be provided, including: a semiconductor substrate; an integrated circuit layer on the semiconductor substrate; first to nth metal wiring layers (where n is a positive integer), sequentially stacked on the semiconductor substrate and the integrated circuit layer; a first through-hole structure extending in a vertical direction from a first via connection metal wiring layer to the semiconductor substrate and through the semiconductor substrate, the first via connection metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer; and a second through-hole structure separate from the first through-hole structure, extending in a vertical direction from a second via connection metal wiring layer to the semiconductor substrate and through the semiconductor substrate, the second via connection metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0038273, filed with the Korean Intellectual Property Office on March 24, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to semiconductor devices including through-hole structures. Background Technology

[0004] As electronic devices process increasing amounts of data, there is a growing need for semiconductor devices with high capacity and high bandwidth. To address this, techniques have been proposed that use through-hole structures (e.g., through-silicon vias (TSVs)) as through electrodes, achieved by forming tiny holes in the semiconductor device.

[0005] When using via structures as electrodes, the resistance of the via structure needs to be adjusted. Furthermore, when an integrated circuit layer (e.g., a transistor) is arranged near the via structure, the via structure must mitigate or prevent degradation of the electrical performance of the integrated circuit layer (e.g., the transistor). Summary of the Invention

[0006] The present invention provides a semiconductor device including a through-hole structure, which can adjust resistance and reduce or prevent degradation of the electrical performance of the peripheral integrated circuit layer.

[0007] According to one aspect of the present invention, a semiconductor device includes: a semiconductor substrate; an integrated circuit layer on the semiconductor substrate; first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer; a first via structure extending vertically from the first via-connected metal wiring layer toward and through the semiconductor substrate, the first via-connected metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer; and a second via structure separate from the first via structure, extending vertically from the second via-connected metal wiring layer toward and through the semiconductor substrate, the second via-connected metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer.

[0008] According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate including a first surface and a second surface opposite to the first surface; a front-end layer on the first surface of the semiconductor substrate, the front-end layer including an integrated circuit layer; a back-end layer on the front-end layer, the back-end layer including first to nth metal wiring layers (where n is a positive integer) sequentially stacked on and electrically connected to the integrated circuit layer; a first via structure extending vertically from the first via-connected metal wiring layer toward the semiconductor substrate and passing through the back-end layer, the front-end layer, and the region between the first surface and the second surface of the semiconductor substrate, the first via-connected metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer; and a second via structure separate from the first via structure, extending vertically from the second via-connected metal wiring layer toward the semiconductor substrate and passing through the back-end layer, the front-end layer, and the region between the first surface and the second surface of the semiconductor substrate, the second via-connected metal wiring layer being one of the second to nth metal wiring layers other than the first metal wiring layer.

[0009] According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate; a front-end layer on the semiconductor substrate, the front-end layer including an integrated circuit layer, an interlayer insulating layer configured to insulate the integrated circuit layer, and a contact plug layer in the interlayer insulating layer and electrically connected to the integrated circuit layer; a back-end layer on the front-end layer, the back-end layer including first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the front-end layer and electrically connected to the integrated circuit layer, a plurality of wiring insulating layers configured to insulate the first to nth metal wiring layers from each other, and a plurality of wiring via layers in the plurality of wiring insulating layers and configured to connect the first to nth metal wiring layers; and a first through-hole structure extending vertically from... A first via-connected metal wiring layer extends toward the semiconductor substrate and passes through multiple wiring insulating layers, interlayer insulating layers, and the semiconductor substrate. The first via-connected metal wiring layer is one of the second to nth metal wiring layers other than the first metal wiring layer. A second through-hole structure is separate from the second through-hole structure and extends vertically from the second via-connected metal wiring layer toward the semiconductor substrate, passing through multiple wiring insulating layers, interlayer insulating layers, and the semiconductor substrate. The second via-connected metal wiring layer is one of the second to nth metal wiring layers other than the first metal wiring layer. The first through-hole structure is located in a first exclusion region on one side of the integrated circuit layer, while the second through-hole structure is located in a second exclusion region on the other side of the integrated circuit layer. Attached Figure Description

[0010] Some exemplary embodiments of the inventive concept will become clearer from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0012] Figure 2 yes Figure 1 An enlarged view of region EN1;

[0013] Figure 3 It is used to describe Figure 1 A plan view showing the arrangement relationship between the integrated circuit layer and the through-hole structure;

[0014] Figure 4 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0015] Figure 5 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0016] Figure 6 It is used to describe Figure 5 A plan view showing the arrangement relationship between the integrated circuit layer and the through-hole structure;

[0017] Figure 7 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0018] Figure 8 It is used to describe Figure 7 A plan view showing the arrangement relationship between the integrated circuit layer and the through-hole structure;

[0019] Figure 9 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0020] Figure 10 It is used to describe Figure 9 A plan view showing the arrangement relationship between the integrated circuit layer and the through-hole structure;

[0021] Figure 11 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment;

[0022] Figure 12 It is used to describe Figure 11 A plan view showing the arrangement relationship between the integrated circuit layer and the through-hole structure;

[0023] Figures 13 to 16 It is used to describe Figure 1 A cross-sectional view of a semiconductor device manufacturing method;

[0024] Figure 17 This is a block diagram illustrating the configuration of a semiconductor chip including a semiconductor device according to an example embodiment;

[0025] Figure 18This is a block diagram illustrating the configuration of a semiconductor chip including semiconductor devices according to an example embodiment;

[0026] Figure 19 This is a block diagram illustrating the configuration of a semiconductor package including semiconductor devices according to an example embodiment;

[0027] Figure 20 This is an equivalent circuit diagram of a static random access memory (SRAM) cell included in a semiconductor device according to an example embodiment;

[0028] Figure 21 This illustrates a cross-sectional view of a semiconductor package including a semiconductor device according to an example embodiment; and

[0029] Figure 22 and Figure 23 This is a schematic diagram illustrating a semiconductor package according to some example embodiments. Detailed Implementation

[0030] In the following description, some exemplary embodiments will be described in detail with reference to the accompanying drawings. These exemplary embodiments may be implemented as individual examples, or by combining two or more exemplary embodiments. Therefore, they should not be construed as limiting the inventive concept to the disclosed embodiments.

[0031] As used herein, the singular forms “a,” “an,” and “the” are intended to further include the plural forms unless the context explicitly indicates otherwise. Throughout this document, the accompanying drawings are exaggerated and shown for clarity of description of the embodiments.

[0032] Although the terms “identical,” “equal,” or “the same” are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0033] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) around said numerical values. Furthermore, when the terms “approximately” and “substantially” are used in conjunction with geometry, it is intended that no precision of the geometry is required, but rather a tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “approximately” or “substantially”, it should be understood that these values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the numerical values ​​or shapes.

[0034] Figure 1 This is a cross-sectional view used to describe the semiconductor device 1 according to an example embodiment. Figure 2yes Figure 1 An enlarged view of region EN1, and Figure 3 It is used to describe Figure 1 A plan view showing the arrangement of integrated circuit layers and via structures.

[0035] For example, semiconductor device 1 may include semiconductor substrate 10. Semiconductor substrate 10 may form a substrate-level layer SUL. Semiconductor substrate 10 may be configured with a semiconductor wafer. Semiconductor substrate 10 may include group IV materials or group III-V compounds. Semiconductor substrate 10 may be configured with a single-crystal wafer (e.g., a silicon wafer).

[0036] Semiconductor substrate 10 is not limited to single-crystal wafers and may include various wafers, such as epitaxial wafers, polished wafers, annealed wafers, and silicon-on-insulator (SOI) wafers. An epitaxial wafer may represent a wafer on which crystalline material is grown on a single-crystal silicon substrate. Semiconductor substrate 10 may include a silicon substrate. Semiconductor substrate 10 may include a first surface 10a and a second surface 10b opposite to the first surface 10a.

[0037] Semiconductor device 1 may include an integrated circuit layer 14. The integrated circuit layer 14 may be formed on a first surface 10a of the semiconductor substrate 10. The integrated circuit layer 14 may include multiple circuit elements (e.g., transistors, capacitors, and / or registers). Based on the structure of the integrated circuit layer 14, semiconductor device 1 can be used as a memory device or a logic device. For example, the memory device may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM). The structure of the integrated circuit layer 14 is well known and does not limit the inventive concept.

[0038] The first lower portion of the first surface 10a of the semiconductor substrate 10, where the integrated circuit layer 14 is formed, can be an active region, while the second lower portion of the first surface 10a of the semiconductor substrate 10, where the integrated circuit layer 14 is not formed, can be a passive region. For convenience, Figure 1 The impurity-doped regions (e.g., source / drain regions and well regions) formed beneath the first surface 10a of the semiconductor substrate 10 are not shown. For convenience, Figure 1 An isolation region formed beneath the first surface 10a of the semiconductor substrate 10 is not shown.

[0039] An interlayer insulating layer 12 may be formed on the semiconductor substrate 10 and the integrated circuit layer 14. The interlayer insulating layer 12 may include a silicon oxide layer. A contact plug layer 16 electrically connected to the integrated circuit layer 14 may be formed in the interlayer insulating layer 12. The contact plug layer 16 may include a metal layer (e.g., a tungsten layer).

[0040] The integrated circuit layer 14, the interlayer insulating layer 12, and the contact plug layer 16, each formed on the semiconductor substrate 10, can constitute the front-end layer FEOL. In terms of manufacturing process, the front-end layer FEOL can be referred to as the front end of the production line.

[0041] Semiconductor device 1 may include multiple metal wiring layers 20. Each metal wiring layer 20 may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). The metal wiring layers 20, sequentially electrically connected to each other, may be formed on the semiconductor substrate 10 and the integrated circuit layer 14. The metal wiring layers 20 may include a first metal wiring layer 20a, a second metal wiring layer 20b, a third metal wiring layer 20c, a fourth metal wiring layer 20d, a fifth metal wiring layer 20e, and a sixth metal wiring layer 20f. The sixth metal wiring layer 20f may be the uppermost metal wiring layer.

[0042] In the example embodiment, for convenience, only the first to sixth metal wiring layers 20 are shown, but the first to nth (where n is a positive integer) metal wiring layers can be formed on the semiconductor substrate 10 and the integrated circuit layer 14. Here, the nth metal wiring layer can be the uppermost metal wiring layer. In some example embodiments, n can be a positive integer of 30 or less in the first to nth metal wiring layers.

[0043] Semiconductor device 1 may include multiple wiring insulating layers 18. The wiring insulating layers 18 may insulate the first to sixth metal wiring layers 20. The wiring insulating layers 18 may include silicon oxide layers. The wiring insulating layers 18 may include a first wiring insulating layer 18a, a second wiring insulating layer 18b, a third wiring insulating layer 18c, a fourth wiring insulating layer 18d, a fifth wiring insulating layer 18e, and a sixth wiring insulating layer 18f.

[0044] Semiconductor device 1 may include a plurality of wiring via layers 22. The wiring via layers 22 can electrically connect the metal wiring layers 20 to each other. The wiring via layers 22 may include metal layers (e.g., copper, aluminum, or tungsten layers). The wiring via layers 22 may include a first wiring via layer 22a, a second wiring via layer 22b, a third wiring via layer 22c, a fourth wiring via layer 22d, a fifth wiring via layer 22e, and a sixth wiring via layer 22f.

[0045] The metal wiring layer 20, wiring insulation layer 18, and wiring via layer 22, each formed on the front-end layer FEOL, can constitute the back-end layer BEOL. In terms of manufacturing process, the back-end layer BEOL can be referred to as the back end of the production line.

[0046] Semiconductor device 1 may include a first through-hole structure 31. The first through-hole structure 31 may include a first through-silicon via (TSV) structure. The first through-hole structure 31 may include a signal transmission via structure or a power transmission via structure. The first through-hole structure 31 may be arranged to be separated from one side of integrated circuit layer 14 by a first pitch sp1. In some example embodiments, the first pitch sp1 may be from a few micrometers to tens of micrometers. In some example embodiments, the first pitch sp1 may be from about 1 micrometer to about 20 micrometers.

[0047] The first through-hole structure 31 may have a first diameter d1. The first diameter d1 may be a first critical dimension CD1. In some example embodiments, the first diameter d1 may be from a few micrometers to tens of micrometers. In some example embodiments, the first diameter d1 may be from about 1 micrometer to about 15 micrometers.

[0048] The first via structure 31 can extend vertically from the first via-connected metal wiring layer VL1 to the semiconductor substrate 10 and can pass through the semiconductor substrate 10. The first via-connected metal wiring layer VL1 is one of the second metal wiring layer 20b to the sixth metal wiring layer 20f. The first via-connected metal wiring layer VL1 may include a fourth metal wiring layer 20d.

[0049] The first via connection metal wiring layer VL1 may use, but is not limited to, a fourth metal wiring layer 20d, and may include one of the second metal wiring layers 20b to the sixth metal wiring layers 20f. The first via connection metal wiring layer VL1 may be located in the middle portion of the second metal wiring layers 20b to the sixth metal wiring layers 20f or in the middle portion of the back-end layer BEOL in the vertical direction (e.g., the Z direction).

[0050] Compared to the case where the first metal wiring layer 20a is used as the first via to connect the metal wiring layer VL1, the resistance of the first via structure 31 can be reduced when one of the second to sixth metal wiring layers 20b is used as the first via to connect the metal wiring layer VL1. Furthermore, the resistance of the first via structure 31 can be easily adjusted when one of the second to sixth metal wiring layers 20b is used as the first via to connect the metal wiring layer VL1.

[0051] The first via structure 31 can penetrate all of the first wiring insulating layer 18a to the third wiring insulating layer 18c constituting the back-end layer BEOL, the interlayer insulating layer 12 constituting the front-end layer FEOL, and the semiconductor substrate 10. The first via structure 31 can have a first height h1. In some example embodiments, the first height h1 can be tens of micrometers. In some example embodiments, the first height h1 can be about 50 micrometers to about 90 micrometers.

[0052] like Figure 1 and Figure 2 As shown, the first through-hole structure 31 may include a first via 24 formed in the back-end layer BEOL, the front-end layer FEOL and the semiconductor substrate 10, a first via insulating layer 28 formed on the inner wall of the first via 24, and a first via electrode 30 that buries (e.g., fills) the first via 24 in the first via insulating layer 28.

[0053] In other words, such as Figure 1 and Figure 2 As shown, the first through-hole structure 31 may include: a first via 24 passing through the entire first wiring insulating layer 18a to the third wiring insulating layer 18c, the interlayer insulating layer 12, and the semiconductor substrate 10; a first via insulating layer 28 formed on the inner wall of the first via 24; and a first via electrode 30 buried (e.g., filled) in the first via insulating layer 28. The first via insulating layer 28 may include a silicon oxide layer or a silicon nitride layer. The first via electrode 30 may include a first via blocking layer 30a and a first via metal layer 30b. The first via electrode 30 may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). The first via blocking layer 30a may include a blocking metal layer (e.g., tantalum (Ta) or titanium nitride (TiN)).

[0054] Semiconductor device 1 may include a second via structure 35. The second via structure 35 may include a second TSV structure. The second via structure 35 may include a signal transmission via structure or a power transmission via structure. The second via structure 35 may be arranged separately from the first via structure 31. The second via structure 35 may be arranged separately from the other side (e.g., the opposite side) of the integrated circuit layer 14 by a second pitch sp2. In some example embodiments, the second pitch sp2 may be from a few micrometers to tens of micrometers. In some example embodiments, the second pitch sp2 may be from about 1 micrometer to about 20 micrometers.

[0055] The second diameter d2 of the second through-hole structure 35 can be larger than the first diameter d1. The second diameter d2 can be a second critical dimension CD2. In some example embodiments, the second diameter d2 can be from a few micrometers to tens of micrometers. In some example embodiments, the second diameter d2 can be from about 1 micrometer to about 15 micrometers. When the second diameter d2 of the second through-hole structure 35 is larger than the first diameter d1 of the first through-hole structure 31, the resistance of the second through-hole structure 35 can be lower than the resistance of the first through-hole structure 31.

[0056] In some example embodiments, when the second diameter d2 of the second through-hole structure 35 is greater than the first diameter d1 of the first through-hole structure 31, the second through-hole structure 35 may include a power transmission via structure, while the first through-hole structure 31 may include a signal transmission via structure.

[0057] The second via structure 35 can extend vertically from the second via connection metal wiring layer VL2 to the semiconductor substrate 10 and can pass through the semiconductor substrate 10. The second via connection metal wiring layer VL2 is one of the second metal wiring layers 20b to the sixth metal wiring layer 20f. The second via connection metal wiring layer VL2 may include the sixth metal wiring layer 20f. The second via connection metal wiring layer VL2 may include the uppermost sixth metal wiring layer 20f.

[0058] The second via connection metal wiring layer VL2 can be a sixth metal wiring layer 20f, but is not limited to it, and can be any one of the second metal wiring layers 20b to the sixth metal wiring layer 20f. The second via connection metal wiring layer VL2 can be located in the middle portion of the second metal wiring layer 20b to the sixth metal wiring layer 20f or in the middle portion of the back-end layer BEOL in the vertical direction (e.g., the Z direction).

[0059] Compared to the case where the first metal wiring layer 20a is used as the second via connecting the metal wiring layer VL2, the resistance of the second via structure 35 can be reduced when one of the second metal wiring layers 20b to the sixth metal wiring layer 20f is used as the second via connecting the metal wiring layer VL2. Furthermore, the resistance of the second via structure 35 can be easily adjusted when one of the second metal wiring layers 20b to the sixth metal wiring layer 20f is used as the second via connecting the metal wiring layer VL2.

[0060] The second height h2 of the second through-hole structure 35 can be greater than the first height h1. In some example embodiments, the second height h2 can be tens of micrometers. In some example embodiments, the second height h2 can be about 50 micrometers to about 90 micrometers.

[0061] On the semiconductor substrate 10, the second via connection metal wiring layer VL2 can be arranged at a different level than the first via connection metal wiring layer VL1. In other words, the level of the first through-hole structure 31 can be different from the level of the second through-hole structure 35.

[0062] In some example embodiments, on the semiconductor substrate 10, the second via connection metal wiring layer VL2 may be disposed at a higher level than the first via connection metal wiring layer VL1. In other words, the level of the second via structure 35 may be higher than the level of the first via structure 31.

[0063] When the second via connection metal wiring layer VL2 is positioned at a higher level than the first via connection metal wiring layer VL1, the resistance of the second via structure 35 can be lower than the resistance of the first via structure 31. In other words, when the second height h2 of the second via structure 35 is greater than the first height h1 of the first via structure 31, the resistance of the second via structure 35 can be lower than the resistance of the first via structure 31.

[0064] The second through-hole structure 35 can pass through the first wiring insulation layer 18a to the fifth wiring insulation layer 18e constituting the back-end layer BEOL, the interlayer insulation layer 12 constituting the front-end layer FEOL, and the entire semiconductor substrate 10.

[0065] like Figure 1 As shown, the second via structure 35 may include a second via 26 formed in all back-end layer BEOL, front-end layer FEOL and semiconductor substrate 10, a second via insulating layer 32 formed on the inner wall of the second via 26, and a second via electrode 34 that buries (e.g., fills) the second via 26 in the second via insulating layer 32.

[0066] In other words, such as Figure 1 As shown, the second via structure 35 may include: a second via 26 passing through the entirety of the first wiring insulating layer 18a to the fifth wiring insulating layer 18e, the interlayer insulating layer 12, and the semiconductor substrate 10; a second via insulating layer 32 formed on the inner wall of the second via 26; and a second via electrode 34 buried (e.g., filled) in the second via insulating layer 32. Figure 2 As shown, the second via electrode 34 may include a via blocking layer.

[0067] This article will refer to Figure 3 Describe the arrangement relationship between integrated circuit layer 14, first through-hole structure 31 and second through-hole structure 35.

[0068] like Figure 3As shown, a first through-hole structure 31 can be formed in a first exclusion region KOZ1, which is disposed on one side of the integrated circuit layer 14. The first exclusion region KOZ1 can be a region where the integrated circuit layer 14 is not formed. The integrated circuit layer 14 can be formed near the first exclusion region KOZ1. As described above, the first through-hole structure 31 can have a first diameter d1. The first through-hole structure 31 can be arranged to be separated from one side of the integrated circuit layer 14 by a first spacing sp1.

[0069] The second through-hole structure 35 can be formed in the second exclusion region KOZ2, which is disposed on the other side (e.g., opposite side) of the integrated circuit layer 14. The area of ​​the second exclusion region KOZ2 can be the same as the area of ​​the first exclusion region KOZ1. The second exclusion region KOZ2 can be a region where the integrated circuit layer 14 is not formed.

[0070] The integrated circuit layer 14 can be formed near the second exclusion region KOZ2. As described above, the second diameter d2 of the second via structure 35 can be larger than the first diameter d1. The second via structure 35 can be arranged to be separated from the other side (e.g., the opposite side) of the integrated circuit layer 14 by a second spacing sp2.

[0071] Furthermore, the semiconductor device 1 may include an upper pad 33. The upper pad 33 may be formed on the back-end layer BEOL. The upper pad 33 may be electrically connected to the uppermost sixth metal wiring layer 20f among the first to sixth metal wiring layers 20.

[0072] In other words, the upper pad 33 can be electrically connected to the uppermost sixth metal wiring layer 20f of the first to sixth metal wiring layers 20 through the sixth wiring via layer 22f. According to some example embodiments, solder bumps as external connection terminals can be further formed on the upper pad 33.

[0073] According to some example embodiments, other semiconductor devices (not shown) may be stacked on and bonded to the upper pad 33. In this case, the upper pad 33 may be insulated by an upper protective insulating layer (not shown) formed on the sixth wiring insulating layer 18f.

[0074] According to some example embodiments, the semiconductor device 1 may include a lower pad 48. The lower pad 48 may be electrically connected to a first through-hole structure 31 and a second through-hole structure 35 in the bottom surface of the semiconductor substrate 10. The lower pad 48 may be insulated from the semiconductor substrate 10 by a lower protective insulating layer 46 disposed on the second surface 10b of the semiconductor substrate 10. The lower protective insulating layer 46 may include a silicon oxide layer or a silicon nitride layer.

[0075] The lower protective insulating layer 46 can form an insulating level layer INL on the second surface 10b of the semiconductor substrate 10. The first height h1 of the first via structure 31 can extend from the bottom surface of the lower pad 48 (e.g., the surface in contact with the insulating level layer INL) to the first via-connected metal wiring layer VL1. The second height h2 of the second via structure 35 (greater than the first height h1) can extend from the bottom surface of the lower pad 48 (e.g., the surface in contact with the insulating level layer INL) to the second via-connected metal wiring layer VL2.

[0076] According to some example embodiments, solder bumps serving as external connection terminals may be further formed on the lower pad 48. According to some example embodiments, other semiconductor devices (not shown) may be stacked on and bonded to the lower pad 48.

[0077] In the aforementioned semiconductor device 1, the first through-hole structure 31 can be connected to a first via-connected metal wiring layer VL1 located in the central portion or middle portion of the rear-end layer BEOL in the vertical direction (e.g., the Z direction), while the second through-hole structure 35 can be connected to a second via-connected metal wiring layer VL2 located in the central portion or middle portion of the rear-end layer BEOL in the vertical direction (e.g., the Z direction). The top surface of the first through-hole structure 31 and the top surface of the second through-hole structure 35 can be at different levels.

[0078] Therefore, the semiconductor device 1 can reduce or easily adjust its resistance by using a first via structure 31 and a second via structure 35, each connected to the center portion of the upper rear-end layer BEOL in the vertical direction (e.g., the Z direction) or each connected to the middle portion of the upper rear-end layer BEOL in the vertical direction (e.g., the Z direction). The semiconductor device 1 can adjust the first diameter d1 of the first via structure 31 and the second diameter d2 of the second via structure 35, and the resistance can be easily adjusted by using the first via structure 31 and the second via structure 35.

[0079] Furthermore, the semiconductor device 1 can adjust the first spacing sp1 and the second spacing sp2 between the first through-hole structure 31 and the second through-hole structure 35 and the integrated circuit layer 14, thereby mitigating or preventing the degradation of the electrical performance of the integrated circuit layer 14.

[0080] Figure 4 It is a cross-sectional view used to describe a semiconductor device according to an example embodiment.

[0081] In addition to further forming a redistribution layer 36, bump pads 42, and solder bumps 44, the semiconductor device 2 can be coupled with... Figures 1 to 3 The semiconductor device 1 is the same. Figure 4 In, with Figures 1 to 3 The same reference numerals refer to the same elements. Figure 4 In the text, the above references are briefly given or omitted. Figures 1 to 3 The given description.

[0082] Semiconductor device 2 may further include a redistribution layer RDL on the back-end layer BEOL on semiconductor substrate 10. According to some example embodiments, the redistribution layer RDL may be omitted. The redistribution layer RDL may include a redistribution layer 36 electrically connected to the sixth metal wiring layer 20f and the sixth wiring via layer 22f, and a redistribution insulating layer 38 formed on the redistribution layer 36.

[0083] The redistribution layer 36 may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). The redistribution insulating layer 38 may include a silicon oxide layer. In the semiconductor device 2, a bump pad 42 may be formed in a redistribution exposure via 40 that exposes the redistribution layer 36 in the redistribution insulating layer 38. Solder bumps 44, serving as external connection terminals, may be formed on the bump pad 42.

[0084] Semiconductor device 2 can reduce or adjust the resistance of each of the first via structure 31 and the second via structure 35, and improve wiring freedom by using a redistribution layer RDL.

[0085] Figure 5 This is a cross-sectional view used to describe the semiconductor device 3 according to the example embodiment, and Figure 6 It is used to describe Figure 5 A plan view showing the arrangement of integrated circuit layers and via structures.

[0086] Apart from the different dimensions and arrangement of the second through-hole structure 35-1, the semiconductor device 3 can be... Figures 1 to 3 Semiconductor devices 1 and Figure 4 The semiconductor device 2 is the same. Figure 5 and Figure 6 In, with Figures 1 to 4 The same reference numerals refer to the same elements. Figure 5 and Figure 6 In the text, the above references are briefly given or omitted. Figures 1 to 4 The given description.

[0087] Semiconductor device 3 may include a first through-hole structure 31 and a second through-hole structure 35-1. For example... Figure 5As shown, the second via structure 35-1 may include a second via 26-1 formed in the rear stage layer BEOL, the front stage layer FEOL and the semiconductor substrate 10, a first via insulating layer 32-1 formed on the inner wall of the second via 26-1, and a second via electrode 34-1 buried (e.g., filled) in the second via insulating layer 32.

[0088] The second diameter d3 of the second through-hole structure 35-1 can be the same as the first diameter d1 of the first through-hole structure 31. In some example embodiments, the first diameter d1 and the second diameter d3 can be from a few micrometers to tens of micrometers.

[0089] like Figure 6 As shown, a first through-hole structure 31 can be formed in a first exclusion region KOZ1, which is disposed on one side of the integrated circuit layer 14. A second through-hole structure 35-1 can be formed in a second exclusion region KOZ2, which is disposed on the other side (e.g., opposite side) of the integrated circuit layer 14.

[0090] like Figure 5 and Figure 6 As shown, the first through-hole structure 31 can be arranged to be separated from one side of the integrated circuit layer 14 by a first pitch sp1. The second through-hole structure 35-1 can be arranged to be separated from the other side (e.g., the opposite side) of the integrated circuit layer 14 by a second pitch sp3, which is the same as the first pitch sp1.

[0091] As described above, in semiconductor device 3, the resistance of the second through-hole structure 35-1 can be reduced or easily adjusted by adjusting the second diameter d3 of the second through-hole structure 35-1. In semiconductor device 3, the performance degradation of integrated circuit layer 14 can be mitigated or prevented by adjusting the second spacing sp3 between integrated circuit layer 14 and the second through-hole structure 35-1 in the second exclusion region KOZ2.

[0092] Figure 7 This is a cross-sectional view used to describe the semiconductor device 4 according to the example embodiment, and Figure 8 It is used to describe Figure 7 A plan view showing the arrangement of integrated circuit layers and via structures.

[0093] Except that the top surface of the first through-hole structure 31-1 is at the same level as the top surface of the second through-hole structure 35-2, the semiconductor device 4 can be... Figures 1 to 3 Semiconductor devices 1 and Figure 4 The semiconductor device 2 is the same. Figure 7 and Figure 8 In, with Figures 1 to 4The same reference numerals refer to the same elements. Figure 7 and Figure 8 In the text, the above references are briefly given or omitted. Figures 1 to 4 The given description.

[0094] Semiconductor device 4 may include a first via structure 31-1 and a second via structure 35-2. The first via structure 31-1 may be arranged to be separated from one side of integrated circuit layer 14 by a first pitch sp4. In some example embodiments, the first pitch sp4 may be from a few micrometers to tens of micrometers. In some example embodiments, the first pitch sp4 may be from about 1 micrometer to about 20 micrometers.

[0095] The first through-hole structure 31-1 may have a first diameter d4. The first diameter d4 may be a first critical dimension CD1. In some example embodiments, the first diameter d4 may be from a few micrometers to tens of micrometers. In some example embodiments, the first diameter d4 may be from about 1 micrometer to about 15 micrometers.

[0096] The first via structure-1 can extend vertically from and through the first via-connected metal wiring layer VL3 to the semiconductor substrate 10. The first via-connected metal wiring layer VL3 is one of the second metal wiring layer 20b to the sixth metal wiring layer 20f. The first via-connected metal wiring layer VL3 may include a fifth metal wiring layer 20e.

[0097] The first via connection metal routing layer VL3 may use, but is not limited to, the fifth metal routing layer 20e, and may include any one of the second metal routing layers 20b to the sixth metal routing layer 20f. The first via connection metal routing layer VL3 may be located in the center portion of the second to sixth metal routing layers 20b to 20f or in the middle portion of the back-end layer BEOL in the vertical direction (e.g., the Z direction).

[0098] The first via structure 31-1 can penetrate all of the first wiring insulating layer 18a to the fourth wiring insulating layer 18d constituting the back-end layer BEOL, the interlayer insulating layer 12 constituting the front-end layer FEOL, and the semiconductor substrate 10. The first via structure 31-1 can have a first height h3. In some embodiments, the first height h3 can be tens of micrometers. In some example embodiments, the first height h3 can be about 50 micrometers to about 90 micrometers.

[0099] like Figure 7As shown, the first through-hole structure 31-1 may include a first via 24-1 formed in the entirety of the back-end layer BEOL, the front-end layer FEOL and the semiconductor substrate 10, a first via insulating layer 28-1 formed on the inner wall of the first via 24-1, and a first via electrode 30-1 buried (e.g., filled) in the first via insulating layer 28-1.

[0100] In other words, such as Figure 7 As shown, the first through-hole structure 31-1 may include: a first via 24-1 passing through the entire first wiring insulating layer 18a to the fourth wiring insulating layer 18d, the interlayer insulating layer 12, and the semiconductor substrate 10; a first via insulating layer 28-1 formed on the inner wall of the first via 24-1; and a first via electrode 30-1 buried (e.g., filled) in the first via insulating layer 28-1. The first via electrode 30-1 may include a first via blocking layer (not shown) and a first via metal layer (not shown).

[0101] Semiconductor device 4 may include a second via structure 35-2. The second via structure 35-2 may be arranged separately from the first via structure 31-1. The second via structure 35-2 may be arranged separately from the other side (e.g., the opposite side) of integrated circuit layer 1 4 by a second pitch sp5. In some example embodiments, the second pitch sp5 may be from a few micrometers to tens of micrometers. In some example embodiments, the second pitch sp5 may be from about 1 micrometer to about 20 micrometers.

[0102] The second diameter d5 of the second through-hole structure 35-2 can be larger than the first diameter d4. The second diameter d5 can be a second critical dimension CD2. In some example embodiments, the second diameter d5 can be from a few micrometers to tens of micrometers. In some example embodiments, the second diameter d5 can be from about 1 micrometer to about 15 micrometers. When the second diameter d5 of the second through-hole structure 35-2 is larger than the first diameter d4 of the first through-hole structure 31-1, the resistance of the second through-hole structure 35-2 can be lower than the resistance of the first through-hole structure 35-2.

[0103] In some example embodiments, when the second diameter d5 of the second through hole structure 35-2 is greater than the first diameter d4 of the first through hole structure 31-1, the second through hole structure 35-2 may include a power transmission via structure, while the first through hole structure 31-1 may include a signal transmission via structure.

[0104] The second via structure 35-2 can extend vertically from the second via connection metal wiring layer VL4 to the semiconductor substrate 10 and can pass through the semiconductor substrate 10. The second via connection metal wiring layer VL4 is one of the second metal wiring layers 20b to the sixth metal wiring layer 20f. The second via connection metal wiring layer VL4 may include a fifth metal wiring layer 20e. The second via connection metal wiring layer VL4 may include an intermediate wiring layer, namely the fifth metal wiring layer 20e.

[0105] The second via connection metal routing layer VL4 may use, but is not limited to, the fifth metal routing layer 20e, and may include any one of the second metal routing layers 20b to the sixth metal routing layer 20f. The second via connection metal routing layer VL4 may be located in the middle portion of the second metal routing layers 20b to the sixth metal routing layers 20f or in the middle portion of the back-end layer BEOL in the vertical direction (e.g., the Z direction).

[0106] The second height h4 of the second through-hole structure 35-2 can be the same as the first height h3. In some example embodiments, the second height h4 can be tens of micrometers. In some example embodiments, the second height h4 can be about 50 micrometers to about 90 micrometers.

[0107] The second via-connected metal wiring layer VL4 can be arranged at the same level as the first via-connected metal wiring layer VL3. In other words, the level of the first through-hole structure 31-1 can be the same as the level of the second through-hole structure 35-2.

[0108] The second through-hole structure 35-2 can pass through the first wiring insulating layer 18a to the fourth wiring insulating layer 18d constituting the back-end stage layer BEOL, the interlayer insulating layer 12 constituting the front-end stage layer FEOL, and the entire semiconductor substrate 10. For example... Figure 7 As shown, the second via structure 35-2 may include a second via 26-2 formed in the entirety of the back-end layer BEOL, the front-end layer FEOL and the semiconductor substrate 10, a first via insulating layer 32-2 formed on the inner wall of the second via 26-2, and a second via electrode 34-2 buried (e.g., filled) in the second via insulating layer 32.

[0109] In other words, such as Figure 7As shown, the second via structure 35-2 may include: a second via 26-2 passing through the entirety of the first wiring insulating layer 18a to the fourth wiring insulating layer 18d, the interlayer insulating layer 12, and the semiconductor substrate 10; a second via insulating layer 32-2 formed on the inner wall of the second via 26-2; and a second via electrode 34-2 buried (e.g., filled) in the second via insulating layer 32-2. The second via electrode 34-2 may include a via blocking layer (not shown).

[0110] Here, we will refer to Figure 8 Describe the arrangement relationship between integrated circuit layer 14, first through-hole structure 31-1 and second through-hole structure 35-2.

[0111] like Figure 8 As shown, a first through-hole structure 31-1 can be formed in a first exclusion region KOZ1, which is disposed on one side of the integrated circuit layer 14. The integrated circuit layer 14 can be formed near the first exclusion region KOZ1. As described above, the first through-hole structure 31-1 can have a first diameter d4. The first through-hole structure 31-1 can be arranged to be separated from one side of the integrated circuit layer 14 by a first spacing sp4.

[0112] The second via structure 35-2 can be formed in the second exclusion region KOZ2, which is disposed on the other side (e.g., the opposite side) of the integrated circuit layer 14. The area of ​​the second exclusion region KOZ2 can be the same as the area of ​​the first exclusion region KOZ1. The integrated circuit layer 14 can be formed near the second exclusion region KOZ2. As described above, the second diameter d5 of the second via structure 35-2 can be larger than the first diameter d4. The second via structure 35-2 can be arranged to be separated from the other side (e.g., the opposite side) of the integrated circuit layer 14 by a second spacing sp5.

[0113] The first height h3 of the first through-hole structure 31-1 may extend from the bottom surface of the lower pad 48 (e.g., the surface in contact with the insulating layer INL) to the first via-connected metal wiring layer VL3. The second height h4 of the second through-hole structure 35-2 (same as the first height h3) may extend from the bottom surface of the lower pad 48 (e.g., the surface in contact with the insulating layer INL) to the second via-connected metal wiring layer VL4.

[0114] In the aforementioned semiconductor device 4, the first through-hole structure 31-1 can be connected to a first via-connected metal wiring layer VL3 located in the central portion or middle portion of the rear-end layer BEOL in the vertical direction (e.g., the Z direction), while the second through-hole structure 35-2 can be connected to a second via-connected metal wiring layer VL4 located in the central portion or middle portion of the rear-end layer BEOL in the vertical direction (e.g., the Z direction). The horizontal level of the first through-hole structure 31-1 can be the same as the horizontal level of the second through-hole structure 35-2.

[0115] Therefore, the semiconductor device 4 can reduce or easily adjust its resistance by using a first through-hole structure 31-1 and a second through-hole structure 35-2, each connected to the center portion of the vertical (e.g., Z-direction) rear-end layer BEOL or each connected to the middle portion of the vertical (e.g., Z-direction) rear-end layer BEOL. The semiconductor device 4 can adjust the diameter of each of the first through-hole structure 31-1 and the second through-hole structure 35-2, and the resistance of each of the first through-hole structure 31-1 and the second through-hole structure 35-2 can be easily adjusted.

[0116] In addition, the semiconductor device 4 can adjust the first spacing sp4 and the second spacing sp5 between the first through-hole structure 31-1 and the second through-hole structure 35-2 and the integrated circuit layer 14, thereby reducing or preventing the degradation of the electrical performance of the integrated circuit layer 14.

[0117] Figure 9 This is a cross-sectional view used to describe the semiconductor device 5 according to an example embodiment, and Figure 10 It is used to describe Figure 9 A plan view showing the arrangement of integrated circuit layers and via structures.

[0118] Apart from the different dimensions and arrangement of the second through-hole structure 35-3, the semiconductor device 5 can be... Figure 7 and Figure 8 The semiconductor device 4 is the same. Figure 9 and Figure 10 In, with Figure 7 and Figure 8 The same reference numerals refer to the same elements. Figure 9 and Figure 10 In the text, the above references are briefly given or omitted. Figure 7 and Figure 8 The given description.

[0119] Semiconductor device 5 may include a first through-hole structure 31-1 and a second through-hole structure 35-3. For example... Figure 9As shown, the second via structure 35-3 may include a second via 26-3 formed in the rear stage layer BEOL, the front stage layer FEOL and the semiconductor substrate 10, a second via insulating layer 32-3 formed on the inner wall of the second via 26-3, and a second via electrode 34-3 buried (e.g., filled) in the second via insulating layer 32-3.

[0120] The second diameter d6 of the second through-hole structure 35-3 can be the same as the first diameter d4 of the first through-hole structure 31-1. In some example embodiments, the first diameter d4 and the second diameter d6 can be from a few micrometers to tens of micrometers.

[0121] like Figure 10 As shown, a first through-hole structure 31-1 can be formed in a first exclusion region KOZ1, which is disposed on one side of the integrated circuit layer 14. A second through-hole structure 35-3 can be formed in a second exclusion region KOZ2, which is disposed on the other side (e.g., opposite side) of the integrated circuit layer 14.

[0122] like Figure 9 and Figure 10 As shown, the first through-hole structure 31-1 can be arranged to be separated from one side of the integrated circuit layer 14 by a first pitch sp4. The second through-hole structure 35-3 can be arranged to be separated from the other side (e.g., the opposite side) of the integrated circuit layer 14 by a second pitch sp6, the second pitch sp6 being the same as the first pitch sp4.

[0123] As described above, in the semiconductor device 5, the resistance of the second through-hole structure 35-3 can be reduced or easily adjusted by adjusting the second diameter d6 of the second through-hole structure 35-3. Furthermore, in the semiconductor device 5, the performance degradation of the integrated circuit layer 14 can be mitigated or prevented by adjusting the second spacing sp6 between the integrated circuit layer 14 and the second through-hole structure 35-3 in the second exclusion region KOZ2.

[0124] Figure 11 This is a cross-sectional view used to describe the semiconductor device 6 according to an example embodiment, and Figure 12 It is used to describe Figure 11 A plan view showing the arrangement of integrated circuit layers and via structures.

[0125] In addition to the first transistor TR1 and the second transistor TR2 constituting the integrated circuit layer 14, the semiconductor device 6 can be connected with... Figures 1 to 3 Semiconductor devices 1 and Figure 4 The semiconductor device 2 is the same. Figure 11 and Figure 12 In, with Figures 1 to 4The same reference numerals refer to the same elements. Figure 11 and Figure 12 In the text, the above references are briefly given or omitted. Figures 1 to 4 The given description.

[0126] Semiconductor device 6 may include a first transistor TR1 and a second transistor TR2 constituting integrated circuit layer 14. Each of the first transistor TR1 and the second transistor TR2 may be a fin-type transistor. The first transistor TR1 may be an N-type transistor. The second transistor TR2 may be a P-type transistor.

[0127] The first transistor TR1 may be formed on a first portion of the semiconductor substrate 10 defined by an isolation region FD. The isolation region FD may be a trench isolation region. The isolation region FD may include an insulating layer. The first transistor TR1 may include a first fin F1, a first source / drain region SD1 disposed on both sides of the first fin F1, and a first gate GP1 formed on the first fin F1. The first source / drain region SD1 and the first gate GP1 may be electrically connected to the first metal wiring layer 20a through a contact plug layer 16.

[0128] The second transistor TR2 can be arranged separately from the first transistor TR1. The second transistor TR2 can be formed in a second portion of the semiconductor substrate 10 defined by the isolation region FD. The second transistor TR2 may include a second fin F2, a second source / drain region SD2 disposed on both sides of the second fin F2, and a second gate GP2 formed on the second fin F2. The second source / drain region SD2 and the second gate GP2 can be electrically connected to the first metal wiring layer 20a through the contact plug layer 16.

[0129] The semiconductor device 6 may include a first through-hole structure 31 and a second through-hole structure 35. For example... Figure 11 and Figure 12 As shown, a first through-hole structure 31 can be formed between the first transistor TR1 and the second transistor TR2. A second through-hole structure 35 can be formed between the first transistor TR1 and the second transistor TR2.

[0130] like Figure 11 As shown, the first through-hole structure 31 may include: a first via 24 formed in the entirety of the back-end layer BEOL, the front-end layer FEOL, the isolation region FD and the semiconductor substrate 10; a first via insulating layer 28 formed on the inner wall of the first via 24; and a first via electrode 30 that buries (e.g., fills) the first via 24 in the first via insulating layer 28.

[0131] like Figure 11As shown, the second via structure 35 may include: a second via 26 formed in the entirety of the back-end layer BEOL, the front-end layer FEOL, the isolation region FD and the semiconductor substrate 10; a second via insulating layer 32 formed on the inner wall of the second via 26; and a second via electrode 34 that buries (e.g., fills) the second via 26 in the first via insulating layer 32.

[0132] like Figure 12 As shown, a first via structure 31 can be formed in a first exclusion region KOZ1, which is disposed on one side of the integrated circuit layer 14 (e.g., the second transistor TR2). A second via structure 35 can be formed in a second exclusion region KOZ2, which is disposed on the other side (e.g., the opposite side) of the integrated circuit layer 14 (e.g., the second transistor TR2).

[0133] like Figure 11 and Figure 12 As shown, the first through-hole structure 31 can be arranged to be separated from one side of the integrated circuit layer 14 (e.g., the second transistor TR2) by a first spacing sp1. The second through-hole structure 35 can be arranged to be separated from the other side (e.g., the opposite side) of the integrated circuit layer 14 (e.g., the second transistor TR2) by a second spacing sp2, the second spacing sp2 being smaller than the first spacing sp1.

[0134] As described above, in the semiconductor device 6, the first transistor TR1 and the second transistor TR2, which each constitute the integrated circuit layer 14, can be formed on the semiconductor substrate 10, and the first through-hole structure 31 and the second through-hole structure 35 can be easily formed between the first transistor TR1 and the second transistor TR2.

[0135] In the semiconductor device 6, the resistance can be reduced or easily adjusted by using a first through-hole structure 31 and a second through-hole structure 35, each connected to the center portion of the rear end layer BEOL in the vertical direction (e.g., the Z direction) or each connected to the middle portion of the rear end layer BEOL in the vertical direction (e.g., the Z direction).

[0136] Furthermore, the semiconductor device 6 can adjust the first spacing sp1 and the second spacing sp2 between the first through-hole structure 31 and the second through-hole structure 35 and the first transistor TR1 and the second transistor TR2 constituting the integrated circuit layer 14, thereby reducing or preventing the degradation of the electrical performance of the first transistor TR1 and the second transistor TR2.

[0137] Figures 13 to 16 It is used to describe manufacturing Figure 1 A cross-sectional view of a method for developing semiconductor devices.

[0138] Reference Figure 13 A semiconductor substrate 10 can be fabricated, comprising a first surface 10a and a second surface 10b opposite to the first surface 10a. The semiconductor substrate 10 can form a substrate-level layer (SUL). An integrated circuit layer 14 can be formed on the first surface 10a of the semiconductor substrate 10. The integrated circuit layer 14 can include multiple circuit elements (e.g., transistors, capacitors, and / or registers).

[0139] An interlayer insulating layer 12 may be formed on the semiconductor substrate 10 and the integrated circuit layer 14. The interlayer insulating layer 12 may include a silicon oxide layer. A contact plug layer 16 electrically connected to the integrated circuit layer 14 may be formed in the interlayer insulating layer 12. The contact plug layer 16 may include a metal layer (e.g., a tungsten layer). The integrated circuit layer 14, the interlayer insulating layer 12, and the contact plug layer 16, each formed on the semiconductor layer 10, may constitute a front-end stage (FEOL).

[0140] The first back-end layer BEOL1 can be formed on the front-end layer FEOL. The first back-end layer BEOL1 may include a first metal wiring layer 20a to a third metal wiring layer 20c, a first wiring insulation layer 18a to a third wiring insulation layer 18c, and a first wiring via layer 22a to a third wiring via layer 22c. The first wiring via layer 22a and the second wiring via layer 22b can be electrically connected to the first metal wiring layer 20a to the third metal wiring layer 20c. The first metal wiring layer 20a can be electrically connected to the contact plug layer 16.

[0141] Each of the first metal wiring layers 20a to the third metal wiring layers 20c may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). Each of the first wiring insulating layers 18a to the third wiring insulating layers 18c may include a silicon oxide layer. Each of the first wiring via layers 22a to the third wiring via layers 22c may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer).

[0142] Subsequently, a first via 24 can be formed by selectively etching the first wiring insulating layer 18a to the third wiring insulating layer 18c, the interlayer insulating layer 12, and the semiconductor substrate 10. The first via 24 can be formed in the first wiring insulating layer 18a to the third wiring insulating layer 18c, the interlayer insulating layer 12, and the semiconductor substrate 10. The first via 24 can be formed by a photolithography process. The first via 24 can be formed with a first diameter d1. The first via 24 can be formed with a first spacing sp1 separated from one side of the integrated circuit layer 14. The first via 24 can be referred to as a first via trench.

[0143] Reference Figure 14A first via insulating layer 28 can be formed on the inner wall of the first via 24. The first via insulating layer 28 may include a silicon oxide layer or a silicon nitride layer. Subsequently, a first via electrode 30 that buries (e.g., fills) the first via 24 can be formed on the first via insulating layer 28.

[0144] As shown above (refer to the reference) Figure 2 The first via electrode 30 may include a first via barrier layer ( Figure 2 30a) and the first via metal layer ( Figure 2 (30b). The first via electrode 30 may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). Through such a manufacturing process, a first through-hole structure 31 including a first via insulating layer 28 and a first via electrode 30 can be formed.

[0145] Reference Figure 15 The second back-end layer BEOL2 can be formed on the first back-end layer BEOL1. The second back-end layer BEOL2 may include a fourth metal wiring layer 20d and a fifth metal wiring layer 20e, a fourth wiring insulation layer 18d and a fifth wiring insulation layer 18e, and a fourth wiring via layer 22d and a fifth wiring via layer 22e. The fourth wiring via layer 22d can electrically connect the fourth metal wiring layer 20d and the fifth metal wiring layer 20e. The fourth metal wiring layer 20d can also be electrically connected to a third wiring via layer 22c.

[0146] The fourth metal wiring layer 20d and the fifth metal wiring layer 20e may each include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). The fourth wiring insulating layer 18d and the fifth wiring insulating layer 18e may each include a silicon oxide layer. The fourth wiring via layer 22d and the fifth wiring via layer 22e may each include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer).

[0147] In the fourth metal wiring layer 20d and the fifth metal wiring layer 20e constituting the second back-end layer BEOL2, the fourth metal wiring layer 20d formed on the first through-hole structure 31 can be a first via-connected metal wiring layer VL1. The first via-connected metal wiring layer VL1 can be electrically connected to the first through-hole structure 31.

[0148] Subsequently, a second via 26 can be formed by selectively etching the first to fifth wiring insulating layers 18a to 18e, the interlayer insulating layer 12, and the semiconductor substrate 10. The second via 26 can be formed within the first to fifth wiring insulating layers 18a to 18e, the interlayer insulating layer 12, and the semiconductor substrate 10. The second via 26 can be formed using a photolithography process. The second via 26 can be formed with a second diameter d2 greater than the first diameter d1. The second via 26 can be formed with a second spacing sp2 separated from the other side (e.g., the opposite side) of the integrated circuit layer 14. The second via 26 can be referred to as a second via trench.

[0149] Reference Figure 16 A second via insulating layer 32 may be formed on the inner wall of the second via 26. The second via insulating layer 32 may include a silicon oxide layer or a silicon nitride layer. Subsequently, a second via electrode 34 may be formed on the second via insulating layer 32 to bury (e.g., fill) the second via 26.

[0150] The second via electrode 34 may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). Through such a manufacturing process, a second through-hole structure 35 comprising a second via insulating layer 32 and a second via electrode 34 can be formed.

[0151] Subsequently, a third back-end layer BEOL3 can be formed on the second back-end layer BEOL2. The third back-end layer BEOL3 may include a sixth metal wiring layer 20f, a sixth wiring insulation layer 18f, and a sixth wiring via layer 22f. The sixth metal wiring layer 20f may be electrically connected to the fifth wiring via layer 22e.

[0152] The sixth metal wiring layer 20f may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer). The sixth wiring insulating layer 18f may include a silicon oxide layer. The sixth wiring via layer 22f may include a metal layer (e.g., a copper layer, an aluminum layer, or a tungsten layer).

[0153] The sixth metal wiring layer 20f formed on the second through-hole structure 35 can be a second via-connected metal wiring layer VL2. The second via-connected metal wiring layer VL2 can be electrically connected to the second through-hole structure 35.

[0154] Through this manufacturing process, the back-end layer BEOL can include a first back-end layer BEOL1, a second back-end layer BEOL2, and a third back-end layer BEOL3. The back-end layer BEOL can include multiple metal wiring layers 20, multiple wiring insulation layers 18, and multiple wiring via layers 22. The metal wiring layers 20 can include first metal wiring layers 20a to sixth metal wiring layers 20f. The wiring insulation layers 18 can include first wiring insulation layers 18a to sixth wiring insulation layers 18f. The wiring via layers 22 can include first wiring via layers 22a to sixth wiring via layers 22f.

[0155] Subsequently, as Figure 1 As shown, the upper pad ( Figure 1 33) can be formed on the sixth wiring via layer 22f. According to some example embodiments, such as... Figure 1 As shown, a chemical mechanical polishing process can be performed on the second surface 10b of the semiconductor substrate 10 to expose the first through-hole structure 31 and the second through-hole structure 35 and form a lower protective layer 46 and a lower pad 48.

[0156] Figure 17 This is a block diagram illustrating the configuration of a semiconductor chip 200 including semiconductor devices according to an example embodiment.

[0157] For example, semiconductor chip 200 may include logic region 202, SRAM region 204, and input / output (I / O) region 206. Semiconductor chip 200 may include semiconductor devices 1 to 6 according to embodiments. Logic region 202 may include logic cell region 203. SRAM region 204 may include SRAM cell region 205 and SRAM peripheral circuit region 208.

[0158] The first transistor 210 can be arranged in the logic cell area 203, while the second transistor 212 can be arranged in the SRAM cell area 205. The third transistor 214 can be formed in the SRAM peripheral circuit area 208, while the fourth transistor 216 can be arranged in the I / O area 206.

[0159] Figure 18 This is a block diagram illustrating the configuration of a semiconductor chip 250 including semiconductor devices according to an example embodiment.

[0160] For example, semiconductor chip 250 may include logic region 252. Semiconductor chip 250 may include semiconductor devices 1 to 6 according to embodiments. Logic region 252 may include logic cell region 254 and I / O region 256. First transistor 258 and second transistor 260 may be arranged in logic cell region 254. First transistor 258 and second transistor 260 may be transistors of different conductivity types. Third transistor 262 may be arranged in I / O region 256.

[0161] Figure 19 This is a block diagram illustrating the configuration of a semiconductor package 300 including semiconductor devices according to an example embodiment, and Figure 20 This is an equivalent circuit diagram of an SRAM cell included in a semiconductor device according to an example embodiment.

[0162] Reference Figure 19 The semiconductor package 300 may include a system-on-a-chip 310. The system-on-a-chip 310 may include a processor 311, embedded memory 313, and cache memory 315. The processor 311 may include one or more processor cores C1 to CN. The processor cores C1 to CN can process data and signals. According to an example embodiment, the processor cores C1 to CN may include semiconductor devices 1 to 6.

[0163] Semiconductor package 300 can perform unique functions using processed data and signals. For example, processor 311 may include an application processor. Embedded memory 313 can exchange first data DATA1 with processor 311. First data DATA1 may be data obtained by processor cores C1 to CN, or data to be processed by processor cores C1 to CN. Embedded memory 313 can manage first data DATA1. For example, embedded memory 313 can buffer first data DATA1. Embedded memory 313 can be used as buffer memory or working memory of processor 311.

[0164] Embedded memory 313 may include SRAM. SRAM can operate at a higher speed than DRAM. When SRAM is embedded in system-on-chip 310, semiconductor package 300 can be implemented with a small size and high speed operation. In addition, when SRAM is embedded in system-on-chip 310, the active power consumption of semiconductor package 300 can be reduced.

[0165] For example, SRAM may include semiconductor devices 1 to 6 according to embodiments. Cache memory 315 may be mounted on the system-on-chip 310 together with processor cores C1 to CN. Cache memory 315 may store cached data DATc. Cache data DATc may be data used by processor cores C1 to CN. Cache memory 315 may have a small storage capacity but can operate at very high speeds.

[0166] For example, cache memory 315 may include SRAM, which includes semiconductor devices 1 to 6 according to embodiments. When cache memory 315 is used, the number of times processor 311 accesses embedded memory 313 and the time spent accessing embedded memory 313 can be reduced. Therefore, when cache memory 315 is used, the operating speed of semiconductor package 300 can be improved. For the sake of understanding, cache memory 315 is shown as an element independent of processor 311. However, cache memory 315 may be configured to be included in processor 311.

[0167] Reference Figure 20 SRAM cells can be implemented using semiconductor devices 1 to 6 according to the example embodiments. For example, SRAM cells can be applied to the above-mentioned references. Figure 19 The embedded memory 313 and / or cache memory 315 are described. The SRAM cell may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PA1, and a second access transistor PA2.

[0168] The first pull-up transistor PU1 and the second pull-up transistor PU2 may each comprise a PMOS transistor, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PA1, and the second access transistor PA2 may each comprise an NMOS transistor. The first pull-up transistor PU1 and the first pull-down transistor PD1 may each be configured with a first inverter. The gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1, which are connected to each other, may each correspond to the input terminal of the first inverter, and the first node N1 may correspond to the output terminal of the first inverter.

[0169] The second pull-up transistor PU2 and the second pull-down transistor PD2 can each be configured with a second inverter. The gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2, which are connected to each other, can each correspond to the input terminal of the second inverter, and the second node N2 can correspond to the output terminal of the second inverter.

[0170] The first inverter and the second inverter can be coupled to each other to form a latch structure. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the second node N2, while the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be electrically connected to the first node N1.

[0171] The first source / drain of the first access transistor PA1 can be connected to the first node N1, and the second source / drain of the first access transistor PA1 can be connected to the first bit line BL1. The first source / drain of the second access transistor PA2 can be connected to the second node N2, and the second source / drain of the second access transistor PA2 can be connected to the second bit line BL2.

[0172] The gate electrodes of the first access transistor PA1 and the second access transistor PA2 can each be electrically connected to the word line WL. Therefore, an SRAM cell can be implemented using semiconductor devices 1 to 6 according to some example embodiments.

[0173] Figure 21 This is a cross-sectional view of a semiconductor package 400 including semiconductor devices according to an example embodiment.

[0174] For example, semiconductor package 400 may include stacked semiconductor chips 440 stacked on package substrate 401. Package substrate 401 may include printed circuit board (PCB). Solder bumps 403, serving as external connection terminals, may be formed on the bottom surface of package substrate 401.

[0175] The stacked semiconductor chip 440 may include a first semiconductor chip 410 and a plurality of second semiconductor chips 420 mounted on the first semiconductor chip 410. The second semiconductor chips 420 may be sequentially stacked on the first semiconductor chip 410 in a vertical direction (Z direction). The width of the first semiconductor chip 410 may be greater than the width of each of the second semiconductor chips 420.

[0176] In the accompanying drawings, the stacked semiconductor chip 440 is shown as including four second semiconductor chips 420, but the exemplary embodiment is not limited thereto. For example, the stacked semiconductor chip 440 may include two or more second semiconductor chips 420. According to some exemplary embodiments, the first semiconductor chip 410 and the second semiconductor chips 420 may include semiconductor devices 1 to 6.

[0177] For example, the first semiconductor chip 410 may include a first pad 412a and a second pad 412b on two surfaces of the first semiconductor substrate 411. The first pad 412a and the second pad 412b may be electrically connected using a first through-hole structure 413a, a first via-connected metal wiring layer VL5, a second through-hole structure 413b, and a second via-connected metal wiring layer VL6.

[0178] The first through-hole structure 413a can be electrically connected to the first via-connected metal wiring layer VL5. The second through-hole structure 413b can be electrically connected to the second via-connected metal wiring layer VL6. In the accompanying drawings, for convenience, it is shown that the horizontal height of the first via-connected metal wiring layer VL5 is the same as the horizontal height of the second via-connected metal wiring layer VL6.

[0179] Solder bumps 405, which serve as external connection terminals, can be used to electrically connect the first pad 412a to the package substrate 401. The active surface 411a can be disposed below the first semiconductor chip 410. The first pad 412a can be a top pad. The second pad 412b can be a bottom pad.

[0180] Each of the second semiconductor chips 420 may include a third pad 422a and a fourth pad 422b on two surfaces of the second semiconductor substrate 421. The third pad 422a and the fourth pad 422b may be electrically connected using a third through-hole structure 423a, a third via-connected metal wiring layer VL7, a fourth through-hole structure 423b, and a fourth via-connected metal wiring layer VL8.

[0181] The third through-hole structure 423a can be electrically connected to the third via-connected metal wiring layer VL7. The fourth through-hole structure 423b can be electrically connected to the fourth via-connected metal wiring layer VL8. In the accompanying drawings, for convenience, it is shown that the horizontal height of the third via-connected metal wiring layer VL7 is the same as the horizontal height of the fourth via-connected metal wiring layer VL8.

[0182] The third pad 422a can be electrically connected to the second semiconductor chip 420 using the internal connection terminal 424. The internal connection terminal 424 may include an internal connection pad 424a and an internal bump 424b.

[0183] The active surface 421a can be disposed below each of the second semiconductor chips 420. The third pad 422a can be a top pad. The fourth pad 422b can be a bottom pad. The second semiconductor chip 420 can be molded from the molding layer 430 on the first semiconductor chip 410.

[0184] Figure 22 and Figure 23 This is a schematic diagram illustrating a semiconductor package 500 according to some example embodiments.

[0185] Reference Figure 22The semiconductor package 500 may include multiple stacked memory devices 510 and a system-on-a-chip (SoC) 520. The stacked memory devices 510 and SoC 520 may be stacked on an interposer 530, and the interposer 530 may be stacked on a package substrate 540. The semiconductor package 500 may send signals to or receive signals from an external package or electronic device via solder balls 501 attached to the underside of the package substrate 540.

[0186] Each of the stacked memory devices 510 may be implemented based on the High Bandwidth Memory (HBM) standard. However, the inventive concept is not limited thereto, and each of the stacked memory devices 510 may be implemented based on Graphics Double Data Rate (GDDR), Hardware Management Console (HMC), or Wide I / O. According to some example embodiments, each of the stacked memory devices 510 may include semiconductor devices 1 to 6.

[0187] SoC 520 may include at least one processor, such as a central processing unit (CPU), application processor (AP), graphics processing unit (GPU), and neural processing unit (NPU), as well as multiple memory controllers for controlling multiple stacked memory devices 510. SoC 520 may send signals to or receive signals from the respective stacked memory devices via the memory controllers.

[0188] Reference Figure 23 The semiconductor package 600 may include a stacked memory device 610, a SoC 620, an interposer 630, and a package substrate 640. The stacked memory device 610 may include a buffer die 611 and multiple core dies 612, 613, 614, and 615.

[0189] Each of core dies 612 to 615 may include multiple memory cells for storing data. Buffer die 611 may include a physical layer (PHY) 606 and a direct access area (DAB) 608. Physical layer 606 is electrically connected to physical layer 621 of SoC 620 via intermediary layer 630. Stacked memory device 610 may receive signals from or send signals to SoC 620 via physical layer 606.

[0190] Direct access region 608 can provide an access path for testing stacked memory devices 610 without going through SoC 620. Direct access region 608 may include conductive means (e.g., ports or pins) for direct communication with external test equipment. Test signals received through direct access region 608 can be transmitted to core dies 612 to 615 through multiple via structures. Data read from core dies 612 to 615 to test core dies 612 to 615 can be transmitted to test equipment through multiple via structures and direct access region 608. Therefore, direct access testing can be performed on core dies 612 to 615.

[0191] The buffer die 611 and core dies 612 to 615 may be electrically connected to each other through a plurality of through-hole structures 631a, 631b, 633a and 633b and a plurality of bumps 635. According to some example embodiments, the buffer die 611 and core dies 612 to 615 may include semiconductor devices 1 to 6.

[0192] For example, the buffer die 611 may include a first through-hole structure 631a, a first via-connected metal wiring layer VL9, a second through-hole structure 631b, and a second via-connected metal wiring layer VL10. The first through-hole structure 631a may be electrically connected to the first via-connected metal wiring layer VL9. The second through-hole structure 631b may be electrically connected to the second via-connected metal wiring layer VL10. In the accompanying drawings, for convenience, it is shown that the horizontal height of the first via-connected metal wiring layer VL9 is the same as the horizontal height of the second via-connected metal wiring layer VL10.

[0193] Each of the core dies 612 to 615 may include a third through-hole structure 633a, a third via-connected metal wiring layer VL11, a fourth through-hole structure 633b, and a fourth via-connected metal wiring layer VL12. The third through-hole structure 633a may be electrically connected to the third via-connected metal wiring layer VL11. The fourth through-hole structure 633b may be electrically connected to the fourth via-connected metal wiring layer VL12. In the accompanying drawings, for convenience, it is shown that the horizontal height of the third via-connected metal wiring layer VL11 is the same as the horizontal height of the fourth via-connected metal wiring layer VL12.

[0194] The buffer die 611 can receive signals provided to channels via bumps 602 assigned by the channel units from the SoC 620, or can send signals to the SoC 620 via bumps 602. For example, bumps 602 may include microbumps.

[0195] The SoC 620 can execute multiple applications supported by the semiconductor package 600 by using a stacked memory device 610. For example, the SoC 620 may include at least one processor, such as a CPU, AP, GPU, NPU, Tensor Processing Unit (TPU), Vision Processing Unit (VPU), Image Signal Processor (ISP), Digital Signal Processor (DSP), and can perform specialized arithmetic operations.

[0196] SoC 620 can control the overall operation of the stacked memory device 610. SoC 620 may include a physical layer 621. Physical layer 621 may include interface circuitry for sending signals to or receiving signals from physical layer 606 of the stacked memory device 610. SoC 620 can provide various signals to physical layer 606 through physical layer 621. Signals provided to physical layer 606 can be transmitted to core dies 612 to 615 through via structures 631a, 631b, 633a, and 633b and the interface circuitry of physical layer 606.

[0197] Intermediate layer 630 can connect stacked memory device 610 to SoC 620. Intermediate layer 630 can connect physical layer 606 of stacked memory device 610 to physical layer 621 of SoC 620 and can provide physical paths including conductive materials. Therefore, stacked memory device 610 and SoC 620 can be stacked on intermediate layer 630 and can send and receive signals between each other.

[0198] Bump 603 may be attached to the upper part of package substrate 640, while solder ball 604 may be attached to the lower part of package substrate 640. For example, bump 603 may include flip chip bumps. Interposer 630 may be stacked on package substrate 640 via bump 603. Semiconductor package 600 may send signals to or receive signals from external packages or electronic devices via solder ball 604. For example, package substrate 640 may include PCB.

[0199] Although the inventive concept has been shown and described in detail with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; An integrated circuit layer is disposed on the semiconductor substrate; The first metal wiring layer to the nth metal wiring layer are sequentially stacked on the semiconductor substrate and the integrated circuit layer, where n is a positive integer; The first through-hole structure, serving as the first through electrode, is separated from one side of the integrated circuit layer by a first distance. The first through-hole structure extends vertically from the first via-connected metal wiring layer to the semiconductor substrate and passes through the semiconductor substrate. The first via-connected metal wiring layer is one of the second to nth metal wiring layers other than the first metal wiring layer. as well as The second through-hole structure, serving as the second through electrode, is separated from the other side of the integrated circuit layer by a second spacing and is separate from the first through-hole structure. The second through-hole structure extends vertically from the second via-connected metal wiring layer to the semiconductor substrate and passes through the semiconductor substrate. The second via-connected metal wiring layer is one of the second to nth metal wiring layers, excluding the first metal wiring layer.

2. The semiconductor device according to claim 1, wherein, The first diameter of the first through hole structure is different from the second diameter of the second through hole structure.

3. The semiconductor device according to claim 1, wherein, The first diameter of the first through-hole structure is smaller than the second diameter of the second through-hole structure, and The second spacing is smaller than the first spacing.

4. The semiconductor device according to claim 1, wherein, The first diameter of the first through hole structure is the same as the second diameter of the second through hole structure.

5. The semiconductor device according to claim 4, wherein: The second spacing is the same as the first spacing.

6. The semiconductor device according to claim 1, wherein, The first via connecting the metal wiring layer and the second via connecting the metal wiring layer are at different levels.

7. The semiconductor device according to claim 1, wherein, The first via connecting the metal wiring layer and the second via connecting the metal wiring layer are on the same level.

8. The semiconductor device according to claim 1, further comprising: The upper pad is on the nth metal wiring layer and electrically connected to the nth metal wiring layer, wherein the nth metal wiring layer is the uppermost layer among the first metal wiring layer to the nth metal wiring layer; as well as The lower pad is located on the bottom surface of the semiconductor substrate and is electrically connected to a corresponding through-hole structure in either the first through-hole structure or the second through-hole structure.

9. The semiconductor device according to claim 1, further comprising: A redistribution layer is placed on and electrically connected to the nth metal wiring layer, wherein the nth metal wiring layer is the uppermost layer among the first metal wiring layer to the nth metal wiring layer. Bump pads, on the redistribution layer and electrically connected to the redistribution layer; and Solder bumps, on the bump pads.

10. A semiconductor device, comprising: A semiconductor substrate, comprising a first surface and a second surface opposite to the first surface; A front-end layer, on the first surface of the semiconductor substrate, the front-end layer includes an integrated circuit layer; A back-end layer, on top of the front-end layer, the back-end layer includes a first metal wiring layer to an nth metal wiring layer that are sequentially stacked on the integrated circuit layer and electrically connected to the integrated circuit layer, where n is a positive integer; The first through-hole structure, serving as the first through electrode, is separated from one side of the integrated circuit layer by a first spacing. The first through-hole structure extends vertically from the first via-connected metal wiring layer to the semiconductor substrate and passes through the back-end layer, the front-end layer, and the region between the first surface and the second surface of the semiconductor substrate. The first via-connected metal wiring layer is one of the second to nth metal wiring layers, excluding the first metal wiring layer. as well as The second via structure, serving as the second through electrode, is separated from the other side of the integrated circuit layer by a second spacing and is separate from the first via structure. The second via structure extends vertically from the second via-connected metal wiring layer to the semiconductor substrate and passes through the back-end layer, the front-end layer, and the region between the first surface and the second surface of the semiconductor substrate. The second via-connected metal wiring layer is one of the second to nth metal wiring layers, excluding the first metal wiring layer.

11. The semiconductor device according to claim 10, wherein, The integrated circuit layer constituting the front-end layer includes transistors, capacitors, or registers.

12. The semiconductor device according to claim 10, wherein, The backend layer includes: Multiple wiring insulation layers are configured to insulate the first metal wiring layer to the nth metal wiring layer from each other; and Multiple wiring via layers are located within the multiple wiring insulation layers and are configured to connect the first metal wiring layer to the nth metal wiring layer.

13. The semiconductor device according to claim 10, wherein, Each of the first through-hole structure and the second through-hole structure includes: The via is located in the rear-end stage layer, the front-end stage layer, and the semiconductor substrate; An insulating layer is provided on the inner wall of the via; and A via electrode is placed on the via insulating layer and fills the via.

14. The semiconductor device according to claim 10, wherein, The first height of the first through-hole structure is different from the second height of the second through-hole structure.

15. The semiconductor device according to claim 10, wherein, The first diameter of the first through-hole structure is different from the second diameter of the second through-hole structure.

16. The semiconductor device of claim 10, wherein... The second diameter of the second through-hole structure is larger than the first diameter of the first through-hole structure. The second through-hole structure includes a power transmission via structure, and The first through-hole structure includes a signal transmission via structure.

17. A semiconductor device, comprising: Semiconductor substrate; A front-end layer on the semiconductor substrate includes an integrated circuit layer, an interlayer insulating layer configured to insulate the integrated circuit layer, and a contact plug layer in the interlayer insulating layer and electrically connected to the integrated circuit. A back-end layer, on top of the front-end layer, the back-end layer includes: a first metal wiring layer to an nth metal wiring layer sequentially stacked on the front-end layer and electrically connected to the integrated circuit layer, where n is a positive integer; a plurality of wiring insulating layers configured to insulate the first metal wiring layer to the nth metal wiring layer from each other; and a plurality of wiring via layers in the plurality of wiring insulating layers and configured to connect the first metal wiring layer to the nth metal wiring layer; A first through-hole structure, serving as a first through electrode, is separated from one side of the integrated circuit layer by a first spacing. The first through-hole structure extends vertically from the first via-connected metal wiring layer towards the semiconductor substrate, passing through the plurality of wiring insulating layers, the interlayer insulating layer, and the semiconductor substrate. The first via-connected metal wiring layer is one of the second to nth metal wiring layers, excluding the first metal wiring layer. The second via structure, serving as a second through electrode, is separated from the other side of the integrated circuit layer by a second spacing and is also separate from the first via structure. The second via structure extends vertically from the second via-connected metal wiring layer towards the semiconductor substrate, passing through the plurality of wiring insulating layers, the interlayer insulating layer, and the semiconductor substrate. The second via-connected metal wiring layer is one of the second to nth metal wiring layers, excluding the first metal wiring layer. The first through-hole structure is located in a first exclusion area on one side of the integrated circuit layer, while the second through-hole structure is located in a second exclusion area on the other side of the integrated circuit layer.

18. The semiconductor device according to claim 17, wherein, Each of the first exclusion zone and the second exclusion zone includes an insulating layer.

19. The semiconductor device of claim 17, wherein The second diameter of the second through-hole structure is larger than the first diameter of the first through-hole structure, and The second spacing is smaller than the first spacing.

20. The semiconductor device according to claim 17, wherein, In the back-end layer, the first via-connected metal wiring layer and the second via-connected metal wiring layer are at different levels.

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