Semiconductor packaging structure and preparation method thereof

Abstract

A semiconductor package structure and a method for manufacturing the same, wherein the semiconductor package structure comprises: a redistribution structure; a first chip flipped onto one side of the redistribution structure, the first chip being electrically connected to the redistribution structure; a first plastic encapsulation layer located on one side of the redistribution structure and covering the first chip; a first annular opening in the first plastic encapsulation layer surrounding the first chip; a first conductive shielding layer located on the sidewall surface of the first opening and on the surface of the first plastic encapsulation layer facing away from the redistribution structure; a conductive member located in the first opening, the conductive member being electrically connected to the redistribution structure at the bottom of the first opening; and a second chip flipped onto the first conductive shielding layer and the first plastic encapsulation layer on a side facing away from the redistribution structure, the second chip being electrically connected to the conductive member. The semiconductor package structure can achieve electromagnetic shielding between vertically stacked chips and has high structural stability and integration.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the popularization of wireless electronic devices, the integration of RF chips is getting higher and higher, and the number of RF devices in the package is increasing. This has led to increasingly serious electromagnetic interference problems between devices and modules. This has put forward higher requirements on how to electromagnetically shield devices with strong electromagnetic radiation in a limited space.

[0003] Fan-out semiconductor packaging has become one of the most popular new packaging formats due to its wafer-level packaging characteristics, low cost, and high integration. However, current semiconductor packaging structures struggle to achieve electromagnetic shielding between vertically stacked chips, and their structural stability and integration are low.

[0004] Therefore, the existing semiconductor packaging structure still needs to be improved. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defects of the semiconductor packaging structure in the prior art that it is difficult to achieve electromagnetic shielding between chips stacked in the vertical direction, and the structural stability and low integration of the semiconductor packaging structure, thereby providing a semiconductor packaging structure and a preparation method thereof.

[0006] The present invention provides a semiconductor packaging structure, comprising: a rewiring structure; a first chip flipped on one side of the rewiring structure, the first chip being electrically connected to the rewiring structure; a first plastic encapsulation layer, located on one side of the rewiring structure and covering the first chip; a first annular opening in the first plastic encapsulation layer located on the peripheral side of the first chip; a first conductive shielding layer located on the sidewall surface of the first opening and on the surface of the first plastic encapsulation layer on a side facing away from the rewiring structure; a conductive member located in the first opening, the conductive member being electrically connected to the rewiring structure at the bottom of the first opening; and a second chip flipped on the first conductive shielding layer and on the side of the first plastic encapsulation layer facing away from the rewiring structure, the second chip being electrically connected to the conductive member.

[0007] Optionally, it also includes: a first metal layer, located between the second chip and the conductive part; a first solder ball, the first solder ball is located between the first metal layer and the second chip; and a filling plastic layer, the filling plastic layer is located in the first opening and surrounds the side wall of the conductive part.

[0008] Optionally, the thickness of the first conductive shielding layer is 50 nm-5 um.

[0009] Optionally, the conductive member is electrically isolated from the first conductive shielding layer.

[0010] Optionally, the device further includes: a second plastic packaging layer, wherein the second plastic packaging layer covers the sidewalls of the second chip and the top surface of the second chip facing away from the first plastic packaging layer.

[0011] Optionally, the method further includes: a second conductive shielding layer located on the sidewalls and top surface of the second plastic packaging layer and surrounding the second chip.

[0012] Optionally, the thickness of the second conductive shielding layer is 50 nm-5 um.

[0013] Optionally, a side of the redistribution structure facing away from the first chip has a plurality of second solder balls, and the second solder balls are electrically connected to the redistribution structure.

[0014] The present invention also provides a method for preparing a semiconductor packaging structure, comprising: forming a first chip and a first plastic encapsulation layer that wraps the side walls and back side of the first chip; forming a first annular opening in the first plastic encapsulation layer on the peripheral side of the first chip; forming a first conductive shielding layer on the side wall surface of the first opening and the surface of the first plastic encapsulation layer located on the back side of the first chip; forming a conductive part in the first opening; flip-chip arranging a second chip vertically stacked with the first chip on the side of the first conductive shielding layer away from the first chip, the second chip being electrically connected to the conductive part; forming a redistribution structure on the front side of the first chip and the bottom of the first opening, the redistribution structure being electrically connected to the first chip and the conductive part, respectively.

[0015] Optionally, it also includes: providing a first carrier and a second carrier; the steps of forming a first chip and a first plastic encapsulation layer wrapping the side walls and back side of the first chip include: arranging a first chip on one side of the first carrier, with the front side of the first chip facing the first carrier; forming a first plastic encapsulation layer wrapping the side walls and back side of the first chip on one side of the first carrier; the preparation method of the semiconductor packaging structure also includes: after flip-chip arranging a second chip vertically stacked with the first chip on the side of the first conductive shielding layer away from the first chip, bonding the side of the second chip facing away from the first chip to the second carrier; after bonding the side of the second chip facing away from the first chip to the second carrier, before forming a redistribution structure on the front side of the first chip and the bottom of the first opening, removing the first carrier; after forming a redistribution structure on the front side of the first chip and the bottom of the first opening, removing the second carrier.

[0016] Optionally, the step of forming a first conductive shielding layer on the side wall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip includes: forming an initial first conductive shielding layer on the bottom and side wall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip; after forming the initial first conductive shielding layer, forming a conductive member in the first opening, one end of the conductive member contacts the initial first conductive shielding layer at the bottom of the first opening; removing the initial first conductive shielding layer at the bottom of the first opening until the conductive member is exposed, and the initial first conductive shielding layer forms a first conductive shielding layer.

[0017] Optionally, before flip-chipping a second chip vertically stacked with the first chip on a side of the first conductive shielding layer facing away from the first chip, the method further includes: forming a filling plastic layer in the first opening to surround the sidewalls of the conductive component.

[0018] Optionally, the step of forming the filling plastic packaging layer and the conductive part also includes: forming an initial conductive part in the first opening, and then forming an initial filling plastic packaging layer in the first opening and on the side of the first conductive shielding layer away from the first chip; thinning the initial filling plastic packaging layer and the initial conductive part so that the initial filling plastic packaging layer forms a filling plastic packaging layer and the initial conductive part forms a conductive part.

[0019] Optionally, it also includes: after forming the filling plastic layer, forming a first metal layer on the surface of the conductive part on the side away from the front of the first chip; forming a first solder ball on the surface of the first metal layer on the side away from the conductive part; and the first solder ball is electrically connected to the second chip.

[0020] Optionally, the method further includes: forming a plurality of second solder balls on a side of the redistribution structure away from the first chip, wherein the second solder balls are electrically connected to the redistribution structure.

[0021] Optionally, the method further includes: forming a second plastic packaging layer on the sidewall of the second chip and the top surface of the second chip facing away from the first plastic packaging layer.

[0022] Optionally, the method further includes: forming a second conductive shielding layer surrounding the second chip on the sidewalls and top surface of the second plastic packaging layer.

[0023] The technical solution of the present invention has the following advantages:

[0024] The semiconductor packaging structure provided by the present invention comprises the following: the first conductive shielding layer is located on the sidewall surface of the first opening and the surface of the first plastic encapsulation layer on the side facing away from the redistribution structure; the first plastic encapsulation layer covers the first chip; the first conductive shielding layer is located between the first chip and the second chip and covers the top and side of the first chip, so as to electromagnetically shield the first chip while preventing the signal of the second chip from interfering with the electromagnetic shielding of the first chip; the thermal expansion coefficient of the first conductive shielding layer is different from that of the first chip; the first plastic encapsulation layer between the first conductive shielding layer and the first chip can act as a stress buffer layer to prevent excessive stress between the first conductive shielding layer and the first chip, thereby improving the stability of the semiconductor packaging structure; the conductive member realizes the stacking and electrical connection of the first chip and the second chip in the vertical direction, which can improve the integration of the semiconductor packaging structure. In summary, the semiconductor packaging structure can realize electromagnetic shielding between chips stacked in the vertical direction and the structural stability and integration of the semiconductor packaging structure are high. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A semiconductor package structure provided by an embodiment of the present invention;

[0027] Figure 2 A semiconductor package structure provided by another embodiment of the present invention;

[0028] Figure 3 A schematic diagram of a manufacturing process of a semiconductor packaging structure provided by another embodiment of the present invention;

[0029] Figures 4 to 9 A structural schematic diagram of a process for preparing a semiconductor package structure according to another embodiment of the present invention;

[0030] Figures 10 to 12 A structural schematic diagram of a process for preparing a semiconductor packaging structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0034] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] Example 1

[0036] This embodiment provides a semiconductor packaging structure, referring to Figure 1 ,include:

[0037] Rewiring structure 1;

[0038] A first chip 2 flip-chip mounted on one side of the redistribution structure 1, wherein the first chip 2 is electrically connected to the redistribution structure 1;

[0039] A first plastic packaging layer 3 is located on one side of the redistribution structure 1 and covers the first chip 2;

[0040] a first annular opening in the first plastic packaging layer 3 located around the first chip 2;

[0041] a first conductive shielding layer 4 located on a sidewall surface of the first opening and a surface of the first plastic packaging layer 3 on a side facing away from the redistribution structure 1;

[0042] a conductive member 5 located in the first opening, the conductive member 5 being electrically connected to the redistribution structure 1 at the bottom of the first opening;

[0043] The second chip 6 is flip-chip mounted on a side of the first conductive shielding layer 4 and the first plastic packaging layer 3 facing away from the redistribution structure 1 , and the second chip 6 is electrically connected to the conductive member 5 .

[0044] In the semiconductor packaging structure provided by this embodiment, the first conductive shielding layer 4 is located on the sidewall surface of the first opening and the surface of the first plastic layer 3 facing away from the redistribution structure 1. The first plastic layer 3 covers the first chip 2. The first conductive shielding layer 4 is located between the first chip 2 and the second chip 6 and covers the top and side of the first chip 2. It can electromagnetically shield the first chip 2 and prevent the signal of the second chip 6 from interfering with the electromagnetic shielding of the first chip 2. The thermal expansion coefficient of the first conductive shielding layer 4 is different from that of the first chip 2. The first plastic layer between the first conductive shielding layer 4 and the first chip 2 can act as a stress buffer layer to prevent excessive stress between the first conductive shielding layer 4 and the first chip 2, thereby improving the stability of the semiconductor packaging structure. The conductive member 5 realizes the vertical stacking and electrical connection of the first chip 2 and the second chip 6, which can improve the integration of the semiconductor packaging structure. In summary, the semiconductor packaging structure can achieve electromagnetic shielding between vertically stacked chips and has high structural stability and integration.

[0045] In this embodiment, the first conductive shielding layer 4 has a larger area, which is more conducive to better heat dissipation of the semiconductor packaging structure.

[0046] In one embodiment, the first chip 2 includes a radio frequency chip.

[0047] In one embodiment, the surface area of the second chip 6 is greater than the surface area of the first chip 2 .

[0048] In one embodiment, the method further includes: a filling plastic layer, wherein the filling plastic layer is located in the first opening and surrounds the sidewall of the conductive component.

[0049] In one embodiment, the material of the first plastic packaging layer 3 includes epoxy resin and additives, and the additives include a hardener, a filler, a flame retardant, and the like.

[0050] In one embodiment, the first conductive shielding layer 4 plays the role of electromagnetic shielding. The material of the first conductive shielding layer 4 can be conductive glue or conductive metal, wherein the conductive filler of the conductive glue can be silver, copper, aluminum, zinc, iron, nickel powder and graphite and some conductive compounds, and the conductive metal is copper, aluminum, zinc, iron, nickel or alloy.

[0051] In one embodiment, the semiconductor package structure further includes: a first metal layer 7 located between the second chip 6 and the conductive member 5; and a first solder ball 8 located between the first metal layer 7 and the second chip 6. The first metal layer 7 can prevent metal diffusion on the first solder ball 8, and the first solder ball 8 is metal-bonded to the chip pad on the second chip 6.

[0052] In one embodiment, the thickness of the first conductive shielding layer 4 is 50nm-5um, for example, 100nm; if the thickness of the first conductive shielding layer is less than 50nm, the thickness of the first conductive shielding layer is too thin, and the degree of electromagnetic shielding effect on the first chip is too small; if the thickness of the first conductive shielding layer is greater than 5um, the thickness of the first conductive shielding layer is too thick, and the degree of reducing the volume of the semiconductor packaging structure is too small.

[0053] In one embodiment, the first conductive shielding layer 4 completely covers the sidewall surface of the first opening.

[0054] In one embodiment, the conductive member 5 is electrically isolated from the first conductive shielding layer 4 .

[0055] In one embodiment, an underfill 9 is provided between the first conductive shielding layer 4, the first plastic packaging layer 3 and the second chip 6. The underfill 9 is beneficial for improving the stability of the semiconductor packaging structure.

[0056] In one embodiment, the semiconductor package structure further includes a second plastic packaging layer 10 , wherein the second plastic packaging layer 10 covers the sidewalls of the second chip 6 and the top surface of the second chip 6 facing away from the first plastic packaging layer 3 .

[0057] In one embodiment, the material of the second plastic packaging layer 10 includes epoxy resin and additives, and the additives include a hardener, a filler, a flame retardant, etc.

[0058] In one embodiment, a side of the redistribution structure 1 facing away from the first chip 2 has a plurality of second solder balls 11 , and the second solder balls 11 are electrically connected to the redistribution structure 1 .

[0059] In one embodiment, a second metal layer is further provided between the redistribution structure 1 and the second solder ball 11 .

[0060] Example 2

[0061] The difference between the semiconductor package structure provided in this embodiment and the semiconductor package structure provided in the previous embodiment is that Figure 2 , further comprising: a second conductive shielding layer 12 located on the sidewalls and top surface of the second plastic packaging layer 10 and surrounding the second chip 6.

[0062] In one embodiment, the thickness of the second conductive shielding layer 12 is 50nm-5um, for example, 100nm; if the thickness of the second conductive shielding layer is less than 50nm, the thickness of the second conductive shielding layer is too thin, and the degree of electromagnetic shielding effect on the second chip is too small; if the thickness of the second conductive shielding layer is greater than 5um, the thickness of the second conductive shielding layer is too thick, and the degree of reducing the volume of the semiconductor packaging structure is too small.

[0063] In one embodiment, the second conductive shielding layer 12 plays the role of electromagnetic shielding. The material of the second conductive shielding layer 12 can be conductive glue or conductive metal, wherein the conductive filler of the conductive glue can be silver, copper, aluminum, zinc, iron, nickel powder and graphite and some conductive compounds, and the conductive metal is copper, aluminum, zinc, iron, nickel or alloy.

[0064] In one embodiment, the second conductive shielding layer 12 is connected to the first conductive shielding layer 4 .

[0065] In one embodiment, the second chip 6 includes a radio frequency chip.

[0066] The parts of this embodiment that are the same as the previous embodiment will not be described in detail.

[0067] Example 3

[0068] This embodiment provides a method for preparing a semiconductor packaging structure. Figure 3 , including the following steps:

[0069] Step S1: forming a first chip and a first plastic packaging layer that wraps the sidewalls and back of the first chip;

[0070] Step S2: forming a first annular opening in the first plastic packaging layer on a peripheral side of the first chip;

[0071] Step S3: forming a first conductive shielding layer on the sidewall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip;

[0072] Step S4: forming a conductive member in the first opening;

[0073] Step S5: flip-chipping a second chip vertically stacked with the first chip on a side of the first conductive shielding layer facing away from the first chip, wherein the second chip is electrically connected to the conductive member;

[0074] Step S6: forming a redistribution structure on the front surface of the first chip and the bottom of the first opening, wherein the redistribution structure is electrically connected to the first chip and the conductive member respectively.

[0075] Reference below Figures 4 to 9 The preparation method of the semiconductor packaging structure is introduced in detail.

[0076] refer to Figure 4 , providing a first carrier 100, forming a first bonding adhesive layer 101 on the first carrier 100, and forming a first chip 2 and a first plastic encapsulation layer 3 that wraps the side walls and back of the first chip 2 includes the following steps: arranging the first chip 2 on one side of the first carrier 100, with the front of the first chip 2 facing the first carrier 100; forming a first plastic encapsulation layer 3 that wraps the side walls and back of the first chip 2 on one side of the first carrier 100, specifically, arranging the first chip 2 on the surface of the side of the first bonding adhesive layer 101 that is away from the first carrier 100, with the front of the first chip 2 facing the first carrier 100; forming a first plastic encapsulation layer 3 that wraps the side walls and back of the first chip 2 on one side of the first carrier 100. Reference Figure 5 A first annular opening is formed in the first plastic packaging layer 3 on the peripheral side of the first chip 2 .

[0077] refer to Figure 6 , a conductive member 5 is formed in the first opening.

[0078] In one embodiment, the conductive member 5 is made of copper.

[0079] In one embodiment, the process of forming the conductive member 5 includes photolithography and electroplating.

[0080] Continue to refer Figure 6 The step of forming a first conductive shielding layer 4 on the side wall surface of the first opening and the surface of the first plastic packaging layer 3 located on the back side of the first chip 2 includes: forming an initial first conductive shielding layer 400 on the bottom and side wall surface of the first opening and the surface of the first plastic packaging layer 3 located on the back side of the first chip 2; after forming the initial first conductive shielding layer 400, forming a conductive member 5 in the first opening, and one end of the conductive member 5 is in contact with the initial first conductive shielding layer 400 at the bottom of the first opening.

[0081] In one embodiment, continue to refer to Figure 6Before the second chip 6 vertically stacked with the first chip 2 is flip-chip arranged on the side of the first conductive shielding layer 4 facing away from the first chip 2, the method further includes: forming a filling plastic layer in the first opening to surround the side wall of the conductive part 5.

[0082] In one embodiment, the step of forming the filling plastic packaging layer and the conductive part also includes: forming an initial conductive part in the first opening, and then forming an initial filling plastic packaging layer in the first opening and on the side of the first conductive shielding layer away from the first chip; thinning the initial filling plastic packaging layer and the initial conductive part so that the initial filling plastic packaging layer forms a filling plastic packaging layer and the initial conductive part forms a conductive part.

[0083] refer to Figure 7 , further comprising: after forming the filling plastic layer, forming a first metal layer 7 on the surface of the conductive part 5 on the side away from the front of the first chip 2; forming a first solder ball 8 on the surface of the first metal layer 7 on the side away from the conductive part 5; the first solder ball 8 is electrically connected to the second chip 6.

[0084] Continue to refer Figure 7 The method for preparing the semiconductor package structure further includes: forming a second plastic encapsulation layer 10 on the sidewall of the second chip 6 and the top surface of the second chip 6 away from the first plastic encapsulation layer 3. Figure 8 , provide a second carrier 200 , form a second bonding adhesive layer 201 on a surface of the second plastic encapsulation layer 10 facing away from the first chip, and bond the second bonding adhesive layer 201 to the second carrier 200 .

[0085] refer to Figure 8 The method for preparing the semiconductor package structure further includes: after flip-chipping the second chip 6 vertically stacked with the first chip 2 on the side of the first conductive shielding layer 4 facing away from the first chip 2, and before forming the redistribution structure 1 on the front surface of the first chip 2 and at the bottom of the first opening, removing the first carrier 100. Specifically, after bonding the second bonding adhesive layer 201 to the second carrier 200, the first carrier 100 is removed.

[0086] Continue to refer Figure 8 , removing the initial first conductive shielding layer 400 at the bottom of the first opening until the conductive member 5 is exposed, and forming the initial first conductive shielding layer 400 into the first conductive shielding layer 4 .

[0087] Continue to refer Figure 8 , further comprising: forming a plurality of second solder balls 11 on a side of the redistribution structure 1 away from the first chip 2 , wherein the second solder balls 11 are electrically connected to the redistribution structure 1 .

[0088] refer to Figure 9 After forming the redistribution structure 1 on the front side of the first chip 2 and the bottom of the first opening, the second carrier 200 and the second bonding adhesive layer 201 are removed. Specifically, after forming a plurality of second solder balls 11 on the surface of the redistribution structure 1 facing away from the first chip 2, the second carrier 200 and the second bonding adhesive layer 201 are removed. Thereafter, the second plastic encapsulation layer 10, the first conductive shielding layer 4, the first plastic encapsulation layer 3 and the redistribution structure 1 on the side of the second chip 6 are cut.

[0089] In one embodiment, after the rewiring structure 1 is formed on the front side of the first chip 2 and the bottom of the first opening, and before a plurality of second solder balls 11 are formed on the side of the rewiring structure 1 facing away from the first chip 2, it also includes: forming a second metal layer on a portion of the surface of the side of the rewiring structure 1 facing away from the first chip 2, and after the second metal layer is formed, forming a plurality of second solder balls 11 on the surface of the side of the second metal layer facing away from the rewiring structure 1, and the second metal layer is located between the rewiring structure 1 and the second solder balls 11.

[0090] The method for preparing the semiconductor packaging structure provided in this embodiment is compatible with existing processes and has process feasibility.

[0091] Example 4

[0092] This embodiment provides a method for preparing a semiconductor package structure. The difference from the method for preparing a semiconductor package structure provided in the previous embodiment is that, in combination with the reference Figures 10 to 12 , Figure 10 for Figure 7 The basic diagram above also includes: forming a second conductive shielding layer 12 surrounding the second chip 6 on the sidewall and top surface of the second plastic packaging layer 10.

[0093] In one embodiment, the specific steps of forming the second conductive shielding layer 12 include: before bonding the side of the second chip 6 facing away from the first chip 2 to the second carrier 200, forming an annular second opening in the second plastic encapsulation layer 10 on the peripheral side of the second chip 6; forming an initial second conductive shielding layer on the bottom and sidewall surfaces of the second opening and on the surface of the second plastic encapsulation layer 10 located on the back side of the second chip 6; and forming a second bonding adhesive layer 201 on the second opening and the side of the second plastic encapsulation layer 10 facing away from the first plastic encapsulation layer 3. Providing a second carrier 200, bonding the second bonding adhesive layer 201 to the second carrier 200, then forming the redistribution structure 1 and the second solder balls 11, then removing the second carrier 200 and the second bonding adhesive layer 201, and then cutting the semiconductor package structure along a cutting line perpendicular to the bottom surface of the second opening and passing through the second opening.

[0094] The parts of this embodiment that are the same as the previous embodiment will not be described in detail.

[0095] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: Rewiring structure; A first chip flip-chip mounted on one side of the redistribution structure, wherein the first chip is electrically connected to the redistribution structure; a first plastic packaging layer, located on one side of the redistribution structure and covering the first chip; a first annular opening in the first plastic packaging layer located on a peripheral side of the first chip; a first conductive shielding layer located on a sidewall surface of the first opening and a surface of the first plastic packaging layer on a side facing away from the redistribution structure; a conductive member located in the first opening, the conductive member being electrically connected to the redistribution structure at the bottom of the first opening; The second chip is flip-chip mounted on a side of the first conductive shielding layer and the first plastic packaging layer away from the redistribution structure, and the second chip is electrically connected to the conductive member.

2. The semiconductor package structure according to claim 1, wherein: Also includes: a first metal layer, located between the second chip and the conductive member; A first solder ball is located between the first metal layer and the second chip.

3. The semiconductor package structure according to claim 1, wherein: The thickness of the first conductive shielding layer is 50nm-5um.

4. The semiconductor package structure according to claim 1, wherein: A filling plastic layer is provided, wherein the filling plastic layer is located in the first opening and surrounds the sidewall of the conductive component.

5. The semiconductor package structure according to claim 1, wherein: The conductive member is electrically isolated from the first conductive shielding layer.

6. The semiconductor package structure according to claim 1, wherein: Also includes: A second plastic packaging layer covers the sidewalls of the second chip and a top surface of the second chip facing away from the first plastic packaging layer.

7. The semiconductor package structure according to claim 6, wherein: Also includes: a second conductive shielding layer located on the sidewalls and top surface of the second plastic packaging layer and surrounding the second chip; The thickness of the second conductive shielding layer is 50nm-5um.

8. The semiconductor package structure according to claim 1, wherein: A side of the redistribution structure facing away from the first chip has a plurality of second solder balls, and the second solder balls are electrically connected to the redistribution structure.

9. A method for preparing a semiconductor packaging structure, characterized in that: include: forming a first chip and a first plastic encapsulation layer wrapping the sidewalls and back surface of the first chip; forming a first annular opening in the first plastic packaging layer on a peripheral side of the first chip; forming a first conductive shielding layer on the sidewall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip; forming a conductive member in the first opening; A second chip is flip-chip mounted on a side of the first conductive shielding layer facing away from the first chip and vertically stacked with the first chip, wherein the second chip is electrically connected to the conductive member; A redistribution structure is formed on the front surface of the first chip and the bottom of the first opening, and the redistribution structure is electrically connected to the first chip and the conductive member respectively.

10. The method for preparing a semiconductor package structure according to claim 9, wherein: Also includes: providing a first slide and a second slide; The step of forming a first chip and a first plastic encapsulation layer that wraps the sidewalls and back surface of the first chip includes: arranging the first chip on one side of the first carrier, with the front surface of the first chip facing the first carrier; forming a first plastic encapsulation layer that wraps the sidewalls and back surface of the first chip on one side of the first carrier; The preparation method of the semiconductor packaging structure also includes: after flip-chip arranging a second chip vertically stacked with the first chip on the side of the first conductive shielding layer facing away from the first chip, bonding the second chip to the second carrier on the side facing away from the first chip; after bonding the second chip to the second carrier on the side facing away from the first chip, removing the first carrier before forming a redistribution structure on the front side of the first chip and the bottom of the first opening; removing the second carrier after forming the redistribution structure on the front side of the first chip and the bottom of the first opening.

11. The method for preparing a semiconductor package structure according to claim 9, wherein: The step of forming a first conductive shielding layer on the side wall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip includes: forming an initial first conductive shielding layer on the bottom and side wall surface of the first opening and the surface of the first plastic packaging layer located on the back side of the first chip; after forming the initial first conductive shielding layer, forming a conductive member in the first opening, one end of the conductive member contacts the initial first conductive shielding layer at the bottom of the first opening; removing the initial first conductive shielding layer at the bottom of the first opening until the conductive member is exposed, and the initial first conductive shielding layer forms a first conductive shielding layer.

12. The method for preparing a semiconductor package structure according to claim 9, wherein: Before a second chip vertically stacked with the first chip is flip-chip mounted on a side of the first conductive shielding layer facing away from the first chip, the method further includes: forming a filling plastic layer in the first opening to surround the sidewall of the conductive member; The step of forming the filling plastic encapsulation layer and the conductive member further includes: forming an initial conductive member in the first opening, and then forming an initial filling plastic encapsulation layer in the first opening and on a side of the first conductive shielding layer facing away from the first chip; thinning the initial filling plastic encapsulation layer and the initial conductive member so that the initial filling plastic encapsulation layer forms a filling plastic encapsulation layer and the initial conductive member forms a conductive member; It also includes: after forming the filling plastic layer, forming a first metal layer on the side surface of the conductive part away from the front surface of the first chip; forming a first solder ball on the side surface of the first metal layer away from the conductive part; and electrically connecting the first solder ball to the second chip.

13. The method for preparing a semiconductor package structure according to claim 9, wherein: Also includes: A plurality of second solder balls are formed on a side of the redistribution structure away from the first chip, and the second solder balls are electrically connected to the redistribution structure.

14. The method for preparing a semiconductor package structure according to claim 9, wherein: Also includes: forming a second plastic encapsulation layer on the sidewalls of the second chip and the top surface of the second chip facing away from the first plastic encapsulation layer; The method further includes forming a second conductive shielding layer surrounding the second chip on the sidewalls and top surface of the second plastic packaging layer.

Images