Semiconductor structure and manufacturing method

Abstract

This application discloses a semiconductor structure and its manufacturing method. The semiconductor structure includes: a gate stack structure comprising alternating stacked conductor layers and multiple insulating layers; multiple channel pillars penetrating the gate stack structure; and multiple dummy gate lines penetrating the gate stack structure. At least one dummy gate line is discontinuous along a direction perpendicular to the multiple channel pillars. The discontinuous dummy gate line has insulating sidewalls and conductive material filling the insulating sidewalls at both the portions located on the channel pillars and the portions located on the dummy gate pillars. This semiconductor structure has discontinuous dummy gate lines, which helps to improve the bottom shape of the gate gap, thereby improving the yield and reliability of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more specifically, to a semiconductor structure and its manufacturing method. Background Technology

[0002] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0003] Existing 3D memory devices are primarily used as non-volatile flash memory. The two main non-volatile flash memory technologies employ NAND and NOR structures, respectively. Compared to NOR memory devices, NAND memory devices have slightly slower read speeds but faster write speeds, simpler erase operations, and can achieve smaller storage cells, thus enabling higher storage density. Therefore, 3D memory devices using the NAND structure have gained widespread application.

[0004] In the semiconductor structure of NAND 3D memory devices, a stacked structure is used to provide conductor layers for selection transistors and memory cells, with the memory cells connected to the source via gate line gaps. As the number of layers in the stacked structure increases, the high aspect ratio (HAR) of the stacked structure during the formation of the gate line gaps can cause structural twisting of the gate line gaps, making them prone to short circuits with surrounding memory cells and even causing device damage.

[0005] Therefore, there is an urgent need to further improve the existing semiconductor structures and manufacturing methods to solve the above problems. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, wherein at least one dummy gate line is discontinuous, thereby improving the bottom shape of the gate line gap.

[0007] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a substrate; a gate stack structure located on the substrate, the gate stack structure comprising a plurality of alternately stacked conductor layers and a plurality of insulating layers; a plurality of channel pillars penetrating the gate stack structure; a plurality of dummy gate lines penetrating the gate stack structure; wherein at least one of the dummy gate lines is discontinuous in a direction perpendicular to the plurality of channel pillars.

[0008] Preferably, it further includes: a plurality of dummy channel posts penetrating the gate stack structure, wherein the dummy gate lines are discontinuous in the transition regions between the plurality of dummy channel posts and the plurality of channel posts.

[0009] Preferably, it further includes: a plurality of conductive channels penetrating the gate stack structure, wherein the conductive channels are parallel to the dummy gate lines, and each of the conductive channels is continuous along a direction perpendicular to the plurality of channel posts.

[0010] Preferably, the conductive channel and the dummy gate line have insulating sidewalls and conductive material filled within the insulating sidewalls.

[0011] Preferably, the plurality of conductive channels are electrically connected to one or more of the channel posts to form a common source conductive channel.

[0012] Preferably, the plurality of channel posts are located in the core region of the grid stack structure, and the plurality of dummy channel posts are located in the stepped region of the grid stack structure.

[0013] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming an insulating stack structure on a substrate, the insulating stack structure comprising a plurality of sacrificial layers and a plurality of insulating layers stacked alternately; forming a plurality of channel pillars penetrating the insulating stack structure; forming a plurality of gate line slots penetrating the insulating stack structure; replacing the plurality of sacrificial layers in the insulating stack structure with a plurality of conductive layers to form a gate stack structure; wherein at least one of the gate line slots is discontinuous along a direction perpendicular to the plurality of channel pillars.

[0014] Preferably, it further includes: forming a plurality of dummy trench posts that penetrate the insulating laminate structure, wherein the grid line gaps are discontinuous in the transition region between the plurality of dummy trench posts and the plurality of trench posts.

[0015] Preferably, it further includes: an insulating sidewall forming the gate line gap; and a conductive material filling the interior of the insulating sidewall, wherein the insulating sidewall and the conductive material located in the discontinuous gate line gaps form dummy gate lines.

[0016] Preferably, at least one of the grid line slots is continuous along a direction perpendicular to the plurality of channel posts, and the insulating sidewalls and the conductive material located in the continuous grid line slots form a conductive channel.

[0017] The semiconductor structure and manufacturing method provided by the present invention have at least one discontinuous dummy gate line, eliminating the need to form a gate line gap in the discontinuous region. This reduces the time required to etch the gate line gap, significantly reduces the probability of distortion at the bottom of the gate line gap, and reduces the length of the dummy gate line, which helps to improve the bottom shape of the gate line gap, thereby improving the yield and reliability of the semiconductor structure. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0019] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively.

[0020] Figure 2 A perspective view of a 3D storage device is shown.

[0021] Figure 3 A top view of the 3D storage device is shown.

[0022] Figure 4a and 4b Cross-sectional views of traditional 3D storage device manufacturing methods are shown.

[0023] Figure 5a A partial top view of a conventional 3D storage device is shown.

[0024] Figure 5b A partial top view of a 3D storage device according to an embodiment of the present invention is shown.

[0025] Figures 6a to 6f Cross-sectional views are shown of various stages of the 3D storage device manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0026] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0027] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0028] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0029] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0030] This invention can be presented in various forms, some of which will be described below.

[0031] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0032] like Figure 1a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string select line SSL, and the gate of the second selection transistor Q2 is connected to the ground select line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0033] like Figure 1bAs shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 each include gate conductors 122 and 123, and the memory transistors M1 to M4 each include a gate conductor 121. The gate conductors 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are sandwiched between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110, the gate conductors 122 and 123 are sandwiched between the gate conductors 122 and 123 and the channel layer 111, thereby forming the first selection transistor Q1 and the second selection transistor Q2. This embodiment only shows four storage transistors as an example. It can be understood that the present invention is not limited to this, and the number of storage transistors can be any number.

[0034] In this embodiment, the channel layer 111 is composed, for example, of doped polysilicon; the tunneling dielectric layer 112 and the barrier dielectric layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the gate conductors 121, 122, and 123 are composed of metals, such as tungsten. The channel layer 111 provides the channel region for the select transistor and the storage transistor, and the doping type of the channel layer 111 is the same as the type of the select transistor and the storage transistor. For example, for an N-type select transistor and a storage transistor, the channel layer 111 can be N-type doped polysilicon.

[0035] In this embodiment, the core of the channel post 110 is a channel layer 111, and the tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a gate stack structure surrounding the sidewalls of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 form a gate stack structure surrounding the core.

[0036] In this embodiment, the first selection transistor Q1, the second selection transistor Q2, and the storage transistors M1 to M4 use a common channel layer 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel layer 111 provides the source / drain regions and channel layer for the plurality of transistors. In an alternative embodiment, the epitaxial layers and barrier dielectric layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the epitaxial layers and barrier dielectric layers of the storage transistors M1 to M4, can be formed in separate steps.

[0037] During the write operation, the memory cell string 100 utilizes FN tunneling efficiency to write data to selected memory transistors among memory transistors M1 to M4. Taking memory transistor M2 as an example, while the source line SL is grounded, the ground select line GSL is biased to approximately zero volts, causing the select transistor Q2 corresponding to the ground select line GSL to turn off, and the string select line SSL is biased to a high voltage VDD, causing the select transistor Q1 corresponding to the string select line SSL to turn on. Further, the bit line BIT2 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, around 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charge and storing it in the charge storage layer 113 of the memory transistor M2.

[0038] During the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer based on the conduction state of selected memory transistors M1 to M4, thereby obtaining the data represented by that charge amount. Taking memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, while the other word lines are biased at a high voltage VPS2. The conduction state of memory transistor M2 is related to its threshold voltage, i.e., related to the amount of charge in the charge storage layer, thus the data value can be determined based on the conduction state of memory transistor M2. Memory transistors M1, M3, and M4 are always in the conduction state; therefore, the conduction state of memory cell string 100 depends on the conduction state of memory transistor M2. The control circuit determines the conduction state of memory transistor M2 based on the electrical signals detected on bit line BL and source line SL, thereby obtaining the data stored in memory transistor M2.

[0039] Figure 2 A perspective view of the 3D storage device is shown. For clarity, [the view is shown in the original text]. Figure 2 The individual insulating layers in the 3D storage device are not shown.

[0040] The 3D storage device 200 shown in this embodiment includes 16 4x4 storage cell strings 100, each storage cell string 100 including 4 storage cells, thereby forming a 4x4x4 storage cell array with a total of 64 storage cells. It is understood that the present invention is not limited thereto; the 3D storage device may include any number of storage cell strings, for example, 1024, and the number of storage cells in each storage cell string may be any number, for example, 32 or 64.

[0041] In the 3D memory device, each memory cell string includes its own channel pillar 110 and a common gate conductor layer 121, 122, and 123. The gate conductor layers 121, 122, and 123 are arranged in the same order as the transistors in the memory cell string 100. Adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0042] The internal structure of the channel column 110 is as follows Figure 1b As shown, further details will not be provided here. In the middle portion of the channel pillar 110, the gate conductor layer 121, together with the channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 inside the channel pillar 110, forms storage transistors M1 to M4. At both ends of the channel pillar 110, the gate conductor layers 122 and 123, together with the channel layer 111 and barrier dielectric layer 114 inside the channel pillar 110, form selection transistors Q1 and Q2.

[0043] The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are connected to the same bit line (i.e., one of bit lines BL1 to BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 101.

[0044] The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 161. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0045] The gate conductors 121 of the storage transistors M1 and M4 are connected together on different layers. If the gate conductors 121 of the storage transistors M1 and M4 are divided into different gate lines by gate line gaps, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 133.

[0046] The gate conductors of the second selection transistor Q2 are connected as one. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line gap 161, the gate lines reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same ground selection line GSL through the conductive channel 133.

[0047] In other embodiments, the 3D memory device 200 has multiple dummy channel pillars (not shown) in the non-memory region. The internal structure of the dummy channel pillars may be the same as or different from that of the channel pillar 110, and they at least penetrate at least a portion of the gate conductor in the gate stack structure. In the final 3D memory device, the dummy channel pillars are not connected to bit lines, thus providing only mechanical support and not used to form select transistors and memory transistors. Therefore, the dummy channel pillars do not form effective memory cells.

[0048] Figure 3 A top view of the 3D storage device is shown. Figure 4a and 4b Cross-sectional views of conventional 3D storage device manufacturing methods are shown. The cross-sectional views are along... Figure 2 The AA line in the middle is cut off.

[0049] like Figure 3 As shown, the 3D memory device includes multiple gate stack structures 120, each gate stack structure 120 having multiple channel pillars (see...). Figure 2 Each gate stack 120 is separated by gate line slots 161, and the gate line slots 161 provide a conductive path between the select transistor and the common source line. The 3D memory device is connected to external circuitry via pads 170, which also have gate line slots 161 between them.

[0050] During the process of forming the grid line gap 161, such as Figure 4a As shown, an insulating stack structure 150 is formed on a substrate 101 by alternating stacks of insulating layer 151 and sacrificial layer 152, and plasma etching is performed on the insulating stack structure 150 to form gate line gaps 161. The substrate 101 is, for example, a single-crystal silicon substrate, the insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride. For clarity, in Figure 4a The channel column is not shown.

[0051] Because the insulating stack structure 150 has a high aspect ratio (HAR), as the plasma etching progresses and the etching process is relatively long, positive charges will accumulate around the bottom of the gate line slot 161, and the trajectory of the accumulated plasma will change, resulting in the bottom of the gate line slot 161 twisting, such as... Figure 4b As shown. Twisting at the bottom of the gate line slot 161 can cause word line leakage, which may damage the 3D memory device and reduce its yield and reliability.

[0052] Figure 5a A partial top view of a conventional 3D storage device is shown; Figure 5bA partial top view of a 3D storage device according to an embodiment of the present invention is shown.

[0053] like Figure 5a As shown, in 3D storage devices, there is a through-gate stack structure (see...). Figure 2 The 3D memory device comprises multiple channel pillars 110 and multiple dummy channel pillars 140. Gate line gaps are provided between the various gate stack structures, which will provide a conductive path 160 between the select transistor and the common source line. In this embodiment, dummy gate lines 180 (DGLs) are formed in some of the gate line gaps. The dummy gate lines 180 are made of the same material and have the same structure as the conductive path 160, but the dummy gate lines 180 in the 3D memory device are not used to provide data transmission to external circuitry. For example, the dummy gate lines 180 may not be electrically connected to the gate in the channel pillar 110, or if the dummy gate lines 180 are electrically connected to the gate of the dummy channel pillar 140, or the dummy gate lines 180 may remain electrically floating during operation of the 3D memory device, thus electrically isolating some channel pillars 110 from others.

[0054] like Figure 5b As shown, in 3D storage devices, there is a through-gate stack structure (see...). Figure 2 The gate stack has multiple channel pillars 110 and multiple dummy channel pillars 140, with gate line gaps between each gate stack structure. Some gate line gaps will provide a conductive path 160 between the select transistor and the common source line, while other gate line gaps form dummy gate lines 180.

[0055] In this embodiment, at least one dummy gate line 180 is discontinuous. Since it is not necessary to form a gate line gap in this discontinuous region, the time required to etch the gate line gap is reduced, the probability of distortion at the bottom of the gate line gap is greatly reduced, and reducing the length of the dummy gate line 180 helps to improve the bottom shape of the gate line gap, thereby improving the yield and reliability of the 3D memory device. Preferably, multiple channel pillars 110 are formed in the core region of the gate stack structure, multiple dummy channel pillars 140 are formed in the stepped region of the gate stack structure, and the discontinuous region of the dummy gate line 180 is formed in the transition region between the multiple channel pillars 110 and the multiple dummy channel pillars 140.

[0056] In a preferred embodiment, to enable data reading and programming operations of the 3D storage device, each storage cell block formed by the gate stack structure has two continuous conductive channels 160; between the two continuous conductive channels 160 are multiple dummy gate lines 180, at least one of which is discontinuous. Preferably, all of the multiple dummy gate lines 180 are discontinuous.

[0057] Figures 6a to 6f Cross-sectional views are shown at various stages of a 3D memory device manufacturing method according to an embodiment of the present invention. The cross-sectional views are along... Figure 2 The AA line in the middle is cut off.

[0058] This method begins with a semiconductor structure that has already formed the channel pillar 110, such as Figure 6a As shown.

[0059] An insulating stack structure 150, consisting of alternating stacked insulating layers 151 and sacrificial layers 152, is formed on a substrate 101, along with channel pillars 110 extending through the insulating stack structure 150. As described below, the sacrificial layer 152 will be replaced by a conductor layer. In this embodiment, the substrate 101 is, for example, a single-crystal silicon substrate, the insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride.

[0060] For clarity, in Figure 6a The internal structure of the channel column 110 is not shown. See also Figure 1b In the middle portion of the channel post 110, the channel post 110 includes a channel layer 111, a tunneling dielectric layer 112, a charge storage layer 113 and a barrier dielectric layer 114 stacked in sequence. At both ends of the channel post 110, the channel post 110 includes a channel layer 111 and a barrier dielectric layer 114 stacked in sequence.

[0061] Furthermore, for example, a photoresist mask is formed on the surface of the semiconductor structure, followed by anisotropic etching to form gate line gaps 161 in the insulating stack structure 150, such as... Figure 6b As shown. In order to form dummy grid lines, at least one grid line gap 161 is discontinuous along a direction perpendicular to the plurality of channel posts 110 (see...). Figure 5b (Dummy gate line 180 in the diagram). In some embodiments, to form a conductive channel, at least one gate line slot 161 is continuous along a direction perpendicular to the plurality of channel posts 110 (see [reference]). Figure 5b Conductive channel 160 in the middle.

[0062] In a preferred embodiment, in order to realize data reading and programming operations of the 3D storage device, each storage cell block has two continuous gate line gaps 161, which are used to form a conductive channel; there is at least one discontinuous gate line gap 161 between the two continuous gate line gaps 161, preferably, there are multiple discontinuous gate line gaps 161 between the two continuous gate line gaps 161, which are used to form dummy gate lines.

[0063] Anisotropic etching can be performed using dry etching methods, such as ion milling, plasma etching, reactive ion etching, and laser ablation. For example, the etching time can be controlled so that etching stops near the surface of substrate 101. After etching, the photoresist mask is removed by dissolving in a solvent or ashing.

[0064] In this embodiment, the gate line gap 161 is not only used to divide the gate conductor into multiple gate lines. For this purpose, the gate line gap 161 extends through the stacked structure 150 to the substrate 101.

[0065] Preferably, ion implantation is performed via gate gap 161 to form an N-type (using N-type dopant, such as P, As) or P-type (using P-type dopant, such as B) doped region 102 in the substrate 101. The doped region 102 serves as a contact region for common source connection, reducing the contact resistance between the subsequently formed conductive channel and the substrate 101.

[0066] Furthermore, using the gate gap 161 as an etchant channel, isotropic etching is employed to remove the sacrificial layer 152 in the insulating stack structure 150, thereby forming the cavity 162, as shown below. Figure 6c As shown.

[0067] Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etchant solution is used as the etchant, in which the semiconductor structure is immersed in the etchant solution. In vapor phase etching, an etching gas is used as the etchant, in which the semiconductor structure is exposed to the etching gas. In the case where the insulating layer 151 and sacrificial layer 152 in the insulating stack structure 150 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution can be used as the etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 can be used in vapor phase etching. During the etching step, the etchant fills the gate line slots 161. The ends of the sacrificial layer 152 in the insulating stack structure 150 are exposed in the openings of the gate line slots 161, thus the sacrificial layer 152 contacts the etchant. The etchant gradually etches the sacrificial layer 152 into the interior of the insulating stack structure 150 from the openings of the gate line slots 161. Due to the selectivity of the etchant, the etching removes the sacrificial layer 152 relative to the insulating layer 151 in the insulating stack structure 150.

[0068] Preferably, after the wet etching step described above, an additional etching step can be used to remove the etching products (e.g., silicon oxide) attached to the insulating layer 151, so that the exposed surface of the insulating layer 151 in the cavity 162 is flat.

[0069] Furthermore, utilizing the gate gaps 161 as deposition channels, atomic layer deposition (ALD) is employed to fill the gate gaps 161 and cavities 162 with conductive material 154, such as... Figure 6d As shown.

[0070] In this embodiment, the conductive material 154 is, for example, composed of tungsten. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride (WF6), and the reducing gas used is, for example, silane (SiH4) or diborane (B2H6). In the atomic layer deposition step, the tungsten material is obtained by the chemisorption of the reaction product of tungsten hexafluoride (WF6) and silane (SiH4), thus achieving the deposition process.

[0071] Furthermore, a photoresist mask is formed on the surface of the semiconductor structure, followed by etchback to reform the gate line gaps 161 in the conductive material 154, as shown. Figure 6e As shown.

[0072] This etching process uses sulfur fluoride, nitrogen, and chlorine as etchants to remove the tungsten material from the gate line slot 161. Furthermore, the gate line slot 161 not only separates the conductive material 154 into different layers to form conductor layers 121, 122, and 123, but also divides each layer of conductor layers into multiple conductive lines. The conductor layers 121, 122, and 123 formed in this step are alternately stacked with the insulating layer 151 to form a gate stack structure 120. Compared to the insulating stack structure 150, the conductor layers 121, 122, and 123 in the gate stack structure 120 replace the sacrificial layer 152 in the insulating stack structure 150.

[0073] Furthermore, an insulating layer 163 is formed on the sidewall of the gate wire gap 161, and a conductive material is filled into the gate wire gap 161 to form a dummy gate wire 180, such as... Figure 6f As shown.

[0074] In this embodiment, a conductive channel (not shown) is formed simultaneously with the formation of the dummy gate line 180. The method for manufacturing the conductive channel is similar to... Figures 6a to 6f The manufacturing method shown is largely the same, except that, when forming the conductive channel, the process of forming such a method is different. Figure 6b When the grid line slot 161 is shown, viewed from a direction perpendicular to the plurality of channel posts 110, the grid line slot 161 is continuous (see [reference]). Figure 5b The conductive channel is connected to the substrate 100 through the doped region 102. As described above, the channel pillar 110 forms a common source connection through the substrate 100 and provides a conductive path from the common source to the source line SL through the conductive channel 160.

[0075] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0076] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor structure, characterized in that, include: A gate stack structure comprising alternating stacked conductor layers and multiple insulating layers; Multiple channel posts penetrate the grid stack structure; Multiple dummy channel posts penetrate the grid stack structure; Multiple dummy gate lines penetrate the gate stack structure; Wherein, at least one of the dummy gate lines is discontinuous along a direction perpendicular to the plurality of channel posts, and the discontinuous dummy gate line has an insulating sidewall and a conductive material filling the insulating sidewall in the portion located at the channel post and the portion located at the dummy channel post.

2. The semiconductor structure according to claim 1, characterized in that, The dummy grid lines are discontinuous in the transition region between the plurality of dummy trench posts and the plurality of trench posts.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: Multiple conductive channels extend through the gate stack structure. The conductive channels are parallel to the dummy gate lines, and each of the conductive channels is continuous along a direction perpendicular to the plurality of channel posts.

4. The semiconductor structure according to claim 3, characterized in that, The conductive channel has insulating sidewalls and conductive material filled within the insulating sidewalls.

5. The semiconductor structure according to claim 3, wherein, The plurality of conductive channels are electrically connected to one or more of the channel posts to form a common source conductive channel.

6. The semiconductor structure according to claim 2, characterized in that, The plurality of channel posts are located in the core region of the grid stack structure, and the plurality of dummy channel posts are located in the stepped region of the grid stack structure.

7. The semiconductor structure according to claim 1, characterized in that, The distribution density of the channel columns is greater than that of the dummy channel columns.

8. The semiconductor structure according to claim 1, characterized in that, The dummy gate line is not electrically connected to the gate in the channel pillar, or the dummy gate line remains electrically floating when the semiconductor structure is in operation, thereby electrically isolating one portion of the plurality of channel pillars from another portion.

9. A method for manufacturing a semiconductor structure, characterized in that, include: An insulating laminate structure is formed, the insulating laminate structure comprising alternating stacked sacrificial layers and multiple insulating layers; Multiple channel pillars are formed that penetrate the insulating laminate structure; Multiple dummy channel pillars are formed that penetrate the insulating laminate structure; Multiple gate wire gaps are formed that penetrate the insulating laminate structure; The multiple sacrificial layers in the insulating stacked structure are replaced with multiple conductor layers to form a gate stacked structure; Insulating sidewalls forming the grid wire gaps; and A conductive material is formed to fill the interior of the insulating sidewalls. The insulating sidewalls and conductive material located in the discontinuous grid line gaps form dummy grid lines. The discontinuous dummy grid lines have the insulating sidewalls and the conductive material filled in the insulating sidewalls in both the portions located at the channel posts and the portions located at the dummy channel posts. At least one of the grid line gaps is discontinuous in a direction perpendicular to the plurality of channel posts.

10. The manufacturing method according to claim 9, characterized in that, The grid line gaps are discontinuous in the transition region between the plurality of dummy trench posts and the plurality of trench posts.

11. The manufacturing method according to claim 9, characterized in that, The distribution density of the channel columns is greater than that of the dummy channel columns.

12. The manufacturing method according to claim 9, characterized in that, At least one of the grid line slots is continuous along a direction perpendicular to the plurality of channel posts, and the insulating sidewalls and the conductive material located in the continuous grid line slots form a conductive channel.

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