Semiconductor devices and data storage systems including semiconductor devices

Abstract

A semiconductor device includes: a structure comprising a stacked structure, the stacked structure including a first stacked structure and a second stacked structure on the first stacked structure; a storage vertical structure extending through the structure; a supporting vertical structure including a portion extending through the structure and including an air gap; and a peripheral contact plug, wherein the first stacked structure and the second stacked structure include alternately stacked interlayer insulating layers and gate layers, the side portion of the storage vertical structure includes a slope-changing portion, and the peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer, the upper region of the peripheral contact plug including a first region, a second region, and a connection region between the first region and the second region, and the slope of the connection region is different from the slope of at least one of the first region and the second region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0038071, filed with the Korean Intellectual Property Office on March 24, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of this disclosure relate to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0004] The demand for semiconductor devices offering higher capacity storage potential is constantly increasing compared to semiconductor devices that include two-dimensionally arranged cells. Therefore, semiconductor devices including three-dimensionally arranged memory cells have been developed. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide a semiconductor device that can improve integration density and reliability.

[0006] An exemplary embodiment of this disclosure provides a data storage system including semiconductor devices.

[0007] According to an example embodiment of this disclosure, a semiconductor device includes: a first structure; a second structure including a stacked structure and an intermediate insulating layer covering at least a portion of the stacked structure, the stacked structure including a first stacked structure on the first structure and a second stacked structure on the first stacked structure; an insulating structure on the second structure; a storage vertical structure extending through the second structure; a supporting vertical structure extending through the second structure and including an air gap and a support layer defining at least a lower portion and sidewalls of the air gap; a peripheral contact plug extending through the second structure; and a gate contact plug, wherein each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers, wherein the gate layers are spaced apart from each other in a vertical direction in a first region and include gate pads disposed in a second region adjacent to the first region, wherein the gate contact plug is electrically connected to the gate pads, and wherein the storage vertical structure extends through the stacked structure in the first region. The storage vertical structure includes a slope-changing portion located between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure. The supporting vertical structure penetrates at least a portion of the gate layer in the second region. The air gap of the supporting vertical structure includes a portion disposed at the same height as the slope-changing portion of the storage vertical structure. The peripheral contact plug is spaced apart from the gate layer. The peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the gate layer of the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the gate layer of the stacked structure. The upper region of the peripheral contact plug includes a first portion, a second portion, and a connecting portion disposed between the first portion and the second portion. The connecting portion has a slope different from the slope of at least one of the first portion and the second portion.

[0008] According to an exemplary embodiment of this disclosure, a semiconductor device includes: a patterned structure including a silicon layer; a stacked structure on the patterned structure, including a first stacked structure and a second stacked structure on the first stacked structure, wherein each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers, and in the first stacked structure and the second stacked structure, the gate layers are vertically stacked and spaced apart from each other in a first region, and include gate pads arranged in a stepped shape in a second region adjacent to the first region; an insulating structure on the stacked structure; a separation structure extending through the stacked structure in the first region and the second region and extending in the insulating structure; a storage vertical structure extending through the stacked structure between the separation structures in the first region; a support vertical structure extending through the stacked structure between the separation structures in the second region and including an air gap; a gate contact plug contacting the gate pads; a peripheral contact plug spaced apart from the gate layer; and a bit line contact plug in the storage vertical structure. The peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the gate layer of the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the gate layer of the stacked structure. The upper region of the peripheral contact plug includes a first portion, a connection portion disposed below the first portion, and a second portion disposed below the connection portion. The side of the connection portion has a slope different from the slope of at least one of the side portions of the first portion and the second portion. The side of the storage vertical structure includes a slope variation portion at a height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure. In the slope variation portion, the slope of the side of the storage vertical structure varies. The side of the lower region of the peripheral contact plug is substantially vertical at the height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure.

[0009] According to an example embodiment of this disclosure, a data storage system includes: a motherboard; a semiconductor device on the motherboard; and a controller electrically connected to the semiconductor device on the motherboard, wherein the semiconductor device includes: a patterned structure including a silicon layer; a stacked structure on the patterned structure, including a first stacked structure and a second stacked structure on the first stacked structure, wherein each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers, and in the first stacked structure and the second stacked structure, the gate layers are vertically stacked and spaced apart from each other in a first region, and include gate pads arranged in a stepped shape in a second region adjacent to the first region; an insulating structure on the stacked structure; a separation structure penetrating the stacked structure and extending into the insulating structure in the first region and the second region; a storage vertical structure penetrating the stacked structure between the separation structures in the first region; a support vertical structure penetrating the stacked structure between the separation structures in the second region and including an air gap; and a gate contact plug bonded to the gate. The storage vertical structure includes a disk contact; a peripheral contact plug spaced apart from the gate layer; and a bit line contact plug. The peripheral contact plug comprises an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the stacked structure. The upper region of the peripheral contact plug includes a first portion, a connection portion disposed below the first portion, and a second portion disposed below the connection portion. The side of the connection portion has a slope different from the slope of at least one of the side of the first portion and the side of the second portion. The side of the storage vertical structure includes a slope variation portion at a height between the uppermost gate layer in the first stacked structure and the lowermost gate layer in the second stacked structure. The side of the lower region of the peripheral contact plug is substantially vertical at the height between the uppermost gate layer in the first stacked structure and the lowermost gate layer in the second stacked structure. Attached Figure Description

[0010] The above and other features of this disclosure will be more clearly understood from the following specific embodiments given in conjunction with the accompanying drawings, in which:

[0011] Figure 1 , Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 3C and Figure 3DThis is a diagram illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 4A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0013] Figure 4B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0014] Figure 5A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0015] Figure 5B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0016] Figure 6A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0017] Figure 6B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0018] Figure 7A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0019] Figure 7B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0020] Figure 7C This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0021] Figure 8A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0022] Figure 8B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0023] Figure 9AThis is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0024] Figure 9B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0025] Figure 10A This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0026] Figure 10B This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0027] Figure 11A , Figure 11B and Figure 12 This is a diagram illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0028] Figure 13 This is an enlarged view showing a modified example of a semiconductor device, illustrating a portion of a semiconductor device according to an exemplary embodiment of this disclosure;

[0029] Figure 14 This is a diagram illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0030] Figure 15 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0031] Figure 16A , Figure 16B and Figure 16C This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0032] Figure 17 This is a diagram illustrating a data storage system including semiconductor devices according to an exemplary embodiment of the present disclosure;

[0033] Figure 18 This is a perspective view illustrating a data storage system including semiconductor devices according to an exemplary embodiment of the present disclosure; and

[0034] Figure 19 This is a cross-sectional view illustrating a data storage system including semiconductor devices according to an example embodiment of the present disclosure. Detailed Implementation

[0035] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals may refer to the same elements.

[0036] Reference Figures 1 to 2C Examples of semiconductor devices according to exemplary embodiments of the present disclosure are described. Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2A It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 2B It shows along Figure 1 A cross-sectional view of the region intercepted by line II-II' in the diagram. Figure 2C It shows along Figure 1 A cross-sectional view of the region intercepted by line III-III' in the diagram.

[0037] refer to Figures 1 to 2C The semiconductor device 1 according to an example embodiment of the present disclosure may include a first structure 3 and a second structure 21' that overlaps with the first structure 3 in the vertical direction Z.

[0038] The first structure 3 may include a patterned structure 17'. The patterned structure 17' may include at least one silicon layer.

[0039] The pattern structure 17' may include a first pattern layer 17a, a second pattern layer 17b', a third pattern layer 17c, and a fourth pattern layer 17d. The second pattern layer 17b' and the fourth pattern layer 17d may be spaced apart from each other on the first pattern layer 17a. In other words, the second pattern layer 17b' and the fourth pattern layer 17d may be disposed on the first pattern layer 17a. The third pattern layer 17c may cover the second pattern layer 17b' and the fourth pattern layer 17d on the first pattern layer 17a. The third pattern layer 17c may contact the first pattern layer 17a between the second pattern layer 17b' and the fourth pattern layer 17d. The thickness of the first pattern layer 17a may be greater than the thickness of each of the second pattern layer 17b', the third pattern layer 17c, and the fourth pattern layer 17d. At least one of the first pattern layer 17a, the second pattern layer 17b', the third pattern layer 17c, and the fourth pattern layer 17d may include a silicon layer. For example, the first patterned layer 17a, the second patterned layer 17b', and the third patterned layer 17c may include silicon layers, such as silicon layers with N-type conductivity, while the fourth patterned layer 17d may include a material different from that of the silicon layers. For example, the fourth patterned layer 17d may include multiple layers stacked in sequence, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0040] The first structure 3 may include a semiconductor substrate 4, peripheral circuitry 8 on the semiconductor substrate 4, and a lower insulating layer covering the peripheral circuitry 8 on the semiconductor substrate 4. The peripheral circuitry 8 may include circuit devices 9 such as transistors and circuit interconnects 11 electrically connected to the circuit devices 9, the circuit devices 9 including a peripheral gate 9a and a peripheral source / drain 9b. A portion of the circuit interconnects 11 may be a first peripheral circuit pad 11p1 and a second peripheral circuit pad 11p2.

[0041] The pattern structure 17' can be set on the lower insulating layer 13.

[0042] The pattern structure 17' may also include a ground pattern 18. For example, the ground pattern 18 may be disposed below the first pattern layer 17a and may be grounded to the semiconductor substrate 4 through a portion of the circuit interconnect 11. The ground pattern 18 may extend from the first pattern layer 17a. For example, when the first pattern layer 17a is formed of a silicon layer, the ground pattern 18 may be formed of a silicon layer extending from that silicon layer.

[0043] The pattern structure 17' may have gaps 17g. Each of the gaps 17g may be implemented as a slit or opening through the pattern structure 17'.

[0044] The first structure 3 may also include an inner insulating layer 19a filling the gap 17g and an outer insulating layer 19b disposed on the outside of the pattern structure 17'.

[0045] The second structure 21' may include a first region MCA and a second region SA. The second structure 21' may include stacked structures 23' and 35' disposed in the first region MCA and extending from the first region MCA into the second region SA.

[0046] In the exemplary embodiments of this disclosure, the first region MCA may be a memory cell region, while the second region SA may be a stepped region, an extended region, or a contact region. Hereinafter, for ease of description, the first region MCA will be referred to as the memory cell region, and the second region SA will be referred to as the stepped region.

[0047] Stacked structures 23' and 35' may include a first stacked structure 23' and a second stacked structure 35' on top of the first stacked structure 23'. The first stacked structure 23' may include a first interlayer insulating layer 25 and a first gate layer 27g alternately stacked along a vertical direction Z. The vertical direction Z may be set in a direction perpendicular to the upper surface of the patterned structure 17'. The first gate layer 27g may have a first gate pad 27p arranged in a stepped shape in a stepped region SA.

[0048] The second stacked structure 35' may include a second interlayer insulating layer 38 and a second gate layer 40g that are alternately stacked along the vertical direction Z. The second gate layer 40g may have a second gate pad 40p arranged in a stepped shape in the stepped region SA.

[0049] Interlayer insulating layer 25 and interlayer insulating layer 38 can be formed, and first gate layer 27g and second gate layer 40g can be formed. Therefore, the first stacked structure 23' and the second stacked structure 35' can include interlayer insulating layers 25 and 38 and gate layers 27g and 40g alternately stacked along the vertical direction Z. Gate layers 27g and 40g can have a first gate pad 27p and a second gate pad 40p arranged in a stepped shape in the stepped region SA.

[0050] In an example embodiment of this disclosure, a “gate pad” may be a region in the stepped region SA where the upper part of the gate layer is not covered by another gate layer disposed thereon.

[0051] In the exemplary embodiments of this disclosure, the first gate pad 27p and the second gate pad 40p can be arranged in the stepped shape shown in the figures, and can also be arranged in various stepped shapes.

[0052] The thickness of each of the first gate pad 27p and the second gate pad 40p can be greater than the thickness of each of the first gate layer 27g and the second gate layer 40g disposed in the memory cell array region MCA.

[0053] The first gate layer 27g and the second gate layer 40g may comprise conductive materials. For example, each of the first gate layer 27g and the second gate layer 40g may be formed of two or more of the following materials: doped polycrystalline silicon, metal semiconductor compounds (e.g., TiSi, TaSi, CoSi, NiSi, WSi, etc.), metal nitrides (e.g., TiN, TaN, or WN, etc.), or metals (e.g., Ti or W, etc.). The interlayer insulating layers 25 and 38 may be formed of an insulating material such as silicon oxide.

[0054] The first stacked structure or multilayer structure 23' and the second stacked structure or multilayer structure 35' may further include one or more through regions TA. Each of the through regions TA may further include insulating horizontal layers 27i and 40i disposed at the same height as the first gate layer 27g and the second gate layer 40g adjacent to the through region TA. For example, in the through region TA, the portion of the through region TA adjacent to the first gate layer 27g may include a first insulating horizontal layer 27i disposed at the same height as the first gate layer 27g, and the portion of the through region TA adjacent to the second gate layer 40g may include a second insulating horizontal layer 40i disposed at the same height as the second gate layer 40g.

[0055] In exemplary embodiments of this disclosure, each of the through regions TA may further include reinforcing horizontal layers 28 and 41 that contact the uppermost insulating horizontal layer on the uppermost insulating horizontal layer of the insulating horizontal layers 27i and 40i. For example, a through region TA at a location spaced apart from the second stack structure 35' may include a first reinforcing horizontal layer 28 that contacts the uppermost first insulating horizontal layer of the first insulating horizontal layer 27i. For example, the first reinforcing horizontal layer 28 may cover the uppermost first insulating horizontal layer of the first insulating horizontal layer 27i. A through region TA disposed in the first stack structure 23' and the second stack structure 35' may include a second reinforcing horizontal layer 41 that contacts the uppermost second insulating horizontal layer of the second insulating horizontal layer 40i. For example, the second reinforcing horizontal layer 41 may cover the uppermost second insulating horizontal layer of the second insulating horizontal layer 40i.

[0056] The first insulating horizontal layer 27i and the second insulating horizontal layer 40i can be formed of an insulating material different from the insulating material of the first interlayer insulating layer 25 and the second interlayer insulating layer 38. For example, the first insulating horizontal layer 27i and the second insulating horizontal layer 40i can be formed of first silicon nitride, while the first interlayer insulating layer 25 and the second interlayer insulating layer 38 can be formed of silicon oxide.

[0057] The first reinforcing horizontal layer 28 and the second reinforcing horizontal layer 41 can be formed of a second silicon nitride having an etch rate different from that of the first silicon nitride of the first insulating horizontal layer 27i and the second insulating horizontal layer 40i. The second silicon nitride can be a material with a higher etch rate than the first silicon nitride.

[0058] When in Figure 1 When viewed on the same plane, in the stacked structures 23' and 35', each of the through regions TA can be accessed by the gate region GA (in Figure 1The second structure 21' may be surrounded by an adjacent first gate layer 27g and a second gate layer 40g. The second gate layer 21' may also include intermediate insulating layers 32 and 44. Intermediate insulating layers 32 and 44 may include a first intermediate insulating layer 32 and a second intermediate insulating layer 44. The first intermediate insulating layer 32 may include a first gate pad 27p, a portion of the patterned structure 17' not covered by the first stacked structure 23', and an outer insulating layer 19b. The second intermediate insulating layer 44 may cover the second gate pad 40p and the first intermediate insulating layer 32. The first intermediate insulating layer 32 and the second intermediate insulating layer 44 may be formed of an insulating material such as silicon oxide.

[0059] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a storage vertical structure 47, which includes a portion penetrating the second structure 21'. The storage vertical structure 47 may include a portion penetrating the first stacked structure 23' and the second stacked structure 35' in the memory cell array region MCA. The storage vertical structure 47 may extend from the portion penetrating the second structure 21' into the patterned structure 17' and may contact the patterned structure 17'. For example, the storage vertical structure 47 may sequentially penetrate the third patterned layer 17c and the second patterned layer 17b', and may extend into the first patterned layer 17a. The storage vertical structure 47 may contact at least one of the first to third patterned layers 17a, 17b', and 17c, which are formed as silicon layers.

[0060] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include a string separation pattern 45 that extends through one or more upper gate layers disposed thereon in the second gate layer 40g. The string separation pattern 45 may be formed of silicon oxide. The string separation pattern 45 may be disposed at a height higher than the second gate layer in the second gate layer 40g, which may be a word line.

[0061] Semiconductor device 1 according to an exemplary embodiment of the present disclosure may include a dummy vertical structure 47d that extends through a string separation pattern 45 and also through a second structure 21' and contacts the pattern structure 17'. The dummy vertical structure 47d may have the same cross-sectional structure as the storage vertical structure 47 and may be formed of the same material as the storage vertical structure 47.

[0062] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include a first upper insulating layer 58 located on the second structure 21'. The first upper insulating layer 58 may include silicon oxide.

[0063] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include a support hole 60s penetrating the first upper insulating layer 58 and the second structure 21' and exposing a portion of the patterned structure 17', and a support vertical structure 61 disposed in the support hole 60s. Each of the support vertical structures 61 may include a portion that penetrates at least a portion of the first gate layer 27g and the second gate layer 40g of the second structure 21' in the stepped region SA. When viewed in a plane, each of the support vertical structures 61 may have a circular or elliptical shape.

[0064] At least a portion of the supporting vertical structure 61 may sequentially penetrate the third pattern layer 17c and the fourth pattern layer 17d of the pattern structure 17', and may extend into the first pattern layer 17a. One of the supporting vertical structures 61 may be spaced apart from the fourth pattern layer 17d, may penetrate the third pattern layer 17c, and may extend into the first pattern layer 17a.

[0065] For ease of description, the single support hole 60s and the single support vertical structure 61 will be described in the following text.

[0066] The upper surface of the supporting vertical structure 61 can be set at a height higher than the upper surface of the storage vertical structure 47.

[0067] In the example embodiment, "level" may refer to the height when viewed relative to the upper surface of the pattern structure 17' or when viewed relative to the upper surface of the semiconductor substrate 4.

[0068] The vertical structure 61 may include an air gap 69a and a support layer 65a that defines at least a portion of the air gap 69a.

[0069] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a capping layer 63 disposed on a first upper insulating layer 58 and covering a support vertical structure 61.

[0070] The capping layer 63 may include a lower capping layer 65c and an upper capping layer 67 on the lower capping layer 65c.

[0071] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include baffle structures 71. Each of the baffle structures 71 may penetrate the capping layer 63, the first upper insulating layer 58, and the second structure 21', and may surround each of the through regions TA. Thus, when viewed in a plane, each of the baffle structures 71 may be disposed in the gate region GA (in Figure 1 (in the middle) and the connecting area TA (in Figure 1 Between each through area in (the middle).

[0072] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a second upper insulating layer 73 located on the capping layer 63. The second upper insulating layer 73 may be in direct contact with the upper capping layer 67.

[0073] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include a separation structure 77 extending through the second upper insulating layer 73, the capping layer 63, the first upper insulating layer 58, and the second structure 21'. Each of the separation structures 77 may be formed of silicon oxide or silicon oxide with voids. In another example, each of the separation structures 77 may include a conductive pattern in contact with the patterned structure 17', and an insulating layer covering the side surface of the conductive pattern.

[0074] Each of the separation structures 77 may include a lower separation portion 77a penetrating the capping layer 63, the first upper insulating layer 58, and the second structure 21', and an upper separation portion 77b penetrating the second upper insulating layer 73. The lower separation portion 77a and the upper separation portion 77b may be integral with each other.

[0075] In at least one of the separation structures 77, the upper separation portion 77b may have a width different from that of the lower separation portion 77a. For example, in at least one of the separation structures 77, the width of the upper separation portion 77b may be greater than the width of the lower separation portion 77a.

[0076] In at least one of the separation structures 77, at least a portion of the side surface of the upper separation portion 77b may not be vertically aligned with at least a portion of the side surface of the lower separation portion 77a.

[0077] The separation structure 77 may include a plurality of main separation structures 77M parallel to each other, and auxiliary separation structures 77S disposed between the main separation structures 77M. Each of the separation structures 77 may include a line portion extending along a first horizontal direction X. The first horizontal direction X may be parallel to the upper surface of the patterned structure 17'. The first horizontal direction X may be a direction from the memory cell array region MCA toward the stepped region SA. Each auxiliary separation structure 77S may have a shorter length than each main separation structure in the main separation structure 77M. For example, a plurality of auxiliary separation structures 77S may be arranged in the first horizontal direction X, adjacent to a single main separation structure 77M arranged in the first horizontal direction X. The main separation structure 77M may penetrate the second structure 21' and may separate the first stacked structure 23' and the second stacked structure 35' in the second horizontal direction Y. The second horizontal direction Y may be parallel to the upper surface of the patterned structure 17' and may be perpendicular to the first horizontal direction X. Each of the separation structures 77 may contact the first gate layer 27g and the second gate layer 40g adjacent to the separation structure 77.

[0078] The separation structure 77 can extend downward from the portion penetrating the second structure 21' and can contact the patterned structure 17'. At least one of the separation structures 77 can contact the first patterned layer 17a.

[0079] The semiconductor device 1 according to an example embodiment of the present disclosure may further include peripheral contact plugs 87. Peripheral contact plugs 87 may include a first peripheral contact plug 87a, a second peripheral contact plug 87b, and a third peripheral contact plug 87c. Peripheral contact plugs 87 may penetrate the second upper insulating layer 73, the capping layer 63, the first upper insulating layer 58, and the second structure 21', and may extend into the lower structure 3.

[0080] The first peripheral contact plug 87a can be spaced apart from the first gate layer 27g and the second gate layer 40g, can penetrate the first intermediate insulating layer 32 and the second intermediate insulating layer 44, can contact the first peripheral circuit pad 11p1, and can be electrically connected to the first peripheral circuit pad 11p1.

[0081] The second peripheral contact plug 87b can be spaced apart from the first gate layer 27g and the second gate layer 40g, can penetrate the first insulating horizontal layer 27i and the second insulating horizontal layer 40i of the through region TA, can contact the second peripheral circuit pad 11p2, and can be electrically connected to the second peripheral circuit pad 11p2.

[0082] The third peripheral contact plug 87c can be spaced apart from the first gate layer 27g and the second gate layer 40g, can penetrate the first intermediate insulating layer 32 and the second intermediate insulating layer 44, and can contact and be electrically connected to the first patterned layer 17a. In the patterned structure 17', the first patterned layer 17a, which can be formed as a polysilicon layer with N-type conductivity, can be a common source, and the third peripheral contact plug 87c can be a common source contact plug electrically connected to the common source.

[0083] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a spacer layer 65b covering the side surfaces of each of the first peripheral contact plugs to the third peripheral contact plugs 87a, 87b and 87c.

[0084] The semiconductor device 1 according to an exemplary embodiment of the present disclosure may further include a gate contact plug that contacts and is electrically connected to the first gate pad 27p and the second gate pad 40p. The gate contact plug 89 may penetrate the second upper insulating layer 73, the capping layer 63 and the first upper insulating layer 58, may extend into the second structure 21', and may contact the first gate pad 27p and the second gate pad 40p.

[0085] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a third upper insulating layer 91 disposed on the second upper insulating layer 73. The first upper insulating layer 58, the second upper insulating layer 73, and the third upper insulating layer 91 may include silicon oxide.

[0086] The semiconductor device 1 according to an example embodiment of the present disclosure may further include peripheral upper plugs 95a, 95b, and 95c extending through the third upper insulating layer 91. The peripheral upper plugs 95a, 95b, and 95c may further include a first peripheral upper plug 95a electrically connected to a first peripheral contact plug 87a, a second peripheral upper plug 95b electrically connected to a second peripheral contact plug 87b, and a third peripheral upper plug 95c electrically connected to a third peripheral contact plug 87c.

[0087] The first peripheral plug 95a may include a side surface that is not vertically aligned with the side surface of the first peripheral contact plug 87a. The second peripheral plug 95b may include a side surface that is not vertically aligned with the side surface of the second peripheral contact plug 87b. The third peripheral plug 95c may include a side surface that is not vertically aligned with the side surface of the third peripheral contact plug 87c.

[0088] The width of each of the peripheral upper plugs 95a, 95b, and 95c from the first peripheral upper plug to the third peripheral upper plug may differ from the width of each of the peripheral contact plugs 87a, 87b, and 87c from the first peripheral contact plug to the third peripheral contact plug. In one example, the width of each of the peripheral upper plugs 95a, 95b, and 95c from the first peripheral upper plug to the third peripheral upper plug may be less than the width of each of the peripheral contact plugs 87a, 87b, and 87c from the first peripheral contact plug to the third peripheral contact plug. In another example, the width of each of the peripheral upper plugs 95a, 95b, and 95c from the first peripheral upper plug to the third peripheral upper plug may be greater than the width of each of the peripheral contact plugs 87a, 87b, and 87c from the first peripheral contact plug to the third peripheral contact plug. The semiconductor device 1 according to an example embodiment of the present disclosure may further include a bit line contact plug 96a that extends through the first upper insulating layer to the third upper insulating layers 58, 73 and 71 and the capping layer 63, and is electrically connected to the storage vertical structure 47.

[0089] The semiconductor device 1 according to an example embodiment of the present disclosure may further include a gate upper plug 96b that penetrates the third upper insulating layer 91 and is electrically connected to the gate contact plug 89.

[0090] The semiconductor device 1 according to an example embodiment of the present disclosure may further include wirings 98b, 98g, 98a, and 98c disposed on a third upper insulating layer 91. Wirings 98b, 98g, 98a, and 98c may include a bit line 98b electrically connected to a bit line contact plug 96a, a gate connection wiring 98g electrically connecting each of the gate plugs 96b to a plurality of second peripheral plugs 95b, a first peripheral wiring 98a electrically connected to a first peripheral plug 95a, and a second peripheral wiring 98c electrically connected to a third peripheral plug 95c.

[0091] In the following text, the height of the upper surface of the uppermost gate layer in the first gate layer 27g and the second gate layer 40g can be referred to as the first height L1, the height of the upper surface of the storage vertical structure 47 can be referred to as the second height L2, and the height of the upper surface of the second upper insulating layer 73 can be referred to as the third height L3.

[0092] In the following description, reference will be made to Figure 3A An example of the first gate layer 27g and the second gate layer 40g, as well as the storage vertical structure 47, described in the foregoing example embodiments is presented. Figure 3A It shows Figure 2A An enlarged view of region "A" in the image.

[0093] refer to Figure 2A and Figure 3A The first gate layer 27g and the second gate layer 40g, also referred to simply as gate layers, may include one or more lower gate layers GL1 and GL2, one or more upper gate layers GU1 and GU2, and a plurality of intermediate gate layers GM disposed between the one or more lower gate layers GL1 and GL2 and the one or more upper gate layers GU1 and GU2. The one or more upper gate layers GU1 and GU2 may be spaced apart from each other in the vertical direction Z. For example, the plurality of upper gate layers GU1 and GU2 may include a first upper gate layer GU1 and a second upper gate layer GU2 disposed below the first upper gate layer GU1.

[0094] One or more lower gate layers GL1 and GL2 may be spaced apart from each other in the vertical direction Z. For example, the plurality of lower gate layers GL1 and GL2 may include a first lower gate layer GL1 and a second lower gate layer GL2 disposed on the first lower gate layer GL1.

[0095] A portion of the multiple intermediate gate layers (GM) can be word lines.

[0096] In one example, the first lower gate layer GL1 can be the ground select gate line of a ground select transistor, while the second lower gate layer GL2 can be a dummy gate line.

[0097] In another example, the first lower gate layer GL1 may be the erase control gate line of an erase control transistor, which can be used to perform an erase operation to remove data stored in a memory cell using the gate-induced drain leakage (GIDL) phenomenon, while the second lower gate layer GL2 may be the ground select gate line of a ground select transistor.

[0098] In the example, the multiple upper gate layers GU1 and GU2 can be the string select gate lines of a string select transistor.

[0099] In another example, the first upper gate layer GU1 of the plurality of upper gate layers GU1 and GU2 may be the erase control gate line of the erase control transistor, while the second upper gate layer GU2 of the plurality of upper gate layers GU1 and GU2 may be the string select gate line of the string select transistor.

[0100] The storage vertical structure 47 may include a lower vertical portion 47L that penetrates the first stacked structure 23' and an upper vertical portion 47U that penetrates the second stacked structure 35'.

[0101] The width of the upper region of the lower vertical portion 47L may differ from the width of the lower region of the upper vertical portion 47U. For example, the width of the upper region of the lower vertical portion 47L may be greater than the width of the lower region of the upper vertical portion 47U. In other words, the width at the intersection of the lower vertical portion 47L and the upper vertical portion 47U of the lower vertical portion 47L may be greater than the width at the intersection of the lower vertical portion 47L and the upper vertical portion 47U of the upper vertical portion 47U.

[0102] The side surfaces of the lower vertical portion 47L and the upper vertical portion 47U, which are adjacent to each other, may not be aligned in the vertical direction Z.

[0103] The storage vertical structure 47 is located on the middle side surface at the height between the uppermost first gate layer 27g of the first stacked structure 23' and the lowermost second gate layer 40g of the second stacked structure 35', and may include a slope variation portion 47V in which the slope can vary.

[0104] In an exemplary embodiment of this disclosure, the "slope variation portion" may be a side surface portion of the storage vertical structure 47 having a third slope different from the first and second slopes between an upper side surface portion having a first slope and a lower side surface portion having a second slope. The third slope may be gentler (e.g., less steep) than the first and second slopes, which may be vertical or nearly vertical. Therefore, the "slope variation portion" may be a portion with a gentle slope between the upper and lower portions. For example, in the storage vertical structure 47, the side surface of the lower vertical portion 47L may have a first slope that may be vertical or nearly vertical, the side surface of the upper vertical portion 47U may have a second slope that may be vertical or nearly vertical, and the slope variation portion 47V may have a gentler slope than the first and second slopes.

[0105] At the same height as the slope variation portion 47V of the middle side surface of the storage vertical structure 47, the side surface of each of the aforementioned supporting vertical structure 61, the first peripheral contact plug to the third peripheral contact plug 87a, 87b and 87c, the separation structure 77 and the baffle structure 71 may have a substantially linear shape or a regularly monotonically varying shape.

[0106] The storage vertical structure 47 may include an insulating gap filler layer 53, a channel layer 51 covering the outer and bottom surfaces of the insulating gap filler layer 53, a data storage structure 49 covering the outer and bottom surfaces of the channel layer 51, and a pad material layer 55 located on the insulating gap filler layer 53.

[0107] The data storage structure 49 may include a first dielectric layer 49c covering the outer and bottom surfaces of the channel layer 51, a data storage material layer 49b covering the outer and bottom surfaces of the first dielectric layer 49c, and a second dielectric layer 49a covering the outer and bottom surfaces of the data storage material layer 49b. The first dielectric layer 49c may be in contact with the channel layer 51, while the data storage material layer 49b may be spaced apart from the channel layer 51. The insulating gap-filling layer 53 may include silicon oxide, such as silicon oxide formed by an atomic layer deposition process or silicon oxide with voids formed therein. The first dielectric layer 49c may include silicon oxide or silicon oxide doped with impurities. The second dielectric layer 49a may include at least one of silicon oxide and a high-k dielectric. The data storage material layer 49b may include a material for trapping charge and storing data, such as silicon nitride.

[0108] The data storage material layer 49b of the data storage structure 49 of the vertical structure 47 may include regions for storing data in a semiconductor device such as a flash memory device. The channel layer 51 may include polysilicon. The pad material layer 55 may include at least one of doped polysilicon, metal nitrides (e.g., TiN), metals (e.g., W), and metal-semiconductor compounds (e.g., TiSi). The pad material layer 55 may be electrically connected to and in contact with the bit line contact plug 96a.

[0109] The vertical storage structure 47 can sequentially penetrate the third pattern layer 17c and the second pattern layer 17b' of the pattern structure 17', and can extend into the first pattern layer 17a. In the pattern structure 17', the second pattern layer 17b' can penetrate the data storage structure 49 and can contact the channel layer 51.

[0110] The semiconductor device 1 according to an exemplary embodiment of this disclosure may further include a dielectric layer 56 covering the upper and lower surfaces of each of the first gate layer 27g and the second gate layer 40g, and disposed between the side surface of the storage vertical structure 47 and the side surface of each of the first gate layer 27g and the second gate layer 40g. The dielectric layer 56 may include a high-k dielectric with a dielectric constant higher than that of silicon oxide. For example, the dielectric layer 56 may be formed of a high-k dielectric such as aluminum oxide, lanthanum oxide, or hafnium oxide.

[0111] In the following description, by reference Figure 3B An example of the above-mentioned supporting vertical structure 61 and capping layer 63 will be described. Figure 3B It shows Figure 2B An enlarged view of region "B" in the image.

[0112] refer to Figure 2B and Figure 3B As described above, the supporting vertical structure 61 may include an air gap 69a and a support layer 65a defining at least a portion of the air gap 69a, and the capping layer 63 may include a lower capping layer 65c and an upper capping layer 67. For example, the support layer 65a may at least limit the lower portion and sidewalls of the air gap 69a.

[0113] The support layer 65a can extend continuously from the lower capping layer 65c. The upper capping layer 67 can restrict the upper part of the air gap 69a.

[0114] The lower capping layer 65c and the support layer 65a can be formed of the same material. The lower capping layer 65c and the support layer 65a can be integral with each other. For example, the lower capping layer 65c and the support layer 65a can be formed of material layers that extend continuously without boundary surfaces. For example, the lower capping layer 65c and the support layer 65a may include an insulating material layer.

[0115] In one example, the lower capping layer 65c and the support layer 65a may be formed of a silicon oxide layer.

[0116] In another example, the lower capping layer 65c and the support layer 65a may be formed of silicon nitride layers.

[0117] In another example, the lower capping layer 65c and the support layer 65a can be formed as a multilayer structure, such as a multilayer structure having a silicon oxide layer and a silicon nitride layer.

[0118] The maximum thickness of the lower capping layer 65c can be greater than the minimum thickness of the support layer 65a. The support layer 65a can have its maximum thickness in the portion adjacent to the lower capping layer 65c. The support layer 65a can have its minimum thickness in the portion away from the lower capping layer 65c.

[0119] The upper capping layer 67 may include a material layer formed by a method different from that used to form the lower capping layer 65c. For example, the lower capping layer 65c may include a silicon oxide layer formed by atomic layer deposition (ALD), while the upper capping layer 67 may include a silicon oxide layer formed by chemical vapor deposition (CVD).

[0120] In one example, the upper end of the air gap 69a may be positioned at a height higher than the upper surface of the storage vertical structure 47. In another example, the air gap 69a may extend upward from the portion disposed in the support hole 60s, and the upper end 69t of the air gap 69a may be positioned at a height higher than the upper surface of the first upper insulating layer 58. The upper end 69t of the air gap 69a may be pointed and narrower than the other portions of the air gap 69a located below the upper end 69t.

[0121] In the example, the upper end 69t of the air gap 69a can be set at a height higher than the height of the upper surface of the lower cover layer 65c.

[0122] In the following description, reference will be made to Figure 3C and Figure 3D Examples of the peripheral contact plug 87, the first peripheral upper plug to the third peripheral upper plug 95a, 95b and 95c, the spacer layer 65b and the gate contact plug 89 described above. Figure 3C It shows Figure 2A Enlarged views of regions "C1" and "C2" in the image, and Figure 3D It shows Figure 2A An enlarged view of region "D" in the image.

[0123] refer to Figure 2A , Figure 3C and Figure 3DEach of the peripheral contact plugs 87 may include a lower region 87LS disposed below the first height L1 and an upper region 87US disposed above the first height L1. For example, in each of the peripheral contact plugs 87, the upper region 87US may be disposed at a height higher than the height of the upper surface of the uppermost gate layer 40g of the first gate layer 27g and the second gate layer 40g, and the lower region 87LS may be disposed at a height lower than the height of the upper surface of the uppermost gate layer 40g.

[0124] The following description will primarily focus on the lower region 87LS and the upper region 87US of one of the peripheral contact plugs 87.

[0125] The side surface profile of the lower region 87LS may differ from that of the upper region 87US. For example, the lower region 87LS may have a substantially vertical side surface, while the upper region 87US may have at least one curved side surface. For example, the upper region 87US may include a first region 87US_1, a connecting region 87US_2 disposed below the first region 87US_1, and a second region 87US_3 disposed below the connecting region 87US_2. The side surface of the connecting region 87US_2 may have a slope different from at least one of the side surfaces of the first region 87US_1 and the second region 87US_3. For example, the side surface of the connecting region 87US_2 may have a slope different from the side surface of the first region 87US_1 having a first slope and the side surface of the second region 87US_3 having a second slope. For example, the side surfaces of the first region 87US_1 and the second region 87US_3 may have steep vertical slopes or nearly vertical slopes, while the side surface of the connecting region 87US_2 may have gentle slopes. In exemplary embodiments of this disclosure, the expression "substantially vertical" may refer to a configuration substantially perpendicular to the upper surface of the lower structure 3 or the upper surface of the semiconductor substrate 4. For example, forming a plug may include forming a hole by an anisotropic etching process and forming a plug in the hole, and the side surface profile of the plug may be the side surface profile of the hole formed by the anisotropic etching process. The side surface of the hole formed by the anisotropic etching process may be perpendicular to or nearly perpendicular to the upper surface of the semiconductor substrate 4. Therefore, the expression "substantially perpendicular" can refer to a configuration perpendicular to the upper surface of the semiconductor substrate 4, but this disclosure is not limited thereto, and the expression can refer to the shape of the side surface of the hole formed within the process margin of the anisotropic etching process, which can be, for example, a shape that is almost perpendicular to the upper surface of the semiconductor substrate 4, such as a shape that is almost perpendicular to the upper surface of the semiconductor substrate 4 and has a constant slope, or a shape that is almost perpendicular to the upper surface of the semiconductor substrate 4 and has a varying slope.

[0126] At least a portion of the first region 87US_1 may contact the second upper insulating layer 73 and the upper capping layer 67.

[0127] The first region 87US_1 may contact the second upper insulating layer 73, the upper capping layer 67, and the lower capping layer 65c. The first region 87US_1 may extend from the connecting region 87US_2 and sequentially contact the lower capping layer 65c, the upper capping layer 67, and the second upper insulating layer 73.

[0128] The side surfaces of the first region 87US_1 and the second region 87US_3 may be misaligned in the vertical direction Z.

[0129] At least a portion of the connection area 87US_2 may be positioned at a height lower than that of the lower cover layer 65c.

[0130] At least a portion of the connection region 87US_2 can be set at a height higher than the second height L2.

[0131] The maximum width of the upper region 87US can be greater than the maximum width of the lower region 87LS.

[0132] In the upper region 87US, the minimum width of the first region 87US_1 can be greater than the minimum width of the connecting region 87US_2, and the maximum width of the second region 87US_3 can be less than the maximum width of the connecting region 87US_2.

[0133] The gate contact plug 89 disposed at the same height as the upper region 87US may have a side surface profile different from that of the upper region 87US. For example, the side surface of each region of the gate contact plug 89 disposed at the same height as the upper region 87US of the peripheral contact plug 87 may have a substantially vertical slope.

[0134] The spacer layer 65b may surround the side surface of the lower region 87LS, may extend upward, and may cover a portion of the side surface of the upper region 87US. For example, the spacer layer 65b may cover the side surface of the second region 87US_3 of the upper region 87US, and may be positioned at a lower height than the first region 87US_1 of the upper region 87US and may be spaced apart from the first region 87US_1.

[0135] The spacer layer 65b may cover at least a portion of the connecting region 87US_2 of the upper region 87US. For example, the spacer layer 65b may cover the lower side surface of the connecting region 87US_2, but may not cover the upper side surface of the connecting region 87US_2.

[0136] Each of the first peripheral upper plugs to the third peripheral upper plugs 95a, 95b, and 95c may have a different width than each of the peripheral contact plugs 87. For example, the width of each of the first peripheral upper plugs to the third peripheral upper plugs 95a, 95b, and 95c may be smaller than the width of each of the peripheral contact plugs 87.

[0137] Each of the peripheral contact plugs 87 may include a plug pattern 87_2 and a conductive liner 87_1 covering the side and bottom surfaces of the plug pattern 87_2. Each of the gate contact plugs 89 may include a plug pattern 89_2 and a conductive liner 89_1 covering the side and bottom surfaces of the plug pattern 89_2.

[0138] In this example, both the peripheral contact plug 87 and the gate contact plug 89 can be formed simultaneously. Therefore, the peripheral contact plug 87 and the gate contact plug 89 can be formed from the same material.

[0139] In this example, the upper surface of the peripheral contact plug 87 may be coplanar with the upper surface of the gate contact plug 89. For example, the upper surfaces of the peripheral contact plug 87 and the gate contact plug 89 may be disposed on a third height L3.

[0140] In exemplary embodiments of this disclosure, the bit line contact plug 96a, the gate plug 96b, and the first peripheral plug to the third peripheral plug 95a, 95b, and 95c can be formed simultaneously and can comprise the same material. For example, each of the bit line contact plug 96a, the gate plug 96b, and the first peripheral plug to the third peripheral plug 95a, 95b, and 95c can include a plug pattern 95_2 and a conductive liner 95_1 covering the bottom and side surfaces of the plug pattern 95_2. The conductive liner 95_1 can be in direct contact with the peripheral contact plug 87 or the gate contact plug 89 located below it. The bit line contact plug 96a, the gate plug 96b, and the first peripheral plug to the third peripheral plug 95a, 95b, and 95c can have upper surfaces that are coplanar with each other.

[0141] In the following description, reference will be made to Figure 4A , Figure 4B , Figure 5A and Figure 5B Various modifications to the aforementioned supporting vertical structure 61 and capping layer 63 are described. Figure 4A , Figure 4B , Figure 5A and Figure 5B It shows Figure 3B The enlarged view shows the modified portion of the example in the enlarged image below. See below for reference. Figure 4A , Figure 4B , Figure 5A and Figure 5BThe various modified structures described can replace Figure 3B The structure in.

[0142] In the modified example, refer to Figure 4A ,refer to Figure 3B The described lower capping layer 65c can be replaced by a lower capping layer 65c' comprising a first layer 65c1 and a second layer 65c2 on top of the first layer 65c1. (See reference) Figure 3B The described support layer 65a can be replaced by a support layer 65a' comprising a first layer 65a1 and a second layer 65a2 on the first layer 65a1. The first layer 65a1 of the support layer 65a' and the first layer 65c1 of the lower cover layer 65c' can be integral with each other, and the second layer 65a2 of the support layer 65a' and the second layer 65c2 of the lower cover layer 65c' can be integral with each other.

[0143] In the example, the first layers 65a1 and 65c1 and the second layers 65a2 and 65c2 can be formed as material layers with different step coverage. For example, one of the first layers 65a1 and 65c1 and the second layers 65a2 and 65c2 can have a higher step coverage than the other layers. For example, one of the first layers 65a1 and 65c1 and the second layers 65a2 and 65c2 can be formed to have a uniform thickness compared to the thickness of the other layers.

[0144] In the example, the first layers 65a1 and 65c1 and the second layers 65a2 and 65c2 can be formed of the same type of material. For example, the first layers 65a1 and 65c1 can be formed of a silicon oxide layer with a uniform thickness compared to the thickness of the second layers 65a2 and 65c2, while the second layers 65a2 and 65c2 can be formed of a silicon oxide layer with a non-uniform thickness compared to the thickness of the first layers 65a1 and 65c1. In another example, the first layers 65a1 and 65c1 and the second layers 65a2 and 65c2 can be formed of different materials. For example, the first layers 65a1 and 65c1 can be formed of a silicon oxide layer, while the second layers 65a2 and 65c2 can be formed of a material different from the silicon oxide layer, such as a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride layer including carbon. The aforementioned spacer layer 65b (in Figure 3C The spacer layer 65b can be formed of the same material as the support layer 65a'. Therefore, the spacer layer 65b (in Figure 3C (middle) can be modified to include the same first and second layers as the first and second layers of the support layer 65a'.

[0145] In another modified example, refer to Figure 4B ,refer to Figure 3BThe described capping layer 63, including the lower capping layer 65c and the upper capping layer 67, and the support layer 65a can be replaced by a capping layer 63' and a support layer 65a" that can limit the air gap 69a through a single material layer. For example, the support layer 65a" can be integral with the capping layer 63'. Figure 3B In the process, the upper capping layer 67, formed by a different process than that used to form the support layer 65a, can restrict the upper part of the air gap 69a, but in Figure 4B In the process of forming the support layer 65a”, the capping layer 63’ can restrict the upper part of the air gap 69a.

[0146] In another modified example, refer to Figure 5A ,refer to Figure 3B The described vertical support structure 61 can be replaced by a vertical support structure 61', which includes an air gap 69a', a support layer 65a defining a portion of the air gap 69a', and an upper gap filling layer 67a defining the upper portion of the air gap 69a'. (See reference) Figure 3B The capping layer 63 described, which includes a lower capping layer 65c and an upper capping layer 67, can be replaced by a capping layer 63', which includes an upper capping layer 67' extending from the upper gap filling layer 67a.

[0147] In the example, the upper end 69t' of the air gap 69a' can be lower than the second height L2 and higher than the first height L1. In this case, the upper gap filling layer 67a can be disposed on the upper end 69t' of the air gap 69a' located between the first height L1 and the second height L2.

[0148] In another modified example, refer to Figure 5B ,refer to Figure 3B The described vertical support structure 61 can be replaced by a vertical support structure 61”, which includes an air gap 69a” having an upper end 69t” lower than the first height L1, a support layer 65a defining a portion of the air gap 69a”, and an upper gap filling layer 67a’ defining the upper part of the air gap 69a”.

[0149] In the following description, reference will be made to Figure 6A , Figure 6B , Figure 7A and Figure 7B Various modification examples of the aforementioned peripheral contact plug 87 and / or spacer layer 65b are described. Figure 6A , Figure 6B , Figure 7A and Figure 7B It shows Figure 3C The enlarged view shows the modified portion of the example in the enlarged image below. See below for reference. Figure 6A , Figure 6B , Figure 7A and Figure 7B The various modified structures described can replace Figure 3C The structure in.

[0150] In the modified example, refer to Figure 6A In reference Figure 3C The described peripheral contact plug 87 includes a lower region 87LS and an upper region 87US, wherein the upper region 87US can be used with Figure 6A Replace the shape of the upper region 87US' with the same shape.

[0151] The upper region 87US' may include a second region 87US_3', a connecting region 87US_2' on the second region 87US_3', and a first region 87US_1' on the connecting region 87US_2'. The connecting region 87US_2' may have a concave side surface. For example, in the upper region 87U', compared to the first region 87US_1' and the second region 87US_3', the connecting region 87US_2' may have a side surface that is concave in a direction toward the center of the upper region 87U'. In the upper region 87U', the minimum width of the connecting region 87US_2' may be smaller than the width of the second region 87US_3' adjacent to the connecting region 87US_2'.

[0152] In the upper region 87US', the minimum width of the connecting region 87US_2' can be less than the minimum width of the first region 87US_1'.

[0153] In the upper region 87US', the width of the first region 87US_1' can be greater than the width of the second region 87US_3'.

[0154] refer to Figure 3C The spacer layer 65b described can be replaced by a spacer layer 65b', which may not cover the lower region 87LS and may cover the side surface of the connecting region 87US_2'. For example, the spacer layer 65b' may fill the concave side surface of the connecting region 87US_2'.

[0155] In the modified example, refer to Figure 6B You don't need to set a reference. Figure 3C The spacer layer 65b is described. For example, the peripheral contact plug 87 may include a portion that is in direct contact with the second structure 21'.

[0156] In the modified example, refer to Figure 7A In reference Figure 3C The described peripheral contact plug 87 includes a lower region 87LS and an upper region 87US, wherein the upper region 87US can be used with Figure 7A The shape of the upper region 87USa is replaced with the same shape.

[0157] The upper region 87USa may include the second region 87US_3a, the connecting region 87US_2a on the second region 87US_3a, and the first region 87US_1a on the connecting region 87US_2a.

[0158] In the upper region 87USa, the minimum width of the first region 87US_1a can be less than the maximum width of the connecting region 87US_2a, the maximum width of the second region 87US_3a can be greater than the minimum width of the connecting region 87US_2a, and the maximum width of the second region 87US_3a can be greater than the maximum width of the first region 87US_1a. (Reference) Figure 3C The spacer layer 65b described can be continuously connected to and integrated with the capping layer 65c.

[0159] In the modified example, refer to Figure 7B In reference Figure 3C The described peripheral contact plug 87 includes a lower region 87LS and an upper region 87US, wherein the upper region 87US can be used with Figure 7B Replace the shape of the upper region 87USb with the same shape, and refer to Figure 3C The spacer layer 65b described can be used as follows Figure 7B The spacer layer 65b is used instead.

[0160] The upper region 87US_3b may include a second region 87US_3b, a connecting region 87US_2b on the second region 87US_3b, and a first region 87US_1b on the connecting region 87US_2b, wherein the width of the first region 87US_1b may be smaller than the width of the second region 87US_3b. The connecting region 87US_2b may have a tapered shape that narrows as it approaches the first region 87US_1b.

[0161] The spacer layer 65b” may cover at least a portion of the side surface of the connecting region 87US_2b. The spacer layer 65b” may not cover the entire side surface of the second region 87US_3b, or may not cover a portion of the side surface of the second region 87US_3b. The peripheral contact plug 87 disposed below the spacer layer 65b” may include a portion that contacts the second structure 21'. The spacer layer 65b” may be continuously connected to and integral with the lower cover layer 65c.

[0162] In the modified example, refer to Figure 7C In reference Figure 3CIn the peripheral contact plug 87 described, which includes a lower region 87LS and an upper region 87US, the upper region 87US can be replaced by an upper region 87USc extending from the lower region 87LS with a constant width or a monotonically varying width. For example, the side surfaces of the peripheral contact plug 87 including the lower region 87LS and the upper region 87USc can have a substantially linear shape or a regularly monotonically varying shape.

[0163] In the following description, reference will be made to Figure 8A This describes a modification example of the aforementioned peripheral contact plug 87. Figure 8A It shows Figure 3C The enlarged view shows the modified portion of the example in the enlarged image below. See below for reference. Figure 8A The modified structure of the described peripheral contact plug 87 can replace Figure 3C The structure of the peripheral contact plug 87 in the middle can also replace the reference. Figures 6A to 7C The structure of the peripheral contact plug 87 is described.

[0164] In the modified example, refer to Figure 8A ,refer to Figure 3C The description of the peripheral contact plug 87 or reference Figures 6A to 7C The described peripheral contact plug 87 can be replaced by a peripheral contact plug 87' that also includes an air gap 873. For example, the peripheral contact plug 87' may include a plug pattern 87_2, a conductive liner 87_1 covering the side and bottom surfaces of the plug pattern 87_2, and an air gap 87_3 in the plug pattern 87_2.

[0165] In the peripheral contact plug 87', the upper end of the air gap 87_3 can be lower than the second height L2.

[0166] In the peripheral contact plug 87', the upper end of the air gap 87_3 can be higher than the first height L1.

[0167] In the following description, reference will be made to Figure 8B This describes a modification example of the aforementioned peripheral contact plug 87. Figure 8B It shows Figure 7A The enlarged view shows the modified portion of the example in the enlarged image below. See below for reference. Figure 8B The modified structure of the described peripheral contact plug 87 can replace Figure 7A The structure of the peripheral contact plug 87 in the middle can also replace the reference. Figure 3C , Figure 6A , Figure 6B , Figure 7B and Figure 7C The structure of the peripheral contact plug 87 is described.

[0168] In the modified example, refer to Figure 8B ,refer to Figure 7A The description of the peripheral contact plug 87 or reference Figure 3C , Figure 6A , Figure 6B , Figure 7B and Figure 7C The described peripheral contact plug 87 can be replaced by a peripheral contact plug 87" that also includes a lower air gap 87_3 and an upper air gap 87_4. For example, the peripheral contact plug 87" may include a plug pattern 87_2, a conductive liner 87_1 covering the side and bottom surfaces of the plug pattern 87_2, and a lower air gap 87_3 and an upper air gap 87_4 disposed in the plug pattern 87_2 and spaced apart from each other. In other words, the lower air gap 87_3 and the upper air gap 87_4 constitute two separate air gaps.

[0169] In the peripheral contact plug 87", the upper end of the lower air gap 87_3 can be lower than the second height L2.

[0170] In the peripheral contact plug 87", the upper end of the lower air gap 87_3 can be higher than the first height L1.

[0171] In the peripheral contact plug 87", the upper air gap 87_4 may be higher than the second height L2. The upper end of the upper air gap 87_4 may be lower than the third height L3. Alternatively, the upper end of the upper air gap 87_4 may be higher than the third height L3.

[0172] In the following description, reference will be made to Figure 9A and Figure 9B This describes a modification example of the aforementioned peripheral contact plug 87. Figure 9A It shows Figure 3C The enlarged view of the example in the enlarged image is a modified part, and Figure 9B It shows Figure 7A The enlarged view shows the modified portion of the example in the enlarged image below. See below for reference. Figure 9A and Figure 9B The modified structure of the peripheral contact plug 87 described, such as the structure in which the height of the upper surface is increased, can be reflected in... Figure 3C and Figure 7A The structure of the peripheral contact plug 87 is reflected in the reference. Figure 6A , Figure 6B , Figure 7B , Figure 7C , Figure 8A and Figure 8B The peripheral contact plugs 87, 87', and 87" are described. For example, refer to... Figure 6A , Figure 6B , Figure 7B , Figure 7C , Figure 8A and Figure 8BThe height of the upper surface of the described peripheral contact plugs 87, 87' and 87" can be modified to increase.

[0173] In the modified example, refer to Figure 9A ,refer to Figure 3C The peripheral contact plug 87 described, including the upper region 87US, can be replaced by a peripheral contact plug 187 including an upper region 187USa, which includes an upper surface disposed at a height higher than that of the previously described peripheral contact plug. The peripheral contact plug 187 may include, as referenced... Figure 3C The lower region 87LS is essentially the same as the lower region 187LS.

[0174] The upper region 187USa may include references Figure 3C The second region 87US_3 and the connecting region 87US_2 described are substantially the same as the second region 187US_3a and the connecting region 187US_2a, and may include a setting that is more advanced than the reference region. Figure 3C The first region 87US_1 is described at a height of 187US_1a.

[0175] The upper region 187USa may have an upper surface that is coplanar with the upper surface of the third upper insulating layer 91. The upper surface of the upper region 187USa of the peripheral contact plug 187 may be higher than the third height L3.

[0176] Peripheral contact plug 187 may have a configuration provided in the gate contact plug 89 (in Figure 2A The upper surface of the middle) is at a high height.

[0177] In the modified example, refer to Figure 9B ,refer to Figure 7A The peripheral contact plug 87 described, including the upper region 87USa, can be replaced by a peripheral contact plug 187 including the upper region 187USb, which has an upper surface disposed at a height higher than some of the peripheral contact plugs previously described.

[0178] Similar to a reference Figure 9A The upper region 187USa and upper region 187USb described may include references Figure 7A The second region 87US_3a and the connecting region 87US_2a described are substantially the same as the second region 187US_3b and the connecting region 187US_2b, and may include a setting that is more advanced than the reference region. Figure 7A The first region 87US_1a is described at a height higher than the first region 187US_1b. Figure 9B The first region 187US_1b can be compared to Figure 9AThe first region 187US_1a is narrow.

[0179] In the following description, reference will be made to Figure 10A and Figure 10B A modified example of the gate contact plug 89 described above is given. Figure 10A and Figure 10B It shows Figure 3D The enlarged view is a modified portion of the example in the enlarged view.

[0180] In the modified example, refer to Figure 10A ,refer to Figure 3D The described gate contact plug 89 can be replaced by a gate contact plug 189a having an upper surface disposed at a lower height than the gate contact plug 89. The gate contact plug 189a may have an upper surface coplanar with the upper surface of the capping layer 63. In other words, the upper surface of the gate contact plug 189a may not extend beyond the second upper insulating layer 73. Therefore, the upper surface of the gate contact plug 189a may be disposed at a lower height than the capping layer 63. Figure 3C , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B The height of the upper surface of the peripheral contact plugs 87, 87', 87" and 187 in the various examples described herein is low.

[0181] In the modified example, refer to Figure 10B ,refer to Figure 3D The described gate contact plug 89 can be replaced by a gate contact plug 189b having an upper surface disposed at a height higher than the gate contact plug 89. The upper surface of the gate contact plug 189b can be coplanar with the upper surface of the third upper insulating layer 91. In this case, the upper surface of the gate contact plug 189b can extend beyond the second upper insulating layer 73. For example, the gate contact plug 189b can have a shape similar to the reference... Figure 9A and Figure 9B The upper surfaces of the peripheral contact plugs 187 described in various examples are coplanar.

[0182] Reference Figure 11A , Figure 11B and Figure 12 This describes a modified example of a semiconductor device based on an example embodiment. Figure 11A This is a cross-sectional view showing the structure taken along the first horizontal direction X. Figure 11B It shows a cross-sectional view of the structure taken along a second horizontal direction Y, which is perpendicular to the first horizontal direction X. Figure 12 It shows Figure 11A Enlarged views of regions "E1" and "E2" in the image.

[0183] refer to Figure 11A , Figure 11B and Figure 12 The semiconductor device 200 according to an example embodiment of the present disclosure may include a first structure 203 and a second structure 221' that overlaps with the first structure 203 in the vertical direction Z.

[0184] The second structure 221' may include a patterned structure 217. The patterned structure 217 may include at least one silicon layer. The patterned structure 217 may be coupled with… Figure 2A and Figure 2B The pattern structure in 17' is basically the same.

[0185] The first structure 203 may include a semiconductor substrate 204, peripheral circuitry 208 located on the semiconductor substrate 204, and a lower insulating layer 213 covering the peripheral circuitry 208 on the semiconductor substrate 204. The peripheral circuitry 208 may include circuit devices 209, such as transistors, and circuit interconnects 211 electrically connected to the circuit devices 209, the circuit devices 209 including a peripheral gate 209a and a peripheral source / drain 209b. A portion of the circuit interconnects 211 may be a first peripheral circuit pad 211p1 and a second peripheral circuit pad 211p2. A pattern structure 217 may be disposed on the lower insulating layer 213. The pattern structure 217 may also include a ground pattern 218. For example, the ground pattern 218 may be disposed below the pattern structure 217 and may be grounded to the semiconductor substrate 204 through a portion of the circuit interconnects 211.

[0186] The second structure 221' may also include an inner insulating layer 219a that penetrates the pattern structure 217 and an outer insulating layer 219b disposed on the outer side of the pattern structure 217.

[0187] The second structure 221' may include a storage cell region MCA and a step region SA. The second structure 221' may include stack structures 223' and 235' disposed in the storage cell region MCA and extending from the storage cell region MCA into the step region SA.

[0188] Stacked structures 223' and 235' may include a first stacked structure 223' and a second stacked structure 235' on top of the first stacked structure 223'. The first stacked structure 223' may include a first interlayer insulating layer 225 and a first gate layer 227g stacked alternately in the vertical direction Z. The first gate layer 227g may have gate pads GP arranged in a stepped shape in a stepped region SA. The second stacked structure 235' may include a second interlayer insulating layer 238 and a second gate layer 240g stacked alternately in the vertical direction Z. The second gate layer 240g may have gate pads GP arranged in a stepped shape in a stepped region SA.

[0189] Interlayer insulating layers 225 and 238 can be formed, and first gate layer 227g and second gate layer 240g can be formed. The thickness of the gate pads GP of gate layers 227g and 240g can be greater than the thickness of each gate layer 227g and 240g disposed in the memory cell array region MCA. Gate layers 227g and 240g can be formed by... Figure 2A and Figure 2B The gate layers of 27g and 40g are formed from essentially the same material.

[0190] The semiconductor device 200 according to an exemplary embodiment of this disclosure may further include a storage vertical structure 47 extending through the second structure 221'. The storage vertical structure 47 may be connected to... Figure 2A , Figure 2B and Figure 3A The storage vertical structure 47 is basically the same as that in the above, and the pattern structure 217 that is in contact with the storage vertical structure 47 can be the same as that in the above. Figure 2A , Figure 2B and Figure 3A The pattern structure in 17' is basically the same.

[0191] The semiconductor device 200 according to an example embodiment of the present disclosure may further include a first upper insulating layer 258 located on the second structure 221'. The first upper insulating layer 258 may include silicon oxide.

[0192] The semiconductor device 200 according to an example embodiment of this disclosure may further include a support hole 60s penetrating the first upper insulating layer 258 and the second structure 221' and exposing a portion of the patterned structure 217, and a support vertical structure 61 disposed in the support hole 60s. The support vertical structure 61 may be related to a reference. Figure 2B , Figure 2C , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5BThe described supporting vertical structures 61 and 61' are substantially the same, for example, see reference 1. Figure 3B The described supporting vertical structure 61. For example, see reference... Figure 3B The vertical support structure 61 may include an air gap 69a and a support layer 65a that defines at least a portion of the air gap 69a.

[0193] The semiconductor device 200 according to an example embodiment of this disclosure may further include a capping layer 263 disposed on a first upper insulating layer 258 and covering a supporting vertical structure 61. Similar to reference... Figures 1 to 3D The described capping layer 63, capping layer 263 may include a lower capping layer 265c and an upper capping layer 267 on the lower capping layer 265c.

[0194] The semiconductor device 200 according to an example embodiment of the present disclosure may further include a second upper insulating layer 273 located on the capping layer 263.

[0195] The height of the upper surface of the uppermost gate layer in gate layers 227g and 240g can be a first height L1, the height of the upper surface of the storage vertical structure 47 can be a second height L2, and the height of the upper surface of the second upper insulating layer 273 can be a third height L3.

[0196] The semiconductor device 200 according to an example embodiment may include a separation structure 77 penetrating the second upper insulating layer 273, the capping layer 263, the first upper insulating layer 258, and the second structure 221'. The separation structure 77 may be connected to... Figure 1 and Figure 2C The separation structure 77 is basically the same.

[0197] The semiconductor device 200 according to an example embodiment of the present disclosure may further include a peripheral contact plug 287. The peripheral contact plug 287 may include a first peripheral contact plug 287a and a second peripheral contact plug 287b. The peripheral contact plug 287 may penetrate the second upper insulating layer 273, the capping layer 263, the first upper insulating layer 258 and the second structure 221', and may extend into the lower structure 203.

[0198] The first peripheral contact plug 287a can be spaced apart from the first gate layer 227g and the second gate layer 240g, can penetrate the intermediate insulating layers 232 and 244, can contact the first peripheral circuit pad 211p1, and can be electrically connected to the first peripheral circuit pad 211p1.

[0199] The second peripheral contact plug 287b may be spaced apart from the first gate layer 227g and the second gate layer 240g, may penetrate the intermediate insulating layers 232 and 244, and may contact and be electrically connected to the patterned structure 217.

[0200] The peripheral contact plug 287 may have the same characteristics as the reference. Figure 3C , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A and Figure 9B The peripheral contact plugs 87, 87', 87" and 187 described in various examples have the same structure as one of them. For example, peripheral contact plug 287 may have the same structure as the reference. Figure 6B The peripheral contact plug 87 described has a structure that is substantially the same. For example, the peripheral contact plug 287 may include a lower region 287LS and an upper region 287US, and the upper region 287US may include regions respectively connected to the first region 87US_1 (in... Figure 6B (in the middle), second region 87US_3 (in Figure 6B (in) and connecting region 87US_2 (in Figure 6B The corresponding first region 287US_1, second region 287US_3 and connecting region 287US_2.

[0201] The semiconductor device 200 according to an example embodiment of this disclosure may further include a gate contact plug 289. The gate contact plug 289 may penetrate the second upper insulating layer 273, the capping layer 263, the first upper insulating layer 258, and the second structure 221', and may extend into the lower structure 203. The gate contact plug 289 may penetrate the gate pad GP of the gate layer 227g and may also penetrate both the gate layers 227g and 240g, and may contact and be electrically connected to the gate pad GP. The gate contact plug 289 may be electrically connected to the second peripheral circuit pad 211p2 in the lower structure 203.

[0202] Gate contact plugs 289 may contact gate pads GP and may be spaced apart from other gate layers 227g and 240g. For example, one of the gate contact plugs 289 may contact the gate pads GP of one of the gate layers 227g and 240g and may be spaced apart from the gate layers 227g and 240g, which are disposed at a height lower than that of one of the gate layers, by buffer insulating layers 227 and 240.

[0203] The gate contact plug 289 may include a protrusion 289E that protrudes horizontally from the portion of the gate contact plug 289 that contacts the gate pad GP. Therefore, the protrusion 289E of the gate contact plug 289 can contact the gate pad GP.

[0204] Each of the gate contact plugs 289 may include an upper region 289US disposed at the same height as the upper region 287US of the peripheral contact plug 287, and the structure of the upper region 289US of the contact plug 289 may be substantially the same as the structure of the upper region 287US of the peripheral contact plug 287. For example, the upper region 289US of each of the gate contact plugs 289 may include a first region 289US_1, a second region 287US_3, and a connecting region 289US_2 corresponding to the first region 287US_1, the second region 287US_3, and the connecting region 287US_2 of the upper region 287US of the peripheral contact plug 287, respectively.

[0205] The semiconductor device 200 according to an example embodiment of the present disclosure may further include a third upper insulating layer 291 disposed on the second upper insulating layer 273.

[0206] The semiconductor device 200 according to an example embodiment of the present disclosure may further include peripheral upper plugs 295a and 295b penetrating the third upper insulating layer 291. The peripheral upper plugs 295a and 295b may include a first peripheral upper plug 295a electrically connected to a first peripheral contact plug 287a, and a second peripheral upper plug 295b electrically connected to a second peripheral contact plug 287b.

[0207] The semiconductor device 200 according to an example embodiment of the present disclosure may further include a bit line contact plug 296a that extends through the first upper insulating layer to the third upper insulating layers 258, 273, 291 and the capping layer 263 and is electrically connected to the storage vertical structure 47.

[0208] Each of the peripheral plugs 295a and 295b and the bit line contact plug 296a may include a plug pattern 295_2 and a conductive liner 295_1 covering the side and bottom surfaces of the plug pattern 295_2.

[0209] The semiconductor device 200 according to an example embodiment of the present disclosure may further include wirings 298b, 298a, and 298c disposed on a third upper insulating layer 291. Wirings 298b, 298a, and 298c may include a bit line 298b electrically connected to a bit line contact plug 296a, a first peripheral wiring 298a electrically connected to a first peripheral upper plug 295a, and a second peripheral wiring 298c electrically connected to a second peripheral upper plug 295b.

[0210] In the following description, reference will be made to Figure 13 Description Reference Figure 11A and Figure 12 A modified example of the described peripheral contact plug 287. Figure 13 It can be shown Figure 12The modified structure of the peripheral contact plug 287 in the example in the enlarged diagram.

[0211] In the modified example, refer to Figure 13 , Figure 12 The peripheral contact plug 287 can be modified to have the same width or a peripheral contact plug 287a' with a monotonically varying width. Therefore, at the same height as the upper region 289US of each gate contact plug in the gate contact plug 289, the side surface profile of the peripheral contact plug 287a' can be different from the side surface profile of the upper region 289US of each gate contact plug in the gate contact plug 289.

[0212] In the following description, reference will be made to Figure 14 This describes a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 14 In this context, region Ia-Ia' can be a cross-sectional region showing a region cut along a first horizontal direction, while region IIa-IIa' can be a cross-sectional region showing a region cut along a second horizontal direction perpendicular to the first horizontal direction.

[0213] refer to Figure 14 The semiconductor device 300 according to an example embodiment of the present disclosure may include a lower structure 303 and an upper structure 403 that overlap in the vertical direction. The lower structure 303 may be a memory semiconductor chip, and the upper structure 403 may be a logic semiconductor chip.

[0214] The lower structure 303 may include a pattern structure 317 and a structure 321 on the pattern structure 317. The pattern structure 317 may include components respectively related to a reference... Figures 1 to 2C The first pattern layer 17a to the fourth pattern layer 17d are described as corresponding to the first pattern layer 317a, the second pattern layer 317b, the third pattern layer 317c, and the fourth pattern layer 317d.

[0215] Structure 321 may have the same characteristics as the reference. Figures 1 to 2C The second structure 21' described is substantially the same as the structure except for the through region TA. For example, structure 321 may include a stacked structure comprising alternately stacked gate layers 327g and 340g and interlayer insulating layers 325 and 338. Gate layers 327g and 340g may include those referenced in the design. Figures 1 to 2C The examples described are substantially the same as gate pads 327p and 340p. Structure 321 may include the same as the reference. Figures 1 to 2C The first intermediate insulating layer 332 and the second intermediate insulating layer 344 are described.

[0216] The lower structure 303 may also include components that can be referenced. Figures 1 to 2CThe examples described are the same as the first upper insulating layer 58, the capping layer 63, the second upper insulating layer 73, and the third upper insulating layer 91.

[0217] The lower structure 303 may include components that can be referenced. Figures 1 to 2C The example described includes the same separate structure 77, storage vertical structure 47, supporting vertical structure 61, gate contact plug 89, bit line contact plug 96a, and gate upper plug 96b. The lower structure 303 may also include the same as the referenced... Figures 1 to 2C The third peripheral contact plug 87c described is substantially the same as the peripheral contact plug 387. The lower structure 303 may also include components similar to those referenced. Figures 1 to 2C The third peripheral plug 95c described is basically the same as the peripheral plug 95a.

[0218] The lower structure 303 may include wirings 98b, 98a and 98c that are in contact with and electrically connected to the bit line contact plug 96a, the gate plug 96b and the peripheral plug 95a, respectively.

[0219] The lower structure 303 may include a capping insulation structure 315 located on the third upper insulation layer 91, and a lower bonding wiring structure 310 electrically connected to wirings 98b, 98a, and 98c in the capping insulation structure 315. The lower bonding wiring structure 310 may also include a lower bonding pad 310p.

[0220] The upper structure 403 may include a semiconductor substrate 404, peripheral circuitry 409 disposed between the semiconductor substrate 404 and the lower structure 303, and an upper bonding wiring structure 410 disposed between the peripheral circuitry 409 and the lower structure 303. The upper bonding wiring structure 410 may include an upper bonding pad 410p. The peripheral circuitry 409 may include peripheral devices such as transistors, including a peripheral gate 409a and a peripheral source / drain 409b. The lower bonding pad 310p of the lower bonding wiring structure 310 may contact the upper bonding pad 410p of the upper bonding wiring structure 410. Both the lower bonding pad 310p and the upper bonding pad 410p may include copper material.

[0221] Reference Figure 15 Examples of methods for forming a semiconductor device according to exemplary embodiments of the present disclosure are described. Figure 15 This is a flowchart illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure.

[0222] refer to Figure 15A preliminary stacked structure comprising alternating interlayer insulating layers and molding layers stacked on a lower structure can be formed (S10). A storage vertical structure can be formed (S20). The storage vertical structure can penetrate the preliminary stacked structure and can contact the lower structure. Support holes and lower peripheral contact holes can be formed (S30). Support holes and lower peripheral contact holes can penetrate the preliminary stacked structure and expose the lower structure. A capping layer defining an air gap and covering the support holes and lower peripheral contact holes can be formed (S40). A separation trench can be formed (S50). The separation trench can expose the side surface of the molding layer of the preliminary stacked structure. The molding layer of the preliminary stacked structure can be replaced by a gate layer (S60). A separation structure can be formed in the separation trench (S70). A peripheral contact hole can be formed, at least penetrating the capping layer and exposing a conductive region disposed below the lower peripheral contact hole (S80). A peripheral contact plug can be formed in the peripheral contact hole (S90).

[0223] In the following description, reference will be made to Figures 16A to 16C Together Figure 15 Together, they form the reference above. Figures 1 to 2C An example of a method for describing semiconductor device 1. Figures 16A to 16C middle, Figure 16A It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 16B It shows along Figure 1 A cross-sectional view of the region intercepted by line II-II' in the diagram, and Figure 16C It shows along Figure 1 A cross-sectional view of the region intercepted by line III-III' in the diagram.

[0224] refer to Figure 1 , Figure 15 as well as Figures 16A to 16C The lower structure 3 can be formed. Forming the lower structure 3 may include: forming a peripheral circuit 8 and a lower insulating layer 13 covering the peripheral circuit 8 on a semiconductor substrate 4; forming a preliminary pattern structure 17 with gaps 17g on the lower insulating layer 13; and forming an inner insulating layer 19a filling the gaps 17g and an outer insulating layer 19b disposed on the outer surface of the preliminary pattern structure 17. The peripheral circuit 8 may include a circuit device 9 such as a transistor and a circuit interconnect 11 electrically connected to the circuit device 9, the circuit device 9 including a peripheral gate 9a and a peripheral source / drain 9b. A portion of the circuit interconnect 11 may be a first peripheral circuit pad 11p1 and a second peripheral circuit pad 11p2.

[0225] Forming the preliminary pattern structure 17 may include: forming a first pattern layer 17a; forming a first preliminary intermediate pattern layer 17b and a second preliminary intermediate pattern layer 17d spaced apart from each other on the first pattern layer 17a; and forming a third pattern layer 17c on the first pattern layer 17a that covers the first preliminary intermediate pattern layers 17b and 17d. The first pattern layer 17a and the third pattern layer 17c may be formed of silicon layers. Each of the first preliminary intermediate pattern layer 17b and the second preliminary intermediate pattern layer 17d may include a plurality of layers stacked sequentially, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially.

[0226] The inner insulating layer 19a and the outer insulating layer 19b may include an inner insulating layer 19a that fills the gap 17g and an outer insulating layer 19b formed on the outer surface of the preliminary pattern structure 17.

[0227] A preliminary stacked structure 23 and 35 can be formed, comprising interlayer insulating layers 25 and 38 alternately stacked on the lower structure 3, and horizontal layers 27 and 40 (S10). An insulating structure can be formed covering at least a portion of the preliminary stacked structures 23 and 35. The preliminary stacked structures 23 and 35 and the insulating structure can form a preliminary upper structure 21. The insulating structure may include a first insulating layer 32 and a second insulating layer 44.

[0228] The formation of the preliminary upper structure 21 may include: forming a first preliminary stacked structure 23 on the preliminary patterned structure 17, forming a first insulating layer 32 covering a portion of the first preliminary stacked structure 23 and the outer insulating layer 19b, forming a second preliminary stacked structure 35 on the first preliminary stacked structure 23, and forming a second insulating layer 44 covering a portion of the second preliminary stacked structure 35 and the first insulating layer 32.

[0229] The first preliminary stack structure 23 may include alternating stacked first interlayer insulating layers 25 and first horizontal layers 27. The second preliminary stack structure 35 may include alternating stacked second interlayer insulating layers 38 and second horizontal layers 40. The first interlayer insulating layers 25 and 38 may be formed of silicon oxide, while the first horizontal layers 27 and 40 may be formed of silicon nitride.

[0230] In an exemplary embodiment of this disclosure, on at least one side of the first preliminary stacking structure 23, the first horizontal layer 27 may include a pad region arranged in a stepped shape. On at least one side of the second preliminary stacking structure 35, the second horizontal layer 40 may include a pad region arranged in a stepped shape. In the preliminary upper structure 21, the area where the pad regions of the first horizontal layer 27 and the second horizontal layer 40 arranged in a stepped shape are disposed may be referred to as the stepped region SA, and the area where the first horizontal layer 27 and the second horizontal layer 40 are disposed in the region adjacent to the stepped region SA may be referred to as the memory cell array region MCA.

[0231] In an exemplary embodiment of this disclosure, a first reinforcing horizontal layer 28 may be formed on the stepped pad regions of the first horizontal layer 27 before the formation of the first insulating layer 32. A second reinforcing horizontal layer 41 may be formed on the stepped pad regions of the second horizontal layer 40 before the formation of the second insulating layer 44. The first reinforcing horizontal layer 28 and the second reinforcing horizontal layer 41 may be formed of silicon nitride.

[0232] A storage vertical structure 47 can be formed (S20). Forming the storage vertical structure 47 may include: forming a sacrificial vertical portion through the first preliminary stacking structure 23, forming a second preliminary stacking structure 35, forming an upper channel hole through the second preliminary stacking structure 35 and exposing the sacrificial vertical portion, forming a lower channel hole by removing the sacrificial vertical portion exposed by the upper channel hole, and forming the storage vertical structure 47 in the lower channel hole and the upper channel hole before forming the second preliminary stacking structure 35.

[0233] A first upper insulating layer 58 can be formed on the initial upper structure 21.

[0234] Support hole 60s and lower peripheral contact holes 60a, 60b and 60c can be formed (S30). Support hole 60s and lower peripheral contact holes 60a, 60b and 60c can be formed simultaneously. Lower peripheral contact holes 60a, 60b and 60c may include a first lower peripheral contact hole 60a, a second lower peripheral contact hole 60b and a third lower peripheral contact hole 60c.

[0235] The support hole 60s can penetrate the first upper insulating layer 58 and the preliminary upper structure 21, and can expose the first patterned layer 17a of the preliminary patterned structure 17. The support hole 60s can penetrate at least a portion of the preliminary stacked structures 23 and 35.

[0236] The first lower peripheral contact hole 60a can penetrate the first upper insulating layer 58, the insulating structure and the outer insulating layer 19b, can extend downwards, and can expose the first peripheral circuit pad 11p1.

[0237] The second lower peripheral contact hole 60b can penetrate the first upper insulating layer 58, the preliminary upper structure 21 and the inner insulating layer 19a, can extend downward and can expose the second peripheral circuit pad 11p2.

[0238] The third lower peripheral contact hole 60c can penetrate the first upper insulating layer 58 and the preliminary upper structure 21, and can expose the first pattern layer 17a of the preliminary pattern structure 17.

[0239] A capping material layer (S40) can be formed that defines air gaps 69a and 69b and covers the support hole 60s and the lower peripheral contact holes 60a, 60b and 60c. In an exemplary embodiment of this disclosure, the formation of the capping material layer may include sequentially forming a first capping layer and an upper capping layer 67. The first capping layer may cover the inner walls of the support hole 60s and the lower peripheral contact holes 60a, 60b and 60c, define at least a portion of the air gaps 69a and 69b in the lower peripheral contact holes 60a, 60b and 60c, and may cover the upper portion of the first upper insulating layer 58. The upper capping layer 67 may cover the support hole 60s and the lower peripheral contact holes 60a, 60b and 60c on the first capping layer, and may limit the upper portion of the air gaps 69a and 69b. The air gaps 69a and 69b may include a first air gap 69a and a second air gap 69b. The first air gap 69a may be limited by the first capping layer and the upper capping layer 67, and at least a portion of the first air gap 69a may be formed in the support hole 60s. The second air gap 69b may be limited by the first capping layer and the upper capping layer 67, and at least a portion of the second air gap 69b may be formed in each of the lower peripheral contact holes 60a, 60b and 60c.

[0240] In the first capping layer, the portion of the first capping layer covering the inner wall of the support hole 60s can be the support layer 65a, the portion covering the lower peripheral contact holes 60a, 60b, and 60c can be the spacer layer 65b, and the portion covering the upper part of the first upper insulating layer 58 can be the lower capping layer 65c. Therefore, the support layer 65a, the spacer layer 65b, and the lower capping layer 65c can be integral with each other. In an exemplary embodiment of this disclosure, the lower capping layer 65c and the upper capping layer 67 can form a capping layer 63.

[0241] In exemplary embodiments of this disclosure, the first capping layer may be formed of a single layer or two or more layers. For example, the first capping layer may include silicon oxide covering the inner wall of the support hole 60s with a minimum thickness, and may be formed on the support hole 60s to have a relatively thick thickness. The first capping layer may include silicon oxide formed by an atomic layer deposition process. In another example, forming the first capping layer may include forming a silicon oxide layer and forming a silicon nitride layer on the silicon oxide layer.

[0242] Return to reference Figure 1 , Figure 15 as well as Figures 2A to 2C This forms a through-capping layer 63, a first upper insulating layer 58, and a preliminary upper structure 21 (in... Figures 16A to 16C The initial separation trench and baffle trench in the middle are formed to form an initial separation structure and a baffle structure 71 that fill the initial separation trench and the baffle trench respectively, and a second upper insulating layer 73 is formed on the capping layer 63.

[0243] The initial separation structure and baffle structure 71 may include an insulating material layer. For example, the formation of the initial separation structure and baffle structure 71 may include: forming an insulating material layer (e.g., a silicon oxide layer and / or a silicon nitride layer, etc.) covering the inner walls of the initial separation trench and the baffle trench, and forming a polycrystalline silicon layer on the insulating material layer.

[0244] The first horizontal layer 27 and the second horizontal layer 40, which are constrained by the baffle structure 71, can be referred to as such in reference. Figures 1 to 2C The first insulating horizontal layer 27i and the second insulating horizontal layer 40i are described. The region of the upper structure 21' in which the first insulating horizontal layer 27i and the second insulating horizontal layer 40i are formed can be referred to as the through region TA.

[0245] A separation trench 75 can be formed (S50). The formation of the separation trench 75 may include: forming an upper separation trench 75b that penetrates the second upper insulating layer 73 and exposes the initial separation structure, and forming a lower separation trench 75a by removing the initial separation structure. Therefore, each of the separation trenches 75 may include a lower separation trench 75a and an upper separation trench 75b. The width of the upper separation trench 75b may be greater than the width of the lower separation trench 75a. The upper separation trench 75b may be disposed on the upper surface of the capping layer 63.

[0246] In an exemplary embodiment of this disclosure, a second preliminary intermediate pattern layer 17d in the stepped region SA may be disposed between the separation trenches 75 and may not be exposed by the separation trenches 75.

[0247] In an exemplary embodiment of this disclosure, in the memory cell array region MCA, the separation trench 75 may penetrate through the first preliminary intermediate pattern layer 17b and may expose the first preliminary intermediate pattern layer 17b. An empty space may be formed by etching a portion of the memory vertical structure 47 while etching the first preliminary intermediate pattern layer 17b, and the first intermediate pattern layer 17b' may be formed in this empty space. The intermediate pattern layer 17b' may be formed of a silicon layer, such as a polysilicon layer with N-type conductivity. Before exposing the first preliminary intermediate pattern layer 17b, sacrificial spacers may be formed on the side surfaces of the preliminary stack structures 23 and 35 exposed by the separation trench 75, and subsequently, the intermediate pattern layer 17b' may be formed, and the sacrificial spacers may be removed to expose the preliminary stack structures 23 and 35 (in...). Figures 16A to 16C The side surface of (middle).

[0248] The initial stacked structures 23 and 35 can be etched (in) Figures 16A to 16C The first horizontal layer 27 and the second horizontal layer 40 exposed by the separation trench 75 (in the middle) Figures 16A to 16C (in the middle) to form an empty space, and a first gate layer 27g and a second gate layer 40g can be formed in this empty space. The first preliminary stacked structure 23 (in...) Figures 16A to 16C (in) can be formed as a first stacked structure 23' including a first interlayer insulating layer 25 and a first gate layer 27g, and a second preliminary stacked structure 35 (in) Figures 16A to 16C The upper structure 21 (in the middle) can be formed as a second stacked structure 35' including a second interlayer insulating layer 38 and a second gate layer 40g. Therefore, the initial upper structure 21 (in Figures 16A to 16C The upper structure 21' can be formed as a first stacked structure 23' and a second stacked structure 35'.

[0249] In an exemplary embodiment of this disclosure, a reference may be conformally formed before the first gate layer 27g and the second gate layer 40g are formed in the empty space. Figure 3A The dielectric layer 56 is described.

[0250] Forming the first gate layer 27g and the second gate layer 40g in the empty space may include: forming a conductive material layer in the empty space and etching the conductive material layer.

[0251] A separation structure 77 may be formed in the separation trench 75. In one example, the separation structure 77 may be formed of silicon oxide. In another example, the separation structure 77 may be formed as including a conductive pattern and an insulating layer covering the side surfaces of the conductive pattern.

[0252] In an exemplary embodiment of this disclosure, gate contact holes may be formed through the second upper insulating layer 73, the capping layer 63, and the insulating structure, and exposing the gate pads 27p and 40p of the first gate layer 27g and the second gate layer 40g in the stepped region SA.

[0253] Peripheral contact holes (S80) can be formed that at least penetrate the capping layer 63 and expose conductive areas disposed below the lower peripheral contact holes 60a, 60b, and 60c. Forming peripheral contact holes may include: forming upper peripheral contact holes that penetrate the second upper insulating layer 73 and the capping layer 63 and overlap with the lower peripheral contact holes 60a, 60b, and 60c, and exposing the first peripheral circuit pad 11p1, the second peripheral circuit pad 11p2, and the first pattern layer 17a of the preliminary pattern structure 17 by etching at least a portion of the spacer layer 65b disposed in the lower peripheral contact holes 60a, 60b, and 60c below the upper peripheral contact holes.

[0254] The upper peripheral contact hole may include a first upper peripheral contact hole, a second upper peripheral contact hole, and a third upper peripheral contact hole. The peripheral contact hole may include a first peripheral contact hole, a second peripheral contact hole, and a third peripheral contact hole. The first peripheral contact hole may include a first lower peripheral contact hole 60a and a first upper peripheral contact hole, the second peripheral contact hole may include a second lower peripheral contact hole 60b and a second upper peripheral contact hole, and the third peripheral contact hole may include a third lower peripheral contact hole 60c and a third upper peripheral contact hole.

[0255] Peripheral contact plugs 87a, 87b, and 87c can be formed in the peripheral contact holes (S90). The peripheral contact plugs 87a, 87b, and 87c may include a first peripheral contact plug 87a in a first peripheral contact hole, a second peripheral contact plug 87b in a second peripheral contact hole, and a third peripheral contact plug 87c in a third peripheral contact hole.

[0256] A gate contact plug 89 can be formed to fill the gate contact hole. The gate contact plug 89 can be formed simultaneously with peripheral contact plugs 87a, 87b, and 87c. For example, peripheral contact plugs 87a, 87b, and 87c and gate contact plug 89 may include plug patterns 87_2 and 89_2 and conductive liners 87_1 and 89_1 covering the side and bottom surfaces of plug patterns 87_2 and 89_2, respectively.

[0257] A third upper insulating layer 91 can be formed on the second upper insulating layer 73.

[0258] Bit line contact plug 96a electrically connected to storage vertical structure 47, gate plug 96b electrically connected to gate contact plug 89, and first peripheral upper plug to third peripheral upper plug 95a, 95b, and 95c electrically connected to first peripheral contact plug to third peripheral contact plug 87a, 87b, and 87c can be formed simultaneously. Each of the bit line contact plug 96a, gate plug 96b, and first peripheral upper plug to third peripheral upper plug 95a, 95b, and 95c may include plug pattern 95_2 and conductive liner 95_1 covering the bottom and side surfaces of plug pattern 95_2.

[0259] The bit line 98b electrically connected to the bit line contact plug 96a, the gate connection wiring 98g electrically connected to the gate plug 96b and the second peripheral plug 95b, the first peripheral wiring 98a electrically connected to the first peripheral plug 95a, and the second peripheral wiring 98c electrically connected to the third peripheral plug 95c can be formed simultaneously on the third upper insulating layer 91.

[0260] In the following description, reference will be made to Figure 17 , Figure 18 and Figure 19The description includes a data storage system for semiconductor devices described in the example embodiments of this disclosure.

[0261] Figure 17 This is a diagram illustrating a data storage system including semiconductor devices according to an example embodiment of the present disclosure.

[0262] refer to Figure 17 The data storage system 1000 according to an example embodiment of this disclosure may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including the semiconductor device 1100, or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD) device including the semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0263] In an example embodiment of this disclosure, the data storage system 1000 may be implemented as an electronic system for storing data.

[0264] Semiconductor device 1100 may be a reference Figures 1 to 16C The semiconductor device described in one of the foregoing example embodiments. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F.

[0265] The first structure 1100F can be configured as a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. For example, the first structure 1100F may include peripheral circuitry 8 (in... Figure 2A middle).

[0266] The second structure 1100S can be configured as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0267] The above pattern structure 17' (in Figures 2A to 2C The (middle) may include a silicon layer with N-type conductivity, and the silicon layer with N-type conductivity may be a common source line (CSL).

[0268] In the second structure 1100S, each of the memory cell string CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary. For example, in the example embodiment of this disclosure, only one lower transistor and only one upper transistor may be used.

[0269] In exemplary embodiments of this disclosure, upper transistors UT1 and UT2 may include string select transistors, while lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0270] Reference Figure 5A and Figure 5B In the first gate layer 27g and the second gate layer 40g described, the lower gate layers GL1 and GL2 can be lower gate lines LL1 and LL2, at least a plurality of intermediate gate layers GM can be word lines WL, and the upper gate layers GU1 and GU2 can be upper gate lines UL1 and UL2.

[0271] In exemplary embodiments of this disclosure, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 can be used for an erase operation that erases data stored in the memory cell using the gate-induced drain leakage (GIDL) phenomenon.

[0272] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0273] In the exemplary embodiments of this disclosure, the lower gate layers GL1 and GL2 described above (in) Figure 3A (in) can be the lower gate lines LL1 and LL2, while the upper gate layers GU1 and GU2 (in) Figure 3A (Middle) can be the upper gate lines UL1 and UL2. Multiple intermediate gate layers GM (in Figure 3AIn the (Chinese), it may be a word line WL.

[0274] The bit line BL can be electrically connected to the page buffer 1120 through a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be the bit line 98b in the above Figure 2A and Figure 2B above.

[0275] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0276] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. In an exemplary embodiment of the present disclosure, the data storage system 1000 can include a plurality of semiconductor devices 1100, and in this case, the controller 1200 can control the plurality of semiconductor devices 1100.

[0277] The processor 1210 can control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 can operate according to a predetermined firmware and can access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 can include a NAND interface 1221 for handling communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be written into the memory cell transistors MCT of the semiconductor device 1100, and data to be read from the memory cell transistors MCT can be sent. The host interface 1230 can provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0278] Figure 18 is a perspective view showing a data storage system including a semiconductor device according to an exemplary embodiment of the present disclosure.

[0279] Reference Figure 18A data storage system 2000 according to an example embodiment of the present disclosure may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0280] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment of this disclosure, the data storage system 2000 may communicate with the external host via one of the following interfaces: for example, Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In an example embodiment of this disclosure, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0281] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0282] DRAM 2004 can be configured as a buffer memory to mitigate the speed difference between the semiconductor package 2003, which can serve as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also be used as a high-speed cache memory and can provide space for temporary data storage during control operations of the semiconductor package 2003. When DRAM 2004 is included in the data storage system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0283] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each semiconductor chip 2200 may include a reference Figures 1 to 16CThe semiconductor device described in one of the foregoing example embodiments. More than two separate semiconductor packages may be included in semiconductor package 2003.

[0284] Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0285] The package substrate 2100 can be configured as a printed circuit board including on-package pads 2130. Each of the semiconductor chips 2200 may include input / output pads 2210.

[0286] In an exemplary embodiment of this disclosure, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a bonding wire method and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In an exemplary embodiment of this disclosure, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs), instead of the connection structure 2400 using a bonding wire method.

[0287] In exemplary embodiments of this disclosure, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the motherboard 2001, and the controller 2002 may be connected to the semiconductor chip 2200 via wiring formed on the interposer substrate.

[0288] Figure 19 This is a cross-sectional view illustrating a data storage system including semiconductor devices according to an example embodiment of the present disclosure. Figure 19 It shows Figure 18 Example embodiment of semiconductor package 2003, which shows Figure 18 The cross-sectional area of ​​semiconductor package 2003 taken along line VI-VI'.

[0289] refer to Figure 19In semiconductor packaging 2003, packaging substrate 2100 can be configured as a printed circuit board. Packaging substrate 2100 may include a packaging substrate body portion 2120, an upper packaging pad 2130 disposed on the upper surface of the packaging substrate body portion 2120, a lower packaging pad 2125 disposed on or exposed through the lower surface of the packaging substrate body portion 2120, and internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 in the packaging substrate body portion 2120. The upper pad 2130 can be electrically connected to a connection structure 2400. The lower pad 2125 can be connected to a wiring pattern 2005 of the motherboard 2001 of the data storage system 2000 via a conductive connection portion 2800.

[0290] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, which includes peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 and a separation structure through the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a gate connection wiring 98g electrically connected to the word line WL of the gate stack structure 3210. Figure 2A (Middle). The first structure 3100 may include Figure 17 The first structure 1100F, and the second structure 3200 may include Figure 17 The second structure 1100S in it.

[0291] Each semiconductor chip 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may pass through the gate stack structure 3210 and may also be disposed on the outside of the gate stack structure 3210.

[0292] Each semiconductor chip 2200 may also include input / output connection wiring electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and input / output pads 2210 electrically connected to the input / output connection wiring.

[0293] exist Figure 19 In the figure, an enlarged portion, indicated by reference numeral 1, is provided to describe the portion thereof. Figure 19 The semiconductor chip 2200 in the middle can be modified to have, for example, Figure 2A An example of the cross-sectional structure in the image. Therefore, each semiconductor chip 2200 may include a reference... Figures 1 to 16CSemiconductor devices 1, 100, and 300 in one of the aforementioned example embodiments are described.

[0294] According to the aforementioned example embodiments, a stable and reliable supporting vertical structure and peripheral contact plugs can be provided.

[0295] While exemplary embodiments of the present disclosure have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made thereto without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: First structure; The second structure includes a stacked structure and an intermediate insulating layer covering at least a portion of the stacked structure, the stacked structure including a first stacked structure on the first structure and a second stacked structure on the first stacked structure; An insulating structure is provided on the second structure; The storage structure is vertical and extends through the second structure; A vertical support structure extends through the second structure and includes an air gap and a support layer that at least defines the lower portion and sidewalls of the air gap; The peripheral contact plug penetrates the second structure; as well as Gate contact plug, Each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers. The gate layers are vertically spaced apart in the first region and include gate pads disposed in a second region adjacent to the first region. The gate contact plug is electrically connected to the gate pad. The vertical storage structure penetrates the stacked structure in the first region. The vertical storage structure includes a slope variation portion located between the uppermost gate layer in the first stacked structure and the lowermost gate layer in the second stacked structure. The vertical supporting structure penetrates at least a portion of the gate layer in the second region. The air gap supporting the vertical structure includes a portion positioned at the same height as the slope-changing portion of the storage vertical structure. The peripheral contact plug is spaced apart from the gate layer. The peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the stacked structure. The upper region of the peripheral contact plug includes a first part, a second part, and a connecting part disposed between the first part and the second part. The side of the connecting portion has a slope that is different from the slope of at least one of the side of the first portion and the side of the second portion.

2. The semiconductor device of claim 1, wherein, In the gate contact plug, the portion of the gate contact plug disposed at a height higher than the upper surface of the uppermost gate layer in the gate layer of the stacked structure has a side surface profile that is different from the side surface profile of the upper region of the peripheral contact plug.

3. The semiconductor device of claim 2, wherein, In the gate contact plug, the side portion of the gate contact plug disposed at a height higher than the upper surface of the uppermost gate layer in the gate layer of the stacked structure is substantially vertical.

4. The semiconductor device of claim 1, wherein, The gate contact plug and the peripheral contact plug have upper surfaces that are coplanar with each other.

5. The semiconductor device of claim 1, wherein, The upper surface of the gate contact plug is positioned at a different height than the upper surface of the peripheral contact plug.

6. The semiconductor device according to claim 1, wherein, The insulation structure includes a lower capping layer extending from the support layer and an upper capping layer on the lower capping layer, and The support layer and the lower cover layer include insulating materials.

7. The semiconductor device of claim 1, wherein, The upper end of the air gap is positioned at a height higher than the upper surface of the vertical storage structure.

8. The semiconductor device of claim 1, wherein, The upper end of the air gap is positioned at a height lower than the upper surface of the uppermost gate layer in the gate layer of the stacked structure.

9. The semiconductor device of claim 1, wherein, In the upper region of the peripheral contact plug, the minimum width of the first portion is greater than the minimum width of the connecting portion, and the maximum width of the second portion is less than the maximum width of the connecting portion.

10. The semiconductor device of claim 1, wherein, In the upper region of the peripheral contact plug, the minimum width of the first portion is less than the maximum width of the connecting portion, the maximum width of the second portion is greater than the minimum width of the connecting portion, and the maximum width of the second portion is greater than the maximum width of the first portion.

11. The semiconductor device according to claim 1, wherein The first structure further includes a semiconductor substrate, a first peripheral circuit pad and a second peripheral circuit pad on the semiconductor substrate, and a pattern structure disposed on the semiconductor substrate at a height higher than the first peripheral circuit pad and the second peripheral circuit pad. The storage vertical structure and the supporting vertical structure are in contact with the pattern structure.

12. The semiconductor device according to claim 11, wherein The pattern structure includes a first pattern layer, a second pattern layer on the first pattern layer, and a third pattern layer on the second pattern layer. The storage vertical structure penetrates the second pattern layer and the third pattern layer, and extends into the first pattern layer; The vertical storage structure includes an insulating gap filling layer, a channel layer covering the sides and bottom of the insulating gap filling layer, a pad material layer on the insulating gap filling layer that contacts the channel layer, and a data storage structure that at least covers the outer side of the channel layer. The data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer; and The second pattern layer extends through the data storage structure and is in contact with the channel layer.

13. The semiconductor device of claim 12, wherein, The lower surface of the peripheral contact plug contacts the first peripheral circuit pad.

14. The semiconductor device according to claim 11, wherein The gate contact plug extends through the gate pad and contacts the gate pad. The lower surface of the gate contact plug contacts the second peripheral circuit pad, and In the gate contact plug, the portion of the gate contact plug disposed at a height higher than the upper surface of the uppermost gate layer in the gate layer of the stacked structure has a side profile that is substantially the same as the side profile of the upper region of the peripheral contact plug.

15. The semiconductor device according to claim 1, further comprising: A chip structure, including peripheral circuitry, wherein the chip structure is disposed on the insulating structure.

16. The semiconductor device according to claim 1, further comprising: Bit line contact plugs are in contact with the storage vertical structure. Wherein, the upper surface of the bit line contact plug and the upper surface of the peripheral contact plug are coplanar, and Each of the bit line contact plug and the peripheral contact plug includes a plug pattern and a conductive liner covering the lower and side surfaces of the plug pattern.

17. The semiconductor device of claim 1, wherein, The peripheral contact plug includes a plug pattern, a conductive liner covering the lower and side surfaces of the plug pattern, and a first air gap disposed in the plug pattern.

18. The semiconductor device of claim 17, further comprising: The second air gap is disposed on the first air gap and spaced apart from the first air gap in the plug pattern.

19. A semiconductor device, comprising: Patterned structures, including silicon layers; The stacked structure on the patterned structure includes a first stacked structure and a second stacked structure on the first stacked structure, wherein each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers, and in the first stacked structure and the second stacked structure, the gate layers are vertically stacked and spaced apart from each other in a first region, and include gate pads arranged in a stepped shape in a second region adjacent to the first region. An insulating structure on the stacked structure; A separation structure that penetrates the stacked structure in the first and second regions and extends within the insulating structure; A vertical structure is stored, which extends through the stacked structure between the separated structures in the first region; A vertical support structure is provided, which extends through the stacked structure between the separated structures in the second region and includes an air gap; A gate contact plug contacts the gate pad; Peripheral contact plugs, spaced apart from the gate layer; and Bit line contact plugs, on the storage vertical structure The peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the stacked structure. The upper region of the peripheral contact plug includes a first portion, a connecting portion disposed below the first portion, and a second portion disposed below the connecting portion. The side of the connecting portion has a slope different from that of at least one of the sides of the first portion and the second portion. Wherein, the side portion of the storage vertical structure includes a slope variation portion at the height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure, wherein the slope variation portion of the side portion of the storage vertical structure, and The side portion of the lower region of the peripheral contact plug is substantially vertical at the height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure.

20. A data storage system, comprising: Motherboard; Semiconductor devices, on the motherboard; as well as The controller is electrically connected to the semiconductor device on the motherboard. The semiconductor device includes: Patterned structures, including silicon layers; The stacked structure on the patterned structure includes a first stacked structure and a second stacked structure on the first stacked structure, wherein each of the first stacked structure and the second stacked structure includes alternately stacked interlayer insulating layers and gate layers, and in the first stacked structure and the second stacked structure, the gate layers are vertically stacked and spaced apart from each other in a first region, and include gate pads arranged in a stepped shape in a second region adjacent to the first region. An insulating structure on the stacked structure; A separation structure extends through the stacked structure and into the insulating structure in the first and second regions; A vertical structure is stored, which extends through the stacked structure between the separated structures in the first region; A vertical support structure is provided, which extends through the stacked structure between the separated structures in the second region and includes an air gap; A gate contact plug contacts the gate pad; Peripheral contact plugs, spaced apart from the gate layer; and Bit line contact plugs, on the storage vertical structure The peripheral contact plug includes an upper region disposed at a height higher than the upper surface of the uppermost gate layer in the stacked structure, and a lower region disposed at a height lower than the upper surface of the uppermost gate layer in the stacked structure. The upper region of the peripheral contact plug includes a first portion, a connecting portion disposed below the first portion, and a second portion disposed below the connecting portion. The side portion of the connecting portion has a slope different from that of at least one of the sides of the first portion and the second portion. Wherein, the side portion of the storage vertical structure includes a slope variation in height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure, and The side portion of the lower region of the peripheral contact plug is substantially vertical at the height between the uppermost gate layer in the gate layer of the first stacked structure and the lowermost gate layer in the gate layer of the second stacked structure.

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