Display panel, display device, and method for manufacturing display panel

Abstract

This application discloses a display panel, a display device, and a method for fabricating the display panel. The display panel includes: a substrate; an insulating layer disposed on the substrate and having a plurality of vias formed therein; an overlap portion formed within the vias, the overlap portion covering at least a portion of the sidewall of the via; and signal connection lines, at least a portion of the signal connection lines including a main body portion located on the first insulating layer away from the substrate layer, and an extension portion extending from the main body portion into the via and interconnected with the overlap portion. In this application embodiment, by forming a metal overlap portion within the vias, at least a portion of the signal connection lines located on both sides of the vias are interconnected through the overlap portion, thereby improving the yield of the signal connection lines.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] With the rapid development of electronic devices, users have increasingly higher requirements for screen ratio, making full-screen displays of electronic devices receive more and more attention from the industry.

[0003] Traditional electronic devices such as mobile phones and tablets need to integrate components such as front-facing cameras, earpieces, and infrared sensors. In existing technology, notches or holes are made in the display screen, allowing external light to enter the photosensitive element located beneath the screen. However, these electronic devices are not truly full-screen displays and cannot display images across the entire screen area; for example, the area corresponding to the front-facing camera cannot display an image.

[0004] To increase the screen-to-body ratio, some display panels place the driving circuit outside the light-transmitting area and connect the pixel electrodes in the light-transmitting area to the driving circuit outside the light-transmitting area through traces. However, this can lead to display defects due to the traces being prone to breakage. Summary of the Invention

[0005] This application provides a display panel, a display device, and a method for manufacturing the display panel, aiming to improve the defect rate of the display panel.

[0006] An embodiment of the first aspect of this application provides a display panel, the display panel comprising: a substrate; an insulating layer located on one side of the substrate and having a plurality of vias formed thereon; an overlap portion formed within the vias, the overlap portion covering at least a portion of the sidewall of the via where it is located; and signal connection lines, at least a portion of the signal connection lines including a main body portion located on the side of the insulating layer opposite to the substrate, and an extension portion extending from the main body portion into the vias and interconnected with the overlap portion.

[0007] According to an embodiment of the first aspect of this application, the insulating layer includes a first insulating layer and a second insulating layer located on the side of the first insulating layer facing away from the substrate, and the via includes a first via formed in the first insulating layer and a second via formed in the second insulating layer;

[0008] The display panel also includes a metal trace layer located between the first insulating layer and the second insulating layer.

[0009] The overlapping portion covers at least a portion of the sidewall of the first via, and the overlapping portion is made of the same material as the metal trace layer.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the size of the first via is smaller than the size of the second via.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the metal trace layer further includes a transition portion located on the surface of the first insulating layer facing the second insulating layer and surrounding at least one first via, the transition portion being interconnected with the overlap portion, the extension portion being interconnected with the overlap portion through the transition portion, or the extension portion being interconnected with both the transition portion and the overlap portion.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the transition portion is located on the surface of the first insulating layer exposed by the second via.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the extension dimension of the transition portion in the first via diameter direction is 1.5μm to 5μm.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the aperture of the first via is 2μm to 4μm, and the aperture of the second via is 4μm to 6μm.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes an active layer disposed between the substrate and the insulating layer, and the active layer further includes a pad, wherein at least a portion of the opening of the first via facing the substrate does not extend beyond the pad.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the display panel has a first display area and a second display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the display panel further includes:

[0017] A pixel electrode layer includes a first pixel electrode located in the first display area and connected to a signal connection line;

[0018] The driving circuit includes a first driving circuit for driving a first pixel electrode, the first driving circuit being connected to the first pixel electrode via a signal connection line.

[0019] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the orthographic projection of the via on the substrate and the orthographic projection of the first pixel electrode on the substrate are at least partially overlapped.

[0020] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the via's orthogonal projection on the substrate lies within the orthogonal projection of the first pixel electrode on the substrate.

[0021] According to any of the foregoing embodiments of the first aspect of this application, the signal connection line is a light-transmitting trace.

[0022] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the vias are located in the first display area.

[0023] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the vias are disposed within the first display area near the second display area.

[0024] According to any of the foregoing embodiments of the first aspect of this application, the second display area includes a main display area and a transition display area, the transition display area being located between the main display area and the first display area, and at least a portion of the vias being located in the transition display area.

[0025] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the vias are disposed in the transition display area close to the first display area.

[0026] According to any of the foregoing embodiments of the first aspect of this application, the radial dimension of the orthographic projection of the overlapping portion on the substrate is 2μm to 3μm.

[0027] According to any of the foregoing embodiments of the first aspect of this application, the signal connection line includes a first signal connection line and a second signal connection line. The first signal connection line includes an extension. The orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via on the substrate are at least partially misaligned.

[0028] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via on the substrate are completely misaligned.

[0029] The second aspect of this application also provides a display device, including the display panel of any of the first aspect embodiments described above.

[0030] An embodiment of the third aspect of this application also provides a method for manufacturing a display panel, comprising:

[0031] An insulating layer is prepared on a substrate, and the insulating layer is patterned to form vias;

[0032] Metal material is deposited inside the via to form an overlap;

[0033] A wiring layer is prepared on an insulating layer. The wiring layer includes signal connection lines, and at least a portion of the signal connection lines includes a main body portion located on the side of the insulating layer away from the substrate, and an extension portion extending from the main body portion into a via and interconnecting with an overlap portion.

[0034] In the display panel provided in this application embodiment, the display panel includes a substrate and an insulating layer, an overlap portion, and signal connection lines disposed on the substrate. A via is formed in the insulating layer, and an overlap portion is formed within the via and covers at least a portion of the sidewalls. Extensions of the signal connection lines are interconnected with the overlap portion, allowing at least a portion of the main body portions of the signal connection lines to be interconnected through the overlap portion. That is, signal connection lines located on both sides of the overlap portion can communicate with each other through the overlap portion. This improves the problem of signal connection lines being prone to breakage due to openings in the insulating layer, ensures the yield of the signal connection lines, and thus improves the yield of the display panel. Therefore, this application embodiment improves the yield of signal connection lines by forming an overlap portion within the via, allowing at least a portion of the signal connection lines located on both sides of the via to communicate with each other through the overlap portion. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0036] Figure 1 This is a top view schematic diagram of a display panel according to an embodiment of this application;

[0037] Figure 2 yes Figure 1 Enlarged structural diagram at point Q;

[0038] Figure 3 yes Figure 2 Sectional view at point BB;

[0039] Figure 4 yes Figure 3 A magnified schematic diagram of the local structure;

[0040] Figure 5 In another example Figure 3 A magnified schematic diagram of the local structure;

[0041] Figure 6 This is yet another example Figure 3 A magnified schematic diagram of the local structure;

[0042] Figure 7 This is yet another example Figure 3 A magnified schematic diagram of the local structure;

[0043] Figure 8 This is yet another example Figure 3 A magnified schematic diagram of the local structure;

[0044] Figure 9 yes Figure 1 A magnified structural diagram of the Q component in another embodiment;

[0045] Figure 10 This is a top view of a partial layer structure of a display panel provided in another embodiment of this application;

[0046] Figure 11 This is a top view schematic diagram of a display device according to an embodiment of this application;

[0047] Figure 12 yes Figure 11 Cross-sectional view along the DD direction;

[0048] Figure 13 This is a schematic flowchart of a method for manufacturing a display panel provided in an embodiment of this application;

[0049] Figure 14 This is a schematic flowchart of a method for manufacturing a display panel according to another embodiment of this application;

[0050] Figure 15 This is a schematic flowchart of a method for manufacturing a display panel according to another embodiment of this application.

[0051] Explanation of reference numerals in the attached figures:

[0052] 100, Display panel; 200, Photosensitive module; S1, First surface; S2, Second surface;

[0053] 01, Substrate; 024, Insulating layer; 024a, Via;

[0054] 02, First insulating layer; 20a, First sub-layer; 20b, Second sub-layer; 210, First via;

[0055] 03. Metal wiring layer; 310. Overlap; 320. Transition section;

[0056] 04. Second insulating layer; 410. Second via;

[0057] 5. Trace layer; 510. Signal connection line; 511. Main body; 512. Extension; 510a. First signal connection line; 510b. Second signal connection line;

[0058] 6. Pixel electrode layer; 610. First pixel electrode; 620. Second pixel electrode; 630. Interconnect structure;

[0059] 07. Active layer; 710. Spacer block;

[0060] 08. First metal layer;

[0061] 09. Second metal layer;

[0062] 10. Pixel definition layer; K1. First opening; 110. First light-emitting unit; K2. Second opening; 120. Second light-emitting unit; 130. Support pillar;

[0063] 11. Common electrode layer;

[0064] 12. Driving circuit; 121. First driving circuit; 122. Second driving circuit;

[0065] AA1, First display area; AA2, Second display area; ZA, Main display area; TA, Transition display area. Detailed Implementation

[0066] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0068] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0069] In electronic devices such as mobile phones and tablets, it is necessary to integrate light-sensing components such as front-facing cameras, infrared light sensors, and proximity sensors on one side of the display panel. In some embodiments, a light-transmitting display area can be provided on the aforementioned electronic device, and the light-sensing components can be placed behind the light-transmitting display area, thereby achieving a full-screen display of the electronic device while ensuring that the light-sensing components function properly.

[0070] In some related technologies, to improve the light transmittance of the light-transmitting area, opaque pixel driving circuits are typically placed in the transition zone between the normal display area and the light-transmitting area. The pixel electrodes in the light-transmitting area are connected to the pixel driving circuit in the transition zone via light-transmitting traces. To prevent stress from the large-area inorganic film layer in the light-transmitting area from being transmitted to the transition zone and causing a shift in the characteristics of the thin-film transistor device in the transition zone, such as leading to differences in hydrogen content in the thin-film transistor device in the transition zone, stress relief holes need to be opened on the inorganic insulating layer in the light-transmitting area to maximize the release of stress in the inorganic film layer in the light-transmitting area and ensure equivalent hydrogen content to ensure the equivalence of the thin-film transistor device.

[0071] As the pixel density in the light-transmitting area increases significantly, the density of light-transmitting traces used to connect the pixel electrodes in the light-transmitting area and the pixel driving circuit in the transition area also gradually increases. At this point, the light-transmitting traces may pass through stress relief holes. The presence of stress relief holes may lead to the risk of open circuits in the light-transmitting traces, thereby affecting the yield of the display panel.

[0072] Furthermore, the inventors discovered that due to the presence of multiple inorganic insulating layers, two processes are required to pattern the inorganic insulating layers to form stress relief holes. Additionally, a metal layer needs to be fabricated above the inorganic insulating layers. This process may result in metal residue forming within the stress relief holes during the fabrication of the metal layer above the inorganic insulating layers. This metal residue ultimately leads to the breakage of the insulating layer above the metal layer, which in turn causes the breakage of the topmost light-transmitting trace. This results in poor connection between the pixel electrode in the light-transmitting area and the pixel driving circuit in the transition area, ultimately leading to the appearance of dark spots in the light-transmitting area.

[0073] To address the aforementioned problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0074] This application provides a display panel, which may be an organic light-emitting diode (OLED) display panel.

[0075] Please refer to the following: Figures 1 to 4 , Figure 1 This diagram shows a top view of a display panel 100 according to one embodiment of the present application. Figure 2 yes Figure 1 Enlarged structural diagram at point Q. Figure 3 yes Figure 2 Sectional view at point BB. Figure 4 yes Figure 3 A magnified schematic diagram of a portion of the structure.

[0076] like Figures 1 to 4 As shown, the display panel 100 provided in this embodiment includes: a substrate 01, an insulating layer 024, an overlap portion 310, and signal connection lines 510. The insulating layer 024 is disposed on the substrate 01 and has a plurality of vias 024a; the overlap portion 310 is formed in the via 024a and covers at least a portion of the sidewall of the via 024a in which it is located; the at least a portion of the signal connection line 510 includes a main body portion 511 located on the side of the insulating layer 024 away from the substrate 01, and an extension portion 512 extending from the main body portion 511 into the via 024a and interconnected with the overlap portion 310.

[0077] In the display panel 100 provided in the embodiments of this application, the display panel 100 includes a substrate 01, an insulating layer 024, an overlap portion 310, and a wiring layer 05. An through-hole 024a is formed on the insulating layer 024. An overlap portion 310 is formed in the through-hole 024a and covers at least part of the sidewall. The extension portion 512 of the signal connection line 510 is connected to the overlap portion 310, so that the main body portion 511 of at least part of the signal connection line 510 can be connected to each other through the overlap portion 310. That is, the signal connection lines 510 located on both sides of the overlap portion 310 can be interconnected through the overlap portion 310. The extension portion 512 of the signal connection line 510 is connected to the overlap portion 310, so that at least part of the signal connection lines 510 located on both sides of the through-hole 024a are connected to the overlap portion 310. That is, the signal connection lines 510 located on both sides of the overlap portion 310 can be interconnected through the overlap portion 310. This can improve the problem of easy breakage of the signal connection line 510 caused by the opening in the insulating layer 024, ensure the yield of the signal connection line 510, and thus improve the yield of the display panel 100. Therefore, by forming an overlap portion 310 in the via 024a, the present application embodiment enables at least a portion of the signal connection lines 510 located on both sides of the via 024a to be interconnected through the overlap portion 310, thereby improving the yield of the signal connection lines 510.

[0078] The substrate 01 can be made of a light-transmitting material such as glass or polyimide (PI). There can be one or more insulating layers. The material of the overlap portion 310 can be metal or other conductive materials; optionally, the material of the overlap portion 310 includes a metal material, which can improve the conductivity of the overlap portion 310. Optionally, the material of the signal connection line 510 includes a light-transmitting material, and the signal connection line 510 is a light-transmitting trace, which can improve the light transmittance of the display panel. For example, the material of the signal connection line 510 includes indium tin oxide (ITO). Optionally, the display panel 100 includes a wiring layer 05, and the signal connection line 510 is located in the wiring layer 05.

[0079] In some embodiments, insulating layer 024 includes a first insulating layer 02 and a second insulating layer 04 located on the side of the first insulating layer 02 facing away from the substrate. Via 024a includes a first via 210 formed in the first insulating layer 02 and a second via 410 formed in the second insulating layer 04. The display panel also includes a metal trace layer 03 located between the first insulating layer 02 and the second insulating layer 04. Overlap 310 covers at least a portion of the sidewall of the first via 210 in which it is located, and overlap 310 is made of the same material as the metal trace layer 03.

[0080] In these embodiments, the insulating layer 024 includes a first insulating layer 02 and a second insulating layer 04 stacked together. A metal trace layer 03 is further disposed between the first insulating layer 02 and the second insulating layer 04. The overlapping portion 310 and the metal trace layer 03 are made of the same material. During the fabrication process of the display panel 100, the metal trace layer 03 can be formed using the same material in the same fabrication process step, so that a portion of the metal material falls into the first via 210 and covers at least a portion of the sidewall of the first via 210 to form the overlapping portion 310.

[0081] Optionally, the first via 210 also has a bottom wall on the side opposite to the second insulating layer 02. The overlap portion 310 can cover the bottom wall of the first via 210 to increase the distribution area of ​​the overlap portion 310, making the connection of the signal connection lines 510 interconnected through the overlap portion 310 more stable and further improving the yield of the signal connection lines 510.

[0082] In some alternative embodiments, the size of the first via 210 is smaller than the size of the second via 410, which ensures that a sufficient area of ​​the overlap 310 is exposed through the second via 410, and avoids the second via 410 being too small to affect the interconnection between the signal connection line 510 and the overlap 310.

[0083] In some alternative embodiments, please continue to refer to Figure 3 and Figure 4The orthographic projection of the first via 210 on the substrate 01 is located within the orthographic projection of the second via 410 on the substrate 01, ensuring that the overlap portion 310 can be fully exposed to the second via 410, thus ensuring the stability of the interconnection between the signal connection line 510 and the overlap portion 310.

[0084] There are several ways to set the size of the overlapping part 310 within the first through hole 210, such as... Figure 4 As shown, the extension dimension of the overlapping portion 310 in the thickness direction of the display panel is smaller than the extension dimension of the first through hole 210 in the thickness direction of the display panel, and the overlapping portion 310 does not completely cover the inner wall surface of the first through hole 210.

[0085] Or, such as Figure 5 As shown, at least part of the overlap portion 310 extends in the thickness direction of the display panel in an dimension equal to the extension dimension of the first via 210 in the thickness direction of the display panel, and the overlap portion 310 completely covers the inner wall surface of the first via 210.

[0086] Optional, such as Figure 6 As shown, the metal trace layer 03 also includes a transition portion 320 located on the surface of the first insulating layer 02 facing the second insulating layer 04 and surrounding at least one first via 210. The transition portion 320 is interconnected with the overlap portion 310. By forming the transition portion 320 on the surface of the first insulating layer 02 facing the second insulating layer 04, the distribution area of ​​the metal material within the via 024a can be increased, thus better improving the breakage resistance of the signal connection line 510. Optionally, the transition portion 320 and the overlap portion 310 are connected through at least a portion of the sidewall via of the first via 210.

[0087] Optionally, the transition portion 320 and the overlapping portion 310 are integrally formed. For example, the transition portion 320 and the overlapping portion 310 can be formed in the same process step. For example, when preparing the metal trace layer 03, at least a portion of the metal material falls on the surface of the first insulating layer 02 surrounding the first via 210 to form the transition portion 320, and at least a portion of the metal material falls into the first via 310 to form the overlapping portion 310.

[0088] like Figure 6 As shown, at least a portion of the transition portion 320 may be disposed between the first insulating layer 02 and the second insulating layer 04.

[0089] In other embodiments, such as Figure 7As shown, the diameter of the second via 410 is larger than that of the first via 210. At least a portion of the first insulating layer 02 is exposed through the second via 410. The transition portion 320 is disposed on the surface of the first insulating layer 02 exposed through the second via 410. That is, the orthographic projection of the transition portion 320 on the substrate 01 is smaller than the orthographic projection of the opening of the second via 410 toward the first insulating layer 02 on the substrate 01, so that the extension portion 512 can be interconnected with the transition portion 320 through the second via 210.

[0090] When the display panel 100 includes the transition portion 320, there are various ways in which the extension portion 512 and the overlapping portion 310 are connected to each other, such as... Figure 6 and Figure 7 As shown, the extension 512 can be connected to the overlapping portion 310 via the transition portion 320, or as... Figure 8 As shown, the extension 512 can also be connected to both the transition portion 320 and the overlapping portion 310, that is, at least part of the extension 512 extends into the first through hole 210 and is connected to the overlapping portion 310 in the first through hole 210.

[0091] Optionally, the extension dimension of the transition portion 320 on the diameter of the first via 210 is 1.5μm to 5μm. When the size of the transition portion 320 is within the above range, it can both improve the beneficial effect of the transition portion 320 on the signal connection line 510 due to its small size, and improve the situation where the transition portion 320 is too large and extends outside the second via 210, resulting in part of the transition portion 320 not being able to connect to the extension portion 512 and part of the transition portion 320 not being able to perform its function.

[0092] Optionally, the diameter of the first via 210 is 2μm to 4μm, and the diameter of the second via 410 is 4μm to 6μm. When the diameters of the first via 210 and the second via 410 are within the above ranges, it can avoid the effect of the first via 210 and the second via 410 on improving the stress of the first insulating layer 02 or the second insulating layer 04 due to the diameters of the first via 210 and the second via 410 being too small, and it can also avoid the effect of the first via 210 and the second via 410 being too large on affecting the structural strength of the first insulating layer 02 or the second insulating layer 04.

[0093] In some alternative embodiments, please continue to refer to Figures 4 to 8 The display panel 100 also includes an active layer 07 disposed between the substrate and the insulating layer 024. The active layer 07 also includes a pad 710, wherein at least a portion of the opening of the first via 210 toward the substrate 01 does not exceed the pad 710, that is, the orthographic projection of the opening of at least a portion of the first via 210 toward the substrate 01 onto the substrate 01 is within the orthographic projection of the pad 710 onto the substrate 01.

[0094] In these alternative embodiments, by providing the pad 710, over-etching of the first via 210 can be avoided, which would affect the shape and performance of the layer structure beneath the first insulating layer 02. The pad 710 is located in the active layer 07, allowing the pad 710 to be fabricated in the same process step as the semiconductor section, thus simplifying the fabrication of the display panel 100.

[0095] Optionally, the bottom wall of the first through hole 210 is the surface of the pad 710 facing the first through hole 210, and at least a portion of the surface of the pad 710 is provided with an overlap portion 310.

[0096] Please continue reading. Figure 1 In some optional embodiments, the display panel 100 has a first display area AA1, a second display area AA2, and a non-display area NA surrounding the first display area AA1 and the second display area AA2, wherein the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2. In other embodiments, the display panel 100 may not include the non-display area NA.

[0097] In this paper, the transmittance of the first display area AA1 is preferably greater than or equal to 15%. To ensure that the transmittance of the first display area AA1 is greater than 15%, or even greater than 40%, or even higher, in this embodiment, the transmittance of each functional film layer of the display panel 100 is greater than 80%, or the transmittance of at least some functional film layers of the display panel 100 is greater than 90%.

[0098] According to the embodiment of this application, the light transmittance of the first display area AA1 of the display panel 100 is greater than that of the second display area AA2, so that the display panel 100 can integrate a photosensitive component on the back of the first display area AA1, realizing the under-screen integration of a photosensitive component such as a camera. At the same time, the first display area AA1 can display an image, increasing the display area of ​​the display panel 100 and realizing the full-screen design of the display device.

[0099] Please continue reading. Figures 2 to 8 In some optional embodiments, the display panel 100 further includes: a pixel electrode layer 06 and a driving circuit 12. The pixel electrode layer 06 includes a first pixel electrode 610 located in the first display area AA1 and connected to the signal connection line 510. The driving circuit 12 is located in the second display area AA2. The driving circuit 12 includes a first driving circuit 121 for driving the first pixel electrode 610. The first driving circuit 121 is connected to the first pixel electrode 610 through the signal connection line 510.

[0100] In the display panel 100 provided in this application embodiment, the first driving circuit 121 for driving the first pixel electrode 610 of the first display area AA1 is located in the second display area AA2. This can reduce the distribution area of ​​the metal material in the first display area AA1, further improve the light transmittance of the first display area AA1, and facilitate the under-display integration of the photosensitive component. The first driving circuit 121 and the first pixel electrode 610 are interconnected through the signal connection line 510, which can also improve the yield of the connection between the first driving circuit 121 and the first pixel electrode 610 and improve the display dark spot problem of the first display area AA1.

[0101] Optional, please continue reading Figure 2 The display panel 100 also includes a second pixel electrode 620 and a second driving circuit 122. The second pixel electrode 620 and the second driving circuit 122 are both located in the second display area AA2. The second driving circuit 122 is used to drive the second pixel electrode 620. Figure 2 Only one set of first driving circuit 121 and one set of second driving circuit 122 are shown in the diagram. The number of first driving circuit 121 and second driving circuit 122 can be set according to requirements. Optionally, the second display area AA2 also includes a transition display area TA and a main display area ZA. The transition display area TA is located between the main display area ZA and the first display area AA1, and the first driving circuit 121 can be located in the transition display area TA.

[0102] Optional, please continue reading Figures 3 to 8 The display panel 100 also includes a pixel definition layer 10, which is located on the side of the pixel electrode layer 06 facing away from the substrate 01. The pixel definition layer 10 may include a first opening K1 located in the first display area AA1 and a second opening K2 located in the second display area AA2. A first light-emitting unit 110 may be disposed in the first opening K1, and a second light-emitting unit 120 may be disposed in the second opening K2. A first driving circuit 121 is used to drive the first light-emitting unit 110 to emit light through the first pixel electrode 610, and a second driving circuit 122 is used to drive the second light-emitting unit 120 to emit light through the second pixel electrode 620.

[0103] Optionally, the display panel 100 also includes a common electrode layer 11 located on the side of the pixel definition layer 10 away from the substrate 01. The common electrode layer 11 is used to work together with the pixel definition layer 10 to drive the first light-emitting unit 110 and / or the second light-emitting unit 120 to emit light.

[0104] Optionally, the display panel 100 may also include a support post 130, which is disposed between the pixel definition layer 10 and the common electrode, and is used to support components such as the cover plate.

[0105] In some optional embodiments, at least a portion of the orthographic projection of the via 024a on the substrate 01 and the orthographic projection of the first pixel electrode 610 on the substrate 01 overlap. In these optional embodiments, when the orthographic projections of the via 024a on the substrate 01 and the first pixel electrode 610 on the substrate 01 overlap at least partially, the first pixel electrode 610 can block a portion of the via 024a, thereby blocking the overlap portion 310 located within the via 024a, further reducing the distribution area of ​​metal within the first display area AA1, and improving the light transmittance of the first display area AA1.

[0106] Optionally, when the overlapping portion 310 is located within the first via 210, the orthographic projection of the first via 210 on the substrate 01 and the orthographic projection of the first pixel electrode 610 on the substrate 01 are at least partially overlapped.

[0107] Optionally, the radial dimension of the via 024a is maximized, and its orthogonal projection on the substrate 01 is located within the orthogonal projection of the first pixel electrode 610 on the substrate 01. This allows the first pixel electrode 610 to completely block the via 024a and the overlapping portion 310. In other words, the first pixel electrode 610 and the overlapping portion 310 overlap along the thickness direction, which can further reduce the distribution area of ​​metal in the first display area AA1 and improve the light transmittance of the first display area AA1.

[0108] Optionally, when the overlapping portion 310 is located within the first via 210, the orthographic projection of the first via 210 on the substrate 01 is located within the orthographic projection of the first pixel electrode 610 on the substrate 01.

[0109] The inventors discovered that placing the first driving circuit 121, which is used to connect the first pixel electrode 610, in the second display area AA2 will result in different structural strengths between the first display area AA1 and the second display area AA2. Stress may be transmitted to the second display area AA2 through the insulating layer, thus affecting the characteristics of the first driving circuit 121.

[0110] Please see Figure 9 , Figure 9 yes Figure 1 A magnified structural diagram of Q in another embodiment.

[0111] In some alternative embodiments, such as Figure 9 As shown, at least part of the via 024a is located in the first display area AA1. The via 024a can absorb the stress in the first display area AA1 and improve the characteristics of stress transmission to the second display area AA2, thus affecting the first driving circuit 121.

[0112] Optionally, at least a portion of the via 024a is positioned within the first display area AA1, close to the second display area AA2. This can better mitigate the impact of stress transmission to the second display area AA2 on the characteristics of the first drive circuit 121.

[0113] Optionally, as described above, the first display area AA1 includes a transition display area TA, and at least a portion of the via 024a is located in the transition display area TA.

[0114] In these alternative embodiments, the via 024a in the transition display area TA can absorb the stress transmitted from the first display area AA1, thereby preventing the stress from affecting the characteristics of the first driving circuit 121.

[0115] Optionally, at least a portion of the via 024a is disposed within the transition display area TA, close to the first display area AA1. In these optional embodiments, the via 024a within the transition display area TA is closer to the first display area AA1, which can better absorb the stress transmitted from the first display area AA1, thereby preventing stress from affecting the characteristics of the first driving circuit 121.

[0116] In some alternative embodiments, please continue to refer to Figures 3 to 8 The first insulating layer 02 includes a first sublayer 20a and a second sublayer 20b located on the side of the first sublayer 20a facing away from the substrate 01. The first via 210 includes a first hole segment formed in the first sublayer 20a and a second hole segment formed in the second sublayer 20b.

[0117] The inventors discovered that when the second and first via segments are fabricated sequentially using different processes, there may be slight differences in their dimensions. When the metal trace layer 03 is further fabricated, this dimensional difference can cause metal residue to easily form within the first via segment. The sharp tip of this metal residue can cause the second insulating layer 04 to easily break within the first via 210, which in turn can cause the signal connection line 510 to easily break at the second via 410, thus affecting the yield of the signal connection line 510.

[0118] In some alternative embodiments, the overlap 310 at least covers the inner wall surface of the first sublayer 20a facing the first hole segment.

[0119] In these alternative embodiments, when the overlap 310 covers the inner wall of the first hole segment, there is no need to pattern the metal in the first hole segment. Therefore, it can effectively improve the problem that metal residue is easily formed in the first hole segment due to the patterning of the metal trace layer 03. This can also effectively improve the problem that the second insulating layer 04 is easily broken in the first via 210 due to metal residue. In addition, the size of the overlap 310 is larger, and the signal connection line 510 can penetrate into the second via 410 and connect with the overlap 310.

[0120] Optionally, the overlap 310 may also cover at least part of the inner wall surface of the second sublayer 20b facing the second hole segment to further increase the size of the overlap 310 and ensure the stability of the interconnection between the signal connection line 510 and the overlap 310.

[0121] In some alternative embodiments, please continue to refer to Figures 3 to 8 The display panel 100 also includes a first metal layer 08 located on the side of the active layer 07 away from the substrate 01, a first sub-layer 20a located between the active layer 07 and the first metal layer 08, and a second sub-layer 20b located on the side of the first metal layer 08 away from the substrate 01.

[0122] Optional, please continue reading Figure 3 and Figure 4 The first driving circuit 121 includes a thin-film transistor (TFT). The TFT includes a semiconductor portion, a gate, a source electrode, and a drain electrode. The semiconductor portion is located on the active layer 07 and includes a source region, a drain region, and a channel region located between the source region and the drain region. The gate is located on the first metal layer 08, and the orthogonal projections of the gate and the channel region on the substrate 01 at least partially overlap. The source electrode and the drain electrode may be located on the metal trace layer 03, with the source electrode interconnected with the source region and the drain electrode interconnected with the drain region.

[0123] In these optional embodiments, the first sub-layer 20a is located between the active layer 07 and the first metal layer 08 as an inter-gate insulating layer. That is, the first via 210 extends to the inter-gate insulating layer between the active layer 07 and the first metal layer 08, making the hole depth of the first via 210 larger, so that the first via 210 can better improve the problem of stress transmission from the first display area AA1 to the second display area AA2.

[0124] Optionally, the material of the first sublayer 20a may include inorganic materials such as silicon oxide. The thickness of the first sublayer 20a can be... For example, the thickness of the first sublayer 20a is wait.

[0125] In some alternative embodiments, please continue to refer to Figures 3 to 8 The display panel 100 also includes a second metal layer 09 located on the side of the first metal layer 08 facing away from the substrate 01. There are two second sub-layers 20b, one of which is located between the first metal layer 08 and the second metal layer 09, and the other is located between the second metal layer 09 and the metal wiring layer 03.

[0126] Optionally, the first driving circuit 121 further includes a capacitor, which includes two capacitor plates disposed opposite each other, at least one capacitor plate being located on the second metal layer 09, and the other capacitor plate being located on the first metal layer 08 or the metal trace layer 03.

[0127] The two second sub-layers 20b can be made of the same material, therefore the two second sub-layers 20b can be patterned using the same process step to form the second hole segment. For example, the material of the second sub-layer 20b can include silicon nitride, and the thickness of the second sub-layer 20b between the first metal layer 08 and the second metal layer 09 can be [missing information]. For example, the thickness of the second sublayer 20b between the first metal layer 08 and the second metal layer 09 is

[0128] Optional, please continue reading Figures 3 to 8 The display panel 100 also includes a third insulating layer, which is located between the wiring layer 05 and the pixel electrode layer 06.

[0129] In some embodiments, please continue reading Figures 3 to 8 Each predetermined number of first pixel electrodes 610 are electrically connected to each other through an interconnection structure 630, so that the first light-emitting units 110 interconnected by the first pixel electrodes 610 form a pixel merging structure. The interconnection structure 630 can be electrically connected to the same first driving circuit 121, thereby driving the predetermined number of first light-emitting units 110 to display through a first driving circuit 121, further reducing the actual PPI of the first display area AA1, reducing the driving wiring in the first display area AA1, and improving its light transmittance.

[0130] In some embodiments, the predetermined number is 2 to 8, for example, 4, meaning that every 4 first pixel electrodes 610 are electrically connected to each other through the interconnect structure 630. In some embodiments, the interconnect structure 630 is disposed on the same layer as the first pixel electrodes 610. Optionally, the first interconnect structure 630 is a light-transmitting and conductive structure, for example, made of ITO.

[0131] In some optional embodiments, the wiring layer 05 is provided with multiple signal connection lines 510, and multiple first vias 210 and second vias 410. The extension paths of these signal connection lines 510 can all pass through the second vias 410, and each signal connection line 510 is interconnected with the overlap portion 310 via the second vias 410. The extension path of the same signal connection line 510 can pass through multiple second vias 410, or the extension path of the same signal connection line 510 can pass through one second via 410.

[0132] Please see Figure 10 , Figure 10 This is a top view of a partial layer structure of a display panel 100 provided in another embodiment of this application.

[0133] In some alternative embodiments, the signal connection line 510 includes a first signal connection line 510a and a second signal connection line 510b. The first signal connection line 510a includes an extension 512. The orthographic projection of the second signal connection line 510b on the substrate 01 and the orthographic projection of the via 024a on the substrate 01 are at least partially misaligned.

[0134] In these alternative embodiments, the extension 512 of the first signal connection line 510a is interconnected with the overlap portion 310. At least a portion of the second signal connection line 510b is offset from the via 024a, so that the second connection signal line can have good connectivity without passing through the overlap portion 310 in the via 024a.

[0135] Optionally, the orthographic projection of the second signal connection line 510b on the substrate 01 and the orthographic projection of the via 024a on the substrate 01 are completely misaligned. This complete misalignment of the second signal connection line 510b and the via 024a ensures a high yield rate for the connection of the second signal connection line 510b.

[0136] In any of the above embodiments, optionally, the circuit structure of the first driving circuit 121 is any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit. In this document, "2T1C circuit" refers to the driving circuit 12 that includes two thin-film transistors (T) and one capacitor (C), and so on for "7T1C circuit", "7T2C circuit", "9T1C circuit", etc.

[0137] In any of the above embodiments, optionally, the size of the first light-emitting unit 110 is smaller than the size of the second light-emitting unit 120 of the same color, so that the non-light-emitting area in the first display area AA1 is larger, which facilitates further improvement of the light transmittance of the first display area AA1.

[0138] The first light-emitting unit 110 and the second light-emitting unit 120 may each include an OLED light-emitting layer. Depending on the design requirements of the first light-emitting unit 110 and the second light-emitting unit 120, each may also include at least one of a hole injection layer, a hole transport layer, an electron injection layer, or an electron transport layer.

[0139] In any of the above embodiments, optionally, the first pixel electrode 610 is a light-transmitting electrode. In some embodiments, the first pixel electrode 610 includes an indium tin oxide (ITO) layer or an indium zinc oxide layer. In some embodiments, the first pixel electrode 610 is a reflective electrode, including a first light-transmitting conductive layer, a reflective layer located on the first light-transmitting conductive layer, and a second light-transmitting conductive layer located on the reflective layer. The first and second light-transmitting conductive layers can be ITO, indium zinc oxide, etc., and the reflective layer can be a metal layer, such as being made of silver.

[0140] In any of the above embodiments, optionally, the common electrode layer 11 includes a magnesium-silver alloy layer.

[0141] In any of the above embodiments, optionally, the orthographic projection of each first light-emitting unit 110 on the substrate 01 is composed of one first graphic unit or composed of two or more first graphic units spliced ​​together. The first graphic unit includes at least one selected from the group consisting of circles, ellipses, dumbbells, gourds, and rectangles.

[0142] In any of the above embodiments, optionally, the orthographic projection of each first pixel electrode 610 on the substrate 01 is composed of one second graphic unit or composed of two or more second graphic units spliced ​​together, wherein the second graphic unit includes at least one selected from the group consisting of circles, ellipses, dumbbells, gourds, and rectangles.

[0143] For example, the display panel 100 may also include an encapsulation layer and a polarizer and a cover plate located above the encapsulation layer. Alternatively, the cover plate may be directly disposed above the encapsulation layer without the need for a polarizer, or at least the cover plate may be directly disposed above the encapsulation layer of the first display area AA1 without the need for a polarizer, thus avoiding the polarizer affecting the amount of light collected by the photosensitive element disposed below the corresponding first display area AA1. Of course, a polarizer may also be disposed above the encapsulation layer of the first display area AA1.

[0144] This application also provides a display device, which may include the display panel 100 of any of the above embodiments. The following description uses one embodiment as an example, in which the display device includes the display panel 100 of the above embodiments.

[0145] Figure 11 This is a top view schematic diagram of a display device according to an embodiment of the present application. Figure 12 Show Figure 11 A cross-sectional view along the DD direction. In the display device of this embodiment, the display panel 100 may be the display panel 100 of one of the above embodiments. The display panel 100 has a first display area AA1 and a second display area AA2, and the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2.

[0146] The display panel 100 includes a first surface S1 and a second surface S2 opposite to each other, wherein the first surface S1 is the display surface. The display device also includes a photosensitive component 200, which is located on the second surface S2 side of the display panel 100 and corresponds to the position of the first display area AA1.

[0147] The photosensitive component 200 can be an image acquisition device used to acquire external image information. In this embodiment, the photosensitive component 200 is a complementary metal-oxide-semiconductor (CMOS) image acquisition device. In other embodiments, the photosensitive component 200 can also be a charge-coupled device (CCD) image acquisition device or other forms of image acquisition device. It is understood that the photosensitive component 200 is not limited to an image acquisition device. For example, in some embodiments, the photosensitive component 200 can also be an infrared sensor, a proximity sensor, an infrared lens, a flood illuminator, an ambient light sensor, and a dot projector, etc., light sensors. In addition, the display device can also integrate other components, such as a handset and a speaker, on the second surface S2 of the display panel 100.

[0148] According to the display device of the present application embodiment, the light transmittance of the first display area AA1 is greater than that of the second display area AA2, so that the display panel 100 can integrate a photosensitive component 200 on the back of the first display area AA1, thereby realizing the under-screen integration of the photosensitive component 200 of an image acquisition device, and at the same time, the first display area AA1 can display the image, thereby increasing the display area of ​​the display panel 100 and realizing the full-screen design of the display device.

[0149] Please see Figure 13 , Figure 13 This is a schematic flowchart of a method for manufacturing a display panel 100 provided in the third aspect embodiment of this application.

[0150] In the method for manufacturing the display panel 100 provided in the embodiments of the third aspect of this application, the display panel 100 can be any of the display panels 100 provided in the embodiments of the first aspect described above, such as... Figures 3 to 12 As shown, the method for manufacturing the display panel 100 includes:

[0151] Step S01: An insulating layer 024 is prepared on the substrate 01, and the insulating layer 024 is patterned to form a via 024a.

[0152] Step S02: Deposit metallic material in the via 024a to form an overlap 310.

[0153] Step S03: A wiring layer 05 is prepared on the insulating layer 024. The wiring layer 05 includes a signal connection line 510. At least part of the signal connection line 510 includes a main body portion 511 located on the insulating layer 024 away from the substrate 01, and an extension portion 512 extending from the main body portion 511 into the via 024a and interconnected with the overlap portion 310.

[0154] In the display panel prepared by the preparation method provided in this application embodiment, the display panel includes a substrate 01 and an insulating layer 024, an overlap portion 310, and signal connection lines 510 disposed on the substrate 01. A via 024a is formed on the insulating layer 024. The overlap portion 310 is formed within the via 024a and covers at least a portion of the sidewall. The extension portion 512 of the signal connection line 510 is interconnected with the overlap portion 310, allowing at least a portion of the main body portion 511 of the signal connection line 510 to be interconnected through the overlap portion 310. That is, the signal connection lines 510 located on both sides of the overlap portion 310 can communicate with each other through the overlap portion 310. This improves the problem of easy breakage of the signal connection lines 510 caused by the opening in the insulating layer 024, ensures the yield of the signal connection lines 510, and thus improves the yield of the display panel. Therefore, in this embodiment of the application, by forming an overlap portion 310 in the via 024a, at least a portion of the signal connection lines 510 located on both sides of the via 024 are interconnected through the overlap portion 310, thereby improving the yield of the signal connection lines 510.

[0155] Optionally, the insulating layer 024 includes a first insulating layer 02 and a second insulating layer 04, and the via 024a includes a first via 210 formed in the first insulating layer 02 and a second via 410 formed in the second insulating layer 04. A metal trace layer 03 is disposed between the first insulating layer 02 and the second insulating layer 04.

[0156] like Figure 14 As shown, the method for manufacturing a display panel may include:

[0157] Step S01': A first insulating layer 02 is prepared on the substrate 01, and the first insulating layer 02 is patterned to form a first via 210.

[0158] Step S02': A metal material layer is formed on the side of the first insulating layer 02 away from the substrate 01. The metal material layer is patterned to form a metal trace layer 03. The metal trace layer 03 includes an overlap portion 310 located in at least a portion of the first via 210.

[0159] Step S03': A second insulating layer 04 is prepared on the side of the metal trace layer 03 away from the first insulating layer 02. The second insulating layer 04 includes a second via 410, and the overlap portion 310 is exposed through the second via 410.

[0160] Step S04': A wiring layer 05 is prepared on the side of the second insulating layer 04 away from the metal wiring layer 03. The wiring layer 05 includes signal connection lines 510, and at least a portion of the signal connection lines 510 are interconnected with the overlap portion 310 via the second via 410.

[0161] In the process of fabricating the display panel 100 using the method provided in this application embodiment, a first via 210 and a second via 410 are formed on the first insulating layer 02 and the second insulating layer 04. The first via 210 and the second via 410 can release the stress on the first insulating layer 02 and the second insulating layer 04. The metal traces form an overlap portion 310 in the first via 210, and the extension path of at least a portion of the signal connection lines 510 passes through the second via 410, so that at least a portion of the signal connection lines 510 located on both sides of the second via 410 are interconnected with the overlap portion 310. That is, the signal connection lines 510 located on both sides of the overlap portion 310 can be interconnected through the overlap portion 310, which can avoid the problem of easy breakage of the connection signal caused by the opening of the first insulating layer 02 and the second insulating layer 04, and can ensure the yield of the signal connection lines 510, thereby improving the yield of the display panel 100. Therefore, in this embodiment of the application, by forming a metal overlap 310 in the first via 210, at least a portion of the signal connection lines 510 located on both sides of the second via 410 are interconnected through the overlap 310, thereby improving the yield of the signal connection lines 510.

[0162] Please refer to the following: Figure 3 , Figure 4 , Figure 14 and Figure 15 , Figure 15 This is a schematic flowchart of a method for preparing a display panel 100 according to another embodiment of the third aspect of this application.

[0163] In some alternative embodiments, such as Figure 3 As shown, the first insulating layer 02 includes a first sub-layer 20a and a second sub-layer 20b located on the side of the first sub-layer 20a facing away from the substrate 01, as follows: Figure 15 As shown, step S01' includes:

[0164] Step S011: Prepare a first sublayer 20a and a second sublayer 20b on substrate 01.

[0165] Optional, such as Figure 3 As shown, when an active layer 07 is also provided on the side of the first sublayer 20a facing the substrate 01, the active layer 07 is also prepared on the substrate 01 before step S011, and the active layer 07 is patterned to form a semiconductor portion. When the active layer 07 includes a pad 710, the active layer 07 is patterned to form the pad 710.

[0166] Optionally, as described above, when the display panel 100 includes a first metal layer 08 and a second metal layer 09, in step S011, after the first sub-layer 20a is fabricated, a first metal layer 08 is also fabricated on the first sub-layer 20a, and the first metal layer 08 is patterned to form a gate electrode. A first second sub-layer 20b is fabricated on the first metal layer 08, and a second metal layer 09 is fabricated on the first second sub-layer 20b, and the second metal layer 09 is patterned to form a capacitor plate. Then, a second second sub-layer 20b is fabricated on the second metal layer 09.

[0167] Step S012: Pattern the second sub-layer 20b to form the second hole segment.

[0168] Optionally, gases such as tetrafluoromethane (CF4) and oxygen can be used to pattern the second sublayer 20b.

[0169] Step S013: Pattern the first sub-layer 20a exposed by the second hole segment to form the first hole segment, and connect the first hole segment and the second hole segment to form the first via 210.

[0170] Optionally, gases such as pentafluoroethane (C2F5H), hydrogen (H2), and argon (Ar) can be used to pattern the first sublayer 20a.

[0171] The overlap 310 formed in step S02' at least covers the inner wall surface of the first sub-layer 20a facing the first hole segment.

[0172] In these alternative embodiments, when the overlap 310 covers the inner wall of the first hole segment, there is no need to pattern the metal in the first hole segment. Therefore, it can effectively improve the problem that metal residue is easily formed in the first hole segment due to the patterning of the metal trace layer 03. This can also effectively improve the problem that the second insulating layer 04 is easily broken in the first via 210 due to metal residue. In addition, the size of the overlap 310 is larger, and the signal connection line 510 can penetrate into the second via 410 and connect with the overlap 310.

[0173] Optionally, when the display panel 100 includes a third insulating layer, a pixel electrode layer 06, a pixel definition layer 10, and other layer structures, other film layers can be prepared after step S04 to form the display panel 100.

[0174] The embodiments described above are not exhaustive, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, the display panel having a first display area and a second display area, characterized in that, The display panel includes: A substrate; An insulating layer located on one side of the substrate and having a plurality of vias formed therein; An overlapping portion formed within the via, and the overlapping portion covers at least a part of the sidewall of the via where it is located; A signal connection line, at least a part of the signal connection line includes a main body portion located on the side of the insulating layer背离 the substrate, and an extending portion extending from the main body portion into the via and connected to the overlapping portion; A pixel electrode layer including a first pixel electrode located in the first display area and connected to the signal connection line, and at least a part of the positive projection of the via on the substrate and the positive projection of the first pixel electrode on the substrate overlap at least partially; Wherein, the light transmittance of the first display area is greater than the light transmittance of the second display area, and at least a part of the via is located in the first display area.

2. The display panel according to claim 1, wherein The insulating layer includes a first insulating layer and a second insulating layer located on the side of the first insulating layer背离 the substrate, and the via includes a first via formed in the first insulating layer and a second via formed in the second insulating layer; The display panel further includes a metal wiring layer located between the first insulating layer and the second insulating layer, Wherein, the overlapping portion covers at least a part of the sidewall of the first via where it is located, and the overlapping portion is made of the same material as the metal wiring layer.

3. The display panel according to claim 2, wherein The size of the first via is smaller than the size of the second via.

4. The display panel according to claim 3, wherein The metal wiring layer further includes a transition portion located on the surface of the first insulating layer facing the second insulating layer and surrounding at least one of the first vias, the transition portion is connected to the overlapping portion, and the extending portion is connected to the overlapping portion through the transition portion, or the extending portion is connected to both the transition portion and the overlapping portion.

5. The display panel according to claim 4, wherein The transition portion is located on the surface of the first insulating layer exposed by the second via.

6. The display panel according to claim 4, wherein The extending dimension of the transition portion in the aperture direction of the first via is 1.5μm to 5μm.

7. The display panel according to claim 3, wherein The aperture of the first via is 2μm to 4μm, and the aperture of the second via is 4μm to 6μm.

8. The display panel according to claim 2, wherein The display panel further includes an active layer disposed between the substrate and the insulating layer, and the active layer further includes a spacer block, and at least a part of the opening of the first via facing the substrate side does not exceed the spacer block.

9. The display panel according to claim 1, wherein The display panel further includes: A driving circuit including a first driving circuit for driving the first pixel electrode, and the first driving circuit is connected to the first pixel electrode through the signal connection line.

10. The display panel according to claim 9, wherein At least a part of the positive projection of the via on the substrate is located within the positive projection of the first pixel electrode on the substrate.

11. The display panel according to claim 9, wherein The signal connection line is a light-transmitting wiring.

12. The display panel according to claim 1, wherein At least a part of the via is disposed near the second display area within the first display area.

13. The display panel according to claim 1, wherein The second display area includes a main display area and a transition display area, the transition display area is located between the main display area and the first display area, and at least a part of the via is located in the transition display area.

14. The display panel according to claim 13, wherein At least a part of the via is disposed near the first display area within the transition display area.

15. The display panel according to claim 1, wherein The radial dimension of the positive projection of the overlapping portion on the substrate is 2μm to 3μm.

16. The display panel according to claim 1, wherein The signal connection line includes a first signal connection line and a second signal connection line. The first signal connection line includes the extension portion. The orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via hole on the substrate are at least partially misaligned.

17. The display panel according to claim 16, wherein The orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via hole on the substrate are completely misaligned.

18. A display device, characterized in that, A display panel according to any one of claims 1-17 is included.

19. A method for manufacturing a display panel, the display panel having a first display area and a second display area, the light transmittance of the first display area being greater than that of the second display area, characterized in that, The method includes: Preparing an insulating layer on the substrate, patterning the insulating layer to form via holes, and at least part of the via holes are located in the first display area; Depositing a metal material in the via holes to form overlapping portions; Preparing a wiring layer on the insulating layer. The wiring layer includes signal connection lines. At least part of the signal connection lines include a main body portion located on the side of the insulating layer away from the substrate, and an extension portion extending from the main body portion into the via holes and connected to the overlapping portions; Preparing a pixel electrode layer on the wiring layer. The pixel electrode layer includes a first pixel electrode located in the first display area and connected to the signal connection lines. The orthographic projection of at least part of the via holes on the substrate and the orthographic projection of the first pixel electrode on the substrate are at least partially overlapped.

Images